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LD7522
12/5/2008
Smart Green-Mode PWM Controller with Multiple Protections
REV:04
General Description
The LD7522 is a low startup current, current mode PWM controller with green-mode power-saving operation. The SOP-8/DIP-8 package integrated functions such as the leading- edge blanking of the current sensing, internal slope compensation, line compensation, and several protection features. The protection functions include cycle-by-cycle current limit, OVP, OTP, OLP, and brownout protection. It provides the users a high efficiency, low external component counts solution for AC/DC power applications. Furthermore, to satisfy various protection requirements, both latch-mode protection and auto-recoverable protection can be easily achieved by configuring LD7522 on different operation modes. The special green-mode control is not only to achieve the low power consumption but also to offer a non-audible-noise operation when the LD7522 is operating under light load or no load condition. -Patent Pending
Features
High-Voltage CMOS Process with Excellent ESD protection Very Low Startup Current (< 35A) Current Mode Control Non-audible-noise Green Mode Control UVLO (Under Voltage Lockout) LEB (Leading-Edge Blanking) on CS Pin Internal Slope Compensation Programmable Line Compensation OVP (Over Voltage Protection) OLP (Over Load Protection) OTP (Over Temperature Protection) through a NTC Brownout Protection Flexibility on Latch/Auto-Recoverable Protection Mode 500mA Driving Capability
Applications
Switching AC/DC Adaptor and Battery Charger Open Frame Switching Power Supply LCD Monitor/TV Power
Typical Application
AC input
EMI Filter
OVP
8
7
VCC
6
OUT
LD7522
BNO
1 3 5 2 4
CS
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(-)LATCH
GND COMP
photocoupler
TL431
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Pin Configuration
SOP-8 & DIP-8(TOP VIEW) GND
5
OVP
VCC
7
8
OUT
6
TOP MARK YYWWPP
1 2 3 4
YY : Year code (D: 2004, E: 2005.....) WW : Week code ## : Production code
(-)LATCH
BNO
COMP
Ordering Information
Part number LD7522 PS LD7522 GS LD7522 PN SOP-8 SOP-8 DIP-8 Package PB Free Green Package DIP-8 TOP MARK LD7522PS LD7522GS LD7522PN Shipping 2500 /tape & reel 2500 /tape & reel 3600/tube /carton
The LD7522 is ROHS Complaint/ Green Package.
Pin Descriptions
PIN 1 NAME BNO FUNCTION Brownout Protection Pin. Connect a resistor divider from this pin to bulk capacitor voltage to set the brownout level and line compensation. When the voltage of this pin is lower than a threshold voltage, the PWM output will be off. 2 COMP Voltage feedback pin (same as the COMP pin in UC384X). Connecting a photo-coupler closes the control loop and achieves the regulation. Pulling this pin to lower than 2.5V will shutdown the controller to the latch mode 3 (-) LATCH until the AC power-on recycling. protection. 4 5 6 7 CS GND OUT VCC Current sense pin, for sensing the MOSFET current Ground Gate drive output to drive the external MOSFET Supply voltage pin This pin is high-active to provide the OVP function. OVP resistor voltage divider to Vcc will set the OVP level. this pin disables the OVP function. Connecting a zener or a Whenever the voltage is Grounding Connecting a NTC from this pin to ground will achieve the OTP protection function. Keep this pin floating to disable the latch
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higher than 2.5V, the OVP is triggered and the gate drive will be off.
CS
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Block Diagram
VCC
32V Vbias 8V 100uA PDR Comparator 16V/10V UVLO Comparator 3.5V/ 2.5V Latch Protection Comparator Gain = 0.04 0 1 =Enable =Disable
internal bias & Vref
Vref OK PG
(-) LATCH
VCC OK
BNO
Line Compensation 1
S
Q
=Power Down Reset
1.25V /1.10V
R
Brownout Comparator
OVP
2.5V
1 OVP Comparator
=OVP
1 1
= ACUV =OLP PG
S
Q
R
5.0V
30mS Delay OLP Comparator
Auto-Recoverable Protections Latched Protections
65KHz OSC
PG
PG
Driver Stage
OUT
Vbias
Green-Mode Control
S
Q
COMP
PWM Comparator 2R R
R
+ Slope Compensation
CS
Leading Edge Blanking
+ +
+
Line Compensation
0.85V
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OCP Comparator
GND
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Absolute Maximum Ratings
Supply Voltage VCC COMP, CS, (-) LATCH OVP, BNO Junction Temperature Operating Ambient Temperature Storage Temperature Range Package Thermal Resistance (SOP-8) Package Thermal Resistance (DIP-8) Power Dissipation (SOP-8, at Ambient Temperature = 85C) Power Dissipation (DIP-8, at Ambient Temperature = 85C) Lead temperature (Soldering, 10sec) ESD Voltage Protection, Human Body Model ESD Voltage Protection, Machine Model Gate Output Current 30V -0.3 ~7V -0.3 ~5V 150C -40C to 85C -65C to 150C 160C/W 100C/W 400mW 650mW 260C 3KV 200V 500mA
Caution:
Stresses beyond the ratings specified in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
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Electrical Characteristics
(TA = +25 C unless otherwise stated, VCC=15.0V) PARAMETER Supply Voltage (VCC Pin) Startup Current Operating Current (with 1nF load on OUT pin) UVLO (off) UVLO (on) Voltage Feedback (Comp Pin) Short Circuit Current Green Mode Threshold VCOMP Current Sensing (CS Pin) VBNO=0V (note 2) Maximum Input Voltage, VCS(OFF) VBNO=1.30V VBNO=3.75V Leading Edge Blanking Time Input impedance Delay to Output Gate Drive Output (OUT Pin) Output Low Level Output High Level Rising Time Falling Time Oscillator Frequency Green Mode Frequency Frequency Temp. Stability Frequency Voltage Stability Latch Protection ((-)LATCH Pin) (-)LATCH Pin Source Current Turn-On Trip Level Turn-Off Trip Level (-)LATCH pin www..comde-bounce time De-latch Vcc Level (PDR, Power Down Reset)
Note 1: When OVP, OLP, or Latch Protection is tripped. Note 2: Guaranteed by design because Vcs(off) can't be measured when VBNO=0V.
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CONDITIONS
MIN
TYP
MAX
UNITS A mA mA mA
20 VCOMP=0V VCOMP=3V Protection Mode (note 1) 9.0 15.0 3.5 3.0 0.7 10.0 16.0
35 5.0
11.0 17.0
V V
VCOMP=0V
2.5 2.35
4.0
mA V
0.800 0.748 0.650
0.850 0.798 0.700 350
0.900 0.848 0.750
V V V nS M
1 150
nS
VCC=15V, Io=20mA VCC=15V, Io=20mA Load Capacitance=1000pF Load Capacitance=1000pF 9.0 50 30
1.0
V V
160 60
nS nS
60
65 20
70
KHz KHz
(-40C -85C) (VCC=12V-30V)
3 1
% % A V V S
92 3.3 2.40 100 6.8
100 3.50 2.50
108 3.7 2.60
8.0
8.7
V
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Electrical Characteristics (Continued)
(TA = +25 C unless otherwise stated, VCC=15.0V) PARAMETER CONDITIONS MIN TYP MAX UNITS
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Brownout Protection & Line Compensation (BNO Pin) Brownout Turn-On Trip Level Brownout Turn-Off Trip Level Saturation Voltage Line Compensation Ratio Over Voltage Protection (OVP Pin) OVP Trip Level OVP de-bounce time Saturation Voltage OLP (Over Load Protection) OLP Trip Level OLP Delay Time VCOMP(OLP) VCOMP>5.2V 5.0 30 V mS IBNO=1.5A 2.35 100 5.0 2.50 2.65 V S V IBNO=1.5A 1.20 1.05 1.25 1.10 5.0 0.04 1.30 1.15 V V V V/V
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Typical Performance Characteristics
18.0
12.0
17.2
11.2
UVLO (on) (V)
16.4
UVLO (off) (V)
40 80 120
10.4
15.6
9.6
14.8
8.8
14.0 -40
8.0
0
-40
0
40
80
120
Temperature (C) Fig. 1 UVLO (on) vs. Temperature
Fig. 2
Temperature (C) UVLO (off) vs. Temperature
70
26
67
Green Mode Frequency (KHz)
-40 0 40 80 120
24
Frequency (KHz)
64
22
61
20
58
18
55
16 -40
0
40
80
120
Temperature (C) Fig. 3 Frequency vs. Temperature
Temperature (C) Fig. 4 Green Mode Frequency vs. Temperature
70
25
Green Mode Frequency (KHz)
16 18 20 22 24
68
23
Frequency (KHz)
66
21
64
19
62
17
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15 12 14 16 18 20 22 24
VCC (V) Fig. 5 Frequency vs. VCC
VCC (V) Fig. 6 Green Mode Frequency vs. VCC
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85 0.90 0.85 80 VLINE= 0V
Max Duty Cycle (%)
0.80
VCS (off) (V)
75
VLINE=1.25V 0.75
70
0.70 VLINE=3.75V 0.65
65
60 -40
0.60 0 40 80 120 -40 0 40 80 120
Temperature (C) Fig. 7 Max Duty Cycle vs. Temperature Fig. 8
Temperature (C) Vcs (off) vs. Temperature
40
2.60
Startup Current (A)
30
2.55
OVP (V)
20
2.50
10
2.45
0 -40 0 40 80 120
2.40 -40
0
40
80
120
Temperature (C) Fig. 9 Startup Current vs. Temperature
Temperature (C) Fig. 10 OVP-Trip Level vs. Temperature
6.0
5.5
5.8
5.3
VCOMP (V)
OLP (V)
0 40 80 120
5.6
5.1
5.4
4.9
5.2
4.7
5.0 www..com -40
4.5 -40 0 40 80 120
Temperature (C) Fig. 11 VCOMP open-loop voltage vs. Temperature
Temperature (C) Fig. 12 OLP-Trip Level vs. Temperature
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2.60 110
2.55
(-)Latch Pin Source Current (A)
100
(-)Latch (V)
2.50
90
2.45
80
2.40 -40
70 0 40 80 120 -40 0 40 80 120
Temperature (C) Fig. 13 (-)Latch Pin Off-Level vs. Temperature Fig. 14
Temperature (C) (-)Latch Pin Source Current vs Temperature
25.0
25
125C 20.0 20
125C
IOVP (A)
25C -40C
IBNO (A)
15.0
15
10.0
10
5.0
5 25C 0 0 1 2 3 4 5 6 -40C 1 1 2 3 4 5 6
VBNO Fig. 15 VBNO vs. IBNO
VOVP Fig. 16 VOVP vs. IOVP
1.27
1.150
1.26
1.125
BNO Pin On (V)
1.25
BNO Pin Off (V)
0 40 80 120
1.100
1.24
1.075
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-40
1.050 -40
0
40
80
120
Temperature (C) Fig. 17 BNO Pin On Level vs. Temperature Fig. 18
Temperature (C) BNO Pin Off Level vs. Temperature
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Application Information
Operation Overview
As long as the green power requirement becomes a trend and the power saving is getting more and more important for the switching power supplies and switching adapters, the traditional PWM controllers are not able to support such new requirements. Furthermore, the cost and size limitation force the PWM controllers need to be powerful to integrate more functions for reducing the external part counts. The LD7522 is targeted on such application to provide an easy and cost effective solution; its detailed features are described as below: to drive power MOSFET. Therefore, the current through R1 will provide the startup current and to charge the capacitor C1. Whenever the Vcc voltage is high enough to
turn on the LD7522 and further to deliver the gate drive signal, the supply current is provided from the auxiliary winding of the transformer. Lower startup current
requirement on the PWM controller will help to increase the value of R1 and then reduce the power consumption on R1. By using CMOS process and the special circuit design, the maximum startup current of LD7522 is only 35A. If a higher resistance value of the R1 is chosen, it usually takes more time to start up. Careful value selection of R1
Under Voltage Lockout (UVLO)
An UVLO comparator is implemented in it to detect the voltage on the VCC pin. It would assure the supply voltage enough to turn on the LD7522 PWM controller and further to drive the power MOSFET. As shown in Fig. 19, a
and C1 will optimize the power consumption and startup time.
hysteresis is built in to prevent the shutdown due to the voltage dip during startup. The turn-on and turn-off
threshold level are set at 16V and 10.0V, respectively.
Vcc
UVLO(on) UVLO(off)
t I(Vcc)
operating current (~ mA)
Fig. 20
Output Stage and Maximum Duty-Cycle
startup current (~uA)
An output stage of a CMOS buffer, with typical 500mA
t
driving capability, is incorporated to drive a power MOSFET directly. And the maximum duty-cycle of LD7522 is limited
Fig. 19
to 75% to avoid the transformer saturation.
www..com and Startup Circuit Startup Current
The typical startup circuit for the LD7522 is shown in Fig. 20. During the startup transient, the Vcc is lower than the UVLO threshold thus there is no gate pulse produced from LD7522
Oscillator and Switching Frequency
The switching frequency of LD7522 is fixed at 65KHz internally to provide the optimized operations by considering
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the EMI performance, thermal treatment, component sizes and transformer design. and achieve regulation. The LD7522 detects the primary MOSFET current from the CS pin, which is not only for the peak current mode control but also for the pulse-by-pulse
Voltage Feedback Loop
The voltage feedback signal is provided from the TL431 in the secondary side through the photo-coupler to the COMP pin of LD7522. The input stage of LD7522, like the
current limit. The maximum voltage threshold of the current sensing pin is set as 0.85V. Thus the MOSFET peak current can be calculated as:
UC384X, has 2 diodes voltage offset before feeding into the voltage divider with 1/3 ratio, that is,
V+ (PWM COMPARATOR ) = 1 x ( VCOMP - 2VF ) 3
IPEAK(MAX) =
(0.85 - VLINE _ COMPENSATION ) RS
A 350nS leading-edge blanking (LEB) time is included in the input of CS pin to prevent the false-trigger due to the current spike. However, the total pulse width of the turn-on spike is decided by the output power, circuit design and PCB layout. It is strongly recommended to adopt a smaller R-C filter (as
A pulling-high resistor is embedded internally to eliminate the requirement of another resistor in the external circuit.
Dual-Oscillator Green-Mode Operation
There are many different topologies implemented in different chips for the green-mode or power saving requirements, such as "burst-mode control", "skipping-cycle mode", "variable off-time control "...etc. The basic operation theory of all these approaches intends to reduce the switching cycles under light-load or no-load condition either by skipping some switching pulses or reduce the switching frequency. By using this dual-oscillator control, the green-mode frequency can be well controlled and further to avoid the generation of audible noise.
shown in figure 21) to avoid the CS pin being damaged by the negative turn-on spike.
Internal Slope Compensation
A fundamental issue of current mode control is the stability problem when its duty-cycle is higher than 50%. To stabilize the control loop, slope compensation is needed in the traditional UC384X design by injecting the ramp signal from the RT/CT pin through a coupling capacitor. In the LD7522, the internal slope compensation circuit has been internally implemented to simplify the external circuit design. Fig. 21
Brownout Protection & Line Compensation
BNO pin plays 2 different roles in LD7522. The major function is to set the brownout protection point, and at the same time, the second function provides the line
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The typical current mode PWM controller feeds back both current signal and voltage signal to close the control loop
compensation function like in LD7520.
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Since the voltage on the BNO pin is proportional to the bulk capacitor voltage, representing the line voltage. A
t Line Voltage
brownout comparator is implemented to detect the abnormal line condition and, upon detection it shuts down the controller to prevent damage. operation. Figure 22 shows the
VBNO
When VBNO is lower than 1.25V, the gate output
1.25V
will be kept off even if the Vcc already achieves UVLO(on), therefore the Vcc will be hiccup between UVLO(on) and UVLO(off). Only if the line voltage is so high that VBNO is
1.10V AC OK area
higher than 1.25V, the gate output will start switching when the next UVLO(on) is tripped. A hysteresis is implemented to prevent the false trigger during turn-on and turn-off. On the other hand, LD7522 detects the voltage on the BNO pin to feed the line compensation signal on the current
UVLO(on) UVLO(off)
t Vcc
t
sense circuit. Figure 23 shows the circuit. Thanks to this
OUT
implementation, the OCP levels of high-line and low-line can be achieved at very close points. The voltage gain from the BNO voltage to line compensation is 0.04 (V/V). The relationship between BNO pin voltage Fig. 22
2 Vac
Non-Switching Switching NonSwitching
t
and the line compensation is illustrated in figure 24. In order to protect BNO pin from being damaged during the dividing resistors floating, an internal zener diode is implemented in BNO pin. Fig. 15 shows the sinking capability of the zener diode. To protect BNO pin, the current flowing in BNO pin must be below 1.5A, as shown in Fig. 15.
BNO C R2 R1
Line Compensation Gain = 0.04 (V/V)
LD7522
+
CS
Leading Edge Blanking
+
OCP Comparator
0.85V
Fig. 23
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Fig. 25 By using such protection mechanism, the average input power can be reduced to a very low level so that the component temperature and stress can be controlled within a safe operating area.
Over Voltage Protection (OVP)
The Vgs ratings of the nowadays power MOSFETs most have the maximum of 30V. To prevent the component damage in a fault condition, the LD7522 is implemented the Fig. 24 with the protection through the OVP pin. Figure 26 and figure 27 show 2 different configurations to program the OVP setting point --- zener detection and voltage divider. Figure 26 shows zero bias current under normal operation so that it will not affect the startup timing. But the tolerance
Over Load Protection (OLP)
To protect the circuit from the damage during over load condition or short condition, a smart OLP function is implemented in the LD7522. Figure 25 shows the waveforms of the OLP operation. Under such fault
of OVP trip point will be higher due to the breakdown voltage variation of a discrete zener diode. On the other hand, the circuit of figure 27 will get the benefits on the cost and that the OVP accuracy, but R1 and R2 must be of high resistance to avoid affecting the startup time due to the load effect. As shown in figure 28, whenever the voltage on the OVP pin is higher than the threshold voltage 2.5V, the output gate drive circuit will be shutdown simultaneously, stopping the switching of the power MOSFET. Whenever the voltage on the OVP pin gets back to lower than 2.5V, the output is automatically returned to the normal operation on the next
condition, the feedback system will force the voltage loop toward saturation and thus pull the voltage on COMP pin (VCOMP) to high. Whenever the VCOMP trips the OLP
threshold, 5.0V, and keeps for more than 30mS, the protection is activated to turn off the gate output and stop the switching of power circuit. The 30mS delay time is to
prevent the false trigger during the power-on and turn-off transient.
VCC
UVLO(on)
UVLO(on) level.
UVLO(off) OLP UVLO(off) OLP Reset
t
Vbulk-cap
COMP
30mS
V(OVP)= Vz+2.5V Vz
OLP trip Level
5.0V
VCC
t
OVP
OUT
LD7522
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Switching Non-Switching Switching
GND
t
Fig. 26
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LD7522. When the device temperature or ambient temperature rises, the resistance of NTC decreases so that the voltage on the (-)LATCH pin will be
V( - )LATCH = 100A x RNTC
V (OVP ) = 2.5V (1 +
R2 ) R1
Fig. 27
VCC
OVP Tripped OVP Level UVLO(on) UVLO(off)
t OUT
Switching
Non-Switching
Switching
t
Fig. 28
(-)LATCH
Pin
and
Over
Temperature
Protection (OTP) --- Latched Mode Protection
Under some abnormal conditions, the ambient temperature may be increased significantly, causing some damage on the components or, in a worsen scenario, endangering the users. Thus, the OTP is required. The OTP circuit is www..com implemented by sensing a hot-spot of power circuit like a power MOSFET or an output rectifier. It can be easily
achieved by connecting a NTC on the (-)LATCH pin of a
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When the V(-)LATCH is lower than the threshold voltage (typical 2.5V), LD7522 will shutdown the gate output and then latch off the power supply. For the LD7522, the
Summary of Protections
There are several ways to control the on/off of the LD7522. The details are listed as the table below. Turn Off COMP OLP OVP Comp Pin < 1.4V Comp Pin > 5.0V OVP Pin > 2.5 V BNO Pin < Brownout 1.25V with Hysteresis OTP (-)LATCH Pin Latch Mode < 2.5V Table 1 Hiccup Mode Non-latch Re-start after next UVLO(on) Operation Cycle by Cycle Mode Non-latch
controller will be kept latched until the Vcc drops lower than 8V (power down reset) and the fault condition is removed. That means the gate output may still be kept off even the abnormal condition is released. The only way to
successfully re-start the circuit needs to meet 2 conditions. One is to cool down the circuit and thus NTC resistance is increased then V(-)LATCH increases over 3.5V. Another condition is to remove the AC power cord and begin another AC power-on recycling. as figure 29. The detailed operation is depicted
Fig. 29
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Package Information
SOP-8
Dimensions in Millimeters Symbols MIN MAX
Dimensions in Inch MIN MAX
A B C D F H I J M
4.801 3.810 1.346 0.330 1.194 0.178 0.102 5.791 0.406 0
5.004 3.988 1.753 0.508 1.346 0.229 0.254 6.198 1.270 8
0.189 0.150 0.053 0.013 0.047 0.007 0.004 0.228 0.016 0
0.197 0.157 0.069 0.020 0.053 0.009 0.010 0.244 0.050 8
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Package Information
DIP-8
Dimension in Millimeters Symbol Min A B C D E F I J L 9.017 6.096 ----0.356 1.143 2.337 2.921 7.366 0.381 Max 10.160 7.112 5.334 0.584 1.778 2.743 3.556 8.255 ------
Dimensions in Inches Min 0.355 0.240 -----0.014 0.045 0.092 0.115 0.29 0.015 Max 0.400 0.280 0.210 0.023 0.070 0.108 0.140 0.325 --------
Important Notice
Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers should
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verify the datasheets are current and complete before placing order.
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Revision History
Rev. 00 01 Date 4/4/06 8/31/06 Change Notice Original Specification. Revision: Latch protection turn-on trip level, OVP trip level, and De-latch Vcc level Add: Application circuit & BOM list 02 03 04 12/8/2006 1/16/2008 12/5/2008 Revision: Block Diagram Green Package Option Additional remark for BNO pin.
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