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TB62206FG
TOSHIBA BiCD Processor IC Silicon Monolithic
TB62206FG
BiCD PWM 2-Phase Bipolar Stepping Motor Driver
The TB62206FG is designed to drive a 2-phase bipolar setpping motor. With BiCD process technology, this device enables output withstand voltage of 40 V and maximum current of 1.8 A to be achieved.
Features
* * * * * * * Bipolar stepping motor driver IC Internal PWM current control 2-phase/1-2 phase excitation is available Monolithic BiCD IC DMOS FET used for output power transistor High voltage output and High current: 40 V/1.8 A (max) On-chip thermal shutdown circuit, overcurrent protection circuit and power-on reset circuit (POR) Package: HSOP20-P-450-1.00 Weight: 0.79 g (typ.)
Pin Assignment
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20 TORQUE OUT B ENABLE B ENABLE A OUT B FIN (GND) OUT A PHASE B PHASE A OUT A 11 STANDBY
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CR 1 VDD Vref A Vref B RS B FIN (GND) RS A VM Ccp C Ccp B Ccp A 10
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TB62206FG
Block Diagram
STANDBY
ENABLE A ENABLE B PHASE A PHASE B OCS Input logic
VDD
Chopper OSC CR
TORQUE Vref
Current Level Set Torque Control
CR-CLK Converter
Current Feedback (x2)
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RS
VRS
RS COMP
Output Control (Mixed Decay Control)
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VM VM
Ccp C Charge Pump Unit
STANDBY
ISD Output (H-Bridge) x2
TSD
Ccp B Ccp A
ENABLE
VM
VDDR/VMR Protect Protection Unit
VDD
Stepping motor
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TB62206FG
Function TableOutput
Phase X H L Enable L H H OUT (+) OFF H L OUT () OFF L H
X:
Don't care
Others
Pin Name ENABLE X PHASE X
STANDBY
H Output OUT X: H Motor operation enable 100%
L Output OFF OUT X : H All functions of the IC stopped 71%
Notes Output is OFF regardless of its phase's state. In high level, current flows OUT X OUT X When STANDBY = L, output stopped while charge pomp stopped. High-level
TORQUE
Protection Function
(1) Thermal shutdown circuit While Tj = 150C, all outputs are OFF. To turn-on, change the state of the STANDBY pin in the order of H, L, H. It has temperature hysteresis to prevent the output from oscillating. (T = 35C)
POR (Power-On Reset Circuit: VM and VDD power supply monitor circuit) .com Output is forcibly turned off until VM and VDD reach their specified levels. ISD Output is forcibly turned off when current higher than the specified level flows in the output block. To turn-on, change the state of the STANDBY pin in the order of H, L, H.
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(2)
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(3)
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TB62206FG
Timing Chart
(1) Full Step
H PHASE A L H PHASE B L H ENABLE A L H ENABLE B L 100% IO (A)
-100%
100% IO (B)
-100%
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(2) Half Step
H PHASE A L H PHASE B L H ENABLE A L H ENABLE B L 100% IO (A) 0%
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-100%
100% IO (B) 0%
-100%
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TB62206FG
Maximum Ratings (Ta = 25C)
Characteristics Logic supply voltage Motor supply voltage Output current Current detect pin voltage Charge pump pin maximum voltage (CCP1 pin) Logic input voltage Power dissipation Operating temperature Storage temperature Junction temperature (Note 2) (Note 3) (Note 4) (Note 1) Symbol VDD VM IOUT VRS VH VIN PD Topr Tstg Tj Rating 7 40 1.8 VM 4.5 V VM + 7.0 to VDD + 0.4 1.4 3.2 Unit V V A/phase V V V W C C C
-40 to 85 -55 to 150
150
Note 1: Perform thermal calculations for the maximum current value under normal conditions. Use the IC at 1.5 A or less per phase. The current value maybe controled according to the ambient temperature or board conditions. Note 2: Input 7 V or less as VIN Note 3: Measured for the IC only. (Ta = 25C) Note 4: Measured when mounted on the board. (Ta = 25C)
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Ta: IC ambient temperature Topr: IC ambient temperature when starting operation .com Tj: IC chip temperature during operation Tj (max) is controlled by TSD (thermal shut down circuit)
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Recommended Operating Conditions (Ta = 0 to 85C, (Note 5))
Characteristics Power supply voltage Motor supply voltage Output current Logic input voltage Phase signal input frequency Chopping frequency Vref reference voltage Current detect pin voltage Symbol VDD VM IOUT (1) VIN fPHASE fchop Vref VRS VDD = 5.0 V VDD = 5.0 V VM = 24 V, Torque = 100% VDD = 5.0 V Test Condition Min 4.5 13 Typ. 5.0 24 1.2 Max 5.5 35 1.5 VDD 150 150 4.0 Unit V V A V KHz KHz V V
VDD = 5.0 V, Ccp1 = 0.22 F, Ccp2 = 0.02 F Ta = 25C, per phase
GND
1.0 100 3.0
50 GND 0
1.0
4.5
Note 5: Because the maximum value of Tj is 120C, recommended maximum current usage is below 120C.
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TB62206FG
Electrical Characteristics 1 (unless otherwise specified, Ta = 25C, VDD = 5 V, VM = 24 V)
Characteristics HIGH Input voltage LOW Input hysteresis voltage VIN (L) VIN (HIS) IIN (H) Input current IIN (H) IIN (L) IDD1 Power dissipation (VDD pin) IDD2 DC DC DC Data input pins Data input pins with resistor Data input pins without resistor VDD = 5 V, all inputs connected to ground, Logic, output all off Output OPEN, fPHASE = 1.0 kHz LOGIC ACTIVE, VDD = 5 V, ChargePump = charged Output OPEN, all inputs connected to ground, Logic, output all off, ChargePump = no operation OUT OPEN, fPHASE = 1 kHz LOGIC ACTIVE, VDD = 5 V, VM = 24 V, Output off, ChargePump = charged OUT OPEN, fPHASE = 4 kHz LOGIC ACTIVE, 100 kHz chopping (emulation), Output OPEN, ChargePump = charged Symbol VIN (H) DC Data input pins Test Circuit Test Condition Min 2.0 GND - 0.4 200 35 Typ. VDD GND 400 50 Max VDD + 0.4 0.8 700 75 1.0 1.0 3.0 mA 1.0 2.5 3.5 mV Unit
V

1.0

2.0
A
IM1
1.0
2.0
3.0
Power dissipation (VM pin)
IM2
DC
2.0
4.0
5.0
mA
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IM3
10
13
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A A A
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Output standby current Output bias current Upper Upper DC IOB DC DC
VRS = VM = 24 V, VOUT = 0 V, STANDBY = H, PHASE = H
-200 -100
66
-150 -50
1.0 100 71

1.0
VOUT = 0 V, STANDBY = H
Output leakage current
Lower HIGH (reference) LOW
IOL VRS (H)
DC
VRS = VM = CcpA = VOUT = 24 V, LOGIC IN = ALL = L Vref = 3.0 V, Vref (Gain) = 1/5.0 TORQUE = (H) = 100% set Vref = 3.0 V, Vref (Gain) = 1/5.0 TORQUE = (L) = 71% set Differences between output current channels IOUT = 1000 mA VRS = 24 V, VM = 24 V STANDBY = L IOUT = 1.0 A, VDD = 5.0 V Tj = 25C, Drain-Source IOUT = 1.0 A, VDD = 5.0 V Tj = 25C, Source-Drain IOUT = 1.0 A, VDD = 5.0 V Tj = 105C, Drain-Source IOUT = 1.0 A, VDD = 5.0 V Tj = 105C, Source-Drain
Comparator reference voltage ratio
% 76 5 5 2 0.6 0.6 % %
DC VRS (L)
Output current differential Output current setting differential RS pin current
IOUT1 IOUT2
IRS RON (D-S) 1 RON (S-D) 1
DC DC DC
-5 -5

1 0.5 0.5 0.6 0.6
A
Output transistor drain-source ON-resistance
DC RON (D-S) 2 RON (S-D) 2
0.75 0.75
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TB62206FG
Electrical Characteristics 2 (unless otherwise specified, Ta = 25C, VDD = 5 V, VM = 24 V)
Characteristics Symbol Test Circuit DC Test Condition VM = 24 V, VDD = 5 V, STANDBY = H, Output on, PHASE = 1 kHz STANDBY = H, Output on, VM = 24 V, VDD = 5 V, Vref = 3.0 V VM = 24 V, VDD = 5 V, STANDBY = H, Output on, Vref = 0.0 to 4.0 V VDD = 5 V, VM = 24 V TjTSD = 130 to 170C VM = 24 V, STANDBY = H VDD = 5 V, STANDBY = H VDD = 5 V, VM = 24 V Min Typ. Max Unit
Vref input voltage
Vref
GND
4.0
V
Vref input current
Iref
DC
20
35
50
A
Vref attenuation ratio TSD temperature (Note 1)
Vref (GAIN) TjTSD
DC DC DC DC DC
1/4.8 130 Tj TSD - 50 2.0 8.0
1/5.0
1/5.2 170 TjTSD - 20 4.0 10
C C V V A
TjTSD - 35 3.0 9.0 3.0
TSD return temperature difference (Note 1) VDD return voltage VM return voltage Over current protected circuit operation current (Note 2)
TjTSD
VDDR VMR ISD
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Note 1: Thermal shut down (TSD) circuit When the IC junction temperature reaches the specified value and the TSD circuit is activated, the internal reset circuit is activated switching the outputs of both motors to off. When the temperature is set between 130 (min) to 170C (max), the TSD circuit operates. When the TSD circuit is activated, the charge pump is halted, and TROTECT pin outputs VDD voltage. Even if the TSD circuit is activated and STANDBY goes H L H instantaneously, the IC is not reset until the IC junction temperature drops -20C (typ.) below the TSD operating temperature (hysteresis function).
Note 2: Overcurrent protection circuit When current exceeding the specified value flows to the output, the internal reset circuit is activated, and the ISD turns off the output. Until the STANDBY signal goes Low to High, the overcurrent protection circuit remains activated. During ISD, IC turns STANDBY mode and the charge pump halts.
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TB62206FG
AC Electrical Characteristics (Ta = 25C, VM = 24 V, VDD = 5 V, 6.8 mH/5.7 )
Characteristics Clock frequency Symbol fPHASE tw (tCLK) Minimum clock pulse width twp twn tr tf Output transistor switching characteristic tpLH tpHL tpLH tpHL Noise rejection dead band time CR reference signal oscillation frequency tBRANK fCR fchop (min) fchop (max) fchop tONG Test Circuit AC Test Condition Min Typ. Max 166 Unit kHz

Output Load: 6.8 mH/5.7
100 50 50

100 100 1000 2000 500 1000 300 800

AC

500 ns kHz ns
s

200
PHASE to OUT Output Load: 6.8 mH/5.7 CR to OUT Output Load: 6.8 mH/5.7 IOUT = 1.0 A Cosc = 560 pF, Rosc = 3.6 k VM = 24 V, VDD = 5 V, Output ACTIVE (IOUT = 1.0 A) Step fixed, Ccp1 = 0.22 F, Ccp2 = 0.01 F Output ACTIVE (IOUT = 1.0 A), CR CLK = 800 kHz Ccp = 0.22 F, Ccp = 0.022 F VM = 24 V, VDD = 5 V, STANDBY = ON OFF
Chopping frequency possible range
40
100
150
kHz
Chopping set frequency

100
kHz
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Charge pump rise time
100
200
s
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TB62206FG
Current Waveform and Setting of MIXED DECAY MODE
To control the constant current, the rate of Mixed Decay Mode which determines current amplitude (ripple current) should be 37.5%.
fchop
CR pin internal CLK waveform DECAY MODE 1 37.5% MIXED DECAY MODE NF
Set current value
MDT Charge mode NF: set current value reached Slow mode Mixed decay timing Fast mode Charge mode
MIXED DECAY MODE Waveform (current waveform)
fchop fchop
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Internal CR CLK signal IOUT
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Set current value
Set current value 25% MIXED DECAY MODE
NF
NF
RNF MDT (MIXED DECAY TIMING) point: 37.5% fixed
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TB62206FG
CLK Signal, Internal CR CLK, and Output Current Waveform
(when CLK signal is input in 2 excitation mode)
37.5 MIXED DECAY MODE fchop fchop fchop
Set current value IOUT
0
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MDT Set current value NF NF
PHASE signal input Reset CR-CLK counter here
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TB62206FG
Current Discharge Path when ENABLE Input During Operation
In Slow Mode, when all output transistors are forced to switch off, coil energy is discharged in the following MODES: Note: Parasitic diodes are located on dotted lines. In normal MIXED DECAY MODE, the current does not flow to the parasitic diodes.
VM RRS RS pin U1 ON (Note) U2 OFF U1 OFF (Note) RRS RS pin U2 OFF U1 OFF (Note) VM RRS RS pin U2 OFF VM
Load OFF L1 ON L2 ON L1
Load
Input ENABLE L2 ON L1 OFF
Load L2 OFF
PGND Charge mode
PGND Slow mode
PGND Forced OFF mode
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As shown in the figure above, an output transistor has parasitic diodes. To discharge energy from the coil, each transistor is switched on allowing current to flow in the reverse direction to that in normal operation. As a result, the parasitic diodes are not used. If all the output transistors are forced to switch off, the energy of the coil is discharged via the parasitic diodes. .com
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TB62206FG
Output Transistor Operating Mode
VM RRS RS pin U1 ON (Note) U2 OFF U1 OFF (Note) RRS RS pin U2 OFF U1 OFF (Note) VM VM RRS RS pin U2 ON
Load L1 OFF L2 ON L1 ON
Load L2 ON L1 ON
Load L2 OFF
PGND Charge mode Current flows into the coil.
PGND Slow mode Current flows between the coil and the IC.
PGND Fast mode The energy in the coil flows back to the power supply.
Output Transistor Operation Functions
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CLK CHARGE SLOW FAST U1 ON OFF OFF U2 OFF OFF ON L1 OFF L2 ON ON OFF
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ON
Note: The above table is an example where current flows in the direction of the arrows in the above figures. When the current flows in the opposite direction of the arrows, see the table below.
CLK CHARGE SLOW FAST
U1 OFF OFF ON
U2 ON OFF OFF
L1 ON ON OFF
L2 OFF ON ON
In this IC, three modes as shown above are automatically switched to control the constant current.
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TB62206FG
Power Supply Sequence (recommended)
VDD (max) VDD (min) VDD VDDR
GND VM VM (min) VMR GND Active Internal operable Non-active
VM
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STANDBY INPUT (Note 1)
H STANDBY L
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Takes up to tONG until operable. Non-operable area
Note 1: If the VDD drops to the level of the VDDR or below while the specified voltage is input to the VM pin, the IC is internally reset. This is a protective measure against malfunction. Likewise, if the VM drops to the level of the VMR or below while regulation voltage is input to the VDD, the IC is internally reset as a protective measure against malfunction. To avoid malfunction, when turning on VM or VDD, to input the STANDBY signal at the above timing is recommended. It takes time for the output control charge pump circuit to stabilize. Wait up to tONG time after power on before driving the motors. Note 2: When the VM value is between 8 to 11 V, the internal reset is released, thus output may be on. In such a case, the charge pump cannot drive stably because of insufficient voltage. The Standby state should be maintained until VM reaches 13 V or more. Note 3: Since VDD = 0 V and VM = voltage within the rating are applied, output is turned off by internal reset. At that time, a current of several mA flows due to the Pass between VM and VDD. When voltage increases on VDD output, make sure that specified voltage is input.
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TB62206FG
How to Calculate Set Current
This IC drives the motor, controlling the PWM constant current in reference to the frequency of CR oscillator. At that time, the maximum current value (set current value) can be determined by setting the sensing resistor (RRS) and reference voltage (Vref).
Torque (Torque = 100, 71%) 1 x Vref (V) x RRS () x 100(%) 5.0
IOUT (max) =
1/5.0 is Vref (gain): Vref attenuation ratio. (for the specifications, see the electrical characteristics.) For example, when applying Vref = 3 V and torque = 100% to drive out IOUT of 0.8 A, RRS = 0.75 (0.5 W or more) is required. (for 1-2 phase excitation with 71% of torque, the peak current should be set to 100%).
How to Calculate the Chopping and OSC Frequencies
At constant current control, this IC chops frequency using the oscillation waveform (saw tooth waveform) determined by external capacitor and resistor as a reference. The TB62206FG requires an oscillation frequency of eight times the chopping frequency. The oscillation frequency is calculated as follows:
1 0.523 x (C x R + 600 x C)
fCR =
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For example, when Cosc = 560 pF and Rosc = 3.6 k are connected, fCR = 813 kHz. At this time, the chopping frequency fchop is calculated as follows: fchop = fCR/8 = 101 kHz
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TB62206FG
IC Power Dissipation
IC power dissipation is classified into two: power consumed by transistors in the output block and power consumed by the logic block and the charge pump circuit.
* *
Power consumed by the Power Transistor (calculated with RON = 0.60 ) In Charge mode, Fast Decay mode, or Slow Decay mode, power is consumed by the upper and lower transistors of the H bridges. The following expression expresses the power consumed by the transistors of a H bridge. P (out) = 2 (Tr) x IOUT (A) x VDS (V) = 2 x IOUT2 x RON ..............................(1) The average power dissipation for output under 4-bit micro step operation (phase difference between phases A and B is 90) is determined by expression (1). Thus, power dissipation for output per unit is determined as follows (2) under the conditions below. RON = 0.60 (1.0 A) IOUT (Peak: max) = 1.0 A VM = 24 V VDD = 5 V P (out) = 2 (Tr) x 1.02 (A) x 0.60 x 2 () = 2.40 (W) ........................................(2) Power consumed by the logic block and IM The following standard values are used as power dissipation of the logic block and IM at operation. I (LOGIC) = 2.5 mA (typ.): I (IM3) = 10.0 mA (typ.): operation/unit I (IM1) = 2.0 mA (typ.): stop/unit The logic block is connected to VDD (5 V). IM (total of current consumed by the circuits connected to VM and current consumed by output switching) is connected to VM (24 V). Power dissipation is calculated as follows: P (Logic&IM) = 5 (V) x 0.0025 (A) + 24 (V) x 0.010 (A) = 0.25 (W) ...............(3) Thus, the total power dissipation (P) is P = P (out) + P (Logic&IM) = 2.65 (W) Power dissipation at standby is determined as follows: P (standby) + P (out) = 24 (V) x 0.002 (A) + 5 (V) x 0.0025 (A) = 0.06 (W) For thermal design on the board, evaluate by mounting the IC.
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TB62206FG
Test Waveforms
Phase
t phase
tpLH VM 90% 50% 10% tr tf tpHL 90% 50% 10%
GND
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Figure 1 Timing Waveforms and Names
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TB62206FG
OSC-Charge Delay H OSC-Fast Delay
OSC (CR)
L tchop H OUTPUT Voltage A L H OUTPUT Voltage A L Set current 50% 50% 50%
OUTPUT Current
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L Charge Slow Fast
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OSC-Charge DELAY: Because the rising edge level of the OSC waveform is used for converting the OSC waveform to the internal CR CLK, a delay of up to 1.25 ns (@fchop = 100 kHz: fCR = 400 kHz) occurs between the OSC waveform and the internal CR CLK.
CR-CR CLK DELAY
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CR Waveform
Internal CR CLK Waveform
Figure 2 Timing Waveforms and Names (CR and output)
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TB62206FG
PD - Ta (package power dissipation)
PD - Ta
3.5 3 (2)
PD (W) Power dissipation
2.5 2 1.5 1 0.5 0 0 (1)
25
50
75
100
125
150
Ambient temperature
Ta
(C)
(4) (5)
HSOP20 Rth (j-a) only (96C/W) When mounted on the board (140 mm x 70 mm x 1.6 mm: 38C/W: typ.: under evaluation)
Note: Rth (j-a): 8.5C/W
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TB62206FG
Relationship between VM and VH (charge pump voltage)
VM - VH (&Vcharge UP)
50
VH voltage
charge up voltage
VM voltage
40 Charge pump output voltage
Input STANDBY
(V) VH voltage, charge up voltage
30
VM voltage
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VMR 20 Maximum rating
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Recommended operation area
Usable area
0 0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Supply voltage VM (V) Charge pump voltage VH = VDD + VM (= Ccp A)
(V)
Note: VDD = 5 V
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TB62206FG
Operation of Charge Pump Circuit
RRS VDD = 5 V RS VM
VM = 24 V
VH i2 Di2 Output Comparator & Controller Output H switch Tr1 Tr2 Vz Di3 Di1 (1) i1
Ccp A
7
(2)
Ccp B Ccp 2 0.022 F Ccp 1 0.22 F
(2)
R1
Ccp C
VH = VM + VDD = charge pump voltage i1 = charge pump output current i2 = gate block power dissipation
*
Initial charging When RESET is released, Tr1 is turned ON and Tr2 turned OFF. Ccp 2 is charged from Ccp 2 via Di1. (2) Tr1 is turned OFF, Tr2 is turned ON, and Ccp 1 is charged from Ccp 2 via Di2. .com (3) When the voltage difference between VM and VH (Ccp A pin voltage = charge pump voltage) reaches VDD or higher, operation halts (steady state). Actual operation (1) (4) (5) Ccp 1 charge is used at fchop switching and the VH potential drops. Charges up by (1) and (2) above.
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*
Output switching Initial charging Steady state
VH VM (1) (2) (3) t (4) (5) (4) (5)
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TB62206FG
Charge Pump Rise Time
Ccp 1 voltage
VDD + VM VM + (VDD x 90%)
VM
5V STANDBY 0V tONG 50%
tONG:
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Delay time taken for capacitor Ccp 2 (charging capacitor) to fill up Ccp 1 (storing capacitor) to VM + VDD after STANDBY is released. The internal IC cannot drive the gates correctly until the voltage of Ccp 1 reaches VM + VDD. Be sure to wait for tONG or longer before driving the motors. .com Basically, the larger the Ccp 1 capacitance, the smaller the voltage fluctuation, though the initial charge up time is longer. The smaller the Ccp 1 capacitance, the shorter the initial charge-up time but the voltage fluctuation is larger. Depending on the combination of capacitors (especially with small capacitance), voltage may not be sufficiently boosted. When the voltage does not increase sufficiently, output DMOS RON turns lower than the normal, and it raises the temperature. Thus, use the capacitors under the capacitor combination conditions (Ccp 1 = 0.22 F, Ccp 2 = 0.022 F) recommended by Toshiba.
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TB62206FG
External Capacitor for Charge Pump
When driving the stepping motor with VDD = 5 V, fchop = 150 kHz, L = 10 mH under the conditions of VM = 13 V and 1.5 A, the logical values for Ccp 1 and Ccp 2 are as shown in the graph below:
Ccp 1 - Ccp 2
0.05 0.045 0.04 Applicable range
(F) Ccp 2 capacitance
0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Recommended value
Ccp 1 capacitance
(F)
Choose Ccp 1 and Ccp 2 to be combined from the above applicable range. We recommend Ccp 1:Ccp 2 at 10:1 or more. (if our recommended values (Ccp = 0.22 F, Ccp 2 = 0.02 F) are used, the drive conditions in the specification sheet are satisfied. (there is no capacitor temperature characteristic as a condition.)
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When setting the constants, make sure that the charge pump voltage is not below the specified value and set the constants with a margin (the larger Ccp 1 and Ccp 2, the more the margin).
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TB62206FG
Driving Mode
2-Phase Excitation Mode 2-Phase Excitation
Phase B
Phase A
100 [%] Phase B
0
Phase A
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-100
STEP
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2-Phase Excitation
100
IA (%)
0
100
IB
(%)
Note: 2-phase excitation has a large load change due to motor induced electromotive force. If a mode in which the current attenuation capability (current control capability) is small is used, current increase due to induced electromotive force may not be suppressed.
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TB62206FG
1-2 Phase Excitation
ENABLE B ENABLE A
Phase B Phase A 100 [%] Phase B
Phase A
0
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-100
STEP
1-2 Phase Excitation (typ.A)
100
IA (%)
0
100
IB
(%)
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TB62206FG
Recommended Application Circuit
The values for the respective devices are all recommended values. For values under each input condition, see the above-mentioned recommended operating conditions.
Rosc = 3.6 k CR Cosc = 560 pF VDD
Vref A Vref B VM RRS A A A B B RRS B RRS A 0.66 Vref AB 3V SGND 1 F
M
Stepping motor RRS B 0.66
FIN PGND 5V 0V 5V 0V 5V 0V 5V 0V ENABLE A EANBLE B PHASE A PHASE B TORQUE 5V 0V FIN SGND
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STANDBY
5V 0V
5V SGND
10 F
Ccp A Ccp B
Ccp C
Ccp 2 Ccp 1 0.22 F 0.01 F SGND
24 V 100 F SGND
Note: Adding bypass capacitors is recommended. Make sure that GND wiring has only one contact point, and to design the pattern that allows the heat radiation. To control setting pins in each mode by SW, make sure to pull down or pull up them to avoid high impedance. To input the data, see the section on the recommended input data.
The IC may be destroyed due to short circuit between output pins, an output pin and the VDD pin, or an output pin and the GND pin. Design an output line, VDD (VM) line and GND line with great care. Also a low-withstand-voltage device may be destroyed when mounted in the wrong orientation, which causes high-withstanding voltage to be applied to the device.
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TB62206FG
Package Dimensions
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Weight: 0.79 g (typ.)
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TB62206FG
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RESTRICTIONS ON PRODUCT USE
.com * The information contained herein is subject to change without notice.
030619EBA
* The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations.
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