View IT7230AFN_37964.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IT7230AFN / IT7230BFN / IT7231FN Single Electrode Cap Sensor Controller Preliminary Specification V0.4.3 (For B Version)
ITE TECH. INC.
www..com
This specification is subject to Change without notice. It is provided "AS IS" and for reference only. For purchasing information, please contact the nearest ITE TECH sales representatives.
Please note that the IT7230AFN/IT7230BFN/IT7231FN V0.4.3 is applicable only to B version.
www..com
Copyright 2009 ITE Tech. Inc. This is a Preliminary document release. All specifications are subject to change without notice. The material contained in this document supersedes all previous material issued for the products herein referenced. Please contact ITE Tech. Inc. for the latest document(s). All sales are subject to ITE's Standard Terms and Conditions, a copy of which is included in the back of this document. ITE, IT7230AFN/IT7230BFN/IT7231FN is a trademark of ITE Tech. Inc. All other trademarks are claimed by their respective owners. All specifications are subject to change without notice. Additional copies of this manual or other ITE literature may be obtained from: ITE Tech. Inc. Marketing Department 7F, No.233-1, Baociao Rd., Sindian City, Taipei County 23145, Taiwan, ROC Tel: Fax: 886-2-29126889 886-2-2910-2551, 886-2-2910-2552
If you have any marketing or sales questions, please contact: P.Y. Chang, at ITE Taiwan: E-mail: p.y.chang@ite.com.tw, Tel: 886-2-29126889 X6052, Fax: 886-2-29102551 You may also find the local sales representative nearest you on the ITE web site. To find out more about ITE, visit our World Wide Web at: http://www.ite.com.tw Or e-mail itesupport@ite.com.tw for more product information/services
www..com
www..com
Revision History
Revision History
Section 12 Revision Top Marking Information Added CODE NO. on the top marking. Page No. 29
www..com
A
www..com
Contents
CONTENTS
1. Features................................................................................................................................................... 1 2. General Description.................................................................................................................................. 3 3. Block Diagram.......................................................................................................................................... 5 4. Pin Configuration...................................................................................................................................... 7 5. Pin Description ....................................................................................................................................... 13 6. Analog Performance............................................................................................................................... 15 6.1 Test Conditions............................................................................................................................ 15 7. Serial Interface ....................................................................................................................................... 17 7.1 Overview ..................................................................................................................................... 17 7.2 I2C- Compatible Interface ............................................................................................................. 17 7.2.1 Device Address ............................................................................................................... 17 7.2.2 Data Transfer................................................................................................................... 17 7.2.3 Timeouts.......................................................................................................................... 18 7.3 SPI- Compatible Interface ............................................................................................................ 18 7.3.1 Device Address ............................................................................................................... 19 7.3.2 Data Transfer................................................................................................................... 19 8. DC Characteristics ................................................................................................................................. 21 9. AC Characteristics.................................................................................................................................. 23 10. Package Information............................................................................................................................... 25 11. Ordering Information............................................................................................................................... 27 12. Top Marking Information......................................................................................................................... 29
FIGURES
Figure 7-1. Example of I C Timing for Single Register Write Operation......................................................... 18 Figure 7-2. Example of I C Timing for Single Register Read Operation ........................................................ 18 Figure 7-3. Example of SPI Timing for Single Register Write Operation........................................................ 19 Figure 7-4. Example of SPI Timing for Burst Register Write Operation ......................................................... 19 Figure 7-5. Example of SPI Timing for Single Register Read Operation........................................................ 20 Figure 7-6. Example of SPI Timing for Burst Register Read Operation ......................................................... 20 Figure 15-1. Definition of Timing for I C Interface ......................................................................................... 23 Figure 15-2. Definition of Timing for SPI Interface ........................................................................................ 23
2 2 2
TABLES
Table 4-1. IT7230AFN Pins Listed in Numeric Order (40-pin QFN)................................................................. 8 Table 4-2. IT7230AFN Pins Listed in Alphabetical Order (40-pin QFN)........................................................... 8 Table 4-3. IT7230BFN Pins Listed in Numeric Order (24-pin QFN)............................................................... 10 Table 4-4. IT7230BFN Pins Listed in Alphabetical Order (24-pin QFN)......................................................... 10 Table 4-5. IT7231FN Pins Listed in Numeric Order (40-pin QFN) ................................................................. 12 Table 4-6. IT7231FN Pins Listed in Alphabetical Order (40-pin QFN) ........................................................... 12 www..com
www.ite.com.tw
i
IT7230AFN/7230BFN/7231FN V0.4.3
IT7230AFN/7230BFN/7231FN (For B Version)
Table 5-1. Pin Description of Capactiance Sensor Related Pins ................................................................... 13 Table 5-2. Pin Descriptions of General Purpose Input/Output....................................................................... 13 Table 5-3. Pin Descriptions of I C Interface (for IT7230AFN/IT7230BFN) ..................................................... 13 Table 5-4. Pin Descriptions of SPI Interface (for IT7231FN) ......................................................................... 13 Table 5-5. Pin Descriptions of Sensor Detected Pins ................................................................................... 14 Table 5-6. Pin Descriptions of Power/Ground Signals .................................................................................. 14 Table 6-1. Analog Performance ................................................................................................................... 15 Table 7-1. IT7230 I C Device Address ......................................................................................................... 17 Table 15-1. I C AC Characteristic ................................................................................................................ 23 Table 15-2. SPI AC Characteristic ............................................................................................................... 24
2 2 2
www..com
www.ite.com.tw
ii
IT7230AFN/7230BFN/7231FN V0.4.3
Features
1. Features
Programmable Capacitance-to-Digital Converter(CDC) - Maximum 13 capacitance sensor inputs - 9 ms update rate, all 13 sensor inputs - No external RC components required - Automatic conversion sequencer On-chip Automatic Calibration Logic - Automatic calibration & compensation for environmental changes - Automatic adaptive threshold and sensitivity levels On-chip RAM to Store Calibration Data - Hardware initialization of SRAM - Host can access SRAM freely at any time Supports 1 Interrupt Output and 2 Touch Detection Outputs Supports a Maximum of 13 General Purpose Input/Output (GPIO) Supports a Maximum of 15 Current-Control Output for LED Dimming Function Supports Dynamic Power Saving Mode - Provides three operational modes: active, idle and sleep modes - Provides host special commands to switch between these modes Hardware Slider Function - Provides two 32-level hardware auto slider function I C Compatible Interface (IT7230AFN/BFN) 2 - Compliant to I C specification v2.1 - Supports slave device only - Supports standard and fast modes - 7-bit device addressing modes - Supports 2 address select pins to configure the device address selection (IT7230AFN only) SPI Compatible Interface (IT7231FN) - Compliant to 4-wire serial peripheral interface (SPI) Operation Power - One power source 2.5V ~ 3.6V - Provides one internal power regulator for core power generation Low Power Consumption - Active mode: 550 uA - Idle mode: 120 uA - Sleep mode: 30 uA Package - 40-pin QFN - 24-pin QFN RoHS Compliant (100% Green Available)
2
www..com
www.ite.com.tw Specifications subject to Change without Notice
1
IT7230AFN/7230BFN/7231FN V0.4.3 ITPM-PN-200962 7/15/2009
IT7230AFN/7230BFN/7231FN (For B Version)
This page is intentionally left blank.
www..com
www.ite.com.tw
2
IT7230AFN/7230BFN/7231FN V0.4.3
General Description
2. General Description
The IT7230/7231 is one programmable controller with capacitance sensors which is used to implement functions such as buttons, scroll bars, and wheels. One single electrode capacitance-to-digital converter (CDC) is integrated into this controller. The IT7230/7231 also provides a post-processing with CDC, and it can automatically calibrate and compensate the front-end CDC values for environmental changes. It also modifies the threshold and sensitivity levels automatically. The chip supports one interrupt output indicated that the CDC value over the user programming sensitivity level. It also supports two touch detection outputs indicated that the two corresponding sensor inputs over the default sensitivity level. The default sensitivity level can be automatically setting by the internal environment detection circuit without any software programming. So the user can use the two outputs to control the power-on or system reset function. The IT7230/7231 supports one I C compatible interface to communicate with the host. It also supports two address select pins to specify the device ID addresses. Through this interface, the host can program the internal controlled registers to configure this chip to meet users' requirements. Furthermore, GPIO and current-control functions are supported to indicate the specific status or LED dimming by the user's definition. The IT7230/7231 is available in 40-pad, 5 mm x 5 mm QFN package type and 24-pad, 4 mm x 4 mm QFN package type. And it operates with only one 2.5V~3.6V power supply.
2
www..com
www.ite.com.tw
3
IT7230AFN/7230BFN/7231FN V0.4.3
IT7230AFN/7230BFN/7231FN (For B Version)
This page is intentionally left blank.
www..com
www.ite.com.tw
4
IT7230AFN/7230BFN/7231FN V0.4.3
Block Diagram
3. Block Diagram
Host
I2C /SPI Slave I/F
Control . Reg File
. Auto Cal. Eng. . Cal RAM 16-bit - ADC Analog Mux Cap Sensor Inputs
INT
Int. Control
THD0 * THD1 Power -On Reset
Direct Touch Detect
Current Control LED
Clock Gen.
GPIO
GPI/OS
* IT7230AFN/IT7231FN only
www..com
www.ite.com.tw
5
IT7230AFN/7230BFN/7231FN V0.4.3
IT7230AFN/7230BFN/7231FN (For B Version)
This page is intentionally left blank.
www..com
www.ite.com.tw
6
IT7230AFN/7230BFN/7231FN V0.4.3
Pin Configuration
4. Pin Configuration
GPIO 2 GPIO 3 GPIO 0 GPIO 1 GPIO 4 31 30 29 28 27 GPIO 5 GPIO 6 GPIO 7 INT# SDA SCLK ADD0 ADD1 GPIO 8 GPIO 9 26 25 24 23 22 11 CIN11 12 CIN12 13 VSHILD 14 VBIAS 15 AVSS 16 AVCC 17 GPIO12 18 GPIO11 19 GPIO10 20 DVCC 21 DVSS 32 THD0 THD1 38 CIN 0
40 CIN 1 CIN 2 CIN 3 CIN 4 CIN 5 CIN 6 CIN 7 CIN 8 CIN 9 CIN10 1 2 3 4 5 6 7 8 9 10
39
37
NC
36
35
34
33
IT7230AFN QFN-40
www..com
www.ite.com.tw
7
IT7230AFN/7230BFN/7231FN V0.4.3
IT7230AFN/7230BFN/7231FN (For B Version)
Table 4-1. IT7230AFN Pins Listed in Numeric Order (40-pin QFN)
Pin 1 2 3 4 5 6 7 8 9 10 Signal CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 CIN10 Pin 11 12 13 14 15 16 17 18 19 20 Signal CIN11 CIN12 VSHILD VBIAS AVSS AVCC GPIO12 GPIO11 GPIO10 DVCC Pin 21 22 23 24 25 26 27 28 29 30 Signal GPIO9 GPIO8 ADD1 ADD0 SCLK SDA INT# GPIO7 GPIO6 GPIO5 Pin 31 32 33 34 35 36 37 38 39 40 Signal GPIO4 DVSS GPIO3 GPIO2 GPIO1 GPIO0 NC THD1 THD0 CIN0
Table 4-2. IT7230AFN Pins Listed in Alphabetical Order (40-pin QFN)
Signal ADD0 ADD1 AVCC AVSS CIN0 CIN1 CIN2 CIN3 CIN4 CIN5 Pin 24 23 16 15 40 1 2 3 4 5 Signal CIN6 CIN7 CIN8 CIN9 CIN10 CIN11 CIN12 DVCC DVSS GPIO0 Pin 6 7 8 9 10 11 12 20 32 36 Signal GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 Pin 35 34 33 31 30 29 28 22 21 19 Signal GPIO11 GPIO12 INT# NC SCLK SDA THD0 THD1 VBIAS VSHILD Pin 18 17 27 37 25 26 39 38 14 13
www..com
www.ite.com.tw
8
IT7230AFN/7230BFN/7231FN V0.4.3
Pin Configuration
GPIO 2
GPIO 3
24 CIN 1 1
23
22
21
20
19 18 GPIO 7
CIN 2 CIN 3 CIN 4 CIN 7
GPIO 4 17 16 15 14 13
DVSS
THD1
NC
2 3
INT# SDA
IT7230BFN QFN-24
4 5
SCLK GPIO 9
CIN 9
6 7 8 9 10 11 12
DVCC
VSHILD
www..com
www.ite.com.tw
9
IT7230AFN/7230BFN/7231FN V0.4.3
GPIO11
CIN11
VBIAS
AVSS
AVCC
IT7230AFN/7230BFN/7231FN (For B Version)
Table 4-3. IT7230BFN Pins Listed in Numeric Order (24-pin QFN)
Pin 1 2 3 4 5 6 Signal
CIN1 CIN2 CIN3 CIN4 CIN7 CIN9
Pin 7 8 9 10 11 12
Signal
CIN11 VSHILD VBIAS AVSS AVCC GPIO11
Pin 13 14 15 16 17 18
Signal
DVCC GPIO9 SCLK SDA INT# GPIO7
Pin 19 20 21 22 23 24
Signal
GPIO4 DVSS GPIO3 GPIO2 NC THD1
Table 4-4. IT7230BFN Pins Listed in Alphabetical Order (24-pin QFN)
Signal
AVCC AVSS CIN1 CIN2 CIN3 CIN4
Pin 11 10 1 2 3 4
Signal
CIN7 CIN9 CIN11 DVCC DVSS GPIO2
Pin 5 6 7 13 20 22
Signal
GPIO3 GPIO4 GPIO7 GPIO9 GPIO11 INT#
Pin 21 19 18 14 12 17
Signal
NC SCLK SDA THD1 VBIAS VSHILD
Pin 23 15 16 24 9 8
www..com
www.ite.com.tw
10
IT7230AFN/7230BFN/7231FN V0.4.3
Pin Configuration
GPIO 2
GPIO 3
GPIO 0
GPIO 1
40 CIN 1 CIN 2 CIN 3 CIN 4 CIN 5 CIN 6 CIN 7 CIN 8 CIN 9 CIN10 1 2 3 4 5 6 7 8 9 10 11 CIN11
39
38
37
36
35
34
33
32
31 30 29 28 27 GPIO 5 GPIO 6 GPIO 7 INT# CS_N SCLK SDI SDO GPIO 8 GPIO 9
IT7231FN QFN-40
GPIO 4 26 25 24 23 22 20 DVCC 21
12 CIN12
13 VSHILD
14 VBIAS
15 AVSS
16 AVCC
17 GPIO12
18 GPIO11
19 GPIO10
www..com
www.ite.com.tw
11
DVSS
THD0
THD1
CIN 0
NC
IT7230AFN/7230BFN/7231FN V0.4.3
IT7230AFN/7230BFN/7231FN (For B Version)
Table 4-5. IT7231FN Pins Listed in Numeric Order (40-pin QFN)
Pin 1 2 3 4 5 6 7 8 9 10 Signal
CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 CIN10
Pin 11 12 13 14 15 16 17 18 19 20
Signal
CIN11 CIN12 VSHILD VBIAS AVSS AVCC GPIO12 GPIO11 GPIO10 DVCC
Pin 21 22 23 24 25 26 27 28 29 30
Signal
GPIO9 GPIO8 SDO SDI SCLK CS_N INT# GPIO7 GPIO6 GPIO5
Pin 31 32 33 34 35 36 37 38 39 40
Signal
GPIO4 DVSS GPIO3 GPIO2 GPIO1 GPIO0 NC THD1 THD0 CIN0
Table 4-6. IT7231FN Pins Listed in Alphabetical Order (40-pin QFN)
Signal
AVCC AVSS CIN0 CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7
Pin 16 15 40 1 2 3 4 5 6 7
Signal
CIN8 CIN9 CIN10 CIN11 CIN12 CS_N DVCC DVSS GPIO0 GPIO1
Pin 8 9 10 11 12 26 20 32 36 35
Signal
GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11
Pin 34 33 31 30 29 28 22 21 19 18
Signal
GPIO12 INT# NC SCLK SDI SDO THD0 THD1 VBIAS VSHILD
Pin 17 27 37 25 24 23 39 38 14 13
www..com
www.ite.com.tw
12
IT7230AFN/7230BFN/7231FN V0.4.3
Pin Description
5. Pin Description
Table 5-1. Pin Description of Capactiance Sensor Related Pins
Pin(s) No. IT7230AFN /7231FN 40, 1-12 IT7230 BFN 1-7 Signal IT7230AFN /7231FN CIN0-12 IT7230 BFN CIN1-4 CIN7,9 CIN11 Attribute Description
Capacitance Sensor Related Pins (Analog I/F)
AI
14
9
VBIAS
AI
13
8
VSHILD
AO
Capacitance Sensor Input Channels These inputs are used to sense the capacitance values. They can be companioned with capacitance sensors to implement functions such as buttons, scroll bars, and wheels. Bias Voltage This pin must be connected to ground with one 0.1uF capacitor to supply one bias voltage. CDC Active Shield Output This pin must be connected to the external plane.
Table 5-2. Pin Descriptions of General Purpose Input/Output
Pin(s) No. IT7230AFN /7231FN 36-33, 31-28, 22-21, 19-17 IT7230 BFN 22-21, 19-18, 14,12 Signal IT7230AFN /7231FN GPIO0-12 IT7230 BFN GPIO2-4 GPIO7 GPIO9 GPIO11 Attribute Description
General Purpose Input/Output (GPIO) (3.3V CMOS I/F, 5V tolerant)
IOK16
General Purpose Input/Output These pins can be used to indicate the corresponding functions of the capacitance sensors are active.
Table 5-3. Pin Descriptions of I C Interface (for IT7230AFN/IT7230BFN)
Pin(s) No.
2
2
Signal IT7230AFN SCLK SDA ADD1-0 IT7230 BFN
Attribute
Description
I C Interface (3.3V CMOS I/F, 5V tolerant)
IT7230AFN 25 26 24-23 IT7230 BFN 15 16 -
-
IOK2 IOK2 IK
I C Clock 2 I C Data 2 I C Address Select Bit 1-0 The bits are used to specify the decoded address of this chip.
2
Table 5-4. Pin Descriptions of SPI Interface (for IT7231FN)
Pin(s) No. 25 26 23 24 Signal SCLK CS_N SDO SDI Attribute IK IK O8 IK SPI Clock SPI Chip Select SPI Output Data SPI Input Data Description
SPI Interface (3.3V CMOS I/F, 5V tolerant)
www..com
www.ite.com.tw
13
IT7230AFN/7230BFN/7231FN V0.4.3
IT7230AFN/7230BFN/7231FN (For B Version)
Table 5-5. Pin Descriptions of Sensor Detected Pins
Pin(s) No. IT7230AFN /7231FN 27 IT7230 BFN 17 Signal IT7230AFN /7231FN INT# IT7230 BFN O8 General Interrupt Output When the CDC value is over the threshold value of the sensor input and the interrupt enable bit is active, the pin will change the state to low. Touch Detection Output 1-0 These pins are multi-function, and are selected by the configuration register. The default function of these pins is touch detection output. When the CDC value is over the default threshold value of the corresponding sensor input, the pin will change the state to high. Attribute Description
Sensor Detected Pins (3.3V CMOS I/F)
39-38
24
THD1-0
THD1
O8
Table 5-6. Pin Descriptions of Power/Ground Signals
Pin(s) No. Signal IT7230AFN /7231FN DVSS DVCC AVSS AVCC NC IT7230 BFN I I I I IK Digital Ground for Digital Component Digital VCC (3.3V) for Digital Component Analog Ground for Analog Component Analog VCC (3.3V) for Analog Component Not Connected The pin can be floating. Attribute Description
Power Ground Signals
IT7230AFN /7231FN 32 20 15 16 37 IT7230 BFN 20 13 10 11 23
Notes: I/O cell types are described below: I: AI: IK: AO: O8: IOK2: IOK16: Input PAD. Analog Input PAD. Schmitt Trigger Input PAD. Analog Output PAD. 8 mA Output PAD. 2 mA Bidirectional PAD with Schmitt Trigger Input PAD. 16 mA Bidirectional PAD with Schmitt Trigger Input PAD.
www..com
www.ite.com.tw
14
IT7230AFN/7230BFN/7231FN V0.4.3
Analog Performance
6. Analog Performance
6.1 Test Conditions
The calibration engine registers set the calibration configuration. AVCC = 3.3V AVSS = 0V Ta=25 Internal ADCCLK = 250Khz
Table 6-1. Analog Performance Parameter ADC Over-sampling Rate, OSR Update-rate, Tperiod OSR=64,128,256 64 13*64*3*(1/ADCCLK) 13*128*3*(1/ADCCLK) 13*256*3*(1/ADCCLK) Output Noise, peak-to-peak Resolution ADC Clock Capacitance Cstray, 7bits resolution CIN 0-12, input range Power Full Power Mode Idle Mode Sleep Mode Full power mode Note 2 Note 3 550 120 30 800 150 40 uA uA uA +/- 20%, note 1 +/- 20%, note 1 0 20 +/-8 PF PF OSR=64,128,256 No-missing code 16 250K 12,7,3 LSB bits Hz 256 clocks second Test Conditions Min. Typ. Max. Unit
Notes: 1. Total unadjusted capacitance tolerance is +/- 20%. 2. LDO low power mode, power save timeout = 800ms, decimation rate = 64 3. PDCR = 0x000F.
www..com
www.ite.com.tw
15
IT7230AFN/7230BFN/7231FN V0.4.3
IT7230AFN/7230BFN/7231FN (For B Version)
This page is intentionally left blank.
www..com
www.ite.com.tw
16
IT7230AFN/7230BFN/7231FN V0.4.3
Serial Interface
7. Serial Interface
7.1 Overview
2
The IT7230 is available with an I C -compatible interface. The IT7231 is available with an SPI-compatible interface. Both IT7230 and IT7231's serial interfaces support 4 transfer types - single write, burst write, single read, and burst read. 7.2 I2C- Compatible Interface
2
The IT7230 supports 2-wire I C serial interface protocol of the industry standard. It is also compatible with System Management Bus(SMBus) protocol. 7.2.1 Device Address
IT7230 supports 4 different 7-bit device addresses which are controlled by the ADD0 and ADD1 pins. The related device addresses are listed below. Table 7-1. IT7230 I C Device Address ADD1 0 0 1 1 ADD0 0 1 0 1 I2C Address 1000 110 0110 101 1101 110 0010 111
2
7.2.2 Data Transfer 2 Data is transferred over the I C bus in 8-bit address and 16-bit data. IT7230 supports the following 4 transfer types. The related protocol and timing diagrams are shown below. Single Write
S
7-BIT DEVICE ADDRESS
W ACK
REGISTER ADDRESS[7:0]
ACK
WRITE DATA LOW [7:0]
ACK
WRITE DATA HIGH [15:8]
ACK
P
Burst Write
Address = n S
7-BIT DEVICE ADDRESS
W
ACK
REGISTER ADDRESS[7:0]
ACK
WRITE DATA LOW [7:0]
ACK
WRITE DATA HIGH [15:8]
ACK
Address = n+1
WRITE DATA LOW [7:0] ACK WRITE DATA HIGH [15:8] ACK WRITE DATA LOW [7:0]
Address = n+2
ACK WRITE DATA HIGH [15:8] ACK ACK
P
Single Read
S
7-BIT DEVICE ADDRESS
W
ACK
REGISTER ADDRESS[7:0]
ACK
SR
7-BIT DEVICE ADDRESS
R
ACK
READ DATA LOW [7:0]
ACK
READ DATA HIGH [15:8]
ACK
P
www..com
www.ite.com.tw
17
IT7230AFN/7230BFN/7231FN V0.4.3
IT7230AFN/7230BFN/7231FN (For B Version)
Burst Read
S
7-BIT DEVICE ADDRESS
W
ACK
REGISTER ADDRESS[7:0]
ACK
SR
7-BIT DEVICE ADDRESS
R
ACK
Address = n
READ DATA LOW [7:0] ACK READ DATA HIGH [15:8] ACK READ DATA LOW [7:0]
Address = n+1
ACK READ DATA HIGH [15:8] ACK ACK
P
S P SR
START BIT STOP BIT REPEATED START BIT
ACK ACK
ACKNOWLEDGE BIT NO ACKNOWLEDGE BIT
OUTPUT FROM HOST OUTPUT FROM IT7230
Figure 7-1. Example of I2C Timing for Single Register Write Operation
START DEVICE ADDRESS SDA
DEV DEV DEV DEV DEV DEV DEV R/W ACK A6 A5 A4 A3 A2 A1 A0 A7 A6 A5 A0 ACK D7 D6 D5 D0 ACK D15 D14 D13 D8 ACK
STOP REGISTER ADDRESS [7:0] REGISTER DATA [7:0] REGISTER DATA [15:8]
SCL
1 2 3 4 5 6 7 8 9 10 11 12 17 18 19 20 21 26 27 28 29 30 35 36 37
Figure 7-2. Example of I C Timing for Single Register Read Operation
START DEVICE ADDRESS SDA
DEV DEV DEV DEV DEV DEV DEV A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A0 ACK DEV DEV DEV DEV A6 A5 A4 A3 DEV DEV DEV A2 A1 A0 R/W ACK
2
REGISTER ADDRESS [7:0]
REPEATED START
DEVICE ADDRESS
SCL
1 2 3 4 5 6 7 8 9 10 11 12 17 18 19 20 21 22 23 24 25 26 27
STOP REGISTER DATA [7:0] SDA
D7 D6 D5 D0 ACK
REGISTER DATA [15:8]
D15 D14 D13 D8 ACK
SCL
28
29
30
35
36
37
38
39
44
45
46
7.2.3 Timeouts 2 2 The IT7230 I C interface supports a timeout reset mechanism to prevent I C bus halt due to any abnormal 2 transaction. If SCL is low over 4ms, the I C interface will reset itself and be ready to receive a new command. 7.3 SPI- Compatible Interface The IT7231 supports 4-wire serial peripheral interface (SPI) protocol of the industry standard. It has a data input pin (SDI) to input www..com data from host to IT7231, a data output pin (SDO) to output data from IT7231 to host, and a clock input pin (SCLK) to support a reference clock for inputting and outputting data. A chip select (CS) is used to enable or disable the IT7231's serial interface. IT7231 supports both SPI mode 0 and mode 3.
www.ite.com.tw
18
IT7230AFN/7230BFN/7231FN V0.4.3
Serial Interface
7.3.1 Device Address To start the transfer correctly, an appropriate 3-bit device address must be sent first. If users want to program on-chip OTP for initial parameter setting, the device address must be set to 3'b010. Otherwise, the registers of IT7231 should be distributed into 2 pages, page 0 and 1. To access registers of page 0, device address must be set to 3'b000 and 3'b001 is bound to page 1. 7.3.2 Data Transfer After the device address, a 1-bit read/write direction bit is used to indicate the direction of the data transfer. This read/write bit is followed by 12-bit addresses necessary to be sent. But address bit [11:8] must be set to 4'b0000 and only bit [7:0] is useful for data transfer. If the value of read/write direction bit is 0(write), there should be 16-bit data sent from host after the address bits. On the contrary, if the read/write direction bit is 1(read), the read data is sent out from IT7231 through SDO pin. The related protocol and timing diagrams are shown below. Figure 7-3. Example of SPI Timing for Single Register Write Operation
TARGET ID R/W = 000 or 001 CS_N 12-BIT REGISTER ADDRESS 16-BIT DATA
SCLK
1
2
3
4
5
6
7
8
9
14
15
16
17
18
19
30
31
32
SDI
CW 15
CW 14
CW 13
CW 12
CW 11
CW 10
CW 9
CW 8
CW 7
CW 2
CW 1
CW 0
D15
D14
D13
D2
D1
D0
must be 4'b000
Figure 7-4. Example of SPI Timing for Burst Register Write Operation
START CS_N TARGET ID R/W = 000 or 001 12-BIT REGISTER ADDRESS 16-BIT DATA
SCLK
1
2
3
4
5
6
7
8
9
14
15
16
17
18
19
30
31
32
SDI
CW 15
CW 14
CW 13
CW 12
CW 11
CW 10
CW 9
CW 8
CW 7
CW 2
CW 1
CW 0
D15
D14
D13
D2
D1
D0
address = n must be 4'b000
16-BIT DATA CS_N
16-BIT DATA
STOP
SCLK
www..com
SDI
33
34
35
46
47
48
49
50
51
62
63
64
D15
D14
D13
D2
D1
D0
D15
D14
D13
D2
D1
D0
address = n + 1
address = n + 2
www.ite.com.tw
19
IT7230AFN/7230BFN/7231FN V0.4.3
IT7230AFN/7230BFN/7231FN (For B Version)
Figure 7-5. Example of SPI Timing for Single Register Read Operation
TARGET ID R/W = 000 or 001 CS_N 12-BIT REGISTER ADDRESS 16-BIT DATA
SCLK
1
2
3
4
5
6
7
8
9
14
15
16
17
18
19
30
31
32
SDI
CW 15
CW 14
CW 13
CW 12
CW 11
CW 10
CW 9
CW 8
CW 7
CW 2
CW 1
CW 0
XX
XX
XX
XX
XX
XX
must be 4'b000 SDO XXX
D15 D14 D13 D2 D1 D0
Figure 7-6. Example of SPI Timing for Burst Register Read Operation
START CS_N TARGET ID R/W = 000 or 001 12-BIT REGISTER ADDRESS 16-BIT DATA
SCLK
1
2
3
4
5
6
7
8
9
14
15
16
17
18
19
30
31
32
SDI
CW 15
CW 14
CW 13
CW 12
CW 11
CW 10
CW 9
CW 8
CW 7
CW 2
CW 1
CW 0
XX
XX
XX
XX
XX
XX
must be 4'b000 SDO XXX
D15 D14 D13 D2 D1 D0
address = n 16-BIT DATA CS_N 16-BIT DATA STOP
SCLK
33
34
35
46
47
48
49
50
51
62
63
64
SDI
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
SDO
D15
D14
D13
D2
D1
D0
D15
D14
D13
D2
D1
D0
address = n+1
address = n+2
www..com
www.ite.com.tw
20
IT7230AFN/7230BFN/7231FN V0.4.3
DC Characteristics
8. DC Characteristics
Absolute Maximum Ratings Power Supply (DVCC) Power Supply (AVCC) Input Voltage Output Voltage Storage Temperature -0.3V to 3.6V -0.3V to 3.6V -0.3V to DVCC + 0.3V -0.3V to DVCC + 0.3V -40C to 125C *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied, and exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics (Operation Condition Vcc=3.0V~3.6V, Tj=0C~115C) Symbol VIL VIH VtVt+ VOL VOH Rl IIL IOZ CIN COUT CBID Parameter Input Low Voltage Input High Voltage Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage Output Low Voltage Output High Voltage Input Pull-up Resistance Input Leakage Current Tri-state Leakage Current Input Capacity Output Capacity Bi-directional Buffer Capacity Condition CMOS CMOS CMOS CMOS IOL=2mA IOH=2mA VIL=0V or VIH=DVCC no pull-up Min. 0.7*DVCC 2.4 -1 -1 Typ. 1.80 2.10 75 10 10 10 Max. 0.3*DVCC 0.4 1 1 Unit V V V V V V K uA mA pF pF pF
www..com
www.ite.com.tw
21
IT7230AFN/7230BFN/7231FN V0.4.3
IT7230AFN/7230BFN/7231FN (For B Version)
This page is intentionally left blank.
www..com
www.ite.com.tw
22
IT7230AFN/7230BFN/7231FN V0.4.3
AC Characteristics
9. AC Characteristics
Figure 9-1. Definition of Timing for I C Interface
2
Table 9-1. I C AC Characteristic Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb VnL VnH ttimeout Parameter SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) Cumulative SCL low timeout limit Min. 1 0.6 1.3 0.6 0.6 0 100 20+0.1Cb 20+0.1Cb 0.6 1.3 0.1VDD 0.2VDD 3 Max. 400 0.9 300 300 400 5 Unit kHz us us us us us ns ns ns us us pF V V ms
2
Figure 9-2. Definition of Timing for SPI Interface
www..com
www.ite.com.tw
23
IT7230AFN/7230BFN/7231FN V0.4.3
IT7230AFN/7230BFN/7231FN (For B Version)
CS_N tSTART tSTOP
SCLK
1 2 3 14 15 16 17 18 19 30 31 32
tsu twidth_h SDI
CW15 CW14 CW13
twidth_l
CW12
thd
CW2 CW1 CW0 XX XX XX XX XX XX
tacc SDO
D15 D14 D13 D2 D1 D0
Table 9-2. SPI AC Characteristic Symbol fSCLK tSTART tSTOP twidth_h twidth_l tSU tHD tacc Parameter SCKL clock frequency CS_N falling to SCLK rising edge SCLK rising to CS_N rising edge SCLK high pulse width SCLK low pulse width SDI to SCLK Setup time SDI to SCLK hold time SDO access time after SCLK falling edge Min. 0 10 10 20 20 10 10 Max. 5 20 Unit MHz ns ns ns ns ns ns ns
www..com
www.ite.com.tw
24
IT7230AFN/7230BFN/7231FN V0.4.3
Package Information
10. Package Information
QFN 40L Outline Dimensions unit: inches/mm
40 30 3 0
4 0
10 20 2 0 1 0
Symbol
Dimensions in inches Min. Nom. Max. 0.028 0.030 0.032 0.000 0.0008 0.002 0.008 REF 0.006 0.008 0.010 0.197BSC 0.126 0.130 0.134 0.197BSC 0.126 0.130 0.134 0.016 BSC 0.012 0.014 0.016 --0.003
Dimensions in mm Min. 0.70 0.00 0.15 Nom. 0.75 0.02 Max. 0.80 0.05
A A1 A3 b D D2 E E2 e L y
0.203 REF 0.20 0.25 5.00 BSC 3.20 3.30 3.40 5.00BSC 3.20 3.30 3.40 0.40 BSC 0.35 0.40 0.45 --0.08
Notes: 1. CONTROLLING DIMENSIONMILLIMETER 2. REFERENCE DOCUMENTJEDEC MO-220. DI-QFN40(5*5)v0
www..com
www.ite.com.tw
25
IT7230AFN/7230BFN/7231FN V0.4.3
IT7230AFN/7230BFN/7231FN (For B Version)
QFN 24L Outline Dimensions
unit: inches/mm
Symbol A A1 A2 A3 b D D2 E E2 e L y
Dimensions in inches Min. Nom. Max.
Dimensions in mm Min. Nom. 0.80 0.02 0.60 Max. 0.84 0.04 0.63 0.30 2.60 2.60 0.45 0.08
0.030 0.031 0.033 0.76 0.000 0.0008 0.0015 0.00 0.022 0.024 0.025 0.57 0.008 REF 0.007 0.010 0.012 0.157 BSC 0.098 0.100 0.102 0.157 BSC 0.098 0.100 0.102 0.020 BSC 0.012 0.014 0.016 --0.003 0.18
0.20 REF 0.25 4.00 BSC 2.50 2.55 4.00 BSC 2.50 2.55 0.50 BSC 0.35 0.40 ---
Notes: 1. CONTROLLING DIMENSIONMILLIMETER 2. REFERENCE DOCUMENTJEDEC MO-220.
www..com
DI-QFN24(4*4)v0
www.ite.com.tw
26
IT7230AFN/7230BFN/7231FN V0.4.3
Ordering Information
11. Ordering Information
Part No. IT7230AFN IT7230BFN IT7231FN Package QFN40 QFN24 QFN40 Code No. CCCC CCCC CCCC
Code No.: 0000 ~ FFFF Example: 1. IT7230AFN/BX--0001 2. IT7230BFN/BX--0005 3. IT7231FN/CX--0007 4. ......
www..com
www.ite.com.tw
27
IT7230AFN/7230BFN/7231FN V0.4.3
IT7230AFN/7230BFN/7231FN (For B Version)
This page is intentionally left blank.
www..com
www.ite.com.tw
28
IT7230AFN/7230BFN/7231FN V0.4.3
Top Marking Information
12. Top Marking Information
a. IT7230AFN (QFN40)
PART NO.
IT7230AFN
DATE CODE (The seventh week of the year2009) LOTID
0607-XXX
TRACKING CODE
XXXXXX CCCC CODE NO.
b. IT7230BFN (QFN24)
PART NO.
IT7230BFN
DATE CODE (The seventh week of the year2009) LOTID
0607-XXX
TRACKING CODE
XXXXXX CCCC CODE NO.
c. IT7231FN (QFN40)
PART NO.
IT7231FN
DATE CODE (The seventh week of the year2009) LOTID
0607-XXX
TRACKING CODE
XXXXXX CCCC CODE NO.
www..com
www.ite.com.tw
29
IT7230AFN/7230BFN/7231FN V0.4.3
ITE TECH. INC. TERMS AND CONDITIONS OF SALE (Rev: 2005)
PARTIES ITE Tech. Inc. ("Seller") is a company headquartered in Taiwan, Republic of China, and incorporated under laws of Republic of China, Buyer is a company or an entity, purchasing product from ITE Tech. Inc..
0.
1.
ACCEPTANCE OF TERMS BUYER ACCEPTS THESE TERMS (i) BY WRITTEN ACCEPTANCE (BY PURCHASE ORDER OR OTHERWISE), OR (ii) BY FAILURE TO RETURN GOODS DESCRIBED ON THE FACE OF THE PACKING LIST WITHIN FIVE DAYS OF THEIR DELIVERY.
2.
Seller may at any time make substitutions for product ordered which do not materially and adversely affect overall performance with the then current specifications in the typical and intended use. Seller reserves the right to halt deliveries and shipments and alter specifications and prices without notice. Buyer shall verify that the literature and information is current before purchasing. 7. CANCELLATION The purchase contract may not be canceled by Buyer except with written consent by Seller and Buyer's payment of reasonable cancellation charges (including but not be limited to expenses already incurred for labor and material, overhead, commitments made by Seller, and a reasonable profit). INDEMNIFICATION Seller will, at its own expense, assist Buyer with technical support and information in connection with any claim that any parts as shipped by Seller under the purchase order infringe any valid and enforceable copyright, or trademark, provided however, that Buyer (i) gives immediate written notice to Seller, (ii) permits Seller to participate and to defend if Seller requests to do so, and (iii) gives Seller all needed information, assistance and authority. However, Seller will not be responsible for infringements resulting from anything not entirely manufactured by Seller, or from any combination with products, equipment, or materials not furnished by Seller. Seller will have no liability with respect to intellectual property matters arising out of products made to Buyer's specifications, code, or designs. Except as expressly stated in this Paragraph 8 or in another writing signed by an authorized officer, Seller makes no representations and/or warranties with respect to intellectual and/or industrial property and/or with respect to claims of infringement. Except as to claims Seller agrees in writing to defend, BUYER WILL INDEMNIFY, DEFEND AND HOLD HARMLESS SELLER FROM ALL CLAIMS, COSTS, LOSSES, AND DAMAGES (INCLUDING ATTORNEYS FEES) AGAINST AND/OR ARISING OUT OF GOODS SOLD AND/OR SHIPPED HEREUNDER.
DELIVERY (a) Delivery will be made Free Carrier (Incoterms), Seller's warehouse, ScienceBased Industrial Park, Hsinchu, Taiwan. (b) Title to the goods and the entire risk will pass to Buyer upon delivery to carrier. (c) Shipments are subject to availability. Seller shall make every reasonable effort to meet the date(s) quoted or acknowledged; and if Seller makes such effort, Seller will not be liable for any delays.
8.
3.
TERMS OF PAYMENT (a) Terms are as stated on Seller's quotation, or if none are stated, net thirty (30) days. Accounts past due will incur a monthly charge at the rate of one percent (1%) per month (or, if less, the maximum allowed by applicable law) to cover servicing costs. (b) Seller reserves the right to change credit terms at any time in its sole discretion. 4. LIMITED WARRANTY (a) Seller warrants that the goods sold will be free from defects in material and workmanship and comply with Seller's applicable published specifications for a period of ninety (90) days from the date of Seller's delivery. Within the warranty period and by obtaining a return number from Seller, Buyer may request replacement or repair for defective goods. (b) Goods or parts which have been subject to abuse (including without limitation repeated or extended exposure to conditions at or near the limits of applicable absolute ratings) misuse, accident, alteration, neglect, or unauthorized repair or improper application are not covered by any warranty. No warranty is made with respect to custom products or goods produced to Buyer's specifications (unless specifically stated in a writing signed by Seller). (c) No warranty is made with respect to goods used in devices intended for use in applications where failure to perform when properly used can reasonably be expected to result in significant injury (including, without limitation, navigation, aviation or nuclear equipment, or for surgical implant or to support or sustain life) and Buyer agrees to indemnify, defend, and hold harmless Seller from all claims, damages and liabilities arising out of any such uses. (d) This Paragraph 4 is the only warranty by Seller with respect to goods and may not be modified or amended except in writing signed by an authorized officer of Seller. (e) Buyer acknowledges and agrees that it is not relying on any applications, diagrams or circuits contained in any literature, and Buyer will test all parts and applications under extended field and laboratory conditions. Notwithstanding any cross-reference or any statements of compatibility, functionality, interchangeability, and the like, the goods may differ from similar goods from other vendors in performance, function or operation, and in areas not contained in the written specifications, or as to ranges and conditions outside such specifications; and Buyer agrees that there are no warranties and that Seller is not responsible for such things. (f) EXCEPT AS PROVIDED ABOVE, SELLER MAKES NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY; AND SELLER EXPRESSLY EXCLUDES AND DISCLAIMS ANY WARRANTY OR CONDITION OF MERCHANTABILITY OR FITNESS FOR PARTICULAR PURPOSE OR APPLICATION. LIMITATION OF LIABILITY (a) Seller will not be liable for any loss, damage or penalty resulting from causes beyond its reasonable control, including but not limited to delay by others, force majeure, acts of God, or labor conditions. In any such event, the date(s) for Seller's performance will be deemed extended for a period equal to any delay resulting. (b) THE LIABILITY OF SELLER ARISING OUT OF THE CONTRACT OR ANY GOODS SOLD WILL BE LIMITED TO REFUND OF THE PURCHASE PRICE OR REPLACEMENT OF PURCHASED GOODS (RETURNED TO SELLER FREIGHT PRE-PAID) OR, WITH SELLER'S PRIOR WRITTEN CONSENT, REPAIR OF PURCHASED GOODS. (c) Buyer will not return any goods without first obtaining a customer return order number. (d) AS A SEPARATE LIMITATION, IN NO EVENT WILL SELLER BE LIABLE FOR COSTS OF SUBSTITUTE GOODS; FOR ANY SPECIAL, CONSEQUENTIAL, INCIDENTAL OR INDIRECT DAMAGES; OR LOSS OF USE, OPPORTUNITY, MARKET POTENTIAL, AND/OR PROFIT ON ANY THEORY (CONTRACT, TORT, FROM THIRD PARTY CLAIMS OR OTHERWISE). THESE LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF ANY REMEDY. (e) No action against Seller, whether for breach, indemnification, contribution or otherwise, shall be commenced more than one year after the cause of action has accrued, or more than one year after either the Buyer, user or other person knew or with reasonable diligence should have known of the matter or of any claim of dissatisfaction or defect involved; and no such claim may be brought unless Seller has first been given commercially reasonable notice, a full written explanation of all pertinent details, and a good faith opportunity to resolve the matter. (f) BUYER EXPRESSLY AGREES TO THE LIMITATIONS OF THIS PARAGRAPH 5 AND TO www..com THEIR REASONABLENESS.
9.
NO CONFIDENTIAL INFORMATION Seller shall have no obligation to hold any information in confidence except as provided in a separate non-disclosure agreement signed by both parties. 10. ENTIRE AGREEMENT (a) These terms and conditions are the entire agreement and the only representations and understandings between Seller and Buyer, and no addition, deletion or modification shall be binding on Seller unless expressly agreed to in written and signed by an officer of Seller. (b) Buyer is not relying upon any warranty or representation except for those specifically stated here.
11.
APPLICABLE LAW
The contract and all performance and disputes arising out of or relating to goods involved will be governed by the laws of R.O.C. (Taiwan, Republic of China), without reference to the U.N. Convention on Contracts for the International Sale of Goods or to conflict of laws principles. Buyer agrees at its sole expense to comply with all applicable laws in connection with the purchase, use or sale of the goods provided hereunder and to indemnify Seller from any failure by Buyer to so comply. Without limiting the foregoing, Buyer certifies that no technical data or direct products thereof will be made available or re-exported, directly or indirectly, to any country to which such export or access is prohibited or restricted under R.O.C. laws or U.S. laws or regulations, unless prior authorization is obtained from the appropriate officials and agencies of the government as required under R.O.C. or U.S. laws or regulations.
12. 13.
JURISDICTION AND VENUE
The courts located in Hsinchu, Taiwan, Republic of China, will have the sole and exclusive jurisdiction and venue over any dispute arising out of or relating to the contract or any sale of goods hereunder. Buyer hereby consents to the jurisdiction of such courts.
ATTORNEYS' FEES
5.
Reasonable attorneys' fees and costs will be awarded to the prevailing party in the event of litigation involving and/or relating to the enforcement or interpretation of the contract and/or any goods sold under it.
6.
SUBSTITUTIONS AND MODIFICATIONS

▲Up To Search▲

Price & Availability of IT7230AFN

	To Download IT7230AFN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .