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INTEGRATED CIRCUITS
DATA SHEET
OQ2535HP SDH/SONET STM16/OC48 multiplexer
Product specification Supersedes data of 1997 Nov 27 File under Integrated Circuits, IC19 1999 Oct 04
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
FEATURES * Normal and loop (test) modes * 3.3 V TTL compatible data inputs * Differential Current-Mode Logic (CML) clock and data outputs * 5 V TTL clock output (low speed interface) * High input sensitivity (100 mV for the high speed clock input) * Boundary Scan Test (BST) at low speed interface, in accordance with "IEEE Std 1149.1-1990" * Low power dissipation (typically 1.65 W). ORDERING INFORMATION TYPE NUMBER OQ2535HP PACKAGE NAME HLQFP100 DESCRIPTION plastic heat-dissipating low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm GENERAL DESCRIPTION
OQ2535HP
The OQ2535HP is a 32-channel multiplexer intended for use in STM16/OC48 applications. It combines data from a total of 32 x 78 Mbits/s input channels onto a single 2.5 Gbits/s output channel. It features 3.3 V TTL data inputs and a 5 V TTL clock output at the low speed interface, and CML compatible inputs and outputs at the high speed interface.
VERSION SOT470-1
BLOCK DIAGRAM
handbook, full pagewidth
78 D0 Mbits/s to D31 ENL
622 Mbits/s
(1)
2.5 Gbits/s 4 : 1 MUX
90 91 82 83
DOUT DOUTQ COUT COUTQ
32 62 load pulse
4x 8 : 1 MUX
4
clock
SYNSEL1 SYNSEL2 TRST TMS TCK TDI TDO CDIV
59 58 2 5 3 7 6 13 BST LOGIC SYNCHRONIZATION
OQ2535HP
65 66 68 69
DLOOP DLOOPQ CLOOP CLOOPQ
622 MHz 78 MHz 2.5 GHz DIVIDE BY 8 DIVIDE BY 4 71 72 74 BAND GAP REFERENCE 1 BAND GAP REFERENCE 2 78 16 14, 37, 63, 85, 86 5 12, 39, 87, 88 4 VEE 60 31 VCC GND
MGK351
CIN CINQ DIOA DIOC
75
(2)
61
38
10
REFC1
REFC2
BGCAP1
BGCAP2 VCC(T) VDD
(1) See Chapter "Pinning" for D0 to D31 pin numbers. (2) Pins 1, 4, 8, 9, 11, 15, 17, 21, 25, 36, 40, 56, 64, 67, 70, 73, 76, 77, 79, 80, 81, 84, 89, 92 to 98 and 100.
Fig.1 Block diagram.
1999 Oct 04
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Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
PINNING SYMBOL GND TRS TCK GND TMS TDO TDI GND GND BGCAP1 GND VEE CDIV VDD GND VCC(T) GND D31 D27 D23 GND D19 D15 D11 GND D7 D3 D30 D26 D22 D18 D14 D10 D6 D2 GND VDD REFC2 VEE 1999 Oct 04 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 TYPE(1) S I I S I O I S S A S S O S S S S I I I S I I I S I I I I I I I I I I S S A S ground test reset input for BST mode (active LOW) test clock input for BST mode ground test mode select input for BST mode serial test data output for BST mode serial test data input for BST mode ground ground DESCRIPTION
OQ2535HP
pin for connecting external band gap decoupling capacitor (4 x 8 : 1 MUX) ground supply voltage (-4.5 V) 78 MHz clock output supply voltage (+3.3 V) ground supply voltage for TTL buffer (+5.0 V); not connected internally to VCC ground 78 Mbits/s data input channel for D31 78 Mbits/s data input channel for D27 78 Mbits/s data input channel for D23 ground 78 Mbits/s data input channel for D19 78 Mbits/s data input channel for D15 78 Mbits/s data input channel for D11 ground 78 Mbits/s data input channel for D7 78 Mbits/s data input channel for D3 78 Mbits/s data input channel for D30 78 Mbits/s data input channel for D26 78 Mbits/s data input channel for D22 78 Mbits/s data input channel for D18 78 Mbits/s data input channel for D14 78 Mbits/s data input channel for D10 78 Mbits/s data input channel for D6 78 Mbits/s data input channel for D2 ground supply voltage (+3.3 V) pin for connecting external reference decoupling capacitor (3.3 V CMOS reference) supply voltage (-4.5 V) 3
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
SYMBOL GND D29 D25 D21 D17 D13 D9 D5 D1 D28 D24 D20 D16 D12 D8 D4 GND D0 SYNSEL2 SYNSEL1 VCC REFC1 ENL VDD GND DLOOP DLOOPQ GND CLOOP CLOOPQ GND CIN CINQ GND DIOA DIOC GND GND BGCAP2 GND 1999 Oct 04
PIN 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
TYPE(1) S I I I I I I I I I I I I I I I S I I I S A I S S O O S O O S I I S A A S S A S ground
DESCRIPTION 78 Mbits/s data input channel for D29 78 Mbits/s data input channel for D25 78 Mbits/s data input channel for D21 78 Mbits/s data input channel for D17 78 Mbits/s data input channel for D13 78 Mbits/s data input channel for D9 78 Mbits/s data input channel for D5 78 Mbits/s data input channel for D1 78 Mbits/s data input channel for D28 78 Mbits/s data input channel for D24 78 Mbits/s data input channel for D20 78 Mbits/s data input channel for D16 78 Mbits/s data input channel for D12 78 Mbits/s data input channel for D8 78 Mbits/s data input channel for D4 ground 78 Mbits/s data input channel for D0 selection input 2 for synchronization pulse timing selection input 1 for synchronization pulse timing supply voltage (+5.0 V) pin for connecting external reference decoupling capacitor (for standard TTL reference) loop mode enable (active LOW) supply voltage (+3.3 V) ground data output to demultiplexer IC OQ2536 (loop mode) inverted data output to demultiplexer IC OQ2536 (loop mode) ground clock output to demultiplexer IC OQ2536 (loop mode) inverted clock output to demultiplexer IC OQ2536 (loop mode) ground clock input from VCO IC inverted clock input from VCO IC ground anode of temperature diode array cathode of temperature diode array ground ground pin for connecting external band gap decoupling capacitor (4 : 1 MUX) ground 4
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
SYMBOL GND GND COUT COUTQ GND VDD VDD VEE VEE GND DOUT DOUTQ GND GND GND GND GND GND GND i.c. GND Note
PIN 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
TYPE(1) S S O O S S S S S S O O S S S S S S S - S ground ground clock output to laser driver IC
DESCRIPTION
inverted clock output to laser driver IC ground supply voltage (+3.3 V) supply voltage (+3.3 V) supply voltage (-4.5 V) supply voltage (-4.5 V) ground data output to laser driver IC inverted data output to laser driver IC ground ground ground ground ground ground ground internally connected, to be left open-circuit ground
1. Pin type abbreviations: O = Output, I = Input, S = power Supply, A = Analog function.
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Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
91 DOUTQ
83 COUTQ
handbook, full pagewidth
78 BGCAP2
90 DOUT
82 COUT
80 GND
79 GND
77 GND
100 GND
GND TRST TCK GND TMS TDO TDI GND GND
1 2 3 4 5 6 7 8 9
76 GND 75 DIOC 74 DIOA 73 GND 72 CINQ 71 CIN 70 GND 69 CLOOPQ 68 CLOOP 67 GND 66 DLOOPQ 65 DLOOP 64 GND 63 VDD 62 ENL 61 REFC1 60 VCC 59 SYNSEL1 58 SYNSEL2 57 D0 56 GND 55 D4 54 D8 53 D12 52 D16 51 D20 D24 50
MGK350
98 GND
97 GND
96 GND
95 GND
94 GND
93 GND
92 GND
89 GND
84 GND
BGCAP1 10 GND 11 VEE 12 CDIV 13 VDD 14 GND 15 VCC(T) 16 GND 17 D31 18 D27 19 D23 20 GND 21 D19 22 D15 23 D11 24 GND 25 D7 26 D3 27 D30 28 D26 29 D22 30 D18 31 D14 32 D10 33 D6 34 D2 35 GND 36 VDD 37 REFC2 38 VEE 39 GND 40 D29 41 D25 42 D21 43 D17 44 D13 45 D9 46 D5 47 D1 48 D28 49
OQ2535HP
Fig.2 Pin configuration.
1999 Oct 04
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81 GND
86 VDD 85 VDD
88 VEE 87 VEE
99 i.c.
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
FUNCTIONAL DESCRIPTION The OQ2535HP is a 32-channel multiplexer intended for use in STM16/OC48 applications. It multiplexes 32 x 78 Mbits/s input channels onto a single 2.5 Gbits/s output channel. The multiplexing is performed in two stages. The 32 input channels are fed into four 8 : 1 multiplexers to generate four 622 Mbits/s channels. These four channels are then combined into a single 2.5 Gbits/s data stream. The ENL control input is used for switching between normal and loop modes. When loop mode is enabled, (ENL = LOW), the output signal is switched to DLOOP and DLOOPQ (these outputs could be connected to the DLOOP and DLOOPQ inputs on the OQ2536HP demultiplexer to form part of a test loop). The 2.5 GHz clock at CIN and CINQ is used as the system reference. It is divided down to 78 MHz and made available on the CDIV TTL output for timing the input data (D0 to D31). Low bit rate stage: 4 x 8 : 1 MUX This part of the circuit consists of four 8-bit shift registers, each acting as an 8 : 1 multiplexer, together with a synchronization block. The 32 data input signals are loaded into the shift registers before being shifted out on a 622 MHz clock. The load pulse for the shift registers is generated in the synchronization block. The inputs SYNSEL1 and SYNSEL2 can be used to adjust the phase of the load pulse with respect to the input data (see Table 3) to synchronize the data and clock signals. High bit rate stage: 4 : 1 MUX The four 622 Mbits/s data outputs from the low bit rate stage are combined into a single 2.5 Gbits/s data stream in two stages: two 2 : 1 multiplexers are used to generate two 1244 Mbits/s data streams; these signals are then fed into a third 2 : 1 multiplexer to generate the 2.5 Gbits/s data stream. The 2.5 Gbits/s serial data stream is passed either to the DOUT and DOUTQ outputs (normal mode), or to the DLOOP and DLOOPQ outputs (loop mode). The output sequence is D31 (MSB) to D0 (LSB). Data and clock output buffers are terminated internally with 100 resistors to GND and are capable of driving 50 loads. The unused output buffers are switched off to help minimize power dissipation.
OQ2535HP
The outputs CLOOP, CLOOPQ, DLOOP and DLOOPQ are terminated internally with 100 resistors to GND and are specifically designed to drive 50 printed-circuit board transmission lines. The 2.5 GHz clock connected to CIN and CINQ is terminated internally with 50 to GND. Power supply connections The power supply pins need to be individually decoupled using chip capacitors mounted as close as possible to the IC. If multiple decoupling capacitors are used for a single supply node, they must be placed close to each other to avoid RF resonance. To minimize low frequency switching noise in the vicinity of the OQ2535HP, all power supply lines should be filtered once by an LC-circuit with a low cut-off frequency (as shown in the application diagram, Fig.6). VCC(T) needs to be filtered separately via an LC-circuit because of the high switching currents present at the CDIV TTL output. As this current contains only 78 MHz harmonics, filtering can be achieved with relatively small values of L and C. Ground connection The ground connection on the printed-circuit board needs to be a large copper area fill connected to a common ground plane with low inductance. RF connections A coupled stripline or microstrip with an odd mode characteristic impedance of 50 (nominal value) should be used for the RF connections on the printed-circuit board. The connections should be kept as short as possible. This applies to the CML differential line pairs CIN and CINQ, DOUT and DOUTQ, COUT and COUTQ, DLOOP and DLOOPQ, and CLOOP and CLOOPQ. In addition, the following lines should not vary in length by more than 5 mm: * CIN and CINQ * DOUT, DOUTQ, COUT and COUTQ * DLOOP, DLOOPQ, CLOOP and CLOOPQ. Interface to transmit logic The 78 Mbits/s interface lines, CDIV and D0 to D31, should not vary in length by more than 20 mm. The parasitic capacitance of these lines should be as small as possible.
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Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
ESD protection All pads are protected by ESD protection diodes with the exception of the high frequency outputs DOUT, DOUTQ, DLOOP, DLOOPQ, COUT, COUTQ, CLOOP and CLOOPQ and clock inputs CIN and CINQ. Cooling In many cases it is necessary to mount a special cooling device on the package. The thermal resistance from junction to case, Rth j-c and from junction to ambient, Rth j-a, are given in Chapter "Thermal characteristics". Since the heat-slug in the package is connected to the die, the cooling device should be electrically isolated. To calculate if a heatsink is necessary, the maximum allowed total thermal resistance Rth is calculated as: T j - T amb (1) R th = ----------------------P tot where: Rth = total thermal resistance from junction to ambient in the application Tj = junction temperature Tamb = ambient temperature. As long as Rth is greater than Rth j-a of the OQ2536HP including environmental conditions such as air flow and board layout, no heatsink is necessary. For example if Tj = 120 C, Tamb = 55 C and Ptot = 1.65 W, then: ( 120 - 55 ) R th = -------------------------- = 39.4 K/W (2) 1.65 which is more than the worst case Rth j-a = 33 K/W, so no heatsink is necessary. Another example; if for safety reasons Tj should stay as low as 110 C, while Tamb = 85 C and Ptot = 2 W, then: ( 110 - 85 ) R th = -------------------------- = 12.5 K/W (3) 2.0 In this case extra cooling is needed. The thermal resistance of the heatsink is calculated as follows: Table 1 BST identifier code OQ 01 2535 (BINARY) 00 1001 1110 0111
OQ2535HP
1 -1 1 R th h-a ------- - ------------- - R th j-c - R th c-h R th R th j-a
(4)
where: Rth h-a = thermal resistance from heatsink to ambient Rth c-h = thermal resistance from case to heatsink Rth j-c = thermal resistance from junction to case, see Chapter "Thermal characteristics". If for instance Rth c-h = 0.5 K/W and Rth j-a = 33 K/W then: 1 1 -1 R th h-a ---------- - ----- - 3.1 (5) 12.5 33 17.0 K/W Built in temperature sensor Three series-connected diodes have been integrated for measuring junction temperature. The diode array, accessed by means of the DIOA (anode) and DIOC (cathode) pins, has a temperature dependency of approximately -6 mV/C. With a diode current of 1 mA, the voltage will be somewhere in the range of 1.7 to 2.5 V, depending on temperature. Boundary Scan Test (BST) interface Boundary scan test logic has been implemented for all digital inputs and outputs on the low frequency interface, in accordance with "IEEE Std 1149.1-1990". All scan tests other than SAMPLE mode are available. The boundary scan test logic consists of a TAP controller, a BYPASS register, a 2-bit instruction register, a 32-bit identification register and a 36-bit boundary scan register (the last two are combined). The architecture of the TAP controller and the BYPASS register is in accordance with IEEE recommendations. The four command modes, selected by means of the instruction register, are: EXTEST (00), PRELOAD (01), IDCODE (10) and BYPASS (11). All boundary scan test inputs, TDI, TMS, TCK and TRST, have internal pull-up resistors. The maximum test clock frequency at TCK is 12 MHz.
VERSION 0001 Note
PHILIPS SEMICONDUCTORS 0000 0010 101
LSB(1) 1
1. LSB is shifted out first on the TDO pin.
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Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
Table 2 BST bit order SYMBOL CDIV ENL SYNSEL2 SYNSEL1 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PIN 13 62 58 59 18 28 41 49 19 29 42 50 20 30 43 51 22 31 44 52 23 32 45 53 24 33 46 54 26 34 47 55 27 35 48 57
OQ2535HP
BIT NUMBER 35 (MSB) 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB)(1) Note
1. LSB is shifted out first on the TDO pin.
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Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC, VCC(T) VEE VDD Vn supply voltage supply voltage supply voltage DC voltage pins 18 to 20, 22 to 24, 26 to 35, 41 to 55 and 57 pins 2, 3, 5, 7, 38, 61 and 62 pins 65, 66, 68, 69, 71, 72, 82, 83, 90 and 91 pins 10 and 78 pins 74 and 75 In DC current pins 6 and 13 pins 74 and 75 Ptot Tj Tstg total power dissipation junction temperature storage temperature - - - - -65 50 10 2.35 120 -0.5 -0.5 -1.0 VEE - 0.5 VEE - 0.5 PARAMETER MIN. -0.5 -6.0 -0.5
OQ2535HP
MAX. +6.0 +0.5 +5.0 VDD + 0.5 VCC + 0.5 +0.5 0.5 VCC + 0.5 V V V V V V V V
UNIT
mA mA W C C
+150
THERMAL CHARACTERISTICS SYMBOL Rth j-c Rth j-a PARAMETER thermal resistance from junction to case thermal resistance from junction to ambient see note 1 airflow = 0 ft/min airflow = 100 ft/min airflow = 200 ft/min airflow = 400 ft/min airflow = 600 ft/min Note 1. The thermal resistance from junction to ambient is strongly depending on the board design and airflow. The values given in the table are typical values and are measured on a single sided test board with dimensions of 76 x 114 x 1.6 mm. Better values can be obtained when mounted on multilayer boards with large ground planes. 33 28 25 22 20 K/W K/W K/W K/W K/W CONDITIONS VALUE 2.6 UNIT K/W
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Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
DC CHARACTERISTICS All typical values are at Tamb = 25 C and at typical supply voltages; minimum and maximum values are valid over the entire ambient temperature range and supply voltage range. SYMBOL General VCC, VCC(T) VEE VDD ICC ICC(T) IEE IDD Ptot Tj Tamb VIL VIH IIL IIH VIL VIH IIL IIH Vi(p-p) VIO VI, VIQ Zi VOL VOH IOZ Vo(p-p) VOO VO, VOQ Zo supply voltage supply voltage supply voltage supply current supply current supply current supply current total power dissipation junction temperature ambient temperature note 1 4.75 -4.75 3.14 - - - - - - -40 - 2.0 -65 0 - 2.0 note 3 note 3 50 measurement system for DC signal -100 0 5.0 -4.5 3.3 2.3 20 265 20 1.65 - - - - - - - - - - 250 - - 50 5.25 -4.25 3.47 4 40 400 28 2.35 120 +85 V V V mA mA mA mA W C C V V A A V V A A mV mV mV V V A mV mV mV PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
TTL 3.3 V inputs: D0 to D31; note 2 LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current 0.8 - 0 110
TTL inputs: ENL, SYNSEL1, SYNSEL2, TDI, TCK, TMS and TRST LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current 0.8 - 0 210
CML clock inputs: CIN and CINQ; note 4 input voltage (peak-to-peak value) permitted input offset voltage input voltages single ended input impedance 100 -25 -600 - - 2.4 - outputs terminated externally with 50 resistors for DC signal 230 -25 -600 - 500 +25 +250 - 0.5 - 1
TTL outputs: CDIV and TDO; note 5 LOW-level output voltage HIGH-level output voltage output current in high-impedance state IOL = 4 mA IOH = -400 A 0.3 4.0 - 300 0 - 100
CML outputs in normal mode: COUT, COUTQ, DOUT and DOUTQ; note 4 output voltage (peak-to-peak value) output offset voltage output voltages output impedance 500 +25 0 -
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Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CML outputs in loop mode: CLOOP, CLOOPQ, DLOOP and DLOOPQ; note 4 Vo(p-p) VOO VO, VOQ Zo VDIOA-DIOC Notes 1. VCC and VCC(T) require the same power supply voltage. However, a filter is needed to isolate VCC(T) because of the high peak currents that occur at 78 MHz. 2. The output sequence is D31 (MSB) to D0 (LSB). 3. Only for inputs ENL, SYNSEL1 and SYNSEL2. TDI, TMS, TCK and TRST are connected to VCC through 90 k resistors. 4. See Fig.3 for symbol definitions. 5. TDO is switched to high impedance state if BST is inactive. 6. The temperature diode array can be used to measure the temperature of the die. The temperature dependency of this voltage is approximately -6 mV/K. output voltage (peak-to-peak value) output offset voltage output voltages output impedance outputs terminated externally with 50 for DC signal 230 -25 -600 - - 300 0 - 100 500 +25 0 - - mV mV mV V
Temperature diode array diode voltage range; note 6 II(d) = 1 mA 2.1
handbook, full pagewidth
CML INPUT
CML OUTPUT
VI(max) GND VIQH VIH Vi(p-p) VIQL VIL VI(min) VIO VOQL VOL VO(min) VOO VO(max) VOQH VOH Vo(p-p) GND
MGK144
Fig.3 Logic level symbol definitions for CML.
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Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
TIMING Typical values at Tamb = 25 C and at typical supply voltages; minimum and maximum values are valid over the entire ambient temperature range and supply voltage range. SYMBOL TTL input timing fclk(CDIV) tsu th fclk(COUT) tCDV tDI tr(CML), tf(CML) COUT Notes 1. The set-up and hold times given are valid for SYNSEL1 = SYNSEL2 = HIGH. Different SYNSEL1, SYNSEL2 combinations will produce different set-up and hold times (see Table 3). 2. All CML outputs must be terminated externally with 50 to GND. The specified timing characteristics are applicable in both normal and loop modes. Table 3 Timing relationship between the clock edge and the data valid region (minimum values) SYNSEL1 HIGH LOW HIGH LOW tsu 1200 2800 1700 3300 th 2600 1000 2100 500 UNIT ps ps ps ps low speed output clock frequency input data set-up time input data hold time fclk(CIN) = 2.488 GHz capacitive load of 15 pF note 1 note 1 - - 1200 2600 - - - - 45 77.76 - - - 2.488 - - - 50 - 2600 - - - 250 120 150 55 MHz ps ps ps tr(CDIV), tf(CDIV) CDIV rise/fall time PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
CML output timing; note 2 output clock frequency clock edge to data valid time data invalid time CML output rise/fall time output clock duty factor fclk(CIN) = 2.488 GHz GHz ps ps ps %
SYNSEL2 HIGH HIGH LOW LOW
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Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
handbook, full pagewidth
tf
Tcy(CDIV)
tr 2.0 V 1.5 V 0.8 V
CDIV
D0 to D31
1.5 V
th tsu
valid data
MGK352
Fig.4 TTL input timing.
handbook, full pagewidth
tf
tr
Tcy(COUT) +100 mV
COUT - COUTQ, CLOOP - CLOOPQ
0V -100 mV
+100 mV DOUT - DOUTQ, DLOOP - DLOOPQ -100 mV
MGK353
tCDV tDI
Fig.5 CML output timing.
1999 Oct 04
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Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
APPLICATION INFORMATION
system reference DATA INTERFACE D0 to D31
OQ2535HP
handbook, full pagewidth
PHASE DETECTOR
CDIV D0 to D31 13 10 BGCAP1
VEE 10 nF VEE
78 61 62 38
BGCAP2 REFC1
10 nF PLL LOOP FILTER 68 nF
ENL microcontroller
REFC2 68 nF SYNSEL1 SYNSEL2 CIN CINQ ferrite bead 100 nF ferrite bead 100 nF 1 F VCO 2.488 GHz GND or VCC
TDI TCK BOUNDARY SCAN TEST EQUIPMENT TMS TRST TDO
7 3 5 2 6
59 58 71 72
OQ2535
60 VCC
16
VCC(T)
1 F ferrite bead
DLOOP
DLOOP DLOOPQ CLOOP CLOOPQ
65 66 68 69
(2) (1)
VDD 100 nF VEE 100 nF GND
OQ2536 DLOOPQ
DMUX CLOOP CLOOPQ
1 F ferrite bead 1 F
(3)
90 DOUT D (1) VDD pins 14, 37, 63, 85 and 86 should be connected together, and to the filter network. (2) VEE pins 12, 39, 87 and 88 should be connected together, and to the filter network. (3) All GND pins (pins 1, 4, 8, 9, 11, 15, 17, 21, 25, 36, 40, 56, 64, 67, 70, 73, 76, 77, 79, 80, 81, 84, 89, 92 to 98 and 100) must be connected directly to the printed-circuit board ground plane.
91 DOUTQ
82 COUT CL
83 COUTQ
DQ
CLQ
OQ2545
LASER DRIVER LA LAQ
LASER DIODE
MGK354
Fig.6 Application diagram.
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Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
PACKAGE OUTLINE HLQFP100: plastic heat-dissipating low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
OQ2535HP
SOT470-1
c
y X A 75 76 51 50 Z E
e J wM bp Lp pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X L E HE A A2 A1 (A 3)
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.5 1.3 A3 0.25 bp 0.28 0.16 c 0.18 0.12 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE J(2) L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7 0o
o
16.25 16.25 10.15 15.75 15.75 9.15
Notes 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 2. Heatsink intrusion 0.0127 maximum. OUTLINE VERSION SOT470-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-01-13
1999 Oct 04
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Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
OQ2535HP
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Oct 04
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Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
Suitability of surface mount IC packages for wave and reflow soldering methods
OQ2535HP
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
1999 Oct 04
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Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 68
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465012/50/02/pp20
Date of release: 1999
Oct 04
Document order number:
9397 750 03901

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