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Micrel, Inc.
2.5V, 3.2Gbps DUAL, DIFFERENTIAL 2:1 LVDS MULTIPLEXER WITH INTERNAL TERMINATION
Precision Edge SY89542U
Precision Edge(R) SY89542U (R)
FEATURES
Dual 2:1 multiplexer Guaranteed AC performance over temp and voltage: * DC-to > 3.2Gbps data rate throughput * < 600ps In-to-Out tpd * < 150ps tr/tf Ultra-low jitter design: * < 1psRMS random jitter * < 10psPP deterministic jitter * < 10psPP total jitter (clock) * < 0.7psRMS crosstalk-induced jitter Unique input isolation design minimizes crosstalk Internal input termination Unique input termination and VT pin accepts DC-Coupled and AC-coupled inputs (LVDS, LVPECL, CML) 350mV LVDS output swing CMOS/TTL compatible MUX select Power supply 2.5V 5% -40C to +85C temperature range Available in 32-pin (5mm x 5mm) MLF(R) package Precision Edge(R)
DESCRIPTION
The SY89542U includes two precision, high-speed 2:1 differential Muxes with LVDS (350mV) compatible outputs with a guaranteed data rate throughput of 3.2Gbps over temperature and voltage. The SY89542U differential inputs include a unique, 3-pin internal termination that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards, both AC- and DC-coupled without external resistor-bias and termination networks. The result is a clean, stub-free, low jitter interface solution. The SY89542U operates from a single 2.5V supply, and is guaranteed over the full industrial temperature range (-40C to +85C). For applications that require a 3.3V supply, consider the SY89543L. The SY89542U is part of Micrel's Precision Edge(R) product family. All support documentation can be found on Micrel's web site at www.micrel.com.
APPLICATIONS
Redundant clock/data switchover SONET/SDH multi-channel select applications Fibre Channel applications GigE applications
FUNCTIONAL BLOCK DIAGRAM
INA0 50 VTA0 50 /INA0 0 MUX A 2:1 MUX INB0 50 VTB0 50 /INB0 0
2:1 MUX
LVDS
LVDS MUX B
QA /QA
QB /QB
1 INA1 50 VTA1 50 /INA1 SELA (CMOS/TTL)
S INB1 50 VTB1 50 /INB1 SELB (CMOS/TTL)
1
S
Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. M9999-082407 hbwhelp@micrel.com or (408) 955-1690
Rev.: D Amendment: /0
1
Issue Date: August 2007
Micrel, Inc.
Precision Edge(R) SY89542U
PACKAGE/ORDERING INFORMATION
INA1 VTA1 /INA1 VCC VCC INB0 VTB0 /INB0
Ordering Information(1)
VCC INB1 VTB 1 /INB1 VCC SELB GND VCC
32 31 30 29 28 27 26 25
VCC /INA0 VTA0 INA0 VCC SELA GND VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22 21 20 19 18 17
Part Number SY89542UMI SY89542UMITR(2) SY89542UMG(3) SY89542UMGTR(2,3)
Package Type MLF-32 MLF-32 MLF-32 MLF-32
Operating Range Industrial Industrial Industrial Industrial
Package Marking SY89542U SY89542U SY89542U with Pb-Free bar-line indicator SY89542U with Pb-Free bar-line indicator
Lead Finish Sn-Pb Sn-Pb Pb-Free NiPdAu Pb-Free NiPdAu
32-Pin MLF(R)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC electricals only. 2. Tape and Reel. 3. Recommended for new designs.
PIN DESCRIPTION
Pin Number 4, 2, 32, 30, 27, 25, 23, 21 Pin Name INA0, /INA0, INA1, /INA1, INB0, /INB0, INB1, /INB1 Pin Function Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50. Note that these inputs will default to an indeterminate state if left open. Unused differential input pairs can be terminated by connecting one input to VCC and the complementary input to GND through a 1k resistor. The VT pin is to be left open in this configuration. Please refer to the "Input Interface Applications" section for more details. Input Termination Center-Tap: Each side of the differential input pair, terminates to a VT pin. The VTA0, VTA1, VTB0, VTB1 pins provide a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" section for more details. These single-ended TTL/CMOS-compatible inputs select the inputs to the multiplexers. Note that these inputs are internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. Input switching threshold is VCC/2. Positive Power Supply: Bypass with 0.1F||0.01F low ESR capacitors. The 0.01F capacitor should be as close to VCC pin as possible. Differential Outputs: This differential LVDS output pair provides a copy of the selected input. It is a logic function of the INA0, INA1, INB0, INB1 and SELA and SELB inputs. Please refer to the "Truth Table" for details. Unused output pairs must be terminated with 100 across the differential pair. Ground: Ground pin and exposed pad must be connected to the same ground plane.
3, 31, 26, 22
6, 19
1, 5, 8, 17, 20, 24, 28, 29 10, 11, 14, 15
7, 9, 12, 13, 16, 18
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GND QA /QA GND GND QB /QB GND
VTA0 , VTA1, VTB0, VTB1 SELA, SELB
VCC QA, /QA, QB, /QB
GND, Exposed pad
2
Micrel, Inc.
Precision Edge(R) SY89542U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ................................. -0.5V to +4.0V Input Voltage (VIN) ........................................ -0.5V to VCC Termination Current(3) Source or sink current on VT ..................................... 100mA Input Current Source or sink current on IN, /IN .......................... 50mA Lead Temperature (soldering, 20 sec.) ................... +260C Storage Temperature (TS) ....................... -65C to +150C
Operating Ratings(2)
Supply Voltage (VCC) ............................. 2.375V to 2.625V Ambient Temperature (TA) ........................ -40C to +85C Package Thermal Resistance(4) MLF(R) (JA) Still-Air ................................................................ 35C/W 500lfpm .............................................................. 28C/W MLF(R) (JB) Junction-to-Board ................................................ 20C/W
DC ELECTRICAL CHARACTERISTICS(5)
TA = -40C to +85C; Unless otherwise stated. Symbol VCC ICC RDIFF_IN RIN VIH VIL VIN VDIFF_IN IN-to-VT
Notes: 1. Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to "Absolute Maximum Ratings" conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Due to the limited drive capability use for input of the same package only. 4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. JB uses 4-layer JA in still-air unless otherwise stated. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. Includes current through internal 50 pull-ups. 7. See "Single-Ended and Differential Swings" section for VIN and VDIFF_IN definition.
Parameter Power Supply Power Supply Current Differential Input Resistance (IN-to-/IN) Input Resistance (IN-to-VT, /IN-to-VT) Input High Voltage (IN, /IN) Input Low Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing |IN - /IN| Voltage from Input to VT
Condition
Min 2.375
Typ 2.5 70
Max 2.625 95 120 60 VCC VIH-0.1 VCC
Units V mA V V V V
No Load, Max. VCC
(6)
80 40 1.2 0 Notes 7 Notes 7 0.1 0.2
100 50
1.8
V
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Micrel, Inc.
Precision Edge(R) SY89542U
LVDS OUTPUTS DC ELECTRICAL CHARACTERISTICS(9)
VCC = 2.5V 5%; TA = -40C to +85C; RL = 100 across Q and /Q, unless otherwise stated. Symbol VOH VOL VOUT VDIFF-OUT VOCM VOCM Parameter Output HIGH Voltage (Q, /Q) Output LOW Voltage (Q, /Q) Output Voltage Swing (Q, /Q) Differential Output Voltage Swing |Q - /Q| Output Common Mode Voltage (Q, /Q) Change in Common Mode Voltage (Q, /Q) Condition See Figure 5a See Figure 5a See Figures 1a, 5a See Figure 1b See Figure 5b See Figure 5b 0.925 250 500 1.125 -50 350 700 1.275 +50 Min Typ Max 1.475 Units V V mV mV V mV
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(9)
VCC = 2.5V 5%; TA = -40C to +85C; unless otherwise stated. Symbol VIH VIL IIH IIL
Note: 9. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0
Typ
Max VCC 0.8 40 -300
Units V V A A
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Micrel, Inc.
Precision Edge(R) SY89542U
AC ELECTRICAL CHARACTERISTICS(10)
VCC = 2.5V 5%; TA = -40C to +85C; RL = 100 across Q and /Q, unless otherwise stated. Symbol fMAX tpd tSKEW Parameter Maximum Operating Frequency VOUT > 200mV Differential Propagation Delay IN-to-Q SEL-to-Q Input-to-Input Skew Bank-to-Bank Skew Part-to-Part Skew tJITTER Data Random Jitter (RJ) Deterministic Jitter (DJ) Clock Total Jitter (TJ ) Cycle-to-Cycle Jitter Crosstalk-Induced Jitter tr, tf
Notes: 10. Measured with 100mV input swing. See "Timing Diagrams " section for definition of parameters. High frequency AC-parameters are guaranteed by design and characterization. 11. Input-to-input skew is the difference in time from an input-to-output in comparison to any other input-to-output. In addition, the input-to-input skew does not include the output skew. 12. Bank-to-bank skew is the difference in time from input to the output between banks. 13. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. Total skew is calculated as the RMS (Root Mean Square) of the input skew and output skew. 14. Random jitter is measured with a K28.7 comma detect character pattern, measured at 1.25Gbps and 3.2Gbps. 15. Deterministic jitter is measured at 1.25Gbps and 3.2Gbps, with both K28.5 and 223-1 PRBS pattern. 16. Total jitter definition: with an ideal clock input of frequency fMAX, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. 17. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn-Tn-1 where T is the time between rising edges of the output signal. 18. Crosstalk is measured at the output while applying two similar frequencies to adjacent inputs that are asynchronous with respect to each other at the inputs.
Condition NRZ Data Clock
Min 3.2
Typ
Max
Units Gbps
4 250 200 350 350 450 600 20 25 200 1 10 10 1 0.7 35 80 150
GHz ps ps ps ps ps psRMS psPP psPP psRMS psRMS ps
Note 11 Note 12 Note 13 Note 14 Note 15 Note 16 Note 17 Note 18 At full output swing
Output Rise / Fall Time (20% to 80%)
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Micrel, Inc.
Precision Edge(R) SY89542U
SINGLE-ENDED AND DIFFERENTIAL SWINGS
VIN, VOUT 350mV (Typ.)
VDIFF_IN, VDIFF_OUT 700mV (Typ.)
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
TIMING DIAGRAM
IN /IN tpd Q /Q
SEL SEL-to-Q tpd Q /Q
Figure 2. Timing Diagram
TRUTH TABLE
IN0 0 1 X X IN1 X X 0 1 SEL 0 0 1 1 Q 0 1 0 1 /Q 1 0 1 0
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Micrel, Inc.
Precision Edge(R) SY89542U
FUNCTIONAL CHARACTERISTICS
VCC = 2.5V, TA = 25C.
200MHz Output
Q
1.6GHz Output
Output Swing (70mV/div.)
Q
/Q
Output Swing (70mV/div.)
/Q
TIME (600ps/div.)
TIME (80ps/div.)
2.5GHz Output
Q Q
3.2GHz Output
Output Swing (70mV/div.)
Output Swing (70mV/div.)
/Q
/Q
TIME (50ps/div.)
OC-12 Mask (223-1 PRBS)
TIME (40ps/div.)
2xGBE Mask (223-1 PRBS)
Output Swing (70mV/div.)
TIME (270ps/div.)
3.2Gbps Data Output (223-1 PRBS)
400 OUTPUT AMPLITUDE (mV) 350 300 250 200 150 100 50 0 0
Output Swing (70mV/div.)
TIME (67ps/div.)
Output Amplitude vs. Frequency
Output Swing (70mV/div.)
1
2 3 4 5 FREQUENCY (GHz)
6
TIME (80ps/div.)
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Micrel, Inc.
Precision Edge(R) SY89542U
INPUT AND OUTPUT STAGE INTERNAL TERMINATION
VCC
IN 50 VT 50 /IN GND
Figure 3. Simplified Differential Input Stage
INPUT INTERFACE APPLICATIONS
VCC
VCC
VCC
IN
LVPECL
IN
IN CML /IN SY89542U GND NC VT
CML /IN GND VCC -1.4V VT SY89542U
GND
/IN VCC 0.01F VT Rp For VCC = 2.5V, Rp = 19 SY89542U
GND
Figure 4a. CML Interface (DC-Coupled)
Figure 4b. CML Interface (AC-Coupled)
Figure 4c. LVPECL Interface (DC-Coupled)
VCC
IN
LVPECL
VCC
/IN Rp GND GND Rp VCC -1.4V VT GND For VCC = 2.5V, Rp = 50 SY89542U
IN LVDS /IN SY89542U GND NC VT
Figure 4d. LVPECL Interface (AC-Coupled)
Figure 4e. LVDS Interface
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Micrel, Inc.
Precision Edge(R) SY89542U
OUTPUT INTERFACE APPLICATIONS
LVDS specifies a small swing of 350mV typical, on a nominal 1.25V common mode above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep EMI low.
50
50
50
VOCM, VOCM
50
VOCM, VOCM
GND
GND
Figure 5a. LVDS Differential Measurement
Figure 5b. LVDS Common Mode Measurement
RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION
Part Number SY89543L SY89544U SY89545L SY89546U SY89547L Function 3.3V, 3.2Gbps Dual, Differential 2:1 LVDS Multiplexer with Internal Input Termination 2.5V, 3.2Gbps 4:1 LVDS Multiplexer with Internal Input Termination 3.3V, 3.2Gbps 4:1 LVDS Multiplexer with Internal Input Termination 2.5V 3.2Gbps, Differential 4:1 LVDS Multiplexer with 1:2 Fanout and Internal Input Termination 3.3V 3.2Gbps, Differential 4:1 LVDS Multiplexer with 1:2 Fanout and Internal Input Termination MLF(R) Application Note HBW Solutions New Products and Applications Data Sheet Link http://www.micrel.com/_pdf/HBW/sy89543l.pdf http://www.micrel.com/_pdf/HBW/sy89544u.pdf http://www.micrel.com/_pdf/HBW/sy89545l.pdf http://www.micrel.com/_pdf/HBW/sy89546u.pdf http://www.micrel.com/_pdf/HBW/sy89547l.pdf www.amkor.com/products/notes_papers/LF_AppNote_0902.pdf www.micrel.com/product-info/products/solutions.shtml
M9999-082407 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
Precision Edge(R) SY89542U
32-PIN MicroLeadFrame(R) (MLF-32)
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 32-Pin MLF(R) Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: 1. Package meets Level 2 qualification. 2. All parts are dry-packaged before shipment. 3. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated. M9999-082407 hbwhelp@micrel.com or (408) 955-1690
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