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HD74HC589
8-bit Serial or Parallel-input/Serial-output Shift Register (with 3-state outputs)
REJ03D0631-0200 (Previous ADE-205-511) Rev.2.00 Mar 30, 2006
Description
The HD74HC589 is similar in function to the HD74HC597, which is not a 3-state device. This device consists of an 8-bit storage latch which feeds parallel data to an 8-bit shift register. Data can also be loaded serially (see Function Table). The shift register output, OH, is a three-state output, allowing this device to be used in bus-oriented systems.
Features
* High Speed Operation: tpd (Shift Clock to QH) = 15 ns typ (CL = 50 pF) * High Output Current: Fanout of 15 LSTTL Loads * Wide Operating Voltage: VCC = 2 to 6 V * Low Input Current: 1 A max * Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C) * Ordering Information
Part Name HD74HC589FPEL HD74HC589RPEL Package Type SOP-16 pin (JEITA) SOP-16 pin (JEDEC) Package Code (Previous Code) PRSP0016DH-B (FP-16DAV) PRSP0016DG-A (FP-16DNV) Package Abbreviation FP RP Taping Abbreviation (Quantity) EL (2,000 pcs/reel) EL (2,500 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Latch Clock LCK Shift Clock SCK X X X L, H, Note: X L, H, Serial Shift/ Parallel Load X L L X Output Enable OE X L L H L Function Data are loaded into input latches Data are loaded from input into shift registers Data are transferred from input latches to shift registers Outputs are disabled Serial shift Qn = Qn - 1, Q0 = SER
X H 1. H; High level, L; Low level, X; Irrelevant
Rev.2.00 Mar 30, 2006 page 1 of 8
HD74HC589
Pin Arrangement
B1 C2 D3 E4 F5 G6 H7 GND 8 (Top view) 16 VCC 15 A 14 SA 13 Serial Shift/ Parallel Load
12 Latch Clock 11 Shift Clock 10 Output Enable 9 QH
Rev.2.00 Mar 30, 2006 page 2 of 8
HD74HC589
Logic Diagram
SCK SA Shift/ Load SCK A LCK Q D LCK Q SCK
S SCK Q D SCK R
B
LCK Q D LCK Q
S SCK Q D SCK R
C
D E F G
H LCK LCK QH OE LCK VCC
Rev.2.00 Mar 30, 2006 page 3 of 8
HD74HC589
Absolute Maximum Ratings
Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Symbol VCC VIN, VOUT IIK, IOK IOUT ICC or IGND PT Ratings -0.5 to 7.0 -0.5 to VCC +0.5 20 35 75 500 Unit V V mA mA mA mW
Storage temperature Tstg -65 to +150 C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time Note:
*1
Symbol VCC VIN, VOUT Ta tr , tf
Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500
Unit V V C ns
Conditions
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
0 to 400 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- -- Ta = 25C Typ Max -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.5 0.1 4.0 Ta = -40 to+85C Unit Min Max 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 5.0 1.0 40 V Test Conditions
VIL
V
Output voltage
VOH
V
Vin = VIH or VIL IOH = -20 A
VOL
V
Vin = VIH or VIL
IOH = -6 mA IOH = -7.8 mA IOL = 20 A
IOH = 6 mA IOH = 7.8 mA A Vin = VIH or VIL Vout = VCC or GND A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A
Off-state output current Input current Quiescent supply current
IOZ Iin ICC
Rev.2.00 Mar 30, 2006 page 4 of 8
HD74HC589
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25C Item Maximum clock frequency Propagation delay time Symbol VCC (V) fmax 2.0 4.5 6.0 tPLH tPHL tPLH tPHL tPLH tPHL Output enable time Output disable time Pulse width tZL tZH tLZ tHZ tw 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Setup time tsu 2.0 4.5 6.0 2.0 4.5 6.0 tsu 2.0 4.5 6.0 2.0 4.5 6.0 th 2.0 4.5 6.0 2.0 4.5 6.0 Output rise/fall time Input capacitance tTLH tTHL Cin 2.0 4.5 6.0 -- Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 80 16 14 100 20 17 100 20 17 100 20 17 5 5 5 5 5 5 5 5 5 -- -- -- -- Typ -- -- -- -- 20 -- -- 15 -- -- 16 -- -- 9 -- -- 14 -- -- 8 -- -- 1 -- -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- -- 5 -- 5 Max 5 27 32 200 40 34 175 35 30 175 35 30 150 30 26 150 30 26 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 75 15 13 10 Ta = -40 to +85C Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 20 17 125 25 21 125 25 21 125 25 21 5 5 5 5 5 5 5 5 5 -- -- -- -- Max 4 21 25 250 50 43 220 44 37 220 44 37 190 38 33 190 38 33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 95 19 16 10 ns ns Shift clock to SA ns Serial shift/parallel load to shift clock Latch clock to data ns Data to latch clock ns ns Serial shift/parallel load to QH ns Latch clock to QH Unit MHz Test Conditions
ns
Shift clock to QH
ns
ns
tsu
ns
SA to shift clock
Hold time
th
ns
th
ns
Shift clock to serial shift/ parallel load
pF
Rev.2.00 Mar 30, 2006 page 5 of 8
HD74HC589
Test Circuit
VCC VCC
OE
See Function Table
Output 1 k QH CL = 50 pF TEST t PLH / t PHL t ZH/ t HZ t ZL / t LZ S1 OPEN GND VCC
Input Pulse Generator Zout = 50 Input Pulse Generator Zout = 50
SA Shift/Load SCK LCK A to H
S1 OPEN GND VCC
Note : 1. CL includes probe and jig capacitance.
Waveforms
1. (SERIAL SHIFT / PARALLEL LOAD = "L")
tr Latch Clock 50% 50% tW(H) tPLH QH 50% 10% tTLH 90% 90% tTHL tW(L) tPHL VOH 50% 10% VOL QH tf VCC 50% 0V Shift Clock VCC 50% tw tPLH 50% 50% 0V tPHL VOH 50% 50% VOL
2. (SERIAL SHIFT / PARALLEL LOAD = "H")
3.
Input G 90%
tf 50% 10% tZL
tr 90% 50% tLZ 50% tZH tHZ 50% 90% VCC 0V VOH 10% VOL VOH VOL
4.
Serial Shift / Parallel Load
tw VCC 50% tPLH 50% 50% 0V tPHL VCC 50% 50% 0V
10%
Waveform - A
Waveform - B
Data
Notes : 1. Input waveform : PRR 1 MHz, duty cycle 50%, tr 6 ns, tf 6 ns 2. Waveform - A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform - B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement.
Rev.2.00 Mar 30, 2006 page 6 of 8
HD74HC589
5.
A to H 50% tsu th 0V
Data Valid VCC
6.
SA 50% tsu
Data Valid VCC 50% 0V th VCC 50% 0V
Latch Clock
VCC 50% 0V
Shift Clock
7.
Serial Shift / Parallel Load VCC 50% tsu Shift Clock th VCC 50% 0V 50% 0V
Notes : 1. Input waveform : PRR 1 MHz, duty cycle 50%, tr 6 ns, tf 6 ns 2. The output are measured one at a time with one transition per measurement.
Rev.2.00 Mar 30, 2006 page 7 of 8
HD74HC589
Package Dimensions
JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B Previous Code FP-16DAV MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
8 bp x M L1
Reference Symbol
c
Dimension in Millimeters
A1
y
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 10.06 10.5 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0 8 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15
JEITA Package Code P-SOP16-3.95x9.9-1.27
RENESAS Code PRSP0016DG-A
Previous Code FP-16DNV
*1
D 9
A
MASS[Typ.] 0.15g
F
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
E HE
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
c
8 bp x M L1
Reference Symbol
Dimension in Millimeters
A1
L
y
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 9.90 10.30 3.95 0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 0 8 5.80 6.10 6.20 1.27 0.25 0.15 0.635 0.40 0.60 1.27 1.08
Rev.2.00 Mar 30, 2006 page 8 of 8
A
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