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| TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL for mobile reception Rev. 02 -- 12 May 2006 Product data sheet 1. General description The TDA9884 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL demodulator for positive and negative modulation, including sound AM and FM processing. The device is specially prepared for mobile TV applications. 2. Features I 5 V supply voltage I Gain controlled wide-band VIF amplifier, AC-coupled I Multistandard true synchronous demodulation with active carrier regeneration: very linear demodulation, good intermodulation figures, reduced harmonics, and excellent pulse response I Gated phase detector for L and L-accent standard I Fully integrated VIF VCO, alignment-free, frequencies switchable for all negative and positive modulated standards via I2C-bus I Digital acquisition help, VIF frequencies of 33.4 MHz, 33.9 MHz, 38.0 MHz, 38.9 MHz, 45.75 MHz and 58.75 MHz I 4 MHz reference frequency input: signal from PLL tuning system or operating as crystal oscillator I VIF AGC detector for gain control, operating as peak sync detector for negative modulated signals and as a peak white detector for positive modulated signals I Mobile mode for negative modulation AGC (VIF and SIF) provides very fast reaction time I External AGC setting via pin AGCSW; VIF-AGC and SIF-AGC monitor outputs I Precise fully digital AFC detector with 4-bit digital-to-analog converter; AFC bits readable via I2C-bus I TOP adjustable via I2C-bus or alternatively with potentiometer I Fully integrated sound carrier trap for 4.5 MHz, 5.5 MHz, 6.0 MHz and 6.5 MHz; controlled by FM-PLL oscillator I SIF input for single reference QSS mode; PLL controlled I True split sound mode for sound demodulation at low RF level I SIF-AGC for gain controlled SIF amplifier, single reference QSS mixer able to operate in high performance single reference QSS mode and in intercarrier mode, switchable via I2C-bus I AM demodulator without extra reference circuit I Alignment-free selective FM-PLL demodulator with high linearity and low noise Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL I Four selectable I2C-bus addresses I I2C-bus control for all functions I I2C-bus transceiver with pin programmable MAD 3. Quick reference data Table 1. Symbol VP IP Video part Vi(VIF)(rms) GVIF(cr) fVIF VIF input voltage sensitivity (RMS value) VIF gain control range vision carrier operating frequencies -1 dB video at output see Figure 10 see Table 19 60 fVIF Vo(v)(p-p) VIF frequency window of digital related to fVIF; see Figure 7 acquisition help video output voltage (peak-to-peak value) see Figure 9 normal mode (sound carrier trap active) and sound carrier on trap bypass mode and sound carrier off Gdif differential gain 1.7 2.0 2.3 V 60 66 33.4 33.9 38.0 38.9 45.75 58.75 2.3 100 V dB MHz MHz MHz MHz MHz MHz MHz Quick reference data Parameter supply voltage supply current Conditions [1][2] Min 4.5 52 Typ 5.0 63 Max 5.5 70 Unit V mA 0.95 [3] 1.10 1.25 V "ITU-T J.63 line 330" B/G standard L standard 5 2 6 5 7 4 - % % deg MHz dif Bv(-1dB) differential phase -1 dB video bandwidth "ITU-T J.63 line 330" trap bypass mode and sound carrier off; AC load; CL < 20 pF; RL > 1 k ftrap = 4.5 MHz ftrap = 5.5 MHz ftrap = 6.0 MHz ftrap = 6.5 MHz [4] [4] [4] [4] Bv(-3dB)(trap) -3 dB video bandwidth including sound carrier trap 3.95 4.90 5.40 5.50 30 30 4.05 5.00 5.50 5.95 36 36 59 25 - MHz MHz MHz MHz dB dB dB dB SC1 S/NW PSRRCVBS attenuation at first sound carrier M/N standard; f = 4.5 MHz B/G standard; f = 5.5 MHz weighted signal-to-noise ratio see Figure 5 [5] 56 20 power supply ripple rejection at fripple = 70 Hz; video signal; pin CVBS grey level; positive and negative modulation; see Figure 8 Rev. 02 -- 12 May 2006 TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet 2 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Table 1. Symbol AFCstps Audio part Vo(AF)(rms) THD Quick reference data ...continued Parameter AFC control steepness AF output voltage (RMS value) total harmonic distortion Conditions definition: IAFC/fVIF 27 kHz FM deviation; 50 s de-emphasis FM: 27 kHz FM deviation; 50 s de-emphasis AM: m = 54 % without de-emphasis; measured with FM-PLL filter in Figure 23 Min 0.85 430 80 Typ 1.05 540 0.15 0.5 100 Max 1.25 650 0.50 1.0 Unit A/kHz mV % % kHz BAF(-3dB) -3 dB AF bandwidth S/NW(AF) weighted signal-to-noise ratio of FM-PLL only: audio signal 27 kHz FM deviation; 50 s de-emphasis AM: in accordance with "ITU-R BS.468-4" 52 56 - dB 45 40 50 46 - dB dB AM(sup) AM suppression of FM demodulator referenced to 27 kHz FM deviation; 50 s de-emphasis; AM: f = 1 kHz; m = 54 % fripple = 70 Hz; see Figure 8 for FM for AM PSRR power supply ripple rejection 14 20 90 90 [6] 20 26 140 140 75 180 180 - dB dB mV mV mV Vo(intc)(rms) IF intercarrier output level (RMS value) QSS mode; SC1; SC2 off L standard; without modulation intercarrier mode; PC/SC1 = 20 dB; SC2 off - Reference frequency input (pin REF) fref Vref(rms) reference signal frequency reference signal voltage (RMS value) operation as input terminal [7] 80 4 - 400 MHz mV [1] [2] [3] [4] [5] [6] Values of video and sound parameters can be decreased at VP = 4.5 V. For applications without I2C-bus, the time constant (R x C) at the supply must be > 1.2 s (e.g. 1 and 2.2 F). Condition: luminance range (5 steps) from 0 % to 100 %. AC load: CL < 20 pF and RL > 1 k. The sound carrier frequencies (depending on the TV standard) are attenuated by the integrated sound carrier traps (see Figure 16 to Figure 21; H (s) is the absolute value of transfer function). Measurement using unified weighting filter ("ITU-T J.61"), 200 kHz high-pass filter, 5 MHz low-pass filter and subcarrier notch filter ("ITU-T J.64"). The intercarrier output signal at pin SIOMAD can be calculated by the following formulae taking into account the internal video signal with 1.1 V (p-p) as a reference: V o ( intc ) ( rms ) = 1.1 x --------- x 10 V and r = ----- x --------------- ( dB ) + 6 dB 3 dB , where: --------- is 20 V 1 22 r 1 V i ( SC ) i ( PC ) 1 22 V i ( SC ) the correction term for RMS value, --------------- ( dB ) is the sound-to-picture carrier ratio at pins VIF1 and VIF2 in dB, 6 dB is the correction V i ( PC ) term of internal circuitry and 3 dB is the tolerance of video output and intercarrier output Vo(intc)(rms). [7] Pin REF is able to operate as a 1-pin crystal oscillator input as well as an external reference signal input, e.g. from the tuning system. TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 3 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 4. Ordering information Table 2. Ordering information Package Name TDA9884TS TDA9884HN SSOP24 HVQFN32 Description plastic shrink small outline package; 24 leads; body width 5.3 mm plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm Version SOT340-1 SOT617-3 Type number TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 4 of 58 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Product data sheet Rev. 02 -- 12 May 2006 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. TDA9884_2 5. Block diagram Philips Semiconductors CVAGC(pos) VIF-PLL filter VPLL 19 (21) external reference signal or 4 MHz crystal TOP 9 (8) TAGC 14 (15) CAGC(neg) VAGC 16 (17) CBL to pin OP2 REF 15 (16) AFC(1) 21 (23) TUNER AGC VIF-AGC RC VCO DIGITAL VCO CONTROL AFC DETECTOR VIF2 VIF1 2 (31) 1 (30) VIF-PLL SOUND CARRIER TRAPS 4.5 MHz to 6.5 MHz (18) 17 CVBS video output: 2 V (p-p) [1.1 V (p-p) without trap] TDA9884 (7) 8 SIF2 SIF1 24 (27) 23 (26) SINGLE REFERENCE QSS MIXER INTERCARRIER MIXER AND AM DEMODULATOR to pin AFC MAD (4) 6 SUPPLY SIF-AGC CAGC OUTPUT PORTS I 2C-BUS TRANSCEIVER NARROW-BAND FM-PLL DEMODULATOR AFD CAF AUDIO PROCESSING AND SWITCHES (3) 5 AUD DEEM de-emphasis network audio output I2C-bus controlled multistandard alignment-free IF-PLL 20 (22) VP 18 (20) 13 (14) AGND AGCSW 3 (1) OP1 22 (24) 11 (10) OP2 SCL 10 (9) SDA 7 (5) DGND 12 (11) SIOMAD 4 (2) FMPLL FM-PLL filter 001aae451 sound intercarrier output and MAD select TDA9884 Pin numbers for TDA9884HN in parentheses. (1) SIF-AGC monitor output at pin AFC. 5 of 58 Fig 1. Block diagram Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 6. Pinning information 6.1 Pinning VIF1 VIF2 OP1 FMPLL DEEM AFD DGND AUD TOP 1 2 3 4 5 6 7 8 9 24 SIF2 23 SIF1 22 OP2 21 AFC 20 VP 19 VPLL 18 AGND 17 CVBS 16 VAGC 15 REF 14 TAGC 13 AGCSW 001aae450 TDA9884TS SDA 10 SCL 11 SIOMAD 12 Fig 2. Pin configuration for SOT340-1 (SSOP24) 31 VIF2 30 VIF1 27 SIF2 26 SIF1 32 n.c. 29 n.c. 28 n.c. terminal 1 index area OP1 FMPLL DEEM AFD DGND n.c. AUD TOP 1 2 3 4 5 6 7 8 25 n.c. 24 OP2 23 AFC 22 VP 21 VPLL 20 AGND 19 n.c. 18 CVBS 17 VAGC REF 16 001aae449 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. TDA9884HN SCL 10 SIOMAD 11 n.c. 12 n.c. 13 AGCSW 14 Transparent top view Fig 3. Pin configuration for SOT617-3 (HVQFN32) 6.2 Pin description Table 3. Symbol VIF1 VIF2 n.c. OP1 TDA9884_2 Pin description Pin TDA9884TS 1 2 3 TDA9884HN 30 31 32 1 VIF differential input 1 VIF differential input 2 not connected output port 1; open-collector Description Product data sheet Rev. 02 -- 12 May 2006 TAGC 15 SDA 9 6 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Pin description ...continued Pin TDA9884TS TDA9884HN 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 FM-PLL for loop filter de-emphasis output for capacitor AF decoupling input for capacitor digital ground not connected audio output tuner AGC TakeOver Point (TOP) for resistor adjustment I2C-bus data input and output I2C-bus clock input sound intercarrier output and MAD select with resistor not connected not connected fast external AGC enable switch tuner AGC output 4 MHz crystal or reference signal input VIF-AGC capacitor for L standard composite video output not connected analog ground VIF-PLL for loop filter supply voltage AFC output output port 2; open-collector not connected SIF differential input 1 and MAD select with resistor SIF differential input 2 and MAD select with resistor not connected not connected 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Description Table 3. Symbol FMPLL DEEM AFD DGND n.c. AUD TOP SDA SCL SIOMAD n.c. n.c. AGCSW TAGC REF VAGC CVBS n.c. AGND VPLL VP AFC OP2 n.c. SIF1 SIF2 n.c. n.c. 7. Functional description Figure 1 shows the simplified block diagram of the device which comprises the following functional blocks: * VIF amplifier * Tuner AGC and VIF-AGC * VIF-AGC detector TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 7 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL * * * * * * * * * * * * * FPLL detector VCO and divider AFC and digital acquisition help Video demodulator and amplifier Sound carrier trap SIF amplifier SIF-AGC detector Single reference QSS mixer AM demodulator FM demodulator and acquisition help Audio amplifier and mute time constant Internal voltage stabilizer I2C-bus transceiver and MAD 7.1 VIF amplifier The VIF amplifier consists of three AC-coupled differential stages. Gain control is performed by emitter degeneration. The total gain control range is typically 66 dB. The differential input impedance is typically 2 k in parallel with 3 pF. 7.2 Tuner AGC and VIF-AGC This block adapts the voltages, generated at the VIF-AGC and SIF-AGC detectors, to the internal signal processing at the VIF and SIF amplifiers and performs the tuner AGC control current generation. Normally it is derived from the VIF-AGC, for the true split sound mode it is derived from the SIF-AGC. The onset of the tuner AGC control current generation can be set either via the I2C-bus (see Table 16) or optionally by a potentiometer at pin TOP (in case that the I2C-bus information cannot be stored). The presence of a potentiometer is automatically detected and the I2C-bus setting is disabled. Furthermore, derived from the AGC detector voltage, a comparator is used to test if the corresponding VIF input voltage is higher than 200 V. This information can be read out via the I2C-bus (bit VIFLEV = 1). 7.3 VIF-AGC detector Gain control is performed by sync level detection (negative modulation) or peak white detection (positive modulation). For negative modulation, the sync level voltage is compared with a reference voltage (nominal sync level) by a comparator which charges or discharges the integrated AGC capacitor directly for the generation of the required VIF gain. With mobile mode the currents are increased by a factor of approximately 8 for very fast reaction. By use of an AGC event detector, the gain increase time constant (discharge current) additionally reduces in with a too-low VIF signal. For positive modulation, the white peak level voltage is compared with a reference voltage (nominal white level) by a comparator which charges (fast) or discharges (slow) the external AGC capacitor directly for the generation of the required VIF gain. The need of a TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 8 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL very long time constant for VIF gain increase is because the peak white level may appear only once in a field. In order to reduce this time constant, an additional level detector increases the discharging current of the AGC capacitor (fast mode) in the event of a decreasing VIF amplitude step controlled by the detected actual black level voltage. The threshold level for fast mode AGC is typically -6 dB video amplitude. The fast mode state is also transferred to the SIF-AGC detector for speed-up. In case of missing peak white pulses, the VIF gain increase is limited to typically +3 dB by comparing the detected actual black level voltage with a corresponding reference voltage. 7.4 FPLL detector The VIF amplifier output signal is fed into a frequency detector and into a phase detector via a limiting amplifier for removing the video AM. During acquisition the frequency detector produces a current proportional to the frequency difference between the VIF and the VCO signals. After frequency lock-in the phase detector produces a current proportional to the phase difference between the VIF and the VCO signals. The currents from the frequency and phase detectors are charged into the loop filter which controls the VIF VCO and locks it to the frequency and phase of the VIF carrier. For a positive modulated VIF signal, the charging currents are gated by the composite sync in order to avoid signal distortion in case of overmodulation. The gating depth is switchable via the I2C-bus. 7.5 VCO and divider The VCO of the VIF-FPLL operates as an integrated low radiation relaxation oscillator at double the picture carrier frequency. The control voltage, required to tune the VCO to double the picture carrier frequency, is generated at the loop filter by the frequency phase detector. The possible frequency range is 50 MHz to 140 MHz (typical value). The oscillator frequency is divided-by-two to provide two differential square wave signals with exactly 90 degrees phase difference, independent of the frequency, for use in the FPLL detectors, the video demodulator and the intercarrier mixer. 7.6 AFC and digital acquisition help Each relaxation oscillator of the VIF-PLL and FM-PLL demodulator has a wide frequency range. To prevent false locking of the PLLs and with respect to the catching range, the digital acquisition help provides an individual control, until the frequency of the VCO is within the preselected standard dependent lock-in window of the PLL. The in-window and out-window control at the FM-PLL is additionally used to mute the audio stage (if auto mute is selected via the I2C-bus). The working principle of the digital acquisition help is as follows. The PLL VCO output is connected to a down counter which has a predefined start value (standard dependent). The VCO frequency clocks the down counter for a fixed gate time. Thereafter, the down counter stop value is analyzed. In case the stop value is higher (lower) than the expected value range, the VCO frequency is lower (higher) than the wanted lock-in window frequency range. A positive (negative) control current is injected into the PLL loop filter and consequently the VCO frequency is increased (decreased) and a new counting cycle starts. TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 9 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL The gate time as well as the control logic of the acquisition help circuit is dependent on the precision of the reference signal at pin REF. Operation as a crystal oscillator is possible as well as connecting this input via a serial capacitor to an external reference frequency, e.g. the tuning system oscillator. The AFC signal is derived from the corresponding down counter stop value after a counting cycle. The last four bits are latched and can be read out via the I2C-bus (see Table 10). Also the digital-to-analog converted value is given as current at pin AFC. 7.7 Video demodulator and amplifier The video demodulator is realized by a multiplier which is designed for low distortion and large bandwidth. The VIF signal is multiplied with the `in phase' signal of the VIF-PLL VCO. The demodulator output signal is fed into the video preamplifier via a level shift stage with integrated low-pass filter to achieve carrier harmonics attenuation. The output signal of the preamplifier is fed to the VIF-AGC detector (see Section 7.3) and in the sound trap mode also fed internally to the integrated sound carrier trap (see Section 7.8). The differential trap output signal is converted and amplified by the following post-amplifier. The video output level at pin CVBS is 2 V (p-p). In the bypass mode the output signal of the preamplifier is fed directly through the post-amplifier to pin CVBS. The output video level is 1.1 V (p-p) for using an external sound trap with 10 % overall loss. Noise clipping is provided in both cases. 7.8 Sound carrier trap The sound carrier trap consists of a reference filter, a phase detector and the sound trap itself. A sound carrier reference signal is fed into the reference low-pass filter and is shifted by nominal 90 degrees. The phase detector compares the original reference signal with the signal shifted by the reference filter and produces a DC voltage by charging or discharging an integrated capacitor with a current proportional to the phase difference between both signals, respectively to the frequency error of the integrated filters. The DC voltage controls the frequency position of the reference filter and the sound trap. So the accurate frequency position for the different standards is set by the sound carrier reference signal. The sound trap itself is constructed of three separate traps to realize sufficient suppression of the first and second sound carriers. 7.9 SIF amplifier The SIF amplifier consists of three AC-coupled differential stages. Gain control is performed by emitter degeneration. The total gain control range is typically 66 dB. The differential input impedance is typically 2 k in parallel with 3 pF. TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 10 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 7.10 SIF-AGC detector SIF gain control is performed by the detection of the DC component of the AM demodulator output signal. This DC signal corresponds directly to the SIF voltage at the output of the SIF amplifier so that a constant SIF signal is supplied to the AM demodulator and to the single reference QSS mixer. By switching the gain of the input amplifier of the SIF-AGC detector via the I2C-bus, the internal SIF level for FM sound is 5.5 dB lower than for AM sound. This is to adapt the SIF-AGC characteristic to the VIF-AGC characteristic. The adaption is ideal for a picture-to-sound FM carrier ratio of 13 dB. Via a comparator, the integrated AGC capacitor is charged or discharged for the generation of the required SIF gain. Due to AM sound, the AGC reaction time is slow (fc < 20 Hz for the closed AGC loop). For reducing this AM sound time constant in the event of a decreasing IF amplitude step, the charging and discharging currents of the AGC capacitor are increased by a factor of 12 (fast mode) when the VIF-AGC detector (at positive modulation mode) operates in the fast mode too. An additional circuit (threshold approximately 7 dB) ensures a very fast gain reduction for a large increasing IF amplitude step. For negative modulation and QSS mode the AGC also is set to fast mode. For negative modulation and mobile mode the currents are increased additionally by a factor of 36. 7.11 Single reference QSS mixer With the present system a high performance Hi-Fi stereo sound processing can be achieved. For a simplified application without a SIF SAW filter, the single reference QSS mixer can be switched to the intercarrier mode via the I2C-bus. The single reference QSS mixer generates the 2nd FM TV sound intercarrier signal. It is realized by a linear multiplier which multiplies the SIF amplifier output signal and the VIF-PLL VCO signal (90 degrees output) which is locked to the picture carrier. In this way the QSS mixer operates as a quadrature mixer in the intercarrier mode and provides suppression of the low frequency video signals. In the true split sound mode the VIF-PLL VCO is locked by a synthesizer. By this the 2nd FM TV sound intercarrier signal is generated independently from the vision carrier so that in the case of a low RF level, the sound demodulation is possible where the VIF-PLL would unlock. In the true split sound mode the VIF demodulation is not available. The QSS mixer output signal is fed internally via a high-pass and low-pass combination to the FM demodulator as well as via an operational amplifier to the intercarrier output pin SIOMAD. 7.12 AM demodulator The amplitude modulated SIF amplifier output signal is fed both to a two-stage limiting amplifier that removes the AM and to a linear multiplier. The result of the multiplication of the SIF signal with the limiter output signal is AM demodulation (passive synchronous demodulator). The demodulator output signal is fed via a low-pass filter that attenuates the carrier harmonics and via the input amplifier of the SIF-AGC detector to the audio amplifier. TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 11 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 7.13 FM demodulator and acquisition help The narrow-band FM-PLL detector consists of: * Gain controlled FM amplifier and AGC detector * Narrow-band PLL The intercarrier signal from the intercarrier mixer is fed to the input of an AC-coupled gain controlled amplifier with two stages. The gain controlled output signal is fed to the phase detector of the narrow-band FM-PLL (FM demodulator). For good selectivity and robustness against disturbance caused by the video signal, a high linearity of the gain controlled FM amplifier and of the phase detector as well as a constant signal level are required. The gain control is done by means of an `in phase' demodulator for the FM carrier (from the output of the FM amplifier). The demodulation output is fed into a comparator for charging or discharging the integrated AGC capacitor. This leads to a mean value AGC loop to control the gain of the FM amplifier. The FM demodulator is realized as a narrow-band PLL with an external loop filter, which provides the necessary selectivity (bandwidth approximately 100 kHz). To achieve good selectivity, a linear phase detector and a constant input level are required. The gain controlled intercarrier signal from the FM amplifier is fed to the phase detector. The phase detector controls via the loop filter the integrated low radiation relaxation oscillator. The designed frequency range is from 4 MHz to 7 MHz. The VCO within the FM-PLL is phase-locked to the incoming 2nd SIF signal, which is frequency modulated. As well as this, the VCO control voltage is superimposed by the AF voltage. Therefore, the VCO tracks with the FM of the 2nd SIF signal. So, the AF voltage is present at the loop filter and is typically 5 mV (RMS) for 27 kHz FM deviation. This AF signal is fed via a buffer to the audio amplifier. The correct locking of the PLL is supported by the digital acquisition help circuit (see Section 7.6). 7.14 Audio amplifier and mute time constant The audio amplifier consists of two parts: * AF preamplifier * AF output amplifier The AF preamplifier used for FM sound is an operational amplifier with internal feedback, high gain and high common mode rejection. The AF voltage from the PLL demodulator is 5 mV (RMS) for a frequency deviation of 27 kHz and is amplified by 30 dB. By the use of a DC operating point control circuit (with external capacitor CAF), the AF preamplifier is decoupled from the PLL DC voltage. The low-pass characteristic of the amplifier reduces the harmonics of the sound intercarrier signal at the AF output terminal. For FM sound a switchable de-emphasis network (with external capacitor) is implemented between the preamplifier and the output amplifier. The AF output amplifier provides the required AF output level by a rail-to-rail output stage. A preceding stage makes use of an input selector for switching between FM sound, AM sound and mute state. The gain can be switched between 10 dB (normal) and 4 dB (reduced). TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 12 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Switching to the mute state is controlled automatically, dependent on the digital acquisition help in case the VCO of the FM-PLL is not in the required frequency window. This is done by a time constant: fast for switching to the mute state and slow (typically 40 ms) for switching to the no-mute state. All switching functions are controlled via the I2C-bus: * * * * AM sound, FM sound and forced mute Auto mute enable or disable De-emphasis off or on with 50 s or 75 s Audio gain normal or reduced 7.15 Internal voltage stabilizer The band gap circuit internally generates a voltage of approximately 2.4 V, independent of supply voltage and temperature. A voltage regulator circuit, connected to this voltage, produces a constant voltage of 3.55 V which is used as an internal reference voltage. 7.16 I2C-bus transceiver and module address The device can be controlled via the 2-wire I2C-bus by a microcontroller. Two wires carry serial data (SDA) and serial clock (SCL) information between the devices connected to the I2C-bus. The device has an I2C-bus slave transceiver with auto-increment. The circuit operates up to clock frequencies of 400 kHz. A slave address is sent from the master to the slave receiver. To avoid conflicts in a real application with other devices providing similar or complementing functions, there are four possible slave addresses available. These Module Addresses (MADs) can be selected by connecting resistors on pin SIOMAD and/or pins SIF1 and SIF2 (see Figure 23). Pin SIOMAD relates to bit A0 and pins SIF1 and SIF2 relate to bit A3. The slave addresses of this device are given in Table 4. The power-on preset value is dependent on the use of pin SIOMAD and can be chosen for 45.75 MHz NTSC as default (pin SIOMAD left open-circuit) or 58.75 MHz NTSC (resistor on pin SIOMAD). In this way the device can be used without the I2C-bus as an NTSC only device. Remark: In case of using the device without the I2C-bus, then the rise time of the supply voltage after switching on power must be longer than 1.2 s. Table 4. Slave address detection Selectable address bit A3 MAD1 MAD2 MAD3 MAD4 0 0 1 1 A0 1 0 1 0 Resistor on pin SIF1 and SIF2 no no yes yes SIOMAD no yes no yes Slave address TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 13 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 8. I2C-bus control 8.1 Read format Table 5. S I2C-bus read format (slave transmits data) A 1 Byte 2 D7 D6 D5 D4 D3 D2 D1 D0 data AN P Byte 1 A6 A5 A4 A3 A2 A1 A0 R/W slave address Table 6. Symbol S Slave address R/W = 1 A Data AN P Explanation of Table 5 Function START condition, generated by the master see Table 7 read command, generated by the master acknowledge bit, generated by the slave 8-bit data word, transmitted by the slave, see Table 8 acknowledge-not bit, generated by the master STOP condition, generated by the master The master generates an acknowledge when it has received the dataword READ. The master next generates an acknowledge, then slave begins transmitting the dataword READ, and so on until the master generates an acknowledge-not bit and transmits a STOP condition. 8.1.1 Slave address The first module address MAD1 is the standard address, see Table 4. Table 7. Symbol MAD1 MAD2 MAD3 MAD4 [1] [2] Slave addresses[1][2] Value (hex) Bit A6 43 42 4B 4A 1 1 1 1 A5 0 0 0 0 A4 0 0 0 0 A3 0 0 1 1 A2 0 0 0 0 A1 1 1 1 1 A0 1 0 1 0 For MAD activation via external resistor: see Table 4 and Figure 23. For applications without I2C-bus: see Table 21 and Table 22. 8.1.2 Data byte Table 8. MSB D7 AFCWIN D6 VIFLEV D5 D4 D3 AFC3 D2 AFC2 D1 AFC1 CARRDET AFC4 Data read register (status register) LSB D0 PONR TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 14 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Description of status register bits Value 1 0 Description AFC window VCO in 1.6 MHz AFC window[1] VCO out of 1.6 MHz AFC window VIF input level 1 0 high level; VIF input voltage 200 V (typically) low level FM carrier detection 1 0 detection no detection automatic frequency control see Table 10 power-on reset 1 0 after power-on reset or after supply breakdown after a successful reading of the status register Table 9. Symbol AFCWIN VIFLEV CARRDET AFC[4:1] PONR [1] If no IF input is applied, then bit AFCWIN = 1 due to the fact that the VCO is forced to the AFC window border for fast lock-in behavior. Table 10. Bit AFC4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 [1] Automatic frequency control bits[1] fVIF AFC3 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 AFC2 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 AFC1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (f0 - 187.5 kHz) f0 - 162.5 kHz f0 - 137.5 kHz f0 - 112.5 kHz f0 - 87.5 kHz f0 - 62.5 kHz f0 - 37.5 kHz f0 - 12.5 kHz f0 + 12.5 kHz f0 + 37.5 kHz f0 + 62.5 kHz f0 + 87.5 kHz f0 + 112.5 kHz f0 + 137.5 kHz f0 + 162.5 kHz (f0 + 187.5 kHz) f0 is the nominal frequency of fVIF. TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 15 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 8.2 Write format Table 11. S I2C-bus write format (slave receive data)[1] A R/W 0 Byte 2 A7 to A0 subaddress A Byte 3 bits 7 to 0 data 1 A Byte n bits 7 to 0 data 1 A P Byte 1 A6 to A0 slave address [1] The auto-increment of the subaddress stops if the subaddress is 3. Table 12. Symbol S Explanation of Table 11 Function START condition, generated by the master see Table 7 write command, generated by the master acknowledge bit, generated by the slave see Table 13 8-bit data words, transmitted by the master (see Table 14, Table 15 and Table 17) STOP condition Slave address R/W = 0 A Subaddress (SAD) Data 1, data n P 8.2.1 Subaddress If more than one data byte is transmitted, then auto-increment is performed: starting from the transmitted subaddress and auto-increment of subaddress in accordance with the order of Table 13. Table 13. Register SAD for switching mode SAD for adjust mode SAD for data mode [1] [2] [3] X = don't care. Bit A7 = 1 is not allowed. Bits A6 to A2 will be ignored by the internal hardware. Definition of the subaddress (second byte after slave address)[1] MSB A7[2] 0 0 0 A6[3] X X X A5[3] X X X A4[3] X X X A3[3] X X X A2[3] X X X A1 0 0 1 LSB A0 0 1 0 8.2.2 Data byte for switching mode Table 14. Bit B7 1 0 B6 1 0 TDA9884_2 Bit description of SAD register for switching mode (SAD = 00) Value Description output port 2 e.g. for SAW switching or AGC monitoring high-impedance, disabled or HIGH low-impedance, active or LOW output port 1 e.g. for SAW switching or external AGC input high-impedance, disabled or HIGH low-impedance, active or LOW (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 16 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Bit description of SAD register for switching mode (SAD = 00) ...continued Value 0 1 Description forced audio mute on off TV standard modulation and mobile mode 00 01 10 11 positive AM TV[1] positive AM TV[1][2] negative FM TV negative TV mobile mode[2][3] carrier mode 1 0 QSS mode intercarrier mode auto mute of FM AF output 1 0 active inactive video mode (sound trap) 1 0 sound trap bypass sound trap active Table 14. Bit B5 B4 and B3 B2 B1 B0 [1] [2] [3] For positive AM TV choose 6.5 MHz for the second SIF. SIF-AGC monitor output at pin AFC. AGC (VIF/SIF) provides very fast reaction time. 8.2.3 Data byte for adjust mode Table 15. Bit C7 1 0 C6 1 0 C5 1 0 C4 to C0 Bit description of SAD register for adjust mode (SAD = 01) Value Description audio gain -6 dB 0 dB de-emphasis time constant 50 s 75 s de-emphasis on off tuner takeover point adjustment see Table 16 TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 17 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Tuner takeover point adjustment bits C3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 C2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 C1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 C0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Top adjustment (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0[1] -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 Table 16. Bit C4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [1] 0 dB is equal to 17 mV (RMS). TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 18 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 8.2.4 Data byte for data mode Table 17. Bit E7 E6 1 0 1 0 E5 E4 to E2 E1 and E0 00 01 10 11 Table 18. Options Bit E7 = 1 Bit E5 = 1 Bit E5 = 0 port function VIF-AGC output[1][2][3] Bit E5 = 1 VIF-AGC external input[1][2][3] VIF-AGC output[1][2][3] external gain Bit E5 = 0 Pin OP1 Pin OP2 Gain [1] [2] [3] Bit description of SAD register for data mode (SAD = 10) Value Description VIF-AGC features dependent on bit E5; see Table 18 L standard PLL gating gating in case of 36 % positive modulation (B4 = 0) gating in case of 0 % positive modulation (B4 = 0) optimum for multipath condition (B4 = 1) optimum for overmodulation condition (B4 = 1) VIF, SIF and tuner minimum gain dependent on bit E7; see Table 18 vision intermediate frequency selection see Table 19 and Table 20 sound intercarrier frequency selection (sound 2nd IF); only valid for setting of bit E4 to bit E2 according to Table 19 fFM = 4.5 MHz fFM = 5.5 MHz fFM = 6.0 MHz fFM = 6.5 MHz (for positive modulation choose 6.5 MHz) Function Bit E7 = 0 port function port function port function port function normal gain minimum gain normal gain The corresponding port function has to be disabled (set to `high-impedance'); see Table 14. If selected by the I2C-bus, the VIF-AGC voltage can be monitored at pin OP2. In this case, OP2 cannot be used for the normal port function. If selected by the I2C-bus, pin OP1 can alternatively be used for external AGC control, activated by pin AGCSW. In this case, OP1 cannot be used for the normal port function. Table 19. E4 0 0 0 0 1 1 [1] TV standard selection for VIF fVIF (MHz) E3 0 0 1 1 0 0 E2 0 1 0 1 0 1 58.75[1] 45.75[1] 38.9 38.0 33.9 33.4 Video IF select bits Pin SIOMAD can be used for the selection of the different NTSC standards without I2C-bus. With a resistor on pin SIOMAD, fVIF = 58.75 MHz; without a resistor on pin SIOMAD, fVIF = 45.75 MHz (NTSC-M). (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. TDA9884_2 Product data sheet Rev. 02 -- 12 May 2006 19 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL True split sound mode Bit E4 1 1 1 1 E3 1 1 1 1 E2 1 1 0 0 E1 0 1 0 1 E0 1 1 0 0 Function fsynth (MHz) 40 40 36 36 Sound 2nd IF fFM (MHz) 5.6 6.6 3.1 3.6 Table 20. TV standard M/N B/G I D/K Table 21. Register Data setting after power-on reset (default setting with a resistor on pin SIOMAD) MSB D7 D6 1 0 0 D5 0 1 0 D4 1 1 0 D3 0 0 0 D2 1 0 0 D1 1 0 0 1 0 0 LSB D0 0 0 0 Switching mode Adjust mode Data mode Table 22. Register Switching mode Adjust mode Data mode Data setting after power-on reset (default setting without a resistor on pin SIOMAD) MSB D7 1 0 0 D6 1 0 0 D5 0 1 0 D4 1 1 0 D3 0 0 0 D2 1 0 1 D1 1 0 0 LSB D0 0 0 0 For selection of the different NTSC standards without I2C-bus, an application on pin SIOMAD is used (see Figure 23). Without a resistor, NTSC-M is selected (fVIF = 45.75 MHz); with a resistor, the VIF frequency is 58.75 MHz (see Table 19). 9. Limiting values Table 23. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VP Vn Parameter supply voltage voltage on pins VIF1, VIF2, OP1, FMPLL, AGCSW, VP, AFC, OP2, SIF1 and SIF2 pin TAGC tsc Tstg Tamb Vesd short-circuit time to ground or VP storage temperature ambient temperature electrostatic discharge voltage machine model human body model [1] [2] Conditions Min 0 Max 5.5 VP Unit V V 0 -25 -20 -400 -4000 8.8 10 +150 +70 +400 +4000 V s C C V V [1] [2] TDA9884_2 Class C according to EIA/JESD22-A115-A. Class 3A according to JESD22-A114-B. (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 20 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 10. Thermal characteristics Table 24. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient TDA9884TS (SSOP24) TDA9884HN (HVQFN32) in free air in free air 118 40 K/W K/W Conditions Typ Unit 11. Characteristics Table 25. Characteristics VP = 5 V; Tamb = 25 C; see Table 27 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 23; unless otherwise specified. Symbol Supply (pin VP) VP IP Ptot supply voltage supply current total power dissipation supply voltage for start of reset supply voltage for end of reset time constant (R x C) for network at pin VP VIF input voltage sensitivity (RMS value) decreasing supply voltage increasing supply voltage; I2C-bus transmission enable for applications without I2C-bus [1][2] Parameter Conditions Min 4.5 52 - Typ 5.0 63 305 Max 5.5 70 385 Unit V mA mW Power-On Reset (POR) VP(start) VP(stop) 2.5 3.0 3.5 4.4 V V P 1.2 - - s VIF amplifier (pins VIF1 and VIF2) Vi(VIF)(rms) -1 dB video at output 60 100 V Vi(max)(rms) Vi(ovl)(rms) VIF(int) maximum input +1 dB video at output voltage (RMS value) overload input voltage (RMS value) internal IF amplitude within AGC range; f = 5.5 MHz difference between picture and sound carrier VIF gain control range lower limit -3 dB VIF bandwidth upper limit -3 dB VIF bandwidth Rev. 02 -- 12 May 2006 [3] 150 - 190 0.7 440 - mV mV dB GVIF(cr) BVIF(-3dB)(ll) BVIF(-3dB)(ul) TDA9884_2 see Figure 10 60 - 66 15 80 - dB MHz MHz (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet 21 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Table 25. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 27 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 23; unless otherwise specified. Symbol Ri(dif) Ci(dif) VI fVCO(max) Parameter differential input resistance differential input capacitance DC input voltage demodulator[5] f = 2fPC 120 140 MHz maximum oscillator frequency for carrier regeneration vision carrier operating frequencies Conditions [4] Min - Typ 2 3 1.93 Max - Unit k pF V [4] FPLL and true synchronous video fVIF see Table 19 - 33.4 33.9 38.0 38.9 45.75 58.75 2.3 - MHz MHz MHz MHz MHz MHz MHz fVIF VIF frequency window of digital acquisition help acquisition time input voltage sensitivity for PLL to be locked (RMS value) cycle time of digital acquisition help VIF VCO steepness VIF phase detector steepness related to fVIF; see Figure 7 - tacq Vi(lock)(rms) BL = 70 kHz measured on pins VIF1 and VIF2; maximum IF gain [6] - 30 30 70 ms V Tcy(DAH) KO(VIF) KD(VIF) definition: fVIF/VVPLL definition: IVPLL/VIF - 64 20 23 - s MHz/V A/rad Video output 2 V (pin CVBS) Normal mode (sound carrier trap active) and sound carrier on Vo(v)(p-p) Vo V/S video output voltage see Figure 9 (peak-to-peak value) video output voltage difference ratio between video (black-to-white) and sync level sync voltage level upper video clipping voltage level lower video clipping voltage level difference between L and B/G standard 1.7 -12 1.90 2.0 2.33 2.3 +12 3.00 V % Vsync Vclip(u) Vclip(l) TDA9884_2 1.0 1.2 1.4 0.9 V V V VP - 1.1 VP - 1 0.7 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 22 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Table 25. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 27 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 23; unless otherwise specified. Symbol Ro Ibias(int) Parameter output resistance internal DC bias current for emitter-follower maximum AC and DC output sink current maximum AC and DC output source current deviation of CVBS output voltage black level tilt 50 dB gain control 30 dB gain control negative modulation Conditions [4] Min 1.5 Typ 2.0 Max 30 - Unit mA Io(sink)(max) 1 - - mA Io(source)(max) 3.9 - - mA Vo(CVBS) Vo(bl) Vo(bl)(v) - - 0.5 0.1 1 3 dB dB % % vertical black level tilt vision carrier modulated by for worst case in test line (VITS) only L standard differential gain Gdif "ITU-T J.63 line 330" B/G standard L standard [7] [8] 2 59 51 5 7 4 - % % deg dB dB dif S/NW S/NUW IM(blue) differential phase weighted signal-to-noise ratio unweighted signal-to-noise ratio intermodulation attenuation at `blue' "ITU-T J.63 line 330" see Figure 5 56 47 [9] see Figure 6 f = 1.1 MHz f = 3.3 MHz see Figure 6 f = 1.1 MHz f = 3.3 MHz fundamental wave and harmonics [10] 58 58 [10] 64 64 66 65 2 - 5 12 dB dB dB dB mV kHz IM(yellow) intermodulation attenuation at `yellow' residual picture carrier (RMS value) 60 59 [4] Vr(PC)(rms) funw(p-p) 3 % residual carrier; robustness for unwanted frequency 50 % serration pulses; L standard deviation of picture carrier (peak-to-peak value) robustness for 0 % residual carrier; modulator imbalance 50 % serration pulses; L standard; L-gating = 0 % suppression of video AC load; CL < 20 pF; signal harmonics RL > 1 k - [4] - - 3 % H [11] 35 40 - dB TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 23 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Table 25. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 27 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 23; unless otherwise specified. Symbol spur PSRRCVBS Parameter suppression of spurious elements power supply ripple rejection at pin CVBS fripple = 70 Hz; video signal; grey level; positive and negative modulation; see Figure 8 ftrap = 4.5 MHz [13] Conditions [12] Min 40 20 Typ 25 Max - Unit dB dB M/N standard including Korea; see Figure 16 Bv(-3dB)(trap) -3 dB video bandwidth including sound carrier trap attenuation at first sound carrier attenuation at first sound carrier fSC1 60 kHz 3.95 4.05 MHz SC1 SC1(60kHz) f = 4.5 MHz f = 4.5 MHz 30 21 36 27 - dB dB SC2 SC2(60kHz) attenuation at f = 4.724 MHz second sound carrier f = 4.724 MHz attenuation at second sound carrier fSC2 60 kHz group delay at color carrier frequency -3 dB video bandwidth including sound carrier trap attenuation at first sound carrier attenuation at first sound carrier fSC1 60 kHz f = 3.58 MHz; see Figure 17 ftrap = 5.5 MHz [13] 21 15 27 21 - dB dB td(g)(cc) 110 180 250 ns B/G standard; see Figure 18 Bv(-3dB)(trap) 4.90 5.00 MHz SC1 SC1(60kHz) f = 5.5 MHz f = 5.5 MHz 30 24 36 30 - dB dB SC2 SC2(60kHz) attenuation at f = 5.742 MHz second sound carrier attenuation at f = 5.742 MHz second sound carrier fSC2 60 kHz group delay at color carrier frequency -3 dB video bandwidth including sound carrier trap attenuation at first sound carrier f = 4.43 MHz; see Figure 19 ftrap = 6.0 MHz [13] 21 15 27 21 - dB dB td(g)(cc) 110 180 250 ns I standard; see Figure 20 Bv(-3dB)(trap) 5.40 5.50 MHz SC1 f = 6.0 MHz 26 32 - dB TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 24 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Table 25. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 27 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 23; unless otherwise specified. Symbol SC1(60kHz) Parameter attenuation at first sound carrier fSC1 60 kHz Conditions f = 6.0 MHz Min 20 Typ 26 Max Unit dB SC2 SC2(60kHz) attenuation at f = 6.55 MHz second sound carrier f = 6.55 MHz attenuation at second sound carrier fSC2 60 kHz group delay at color carrier frequency -3 dB video bandwidth including sound carrier trap attenuation at first sound carrier attenuation at first sound carrier fSC1 60 kHz f = 4.43 MHz 12 10 18 15 - dB dB td(g)(cc) - 90 160 ns D/K standard; see Figure 21 Bv(-3dB)(trap) ftrap = 6.5 MHz [13] 5.50 5.95 - MHz SC1 SC1(60kHz) f = 6.5 MHz f = 6.5 MHz 26 20 32 26 - dB dB SC2 SC2(60kHz) attenuation at f = 6.742 MHz second sound carrier attenuation at f = 6.742 MHz second sound carrier fSC2 60 kHz group delay at color carrier frequency f = 4.28 MHz 18 13 24 18 - dB dB td(g)(cc) - 60 130 ns Video output 1.1 V (pin CVBS) Trap bypass mode and sound carrier off[14] Vo(v)(p-p) Vsync Vclip(u) Vclip(l) Bv(-1dB) Bv(-3dB) S/NW S/NUW video output voltage see Figure 9 (peak-to-peak value) sync voltage level upper video clipping voltage level lower video clipping voltage level -1 dB video bandwidth -3 dB video bandwidth weighted signal-to-noise ratio unweighted signal-to-noise ratio AC load; CL < 20 pF; RL > 1 k AC load; CL < 20 pF; RL > 1 k Figure 5 [8] 0.95 1.35 3.5 5 7 56 48 1.10 1.5 3.6 0.9 6 8 59 52 1.25 1.6 1.0 - V V V V MHz MHz dB dB [9] TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 25 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Table 25. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 27 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 23; unless otherwise specified. Symbol VIF-AGC[15] tresp(inc) AGC response time to an increasing VIF step negative modulation; normal mode negative modulation; mobile mode positive modulation; VIF step: 20 dB tresp(dec) AGC response time to a decreasing VIF step negative modulation normal mode fast normal mode mobile mode fast mobile mode positive modulation normal mode; VIF step: 20 dB normal mode fast mode Vi(VIF) VIF amplitude step for activating AGC fast mode gain control voltage range control steepness L standard [16] [16] [16][17] [16] [16][17] [16] Parameter Conditions Min - Typ 4.3 1.5 2.6 Max - Unit s/dB s/dB ms [16] [16] -2 1.9 0.08 0.25 0.01 890 143 2.6 -6 -10 ms/dB ms/dB ms/dB ms/dB ms ms/dB ms/dB dB [16] [16][18] VVAGC CRstps Vth(VIF) Pin VAGC Ich(max) Ich(add) see Figure 10 definition: GVIF/VVAGC; VVAGC = 2 V to 3 V 0.8 120 -80 200 3.5 320 V dB/V V threshold voltage for see Table 8 and Table 9 high level VIF input maximum charge current additional charge current discharge current AGCSW)[19]; L standard L standard: in the event of missing VITS pulses and no white video content L standard; normal mode L standard; fast mode - 100 100 - A nA Idch 2.5 8 35 1.8 - 0.3 - nA A V V k AGC input switch (pin Vext(AGCOFF) Vext(AGCON) Ri see Table 18 voltage level for bit E5 = 1; bit E7 = 1 external AGC = OFF voltage level for external AGC = ON input resistance bit E5 = 1; bit E7 = 1 bit E5 = 1; bit E7 = 1 TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 26 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Table 25. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 27 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 23; unless otherwise specified. Symbol Ii Vi td1 td2 Parameter input current input voltage switching delay for external AGC = ON Conditions bit E5 = 1; bit E7 = 1; VAGCSW = 0 V bit E5 = 1; bit E7 = 1; pin AGCSW open-circuit bit E5 = 1; bit E7 = 1; VAGCSW = 2.5 V Min Typ 5 Max 150 150 Unit A V ns ns VP - 1.7 - switching delay for bit E5 = 1; bit E7 = 1; external AGC = OFF VAGCSW = 0.3 V VIF input signal voltage for minimum starting point of tuner takeover at pins VIF1 and VIF2 (RMS value) ITAGC = 120 A; RTOP = 22 k or no RTOP and -15 dB via I2C-bus (see Table 16) Tuner AGC (pin TAGC); see Figure 4, Figure 10 and Figure 11 Vi(VIF)(start1)(rms) 2 5 mV Vi(VIF)(start2)(rms) ITAGC = 120 A; RTOP = 0 VIF input signal voltage for maximum or no RTOP and +15 dB via starting point of I2C-bus (see Table 16) tuner takeover at pins VIF1 and VIF2 (RMS value) SIF input signal voltage for minimum starting point of tuner takeover at pins SIF1 and SIF2 (RMS value) SIF input signal voltage for maximum starting point of tuner takeover at pins SIF1 and SIF2 (RMS value) tuner takeover point accuracy true split sound mode; ITAGC = 120 A; RTOP = 22 k or no RTOP and -15 dB via I2C-bus (see Table 16) true split sound mode; ITAGC = 120 A; RTOP = 0 or no RTOP and +15 dB via I2C-bus (see Table 16) 45 90 - mV Vi(SIF)(start1)(rms) - 1 2.5 mV Vi(SIF)(start2)(rms) 22.5 45 - mV QVTOP ITAGC = 120 A; RTOP = 10 k; or no RTOP and 0 dB via I2C-bus (see Table 16) normal mode true split sound mode 7 4 17 9 0.03 43 22 0.07 mV mV dB/K QVTOP/T takeover point variation with temperature permissible output voltage saturation voltage ITAGC = 120 A Vo Vsat TDA9884_2 from external source ITAGC = 450 A - - 8.8 0.5 V V (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 27 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Table 25. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 27 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 23; unless otherwise specified. Symbol Isink Parameter sink current Conditions no tuner gain reduction; VTAGC = 8.8 V maximum tuner gain reduction; VTAGC = 1 V GIF IF slip by automatic gain control lower limit saturation voltage lower limit saturation voltage output source current output sink current AFC control steepness analog accuracy of AFC circuit digital accuracy of AFC circuit via I2C-bus SIF-AGC monitor source current SIF-AGC monitor sink current SIF input voltage sensitivity (RMS value) FM mode; -3 dB at intercarrier output pin SIOMAD AM mode; -3 dB at AF output pin AUD Vi(max)(rms) maximum input FM mode; 1 dB at voltage (RMS value) intercarrier output pin SIOMAD AM mode; 1 dB at AF output pin AUD Vi(ovl)(rms) GSIF(cr) BSIF(-3dB)(ll) overload input voltage (RMS value) SIF gain control range lower limit -3 dB SIF bandwidth FM and AM mode; see Figure 11 [3] Min 450 3 Typ 600 5 Max 0.75 750 8 Unit A A dB tuner gain current from 20 % to 80 % AFC circuit (pin AFC)[20][21]; see Figure 7 Vsat(ul) Vsat(ll) Io(source) Io(sink) AFCstps QfVIF(a) QfVIF(d) VP - 0.6 VP - 0.3 160 160 definition: IAFC/fVIF IAFC = 0 A; fREF = 4 MHz IAFC = 0 A; fREF = 4 MHz; 1 digit = 25 kHz 0.85 -20 0.3 200 200 1.05 0.6 240 240 1.25 +20 V V A A A/kHz kHz -20 - 1 digit +20 kHz + 1 digit SIF-AGC monitor (pin AFC)[20]; see Table 14 Io(source) Io(sink) 600 270 A A SIF amplifier (pins SIF1 and SIF2) Vi(SIF)(rms) 30 70 V 50 70 70 100 - V mV 80 60 - 140 66 15 320 - mV mV dB MHz TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 28 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Table 25. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 27 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 23; unless otherwise specified. Symbol BSIF(-3dB)(ul) Ri(diff) Ci(diff) VI SIF-AGC detector tresp AGC response time to an increasing or decreasing SIF step of 20 dB FM or AM fast step; normal mode increasing decreasing FM or AM fast step; mobile mode increasing decreasing AM slow step increasing decreasing Single reference QSS intercarrier mixer (pin SIOMAD) Vo(intc)(rms) IF intercarrier output QSS mode; SC1; SC2 off level (RMS value) L standard; without modulation intercarrier mode; PC/SC1 = 20 dB; SC2 off Bintc(-3dB)(ul) upper limit -3 dB intercarrier bandwidth residual sound carrier (RMS value) fundamental wave and harmonics QSS mode intercarrier mode Vr(PC)(rms) residual picture carrier (RMS value) fundamental wave and harmonics QSS mode intercarrier mode H Ro VO TDA9884_2 Parameter upper limit -3 dB SIF bandwidth differential input resistance differential input capacitance DC input voltage Conditions Min [4] Typ 80 2 3 1.93 Max - Unit MHz k pF V - [4] [20] [20] 8 25 - ms ms 90 90 [22] 0.25 0.7 80 250 140 140 75 15 180 180 - ms ms ms ms mV mV mV MHz 12 Vr(SC)(rms) - 2 2 5 5 mV mV 35 [4] 2 5 40 2 5 20 30 - mV mV dB V suppression of video intercarrier mode; signal harmonics fvideo = 5 MHz output resistance DC output voltage - (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 29 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Table 25. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 27 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 23; unless otherwise specified. Symbol Ibias(int) Parameter internal DC bias current for emitter follower maximum AC output sink current maximum AC output source current DC output source current MAD2 activated [23] Conditions Min 0.90 Typ 1.15 Max - Unit mA Io(sink)(max) Io(source)(max) Io(source) 0.6 0.6 0.75 0.8 0.8 0.93 1.20 mA mA mA FM-PLL demodulator[21][24][25][26][27][28] Sound intercarrier output (pin SIOMAD) VFM(rms) corresponding PC/SC ratio IF intercarrier level at input pins VIF1 and VIF2 for gain controlled operation of FM-PLL is 7 dB to 47 dB (RMS value) IF intercarrier level for lock-in of PLL (RMS value) IF intercarrier level for FM carrier detect (RMS value) sound intercarrier operating FM frequencies see Table 9 3.2 320 mV VFM(lock)(rms) - - 2 mV VFM(det)(rms) - - 2.3 mV fFM see Table 17 - 4.5 5.5 6.0 6.5 3.1 3.6 5.6 6.6 500 540 1.4 600 650 - MHz MHz MHz MHz MHz MHz MHz MHz mV mV V true split sound mode; see Table 20 - Audio output (pin AUD) Vo(AF)(rms) AF output voltage (RMS value) 25 kHz FM deviation; 75 s de-emphasis 27 kHz FM deviation; 50 s de-emphasis Vo(AF)(cl)(rms) Vo(AF)/T AF output clipping level (RMS value) AF output voltage variation with temperature total harmonic distortion 27 kHz FM deviation; 50 s de-emphasis THD < 1.5 % 400 430 1.3 - 3 x 10-3 7 x 10-3 dB/K THD - 0.15 0.50 % TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 30 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Table 25. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 27 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 23; unless otherwise specified. Symbol fAF Parameter frequency deviation Conditions THD < 1.5 % -6 dB AF output via I2C-bus BAF(-3dB) -3 dB AF bandwidth without de-emphasis; measured with FM-PLL filter in Figure 23 FM-PLL only; 27 kHz FM deviation; 50 s de-emphasis black picture; see Figure 12 Vr(SC)(rms) residual sound carrier (RMS value) AM suppression of FM demodulator fundamental wave and harmonics; without de-emphasis referenced to 27 kHz FM deviation; 50 s de-emphasis; AM: f = 1 kHz; m = 54 % fripple = 70 Hz; see Figure 8 [25] [25] Min 80 Typ 100 Max 55 110 - Unit kHz kHz kHz S/NW(AF) weighted signal-to-noise ratio of audio signal 52 56 - dB 50 - 56 - 2 dB mV AM(sup) 40 46 - dB PSRR power supply ripple rejection DC loop voltage maximum phase detector output source current maximum phase detector output sink current output source current of digital acquisition help output sink current of digital acquisition help pulse width of digital acquisition help current cycle time of digital acquisition help VCO steepness phase detector steepness 14 20 - dB FM-PLL filter (pin FMPLL) Vloop Io(source)(PD)(max) 1.5 60 3.3 V A Io(sink)(PD)(max) - 60 - A Io(source)(DAH) - 55 - A Io(sink)(DAH) - 55 - A tW(DAH) - 16 - s Tcy(DAH) KO(FM) KD(FM) definition: fFM/VFMPLL definition: IFMPLL/FM - 64 3.3 4 - s MHz/V A/rad TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 31 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Table 25. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 27 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 23; unless otherwise specified. Symbol Audio amplifier De-emphasis network (pin DEEM) Ro output resistance 50 s de-emphasis; see Table 15 75 s de-emphasis; see Table 15 VAF(rms) VO Vdec IL Ich(max) Idch(max) audio signal (RMS value) DC output voltage DC decoupling voltage leakage current maximum charge current maximum discharge current output resistance DC output voltage load resistance DC load resistance load capacitance upper limit -3 dB AF bandwidth of audio amplifier lower limit -3 dB AF bandwidth of audio amplifier mute attenuation of AF signal DC jump voltage for switching AF output to mute state and vice versa via I2C-bus activated by digital acquisition help or via I2C-bus mute [26] [4] Parameter Conditions Min Typ Max Unit 4.4 6.6 - 5.0 7.5 170 2.37 1.50 1.50 5.6 8.4 3.3 25 1.85 1.85 k k mV V V nA A A fAF = 400 Hz; VAUD = 500 mV AF decoupling (pin AFD) dependent on fFM intercarrier frequency VO(AUD) < 50 mV 1.5 1.15 1.15 Audio output (pin AUD) Ro VO(AUD) RL RL(DC) CL BAF(-3dB)(ul) AC-coupled 10 100 150 2.37 300 1.5 V k k nF kHz BAF(-3dB)(ll) - - 20 Hz mute Vjump 70 - 75 50 150 dB mV TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 32 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Table 25. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 27 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 23; unless otherwise specified. Symbol FM operation[27][29] weighted signal-to-noise ratio PC/SC ratio is 21 dB to 27 dB at pins VIF1 and VIF2 black picture white picture 6 kHz sine wave (black-to-white modulation) sound carrier subharmonics; f = 2.75 MHz 3 kHz Single reference QSS AF performance[31][32] S/NW(SC1) weighted signal-to-noise ratio for SC1 PC/SC1 ratio at pins VIF1 and VIF2; 27 kHz (54 % FM deviation); "ITU-R BS.468-4" black picture white picture 6 kHz sine wave (black-to-white modulation) 250 kHz square wave (black-to-white modulation) sound carrier subharmonics; f = 2.75 MHz 3 kHz sound carrier subharmonics; f = 2.87 MHz 3 kHz 40 dB 50 45 40 56 51 46 dB dB dB Parameter Conditions Min Typ Max Unit Intercarrier AF performance[30] S/NW 35 40 - dB 53 50 44 58 53 48 - dB dB dB 40 45 - dB 45 51 - dB 46 52 - dB TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 33 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Table 25. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 27 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 23; unless otherwise specified. Symbol S/NW(SC2) Parameter weighted signal-to-noise ratio for SC2 Conditions PC/SC2 ratio at pins VIF1 and VIF2; 27 kHz (54 % FM deviation); "ITU-R BS.468-4" black picture white picture 6 kHz sine wave (black-to-white modulation) 250 kHz square wave (black-to-white modulation) sound carrier subharmonics; f = 2.75 MHz 3 kHz sound carrier subharmonics; f = 2.87 MHz 3 kHz AM operation L standard (pin AUD)[33]; see Figure 13 and Figure 14 Vo(AF)(rms) THD BAF(-3dB) S/NW(AF) AF output voltage (RMS value) total harmonic distortion -3 dB AF bandwidth weighted signal-to-noise ratio of audio signal DC potential voltage power supply ripple rejection DC input voltage input resistance resonance resistance of crystal pull-up/down capacitance reference signal frequency tolerance of reference signal frequency operation as crystal oscillator [34] [4] Min 40 Typ - Max - Unit dB 48 46 42 55 51 46 - dB dB dB 29 34 - dB 44 50 - dB 45 51 - dB 54 % modulation 54 % modulation 400 100 500 0.5 125 50 600 1.0 - mV % kHz dB in accordance with "ITU-R BS.468-4" 45 VO(AUD) PSRR fripple = 70 Hz; see Figure 8 20 2.37 26 - V dB Reference frequency input (pin REF) VI Ri Rxtal Cx fref fref 2.3 2.6 5 4 2.9 200 0.1 V k pF MHz % [35] [21] TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 34 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Table 25. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 27 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Figure 23; unless otherwise specified. Symbol Vref(rms) Ro(ref) Parameter Conditions Min 80 Typ Max 400 4.7 Unit mV k reference signal operation as input terminal voltage (RMS value) output resistance of reference signal source decoupling capacitance to external reference signal source SCL clock frequency HIGH-level input voltage LOW-level input voltage HIGH-level input current LOW-level input current LOW-level output voltage output sink current output source current LOW-level output voltage HIGH-level output voltage output sink current maximum output sink or source current pin OP2 functions as VIF-AGC output IOL = 3 mA VP = 0 V VP = 0 V operation as input terminal CK 22 100 - pF I2C-bus transceiver (pins SDA and SCL)[36][37] fSCL VIH VIL IIH IIL VOL Io(sink) Io(source) 0 3 -0.3 -10 -10 400 VCC +1.5 +10 +10 0.4 10 10 kHz V V A A V A A Output ports (pins OP1 and OP2)[15][19][38] VOL VOH Io(sink) Io(sink/source)(max) IOL = 2 mA (sink current) 0.4 6 2 10 V V mA A [1] [2] [3] [4] Values of video and sound parameters can be decreased at VP = 4.5 V. For applications without I2C-bus, the time constant (R x C) at the supply must be > 1.2 s (e.g. 1 and 2.2 F). Level headroom for input level jumps during gain control setting. This parameter is not tested during the production and is only given as application information for designing the receiver circuit. TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 35 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL [5] Loop bandwidth BL = 70 kHz (damping factor d = 1.9; calculated with sync level within gain control range). Calculation of the VIF-PLL filter can be done by use of the following formulae: BL -3dB = ----- O K D R , valid for d 1.2; d = -- R K O K D C , where: KO is the VCO -K 2 2 1 1 Hz A rad steepness -------- or 2 ------ ; KD is the phase detector steepness -------- ; R is the loop resistor; C is the loop capacitor; BL-3dB is the V V rad loop bandwidth for -3 dB; d is the damping factor. [6] [7] [8] [9] Vi(VIF) = 10 mV (RMS); f = 1 MHz (VCO frequency offset related to picture carrier frequency); white picture video modulation. Condition: luminance range (5 steps) from 0 % to 100 %. Measurement using unified weighting filter ("ITU-T J.61"), 200 kHz high-pass filter, 5 MHz low-pass filter and subcarrier notch filter ("ITU-T J.64"). Noise analyzer setting: 200 kHz high-pass and SC-trap switched on. [10] The intermodulation figures are defined for: a) f = 1.1 MHz (referenced to black and white signal) as IM = 20 log ------------------------------------- + 3.6 dB. V at 1.1 MHz 0 V 0 at 4.4 MHz b) f = 3.3 MHz (referenced to color carrier) as IM = 20 log ------------------------------------- . V at 3.3 MHz 0 V 0 at 4.4 MHz [11] Measurements taken with SAW filter M1963M (sound shelf: 20 dB); loop bandwidth BL = 70 kHz. Modulation VSB; sound carrier off; fvideo > 0.5 MHz. [12] Measurements taken with SAW filter M1963M (sound shelf: 20 dB); loop bandwidth BL = 70 kHz. Sound carrier on; fvideo = 10 kHz to 10 MHz. [13] AC load; CL < 20 pF and RL > 1 k. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound carrier traps (see Figure 16 to Figure 21; H (s) is the absolute value of transfer function). [14] The sound carrier trap can be bypassed by switching the I2C-bus. In this way the full composite video spectrum appears at pin CVBS. The amplitude is 1.1 V (p-p). [15] If selected by the I2C-bus, the VIF-AGC voltage can be monitored at pin OP2. In this case, OP2 cannot be used for the normal port function. [16] The response time is valid for a VIF input level range from 200 V to 70 mV. [17] The fast mode will be activated automatically, if within a time of typically 150 s for mobile mode and 1.2 ms for normal mode no AGC event occurs. An AGC event is a charge current pulse into the AGC capacitor due to reaching AGC reference voltage the sync level. [18] The fast mode will be activated automatically, if the black level drops down by half of the sync amplitude. [19] If selected by the I2C-bus, pin OP1 can alternatively be used for external AGC control, activated by pin AGCSW. In this case, OP1 cannot be used for the normal port function. [20] Pin AFC is usable as AFC output or as SIF-AGC. a) To match the AFC output signal to different tuning systems a current source output is provided. The test circuit is given in Figure 7. The AFC steepness can be changed by resistors R1 and R2. b) In mobile mode the internal SIF-AGC is switched to pin AFC. In this case AFC out is disabled. [21] The tolerance of the reference frequency determines the accuracy of the VIF-AFC, FM demodulator center frequency and maximum FM deviation. [22] The intercarrier output signal at pin SIOMAD can be calculated by the following formulae taking into account the internal video signal with 1.1 V (p-p) as a reference: V o ( intc ) ( rms ) = 1.1 x --------- x 10 V and r = ----- x --------------- ( dB ) + 6 dB 3 dB , where: --------- is 20 V i ( PC ) 22 22 1 r 1 V i ( SC ) 1 the correction term for RMS value, --------------- ( dB ) is the sound-to-picture carrier ratio at pins VIF1 and VIF2 in dB, 6 dB is the correction term of internal circuitry and 3 dB is the tolerance of video output and intercarrier output Vo(intc)(rms). [23] For normal operation (with the I2C-bus) no DC load at pin SIOMAD is allowed. The second module address (MAD2) will be activated by the application of a 2.2 k resistor between pin SIOMAD and ground. If this MAD2 is activated, also the power-on setup state activates a VIF frequency of 58.75 MHz. [24] SIF input level is 10 mV (RMS); VIF input level is 10 mV (RMS) unmodulated. V i ( SC ) V i ( PC ) TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 36 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL [25] Measured with an FM deviation of 25 kHz and the typical AF output voltage of 500 mV (RMS). The AF output signal can be attenuated by 6 dB to 250 mV (RMS) via the I2C-bus. For handling a frequency deviation of more than 55 kHz, the AF output signal has to be reduced in order to avoid clipping (THD < 1.5 %). [26] The lower limit of the audio bandwidth depends on the value of the capacitor at pin AFD. A value of CAF = 470 nF leads to fAF(-3dB) 20 Hz and CAF = 220 nF leads to fAF(-3dB) 40 Hz. [27] For all S/N measurements the VIF modulator in use has to meet the following specifications: a) Incidental phase modulation for black-to-white jump less than 0.5 degrees. b) QSS AF performance, measured with the television demodulator AMF2 (audio output, weighted S/N ratio) better than 60 dB (at deviation 27 kHz) for 6 kHz sine wave black-to-white video modulation. c) Picture-to-sound carrier ratio PC/SC1 = 13 dB (transmitter). [28] Calculation of the loop filter parameters can be done approximately using the following formulae: f o = ----- --------------- ; 2 CP 1 K OK D 1 = ---------------------------------- ; BL-3dB = fo(1.55 - 2). The formulae are only valid under the following conditions: 1 and CS > 5CP, where: 2R K O K D C P rad Hz A KO is the VCO steepness -------- or 2 ------ ; KD is the phase detector steepness -------- ; R is the loop resistor; CS is the series V V rad capacitor; CP is the parallel capacitor; fo is the natural frequency of the PLL; BL-3dB is the loop bandwidth for -3 dB; is the damping factor. For examples, see Table 26. [29] The PC/SC ratio is calculated as the addition of TV transmitter PC/SC1 ratio and SAW filter PC/SC1 ratio. This PC/SC ratio is necessary to achieve the S/NW values as noted. A different PC/SC ratio will change these values. [30] Measurements taken with SAW filter G1984 (Siemens) for vision and sound IF (sound shelf: 14 dB). Picture-to-sound carrier ratio of transmitter PC/SC = 13 dB. Input level on pins VIF1 and VIF2 of Vi(SIF) = 10 mV (RMS) sync level, 27 kHz FM deviation for sound carrier, fAF = 400 Hz. Measurements in accordance with "ITU-R BS.468-4". De-emphasis is 50 s. [31] The QSS signal output on pin SIOMAD is analyzed by a test demodulator TDA9820. The S/N ratio of this device is more than 60 dB, related to a deviation of 27 kHz, in accordance with "ITU-R BS.468-4". [32] Measurements taken with SAW filter K3953 for vision IF (suppressed sound carrier) and K9453 for sound IF (suppressed picture carrier). Input level Vi(SIF) = 10 mV (RMS), 27 kHz (54 % FM deviation). [33] Measurements taken with SAW filter K9453 (Siemens) for AM sound IF (suppressed picture carrier). [34] The value of Cx determines the accuracy of the resonance frequency of the crystal. It depends on the type of crystal used. [35] Pin REF is able to operate as a 1-pin crystal oscillator input as well as an external reference signal input, e.g. from the tuning system. [36] The SDA and SCL lines will not be pulled down if VCC is switched off. [37] The AC characteristics are in accordance with the I2C-bus specification for fast mode (maximum clock frequency is 400 kHz). Information about the I2C-bus can be found in the brochure "The I2C-bus and how to use it" (order number 9398 393 40011). [38] Port P1 and port P2 are open-collector outputs. Table 26. 100 160 Table 27. VIF carrier SIF carrier Examples for Table note 28 of Table 25 (FM-PLL filter) CS (nF) 10 10 Input frequencies and carrier ratios Symbol B/G standard fPC fSC1 fSC2 SC1 SC2 38.9 33.4 33.158 13 20 M/N standard 45.75 or 58.75 41.25 or 54.25 7 L standard L accent standard Unit 38.9 32.4 10 33.9 40.4 10 MHz MHz MHz dB dB CP (pF) 390 150 R (k) 5.6 9.1 0.5 0.5 BL-3dB (kHz) Description Picture-to-sound carrier ratio TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 37 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 110 Vi (dBV) 100 (1) mhc576 80 S/N (dB) 60 (2) mhc112 90 40 80 70 20 60 0 4 8 12 16 20 24 RTOP (k) 0 30 50 70 110 90 Vi(VIF) (dBV) (1) Vi(VIF). (2) Vi(SIF); true split sound mode. Fig 4. Typical tuner takeover point as a function of resistor RTOP Fig 5. Typical signal-to-noise ratio as a function of VIF input voltage 3.2 dB 10 dB 13.2 dB 21 dB 13.2 dB 21 dB SC CC PC SC CC PC BLUE YELLOW mha739 SC is sound carrier, with respect to sync level. CC is chrominance carrier, with respect to sync level. PC is picture carrier, with respect to sync level. The sound carrier levels take into account a sound shelf attenuation of 14 dB (SAW filter G1984M). Fig 6. Input signal conditions TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 38 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL lock range without SAW filter AFC window 5 VP VAFC (V) 4 -100 IAFC R1 22 k IAFC (A) -200 3 0 2 +100 1 +200 0 36 37 38 38.9 38.71 39.09 40 f (MHz) 001aae454 TDA9884 21 (23) VAFC R2 22 k 41 Pin numbers for TDA9884HN in parentheses. Fig 7. Typical analog AFC characteristic VP = 5 V VP (V) 5 100 mV TDA9884 fripple = 70 Hz 001aae455 t (s) Fig 8. Ripple rejection condition trap bypass mode normal mode 2.72 V 2.6 V 3.41 V 3.20 V zero carrier level white level 1.83 V 1.80 V black level 1.5 V 1.20 V sync level mhc115 Fig 9. Typical video signal levels on output pin CVBS (sound carrier off) TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 39 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL mhc116 VVAGC (V) 4 I TAGC (A) 600 500 400 3 300 200 2 (1) (2) (3) (4) 100 0 1 30 40 50 60 70 80 90 100 110 120 Vi(VIF) (dBV) (1) VVAGC is VIF-AGC voltage and can only be measured at pin OP2 controlled by the I2C-bus (see Table 18). (2) ITAGC is tuner current with RTOP = 22 k or setting via I2C-bus at -15 dB. (3) ITAGC is tuner current with RTOP = 10 k or setting via I2C-bus at 0 dB. (4) ITAGC is tuner current with RTOP = 0 or setting via I2C-bus at +15 dB. Fig 10. Typical VIF and tuner AGC characteristic mhc581 VSAGC (V) 4 I TAGC (A) 600 500 400 3 300 200 2 (1) (2) (3) (4) 100 0 1 30 40 50 60 70 80 90 100 110 120 Vi(SIF) (dBV) (1) VSAGC is SIF-AGC voltage in FM mode and can only be measured at pin AFC controlled by the I2C-bus (see Table 14). (2) ITAGC is tuner current in true split sound mode with RTOP = 22 k or setting via I2C-bus at -15 dB. (3) ITAGC is tuner current in true split sound mode with RTOP = 10 k or setting via I2C-bus at 0 dB. (4) ITAGC is tuner current in true split sound mode with RTOP = 0 or setting via I2C-bus at +15 dB. Fig 11. Typical SIF and tuner AGC characteristic TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 40 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 10 (1) mhc118 S/NW 0 (dB) -10 -20 -30 -40 (2) -50 -60 -70 (3) 52 49 46 43 40 37 34 31 28 25 22 19 16 13 10 7 4 PC/SC ratio gain controlled operation of FM-PLL Conditions: PC/SC ratio measured at pins VIF1 and VIF2; via transformer; 27 kHz FM deviation; 50 s de-emphasis. (1) Signal. (2) Noise at H-picture (weighted in accordance with "ITU-R BS.468-4" quasi peak). (3) Noise at black picture (weighted in accordance with "ITU-R BS.468-4" quasi peak). Fig 12. Audio signal-to-noise ratio as a function of picture-to-sound carrier ratio in intercarrier mode 10 S/NW 0 (dB) -10 -20 -30 -40 -50 -60 -70 30 40 50 60 70 80 90 (2) (1) mhc119 100 Vi (dBV) 110 Condition: m = 54 %. (1) Signal. (2) Noise (weighted in accordance with "ITU-R BS.468-4" quasi peak). Fig 13. Typical audio signal-to-noise ratio as a function of input signal at AM standard TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 41 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 1.5 THD (%) 1.0 mhc120 0.5 0 10-2 10-1 1 10 fAF (kHz) 102 CAGC = 2.2 F; m = 54 %. Fig 14. Typical total harmonic distortion as a function of audio frequency at AM standard TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 42 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 140 antenna input (dBV) 001aae456 10 IF signals RMS value (V) video 2 V (p-p) 120 1 (1) 100 SAW insertion loss 20 dB 10-1 IF slip 6 dB 80 tuning gain control range 70 dB VIF-AGC 60 10-2 (TOP) 10-3 0.66 x 10-3 SAW insertion loss 20 dB 40 40 dB RF gain 10-4 20 10-5 0.66 x 10-5 10 VHF/UHF tuner tuner VIF SAW filter VIF amplifier, demodulator and video TDA9884 (1) Depends on TOP. Fig 15. Front-end level diagram TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 43 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 10 H(s) (dB) 0 mhc122 -10 -20 -30 minimum requirements -40 2 2.5 3 3.5 4 4.5 f (MHz) 5 Fig 16. Typical amplitude response for sound trap at M/N standard (including Korea) 400 group delay (ns) 300 mhb167 200 ideal characteristic due to pre-correction in the transmitter 100 0 minimum requirements -100 0 0.5 1 1.5 2 2.5 3 3.5 f (MHz) 4 Overall delay is not shown, here the maximum ripple is specified. Fig 17. Typical group delay for sound trap at M/N standard TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 44 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 10 H(s) (dB) 0 mhb168 -10 -20 -30 minimum requirements -40 4 4.5 5 5.5 6 6.5 f (MHz) 7 Fig 18. Typical amplitude response for sound trap at B/G standard 400 group delay (ns) 300 mhb169 200 ideal characteristic due to pre-correction in the transmitter 100 0 minimum requirements -100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 f (MHz) 5 Overall delay is not shown, here the maximum ripple is specified. Fig 19. Typical group delay for sound trap at B/G standard TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 45 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL mhc123 10 H(s) (dB) 0 -10 -20 -30 minimum requirements -40 4 4.5 5 5.5 6 6.5 f (MHz) 7 Fig 20. Typical amplitude response for sound trap at I standard mhb171 10 H(s) (dB) 0 -10 -20 -30 minimum requirements -40 4 4.5 5 5.5 6 6.5 f (MHz) 7 Fig 21. Typical amplitude response for sound trap at D/K standard TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 46 of 58 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Product data sheet Rev. 02 -- 12 May 2006 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. TDA9884_2 12. Application information Philips Semiconductors VP port 10 nF 680 k 220 k BC847C BA277 10 F BA277 75 (3) 22 k 5V CVBS output fref tuner AGC 1 2 SAW FILTER K9456 3 6.8 k 6.8 k 5 4 VIF-AGC(1) AFC or SIF-AGC 12 k 1.5 nF 330 220 5V 100 k CVAGC 470 nF 47 F BC847 BA277 10 nF 220 nF 100 pF SIF2 24 (27) SIF1 23 (26) OP2 22 (24) AFC 21 (23) VP 20 (22) VPLL 19 (21) AGND 18 (20) CVBS 17 (18) VAGC 16 (17) REF 15 (16) TAGC 14 (15) AGCSW 13 (14) 10 nF 5V TDA9884 22 k I2C-bus controlled multistandard alignment-free IF-PLL (30) 1 VIF1 (31) 2 VIF2 (1) 3 OP1 (2) 4 FMPLL (3) 5 DEEM (4) 6 AFD (5) 7 DGND (7) 8 AUD (8) 9 TOP (9) 10 SDA 100 (10) 11 SCL 100 (11) 12 SIOMAD VIF/SIF 1 51 5 SAW FILTER K3953 3 4 390 pF 10 nF Cde-em 10 nF CAF 470 nF 2 5.6 k (3) AF output OP1 or FM-PLL filter external (2) AGC input positive supply I 2C-bus controller I 2C-bus intercarrier output 001aae453 TDA9884 Pin numbers for TDA9884HN in parentheses. (1) See Table note 15 of Table 25. (2) See Table note 19 of Table 25. (3) Optional measures to improve ESD performance within a TV-set application. 47 of 58 Fig 22. Application circuit xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Product data sheet Rev. 02 -- 12 May 2006 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. TDA9884_2 13. Test information Philips Semiconductors SIF input optional VIF-AGC 1:1 22 k AFC output VP 100 nF 1.5 nF VIF-PLL filter(3) CVBS output external reference tuner AGC output 150 100 pF 4 MHz Cx 51 R3 150 k (1) R2 150 k 22 k CVAGC 470 nF 220 nF SIF2 24 (27) SIF1 23 (26) OP2 22 (24) AFC(2) 21 (23) VP 20 (22) VPLL 19 (21) AGND 18 (20) CVBS 17 (18) VAGC 16 (17) REF 15 (16) TAGC 14 (15) AGCSW 13 (14) TDA9884 (30) 1 VIF1 VIF input (31) 2 VIF2 (1) 3 OP1 (2) 4 FMPLL (3) 5 DEEM (4) 6 AFD (5) 7 DGND (7) 8 AUD (8) 9 TOP (9) 10 SDA (10) 11 SCL (11) 12 SIOMAD I2C-bus controlled multistandard alignment-free IF-PLL 1:1 10 nF 390 pF Cde-em 10 nF CAF 470 nF 22 k 51 5.6 k MAD select R1 2.2 k (1) optional VIF-AGC input FM-PLL filter audio output intercarrier output 001aae452 TDA9884 Pin numbers for TDA9884HN in parentheses. (1) Optional for I2C-bus address selection; see Table 28. (2) SIF-AGC monitor output at pin AFC. (3) Different VIF loop filter in comparison with the application circuit due to different input characteristics (SAW filter or transformer). 48 of 58 Fig 23. Test circuit Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL I2C-bus address selection[1] R1 not used 1000 011S 1001 011S R1 = 2.2 k 1000 010S 1001 010S Table 28. Option R2 and R3 not used R2 = R3 = 150 k [1] S = R/W selection bit. TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 49 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 14. Package outline SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 D E A X c y HE vMA Z 24 13 Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 12 wM detail X A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 24. Package outline SOT340-1 (SSOP24) TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 50 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm SOT617-3 D B A terminal 1 index area A E A1 c detail X C e1 e 9 L 8 17 e 1/2 e b 16 vMCAB wM C y1 C y Eh 1/2 e e2 1 terminal 1 index area 32 Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 5.1 4.9 Dh 3.75 3.45 E (1) 5.1 4.9 Eh 3.75 3.45 25 24 X 2.5 scale e 0.5 e1 3.5 e2 3.5 L 0.5 0.3 5 mm v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT617-3 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-04-18 02-10-22 Fig 25. Package outline SOT617-3 (HVQFN32) TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 51 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 15. Soldering 15.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 260 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 15.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 52 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C. 15.5 Package related soldering information Table 29. Package[1] BGA, HTSSON..T[3], LBGA, LFBGA, SQFP, SSOP..T[3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L[8], PMFP[9], WQCCN..L[8] [1] [2] Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable[4] Reflow[2] suitable suitable suitable not not recommended[5][6] recommended[7] suitable suitable suitable not suitable not suitable For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. [3] TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 53 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages. [5] [6] [7] [8] [9] TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 54 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 16. Abbreviations Table 30. Acronym AFC AGC FPLL MAD NTSC PAL PLL QSS SECAM SIF TOP VCO VIF VSB Abbreviations Description Automatic Frequency Control Automatic Gain Control Frequency Phase-Locked Loop Module Address National Television Standards Committee Phase Alternating Line Phase-Locked Loop Quasi Split Sound Sequentiel Couleur avec Memoire Sound Intermediate Frequency TakeOver Point Voltage-Controlled Oscillator Vision Intermediate Frequency Vestigial Side Band 17. Revision history Table 31. Revision history Release date 20060512 Data sheet status Product data sheet Change notice Supersedes TDA9884TS_1 Document ID TDA9884_2 Modifications: * * * The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors Added type number TDA9884HN Table 25: inserted the value for tresp, FM or AM fast step, mobile mode, increasing Product specification - TDA9884TS_1 20031128 TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 55 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.semiconductors.philips.com. 18.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Philips Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Philips Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. to result in personal injury, death or severe property or environmental damage. Philips Semiconductors accepts no liability for inclusion and/or use of Philips Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.semiconductors.philips.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, Philips Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- Philips Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Philips Semiconductors product can reasonably be expected 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of Koninklijke Philips Electronics N.V. 19. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 56 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL Notes TDA9884_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 12 May 2006 57 of 58 Philips Semiconductors TDA9884 I2C-bus controlled multistandard alignment-free IF-PLL 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 8 8.1 8.1.1 8.1.2 8.2 8.2.1 8.2.2 8.2.3 8.2.4 9 10 11 12 13 14 15 15.1 15.2 15.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 VIF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Tuner AGC and VIF-AGC . . . . . . . . . . . . . . . . . 8 VIF-AGC detector . . . . . . . . . . . . . . . . . . . . . . . 8 FPLL detector . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCO and divider . . . . . . . . . . . . . . . . . . . . . . . . 9 AFC and digital acquisition help . . . . . . . . . . . . 9 Video demodulator and amplifier . . . . . . . . . . 10 Sound carrier trap . . . . . . . . . . . . . . . . . . . . . . 10 SIF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SIF-AGC detector . . . . . . . . . . . . . . . . . . . . . . 11 Single reference QSS mixer . . . . . . . . . . . . . . 11 AM demodulator . . . . . . . . . . . . . . . . . . . . . . . 11 FM demodulator and acquisition help. . . . . . . 12 Audio amplifier and mute time constant . . . . . 12 Internal voltage stabilizer . . . . . . . . . . . . . . . . 13 I2C-bus transceiver and module address . . . . 13 2C-bus control . . . . . . . . . . . . . . . . . . . . . . . . . 14 I Read format . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Slave address . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write format . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Subaddress. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Data byte for switching mode . . . . . . . . . . . . . 16 Data byte for adjust mode. . . . . . . . . . . . . . . . 17 Data byte for data mode . . . . . . . . . . . . . . . . . 19 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 20 Thermal characteristics. . . . . . . . . . . . . . . . . . 21 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 21 Application information. . . . . . . . . . . . . . . . . . 47 Test information . . . . . . . . . . . . . . . . . . . . . . . . 48 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 50 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 52 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 52 15.4 15.5 16 17 18 18.1 18.2 18.3 18.4 19 20 Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 53 55 55 56 56 56 56 56 56 58 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. Date of release: 12 May 2006 Document identifier: TDA9884_2 |
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