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iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 1/23 FEATURES E E E E E E E E E E E E E E 2 x 4 bidirectional input/output stages at 24 V Input/output mode programmable in 4-bit blocks Guaranteed high-side driving capability of 100 mAdc and 500 mApeak for pulse load Short-circuit-proof drivers with high dielectric strength Low saturation voltage of 0.6 V at 100 mA and 2 V at 500 mA Integrated flyback circuits PWM function with programmable duty cycle Flash mode for the outputs Power outputs can be disabled together Programmable current sources define logic levels and allow load monitoring Digital input filters with externally adjustable filtering times Can be bus operated due to the high-speed P interface Programmable interrupt output Voltage and two-stage temperature monitoring APPLICATIONS E Dual quad high-side driver as a bidirectional P interface with digital filtering in industrial 24 V applications
PACKAGES
PLCC44
BLOCK DIAGRAM
E/A LOGIK
30 VCCA
OUT0 PEN0
EIN-/AUSGANG STUFE 0
&
OUT SC0 POE
VB01
28
&
&
0A 200A
34
VCCD
PSEL0 SC0
PSEL0 IN
+ Toff1
IO0
29
VB -5.8V 3.8V
Q
D
0A 200A 600A 2.0mA
IO0
IO0
VT NTC NIOL IL0 IL1
Q
D
1 2 3
CSN WRN RDN
Toff2
E/A LOGIK E/A LOGIK E/A LOGIK
NIOL IL0 IL1
EIN-/AUSGANG STUFE 1 EIN-/AUSGANG STUFE 2 EIN-/AUSGANG STUFE 3
IO1 VB23 IO2 IO3
27 25 26 24
39 40 41 42 43
A0 A1 A2 A3 A4
VB45
21 22 20 18 19 17
E/A LOGIK
38 8 37 9 36 10 35 11 12 7 D0 D1 D2 D3 D4 D5 D6 D7 GNDD RESN
NIOH IH0 IH1
EIN-/AUSGANG STUFE 4 EIN-/AUSGANG STUFE 5 EIN-/AUSGANG STUFE 6 EIN-/AUSGANG STUFE 7
UNTERSPANNUNGSERKENNUNG VCCA
IO4 IO5 VB67 IO6 IO7
E/A LOGIK E/A LOGIK E/A LOGIK
PGND GNDA POE
23 16 31
iC-JRX
INTN 6 BLFQ 4 CLK 5 TEST 15
Copyright (c) 2003, iC-Haus
www.ichaus.com
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 2/23 DESCRIPTION iC-JRX is an 8-fold high-side driver with integrated control logic, internally divided into two independent blocks (nibbles). Both blocks can be individually set to input or output. The P interface is made up of eight data, five address and three control pins. Two further clock inputs control internal sequences (input filter, pulse operation of the outputs). Starting with reset state, various register partitionings dependent on the selected operating mode are possible. Input mode is used to log logic levels at 24 V. An interrupt message can be generated when a signal at the inputs changes. Spurious signals are rejected by the device's adjustable digital filters. When the inputs are open the programmable pull-down current sets defined levels and acts as the bias current for switching contacts. In output mode the power output stages can drive any desired load to GND (e.g. lamps, long cables or relays) at a continuous current of 100 mA or 500 mA in pulse operation. Spikes and flyback currents are discharged through the integrated flyback circuits. All output stages are short-circuit-proof and two-stage temperature monitoring (with interrupt messages) protects against thermal damage caused by large power dissipation. A short circuit at one of the outputs can cause an interrupt; the current short circuit status can be scanned via the P interface. Pulse mode can be selected for each output, such as for indicator lamps in plugboards, in order to offload the control software used. The actual switching level of the output can be read out via the P interface and be used to check for cable fractures with the pull-up currents. A PWM signal can also be switched to any selected output. All outputs can be switched off via a mutual disable input e.g. by a processorindependent watchdog circuit. An interrupt pipeline which prevents the loss of interrupts allows reliable processing of interrupts using the applied control software. With low voltage the voltage monitor resets all registers and in doing so switches off the power output stages. Diodes protect all inputs and outputs against ESD. The device is also immune to burst transients according to IEC 1000-4-4 (4 kV; previously IEC 801-4).
5V 5V C1 100 nF 34 30 31 POE VB01 IO0 IO1 28 29 27 C4 100 nF S3 S4 C3 100 nF S1 S2 24 V C2 3.3 ... 10 uF
5V
ADRESSDEKODIERER 1 WR RD 2 3 39 40 41 42 8 5 43 38 8 36 9 36 10 35 8 11 CSN WRN RDN A0 A1 A2 A3 A4 D0 D1 D2 D3 D4 D5 D6 D7
24 V
VCCD VCCA
VB23 IO2 LOWER NIBBLE IO3
25 26 24
A0..A7
P
VB45 IO4 IO5
21 22 20
C5
100 nF
VB67 IO6 HIGHER NIBBLE IO7
18 19 17
C6
100 nF
D0..D7 7 INT RES 6 RESN INTN
KONTROLLREGISTER PLCC44
BLFQ CLK 4 5 GNDD GNDA PGND 12 16 23
iC-JRX
LA1
LA2
LA3
REL1
5V
TEST 15
RESET CONTROLLER 1.25 MHz
5V
Typical application circuit
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 3/23 PACKAGES PLCC44 to JEDEC Standard PIN CONFIGURATION PLCC44 (top view)
PIN FUNCTIONS PLCC44
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Name CSN WRN RDN BLFQ CLK INTN RESN D1 D3 D5 D7 GNDD n.c. n.c. TEST GNDA IO7 VB67 IO6 IO5 VB45 IO4 Fct. I I I I I O I B B B B Description Chip Select, active low Write Enable, active low Read Enable, active low Clock Flash Mode Clock Filter and PWM Function Interrupt Message, active low Reset, active low Data Bus Bit 1 Data Bus Bit 3 Data Bus Bit 5 Data Bus Bit 7 Ground (digital section) Test Pin Ground (analog section) I/O Stage 7 Power Supply Driver Stage 6+7 I/O Stage 6 I/O Stage 5 Power Supply Driver Stage 4+5 I/O Stage 4 No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name PGND IO3 VB23 IO2 IO1 VB01 IO0 VCCA POE n.c. n.c. VCCD D6 D4 D2 D0 A0 A1 A2 A3 A4 n.c. Fct. B B B B I Description Ground (ESD protection circuitry) I/O Stage 3 Power Supply Driver Stage 2+3 I/O Stage 2 I/O Stage 1 Power Supply Driver Stage 0+1 I/O Stage 0 +5 V Supply Voltage (analog section) Power Output Enable +5 V Supply Voltage (digital section) Data Bus Bit 6 Data Bus Bit 4 Data Bus Bit 2 Data Bus Bit 0 Address Bus Bit 0 Address Bus Bit 1 Address Bus Bit 2 Address Bus Bit 3 Address Bus Bit 4
B B B B B
B B B B I I I I I
Functions: I = Input, O = Output, B = bidirectional External wiring VCCA, VCCD to +5 V and GNDA, GNDD, PGND to 0 V required.
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 4/23 PROGRAMMING Register Overview Address A(4..0)d A4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ... 26 27 28 29 30 31
1 2
A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 ... 1 1 1 1 1 1
A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 ... 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 ... 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ... 0 1 0 1 0 1
Write -
Read Input Register 1 Change-of-input Message 2 Interrupt Status Register Overcurrent Message 3 Overcurrent Status Device ID Output Register Flash Pulse Enable Change-of-input Interrupt Enable 4 Overcurrent Interrupt Enable Control Word 1 (I/O filters) Control Word 2 (I/O pin functions) Control Word 3 (flash pulse settings) Control World 4 (filter settings for overcurrent message) Control Word 5 (PWM enable and pin selection) PWM Register Test Register 1 Test Register 2 Test Register 3 Test Control Register A/D Interface
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ... 1 1 1 1 1 1
) ) 3 ) 4 )
Reads the inputs or reads back the outputs, depending on I/O pin mode For I/O pins in input mode (register is `0' in output mode) For I/O pins in output mode (register is `0' in input mode) Only writable in input mode
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 5/23 Control Word 1 (I/O filters) higher nibble Bit Name 7 BYPH 6 5 FH1 4 FH0 lower nibble 3 BYPL 2 1 FL1 0 FL0 Add.: 10 reset entry: 00h
higher nibble
Bit 7 BYPH Bit 5..4 FH1..0 0 1 I/O filters active Bypass for I/O filters: the I/O signals are reprocessed in their unfiltered state. FH1 0 0 1 1 FH0 0 1 0 1 Filter times 14.5 x tc(CLK) 896.5 x tc(CLK) 3584.5 x tc(CLK) 7168.5 x tc(CLK) 1 x tc(CLK) 64 x tc(CLK) 256 x tc(CLK) 512 x tc(CLK) (r)
lower nibble
Bit 3 BYPL Bit 1..0 FL1..0 0 1 I/O filters active Bypass for I/O filters: the I/O signals are reprocessed in their unfiltered state. FL1 0 0 1 1 FL0 0 1 0 1 Filter times 14.5 x tc(CLK) 896.5 x tc(CLK) 3584.5 x tc(CLK) 7168.5 x tc(CLK) 1 x tc(CLK) 64 x tc(CLK) 256 x tc(CLK) 512 x tc(CLK) (r) (r)
'-' 'xx'h (r)
Free memory location without a function. Status after a reset is `0' Indicates hexadecimal data for logic states. `x' indicates binary data Status after a reset
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 6/23 Control Word 2 (I/O pin functions) higher nibble Bit Name 7 NIOH 6 5 IH1 4 IH0 lower nibble 3 NIOL 2 1 IL1 0 IL0 Add.: 11 reset entry: 00h
higher nibble
Bit 7 NIOH Bit 5..4 IH1..0 0 1 Input mode Output mode Current sources at I/O pins 4..7 IH1 0 0 1 1 IH0 0 1 0 1 in input mode (sources low-side) 0 A 200 A 600 A 2 mA in output mode (sources high-side) 0 A 200 A 0 A 200 A
(r)
lower nibble
Bit 3 NIOL Bit 1..0 IL1..0 0 1 Input mode Output mode Current sources at I/O pins 0..3 IL1 0 0 1 1 IL0 0 1 0 1 in input mode (sources low-side) 0 A 200 A 600 A 2 mA in output mode (sources high-side) 0 A 200 A 0 A 200 A
(r)
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 7/23 Control Word 3 (flash pulse settings) higher nibble Bit Name 7 NOBLFQ 6 NOCLK 5 PH1 4 PH0 lower nibble 3 2 1 PL1 0 PL0 Add.: 12 reset entry: 00h
higher nibble
Bit 7 NOBLFQ Bit 6 NOCLK Bit 5..4 PH1..0 0 1 0 1 Flash pulse is generated from the external clock signal at BLFQ Flash Pulse is generated from clock signal CLK Operation with the clock signal at CLK (all clock controlled actions are possible) Operation without the clock signal at CLK (filtering etc. deactivated) Flash frequency for I/O pins 4..7 PH1 0 0 1 1 PH0 0 1 0 1 NOBLFQ = 0 f(BLFQ) f(BLFQ) / 2 f(BLFQ) / 4 f(BLFQ) / 16 NOBLFQ = 1 f(CLK) / 219 f(CLK) / 220 f(CLK) / 221 f(CLK) / 223 (r) (r)
(r)
lower nibble
Bit 1..0 PL1..0 Flash frequency for I/O pins 0..3 PL1 0 0 1 1 PL0 0 1 0 1 NOBLFQ = 0 f(BLFQ) f(BLFQ) / 2 f(BLFQ) / 4 f(BLFQ) / 16 NOBLFQ = 1 f(CLK) / 219 f(CLK) / 220 f(CLK) / 221 f(CLK) / 223
(r)
Control Word 4 (filter settings for overcurrent message) Bit Name
Bit 7 EOI
Add.: 13 reset entry: 00h 3 BYPSCF 2 1 0 SCFL
7 EOI
0 1
6 -
5 -
4 SCFH
No effect (r) "DELETE"s the interrupt message (change-of-input message; interrupt status register, overcurrent message), accepts successive interrupts from the pipeline, deletes the message at INTN when the pipeline is empty; Bit automatically resets to '0'.
Bit 4 SCFH
0 1
Overcurrent message with 2.3ms filtering (higher nibble) Overcurrent message with 4.6ms Filtering (higher nibble) Gives the filter times with the maximum clock frequency permitted at CLK, i.e. 1.25 MHz: 2.3ms from (2689.5 192)x t(CLK) and 4.6ms from (5378.5 384) x t(CLK) respectively
(r)
Bit 3 BYPSCF Bit 0 SCFL
0 1 0 1
Filters for the overcurrent message are active Bypass for the filters: overcurrent messages are reprocessed in their unfiltered state Overcurrent message with 2.3 ms filtering (lower nibble) Overcurrent message with 4.6 ms filtering (lower nibble)
(r) (r)
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 8/23 Control Word 5 (PWM enable and pin selection) Bit Name 7 6 5 4 PWMEN 3 PWMPN 2 PWM ADR(2) 1 PWM ADR(1) Add.: 14 reset entry: 00h 0 PWM ADR(0)
(r)
Bit 4 PWMEN Bit 3 PWMPN Bit 2..0 PWMADR 2..0
0 1 0 1
PWM "DISABLED" PWM "ENABLED": the output selected with PWMADR receives the PWM signal. The relevant current sources are switched off. PWM signal active low PWM signal active high PWMADR2 0 0 0 0 1 1 1 1 PWMADR1 0 0 1 1 0 0 1 1 PWMADR0 0 1 0 1 0 1 0 1 Selected I/O pin IO0 (control line PSEL0= 1) IO1 IO2 IO3 IO4 IO5 IO6 IO7
(r)
PWM Register Bit Name
Bit 7..0 PWM7..0
Add.: 15 reset entry: 00h 6 PWM6 5 PWM5 4 PWM4 3 PWM3 2 PWM2 1 PWM1 0 PWM0
(r)
7 PWM7
'00'h '...'h 'FF'h
Output stage "OFF" (continously) Duration of the PWM signal in steps of 16x t(CLK) Output stage "ON" (continously)
The PWM register determines the pulse length of the PWM signal. Output selection and enable are set via Control Word 5.
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 9/23 Input Register (read only) reading of inputs / output feedback Bit Name
Bit 7..0 IN7..0
Add.: 0 reset entry: 00h
7 IN7
0 1
6 IN6
5 IN5
4 IN4
3 IN3
2 IN2
1 IN1
0 IN0
(r)
Input/Output IOx reads '0' Input/Output IOx reads '1' INx indicates the state for IOx (via I/O filter or bypass).
Change-of-input Message (read only) for I/O stages in input mode Bit Name
Bit 7..0 DCH7..0
Add.: 1 reset entry: 00h
7 DCH7
0 1
6 DCH6
5 DCH5
4 DCH4
3 DCH3
2 DCH2
1 DCH1
0 DCH0
(r)
No change of state at the input IOx or no interrupt enable Input IOx has had a change of state enabled for interrupt messages
Read access gates off changes to the register; the register is reenabled only when reset via EOI. Any successive interrupts which occur during the read-out phase and before a reset with EOI are trapped by an interrupt pipeline. If this happens, the message at INTN cannot be deleted by EOI, i.e. INTN constantly remains on low. In this instance, EOI fills the change-of-input message from the pipeline. Status bits can also be selectively deleted by disabling and reenabling IENx. `0' is output for IOx pins in output mode.
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 10/23 Interrupt Status Register (read only) higher nibble Bit Name 7 DCHI 6 IET2 5 IET1 4 ISCI lower nibble 3 2 ET2 1 ET1 0 SCS Add.: 2 reset entry: 00h
higher nibble overcurrent, excessive temperature, change-of-input data (interrupts stored)
Read access gates off changes to the register; the register is reenabled only when reset via EOI. Any successive interrupts for IET1 and IET2 which occur during the read-out phase and before a reset with EOI are trapped (pipeline). If this happens, the message at INTN cannot be deleted by EOI, i.e. INTN constantly remains on low. In this instance, EOI fills the excessive temperatue message from the pipeline. Bit 7 DCHI Bit 6 IET2 Bit 5 IET1 Bit 4 ISCI 0 1 0 1 0 1 0 1 No message Interrupt through change-of-input message No message Interrupt through excessive temperature level 2 No message Interrupt through excessive temperature level 1 No message Interrupt through overcurrent message (r) (r) (r) (r)
lower nibble overcurrent status, excessive temperature status (real time signals, at the time of readout)
Bit 2 ET2 Bit 1 ET1 Bit 0 SCS 0 1 0 1 0 1 No error message Excessive temperature level 2 (shutdown) No error message Excessive temperature level 1 (warning) No error message Overcurrent status (e.g. caused by low-side short circuit) (r) (r) (r)
Overcurrent Message (read only) Bit Name
Bit 7..0 SCI7..0
Add.: 3 reset entry: 00h 5 SCI5 4 SCI4 3 SCI3 2 SCI2 1 SCI1 0 SCI0
(r)
7 SCI7
0 1
6 SCI6
No message Output IOx has had an overcurrent state enabled for interrupt messages (short circuit)
Read access gates off changes to the register; the register is reenabled only when reset via EOI. Any successive interrupts which occur during the read-out phase and before a reset with EOI are trapped by an interrupt pipeline. If this happens, the message at INTN cannot be deleted by EOI, i.e. INTN constantly remains on low. In this instance, EOI fills the overcurrent message from the pipeline. `0' is output for IOx pins in input mode. SCIx reports for IOx.
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 11/23 Overcurrent Status (read only) Bit Name
Bit 7..0 SC7..0
Add.: 4 reset entry: 00h 5 SC5 4 SC4 3 SC3 2 SC2 1 SC1 0 SC0
7 SC7
0 1
6 SC6
No overcurrent Overcurrent in output IOx, e.g. through a low-side short circuit This signal acts as error analysis and does not generate any interrupts (real time, no register). `0' is output for IOx pins in input mode. SCx reports for IOx.
Device Identification (read only) Bit Name
Bit 5..0 DID5..0
Add.: 5 reset entry: 00h 5 DID5 4 DID4 3 DID3 2 DID2 1 DID1 0 DID0
(r)
7 -
6 -
ID code for iC-JRX: '00 0000' (binary) DID0= `1' with RESN= `0' and with undervoltage
Output-Register for I/O stages with output function Bit Name
Bit 7..0 OUT7..0
Add.: 6 reset entry: 00h
7 OUT7
0 1
6 OUT6
5 OUT5
4 OUT4
3 OUT3
2 OUT2
1 OUT1
0 OUT0
(r)
H High-side driver "OFF" High-side driver "ON", i.e. normally, IOx = '1' OUTx switches the high-side driver for IOx.
Flash Pulse Enable for I/O stages with output function Bit Name
Bit 7..0 PEN7..0
Add.: 7 reset entry: 00h
7 PEN7
0 1
6 PEN6
5 PEN5
4 PEN4
3 PEN3
2 PEN2
1 PEN1
0 PEN0
(r)
Flash pulse "DISABLED" Flash pulse "ENABLED" PENx enables the flash pulse for IOx.
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 12/23 Change-of-input Interrupt Enable for I/O stages with input function Bit Name
Bit 7..0 IEN7..0
Add.: 8 reset entry: 00h
7 IEN7
0 1
6 IEN6
5 IEN5
4 IEN4
3 IEN3
2 IEN2
1 IEN1
0 IEN0
(r)
"DISABLED" for interrupt "ENABLED" for interrupt: a hi6lo or lo6hi change of state at the input IOx triggers an interrupt. Outputs IOx cannot be enabled for messaging. IENx enables the input IOx for interrupt.
Overcurrent Interrupt Enable Bit Name
Bit 7..0 SCEN7..0
Add.: 9 reset entry: 00h 5 SCEN5 4 SCEN4 3 SCEN3 2 SCEN2 1 SCEN1 0 SCEN0
(r)
7 SCEN7
0 1
6 SCEN6
"DISABLED" for interrupt "ENABLED" for interrupt: a short-circuit at IOx triggers an interrupt. SCENx enables the output IOx for interrupt.
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 13/23 ABSOLUTE MAXIMUM RATINGS
Values beyond which damage may occur; device operation is not guaranteed. Item Symbol Parameter Supply Voltage VCCD, VCCA Supply Voltage VB Voltage at IO0..7 Current in IO0..7 Pulse Current in IOx Current in VCCD, VCCA Current in Clamping Diodes CSN, WRN, RDN, A0..4, D0..7, RESN, CLK, BLFQ, POE Current in D0..7, INTN D0..7 with input function IOx= hi (*), = 2ms, T$ 2s IOx= off 1 2 Conditions Fig. Min. G001 VCCD VCCA G002 VB G003 V(IO) G004 Idc(IO) G005 Ipk(IO) G006 Imax() G008 Ic() -0.3 -0.3 -10 -500 -1 -50 -4 -20 50 4 20 Max. 7 30 30 100 V V V mA A mA A mA Unit
G007 Imax(VB) Current in VB01, VB23, VB45, VB67
G009 I() G010 Ilu()
D0..7 with output function
-25 -100
25 100
mA mA
Pulse Current in CSN, WRN, RDN, pulse duration < 10s, A0..4, D0..7, RESN, CLK, BLFQ, all in-/outputs open INTN, POE, IO0..7 (Latch-Up Strength) ESD Susceptibility at all Pins MIL-STD-883.D, Method 3015.7; HBM 100pF discharged through 1.5k
E001 Vd()
2
kV
E002 Vb() TG1 Tj TG2 Ts
Permissible Burst-Transients at IO0..7 according to IEC 1000-4-4 Junction Temperature Storage Temperature -40 -40
4 150 150
kV EC EC
(*) IOx= hi: pin set to output, active high, x= 0..7
THERMAL DATA
Operating Conditions: VCCD= VCCA= 5V 10%, VB= 19.2..25.2V GNDA= GNDD= PGND= 0V, alle inputs wired (to hi respectively to lo) Item T1 T2 Symbol Ta Rthja Parameter Operating Ambient Temperature Range Thermal Resistance Chip to Ambient surface mounted on PCB, no additional cooling areas Conditions Fig. Min. 0 55 Typ. Max. 70 EC K/W Unit
All voltages are referenced to ground unless otherwise noted. All currents into the device pins are positive; all currents out of the device pins are negative.
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 14/23 ELECTRICAL CHARACTERISTICS
Operating Conditions: VCCD= VCCA= 5V 10%, VB= 19.2..25.2V, GNDA= GNDD= PGND= 0V, all inputs wired (to hi respectively to lo), Tj= 0..125EC unless otherwise noted. Item Symbol Parameter Conditions Tj C Total Device 001 VCCA 002 I(VCCA) 003 I(VCCA) 004 VCCD Permissible Supply Voltage VCCA Supply Current in VCCA Supply Current in VCCA Permissible Supply Voltage VCCD all logic inputs lo= 0V or hi= VCCD continously repeated read access: tlo(RDN)= thi(RDN)= 200ns; data word changes every other cycle between "00" and "FF", CL(D0..7)= 200pF all logic inputs lo= 0.8V all logik inputs hi= 2.0V 19.2 POE= hi, IOx= hi, no load IOx= off I()= -20mA I()= 20mA I()= 20mA I()= -20mA I()= 20mA Vs()hi= VB -V(IOx); I(IOx)= -10mA Vs()hi= VB -V(IOx); I(IOx)= -100mA Vs()hi= VB -V(IOx); I(IOx)= -500mA, = 2ms, T$ 2s IOx= hi, V(IOx)= 0..VB-3V 1 1 2 -1.8 -1.2 I(IOx)= -100mA CL= 0..100pF, RL= 240..1k CL= 0..100pF, RL= 240..1k write cycle, WRN: lo6hi until V(IOx) > V0(IOx)+1V write cycle, WRN= lo6hi until V(IOx) < 80% (VB-Vs(IOx)hi) -15 15 15 30 -30 30 47 47 -1.4 8.5 2 80 100 25.2 14 4 -0.3 11 60 -10 60 0.2 0.6 2 -0.55 -0.55 -12 40 40 5 5 no supply voltage VB 4.5 0.3 4.5 7.5 5.5 13 25 5.5 3 35 V mA mA V mA mA Fig. Min. Typ. Max. Unit
005 I(VCCD) Supply Current in VCCD (static) 006 I(VCCD) Supply Current in VCCD (dynamic)
007 I(VCCD) Supply Current in VCCD 008 I(VCCD) Supply Current in VCCD 009 VB 010 I(VB) 011 I(VB) 012 Vc()lo 013 Vc()hi 014 Vc()hi 015 Vc()lo 016 Vc()hi 101 Vs()hi 102 Vs()hi 103 Vs()hi 104 Isc()hi 105 It()scs 106 Vc()lo 107 SRhi() 108 SRlo() 109 tplh() 110 tphl() Permissible Supply Voltage VB (operating range) Supply Current in VB Supply Current in VB ESD Clamp Voltage lo at VCCA, VCCD, VB ESD Clamp Voltage hi at VCCA ESD Clamp Voltage hi at VB ESD Clamp Voltage lo at IOx ESD Clamp Voltage hi at IOx Saturation Voltage hi Saturation Voltage hi Saturation Voltage hi for pulse load Overcurrent Cut-off Threshold Current for Overcurrent Message Free-wheeling Clamp Voltage Slew Rate hi Slew Rate lo Propagation Delay until IOx: lo6hi Propagation Delay until IOx= off
mA mA V mA mA V V V V V V V V A A V V/s V/s s s
I/O Stages: High-Side Driver IO0..7
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 15/23 ELECTRICAL CHARACTERISTICS
Operating Conditions: VCCD= VCCA= 5V 10%, VB= 19.2..25.2V, GNDA= GNDD= PGND= 0V, all inputs wired (to hi respectively to lo), Tj= 0..125EC unless otherwise noted. Item Symbol Parameter Conditions Tj C I/O Stages: Current Sources at IO0..7 201 Ipd() Pull-down Current Source (200A) Pull-down Current Source (600A) Pull-down Current Source (2mA) Pull-up Current Source (200A) IOx with input function, IL1= IH1= 0, IL0= IH0= 1, V(IOx)= 3V..VB IOx with input function, IL1= IH1= 1, IL0= IH0= 0, V(IOx)= 3V..VB IOx with input function, IL1= IH1= 1, IL0= IH0= 1, V(IOx)= 3V..VB IOx with output function and IOx= off, IL0, IH0= 1; V(IOx)= -7V..VB-2V write cycle, WRN: lo6hi til I(IOx) > 90% Ipd(IOx) or I(IOx) > 90% Ipu(IOx) write cycle, WRN: lo6hi til I(IOx) < 10% Ipd(IOx) or I(IOx) < 10% Ipu(IOx) IOx with input function or output function with IOx= off and IL1, IH1, IL0, IH0= 0; V(IOx)= -7V..VB logic see item 207; V(IOx)= -10V..-7V logic see item 207; V(IOx)= VB..VB+0.4V logic see item 207; V(IOx)= VB..30V no supply voltage VB V(VB)= 0..25.2V, (see also max. rating G003) IOx with input function IOx with input function IOx with input function, Vt()hys= Vt()hi -Vt()lo IOx with output function, Vt()hi= VB -V(IOx) IOx with output function, Vt()lo= VB -V(IOx) IOx with output function, Vt()hys= Vt()lo -Vt()hi I/O filter inactive, CSN= lo, RDN= lo, A0..4= lo 100 10 66 100 5 6.7 -20 120 200 280 A Fig. Min. Typ. Max. Unit
202 Ipd()
400
600
800
A
203 Ipd()
1.4
2
2.7
mA
204 Ipu()
120
200
280
A
205 tp()Ion
Current Source Enable Time (pull-down and pull-up sources) Current Source Disable Time (pull-down and pull-up sources) Leakage Current
5
s
206 tp()Ioff
5
s
207 Ilk()
20
A
208 Ilk() 209 Ilk() 210 Ilk() 211 Ilk() 301 Vin() 302 Vt()hi 303 Vt()lo 304 Vt()hys 305 Vt()hi 306 Vt()lo 307 Vt()hys 308 tp(IOx -Dx)
Leakage Current Leakage Current Leakage Current Leakage Current Permissible Input Voltage referenced to VB Threshold Voltage hi Threshold Voltage lo Hysteresis Threshold Voltage hi referenced to VB Threshold Voltage lo referenced to VB Hysteresis Propagation Delay Input IOx to Data Output Dx
-100 -20 200
20 100 500 5 25.2 82
A A A mA V %VCC %VCC mV V V mV s
I/O Stages: Comparator IO0..7
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 16/23 ELECTRICAL CHARACTERISTICS
Operating Conditions: VCCD= VCCA= 5V 10%, VB= 19.2..25.2V, GNDA= GNDD= PGND= 0V, all inputs wired (to hi respectively to lo), Tj= 0..125EC unless otherwise noted. Item Symbol Parameter Conditions Tj C Thermal Shutdown 401 Toff1 402 Toff1 403 Thys1 404 Toff2 405 Ton2 406 Thys2 407 T Over-Temperature Threshold Level 1: warning Level 1 Release Level 1 Hysteresis Over-Temperature Threshold Level 2: shutdown Level 2 Release Level 2 Hysteresis Temperatur Difference Level 2 to Level 1 Thys2= Toff2 -Ton2 T= Toff2 -Toff1 Thys1= Ton1 -Toff1 105 100 2 130 100 22 20 130 125 7 155 125 37 30 EC EC EC EC EC EC EC Fig. Min. Typ. Max. Unit
Bias and Low Voltage Detection 501 VCCAon Turn-on Threshold VCCA (Power-on release) 502 VCCAoff Undervoltage Threshold VCCA (Power-down reset) 503 VCCAhys Hysteresis 504 toff 505 tdoff Power Down Time required for low voltage detection Propagation Delay until Reset after Low Voltage at VCCA Leakage Current in Dx Input Current in Schmitt-Trigger Input CSN, WRN ,RDN, A0..4, RESN, CLK, BLFQ, D0..7 Threshold Voltage hi at Schmitt-Trigger Input CSN, WRN, RDN, A0..4, RESN, CLK, BLFQ, D0..7 Threshold Voltage lo at Schmitt-Trigger Input CSN, WRN, RDN, A0..4, RESN, CLK, BLFQ, D0..7 Schmitt-Trigger Input Hysteresis CSN, WRN, RDN, A0..4, RESN, CLK, BLFQ, D0..7 Saturation Voltage hi at INTN Saturation Voltage lo at INTN Saturation Voltage hi at Dx Saturation Voltage lo at Dx D0..7 with input function V()= 0V..VCCD, D0..7 with input function D0..7 with input function -5 -1 VCCAhys= VCCAon -VCCAoff VCCA= 2.5V..VCCAoff 3.9 3.8 80 1 12 4.1 4 100 4.4 4.3 130 V V mV s s
P Interface, I/O Logic, Frequency Divider, Interrupt 701 Ilk(Dx) 702 Ii() 5 1 A A
703 Vt()hi
2.2
V
704 Vt()lo
D0..7 with input function
0.8
V
705 Vt()hys
Vt()hys= Vt()hi-Vt()lo; D0..7 with input function Vs()hi= VCCD -V(INTN); I(INTN)= -2mA I(INTN)= 100A I(INTN)= 2mA Vs()hi= VCCD -V(Dx); I(Dx)= -4mA I(Dx)= 4mA
300
mV
706 Vs()hi 707 Vs()lo 708 Vs()hi 709 Vs()lo
0.8 0.2 0.49 0.8 0.49
V V V V V
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 17/23 ELECTRICAL CHARACTERISTICS
Operating Conditions: VCCD= VCCA= 5V 10%, VB= 19.2..25.2V, GNDA= GNDD= PGND= 0V, all inputs wired (to hi respectively to lo), Tj= 0..125EC unless otherwise noted. Item Symbol Parameter Conditions Tj C P Interface, I/O Logic, Frequency Divider, Interrupt (cont`d) 710 Vc()hi ESD Clamp Voltage hi at CSN, WRN, RDN, A0..4, RESN, CLK, BLFQ, D0..7, INTN ESD Clamp Voltage lo at CSN, WRN, RDN, A0..4, RESN, CLK, BLFQ, D0..7, INTN Threshold Voltage hi Threshold Voltage lo Hysteresis Pull-Down Resistor Disable/Enable Pulse Width Permissible Interference Pulse Width Power Output Switch-off Delay POE: hi6lo until IOx disabled, ie. V(IOx)< 80% (VB -Vs(IOx)hi), RL= 240..1k Vc()hi= V(POE) -VCCA; I(POE)= 20mA I(POE)= -20mA 0.8 -1.5 800 400 100 50 Vt()hys= Vt()hi -t()lo 0.8 300 24 1000 100 5 72 Vc()hi= V() -VCCD; D0..7 with input function, I()= 20mA D0..7 with input function, I()= -20mA 0.4 1.5 V Fig. Min. Typ. Max. Unit
711 Vc()lo
-1.5
-0.4
V
Input POE F01 Vt()hi F02 Vt()lo F03 Vt()hys F04 Rpd() F05 tw()lo F06 tsup() F07 td(POEIOx) F08 Vc()hi F09 Vc()lo 801 td() 802 tw() 803 td() 804 tw() 2.2 V V mV k ns ns s
ESD Clamp Voltage hi ESD Clamp Spannung lo Permissible Cycle Duration at CLK Permis. Pulse Width lo at CLK Permissible Cycle Duration at BLFQ Permis. Pulse Width lo at BLFQ
2 -0.4
V V ns ns ms ms
Switching Characteristics
ELECTRICAL CHARACTERISTICS: WAVEFORMS
I
IOxpeak I
IOxmax IOxdc t
T
t
Fig. 1: DC load
Fig. 2: Pulse load, pulse duration 2 ms
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 18/23 OPERATING REQUIREMENTS: P INTERFACE
Operating Cconditions: VCCD, VCCA= 5V 10%, VB= 19.2..25.2V, GNDA= GNDD= PGND= 0V, Ta= 0..70EC, CL()= 150pF, input levels lo= 0.45V, hi= 2.4V, see Fig. 3 for reference levels Item Symbol Parameter Conditions Fig. Min. Data Word Read Timing I1 I2 I3 I4 I5 tAR1 tAR2 tRA tRD tDF tRL Setup Time: CSN, A0..4 set before RDN hi6lo Hold Time: CSN, A0..4 stable after RDN lo6hi Read Data Access Time: data valid after RDN hi6lo Read Data Hold Time: ports high impedance after RDN lo6hi Required Read Signal Duration at RDN Setup Time: CSN, A0..4 set before WRN hi6lo Write Data Setup Time: data valid before WRN lo6hi Hold Time: CSN, A0..4 stable after WRN lo6hi Write Data Hold Time: data valid after WRN lo6hi Required Write Signal Duration at WRN Recovery Time between cycles: RDN lo6hi to RDN hi6lo, RDN lo6hi to WRN hi6lo, WRN lo6hi to WDN hi6lo, WRN lo6hi to RDN hi6lo 4 4 4 4 4 4 4 4 4 50 30 10 120 65 ns ns ns ns ns Max. Unit
Data Word Write Timing I6 I7 I8 I9 I10 tAW1 tAW2 tDW tWA tWD tWL 30 100 10 10 50 ns ns ns ns ns
Read/Write Timing I11 tcyc 4 165 ns
Fig. 3: Reference levels
Fig. 4: Data word read/write timing
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 19/23 DESCRIPTION OF FUNCTIONS iC-JRX is a bidirectional device which can analyze signals at the I/O pins and drive loads connected to ground. The input and output modes can be set in blocks of 4 bits (using nibbles). I/O stages in input mode pass on the external signal via digital filtering which can be switched off as required by way of a bypass. Changes of level at any one input can generate an interrupt at the INTN port - providing that messaging is enabled. Individually programmable low-side current sources are available for each pin, enabling logic levels for the inputs to be defined (ranges 200 A, 600 A and 2 mA). I/O stages in output mode can switch currents of up to 500 mA. A 200 A high-side current source can be activated to check the load for any interruptions. A PWM function and a flash mode for indicator lamps are integrated in the device, both of which can be selected for any chosen output pin. If overcurrent is determined at any of the outputs, caused for example by a short-circuit, this can be reported as an interrupt if suitably enabled. If the device exceeds normal operating temperature, an interrupt gives a temperature warning; if, following this, the device continues to overheat, the outputs are shutdown. I/O stages in input mode Input register (add. 0): reads the inputs A hi level at IOx generates a hi signal at Dx. Any change to an input signal is accepted via digital filtering only after the chosen filter time has ended. Doing this, the input comparator of each I/O stage switches the count direction of a 3-bit counter. The counter output changes only when the final status is reached. The counters are reset to a value of 3 by a lo signal at the RESN reset input. The counter is clocked externally via the CLK pin. The scaling factor for the clock frequency and the input filter bypass can be programmed separately for both nibbles (the bypass with BYPH or BYPL in control word 1). Switching the bypass permits operation without an external clock signal (see below). After the change-of-input message has been enabled (add. 8) a change of level at one of the I/O pins is signaled via an interrupt to the microcontroller. I/O stages in output mode Input register (add. 0): reads the output feedback A hi level at IOx generates a hi signal at Dx. Through this, the microcontroller can make a direct check of the switching state and, in conjunction with the 200 A high-side current source, can monitor the channel for any cable fractures. As with the input read, the read-back signals can be reprocessed in their filtered or unfiltered state. Output register (add. 6): switches the various output stages on and off (for POE= 1) Flash pulse enable (add. 7): enables flash mode With this, each of the various output stages can be set to flash mode, providing the value of the corresponding output register is `1'. The flash frequency is derived from BLFQ or, alternatively, can be generated from CLK (via NOBLFQ in control word 3). Different flash frequencies can be set for both nibbles (ports 0..3 and 4..7). PWM enable (add. 14) A PWM signal for any chosen output stage can be activated with the aid of PWMEN in control word 5. The I/O stage is selected using PWMADR2..0. PWMPN determines the direction of the PWM signal (active hi or active lo). The shape of the PWM signal is given by the value of the PWM register (add. 15), multiplied by 16xtd(CLK).
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 20/23 Interrupts Interrupt outputs at INTN can be triggered by a change of (filtered) input signal, by overcurrent, signaled at an I/O pin (e.g. due to a short circuit), or by exceeding maximum temperature levels (2 stages). For each individual I/O stage, interrupt outputs can be caused by a change of input, or, with stages in output mode, also by a short circuit. The relevant interrupt enables determine which messages are stored and displayed. The display of interrupt messages caused by excessive temperature is not maskable; it is permanently enabled. When an event occurs which is enabled to produce an interrupt output, pin INTN is set to `0'. An interrupt status register read-out (add. 2) enables the nature of the message to be determined and the I/O stage causing the interrupt to be located. Thus with a change-of-input message the initiating I/O stage is shown in the corresponding register (add. 1); with an overcurrent interrupt, the overcurrent message register (add. 3) pinpoints the I/O stage with a short circuit. Interrupts are deleted by simply setting EOI in control word 4. This bit then automatically resets to `0'. If during operation the I/O mode is switched, i.e. from input to output mode, all interrupt messages are deleted via EOI. To avoid interrupt messages caused by other sources in the time between the read-out of an interrupt register and the deletion of the current interrupt being overlooked, successive interrupts are stored in a pipeline. In the event of there being any successive interrupts, output INTN remains at `0' after the current interrupt has been deleted using EOI. The new interrupt source is shown in the interrupt status register and in the type-specific status registers. Overcurrent messages With an overload at one of the outputs the current in IOx is limited. In this instance an interrupt message is displayed, providing relevant interrupt enables have been set for overcurrent messages (add. 9) and the filter time set with control word 4 has elapsed. If this happens, ISCI is set in the interrupt status register (add. 2) and the relevant bit is set for the initiating I/O stage in the overcurrent message register (add. 3). Under address 4 the current, unfiltered overcurrent status of each I/O stage can be read; an overall scan of all the I/O stages is also possible via bit SCS of the interrupt status register. This shows whether any of the I/O stages have overcurrent at the time of the readout. This short-circuit messaging allows permanent monitoring of the output transistors and clear allocation of the error message to the I/O stage affected. Filtering of the overcurrent message can be shutdown via a bypass; this bypass can be activated for all I/O stages together using BYPSCF in control word 4 (add. 13). Temperature monitoring iC-JRX has a two-stage temperature monitor circuit. Stage 1: A warning interrupt (INTN= 0) is generated if the first temperature level (Toff 1 at ca. 125 EC) is exceeded. Suitable measures to decrease the power dissipation of the driver can be implemented via the microcontroller. If the second temperature level is exceeded (Toff 2 at ca. 150 EC), a second interrupt is generated (INTN= 0). At the same time the output transistors and the I/O stage current sources are shutdown, the output register and flash mode enable deleted. Once the temperature level has returned to below that of Toff1 the current sources are reactivated. The output register and flash pulse enable have to be respecified to activate the output stages.
Stage 2:
The interrupt status register (add. 2) gives information as to the stage of temperature interrupt but also on the current status of the temperature monitor. ET2 and ET1 statically indicate when Toff2 and Toff1 are exceeded, whereby the stored interrupt messages IET2 and IET1 and the display at INTN via EOI= 1 can be deleted (control word 4).
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 21/23 Low voltage detection When the supply voltage at VCC is switched on, the output transistors are only released by the low voltage detector after the power-on enable VCCon has been reached. Should the supply voltage drop to VCCoff during operation, the I/O stages are disabled, i.e. the output transistors are turned off and the device reset (signal VOK). If the supply voltage should then rise to VCCon, iC-JRX is in its reset state. Identification of the device An identification code has been introduced to enable identification of device iC-JRX. Bit pattern `000000'b can be read out under address 5. Reset A reset (RESN= 0) sets the register entries to the reset values given in the tables. The output transistors and the current sources in the I/O stages are shutdown and all stages switched to input mode. Operation without the BLFQ signal Should no clock signal be available at pin BLFQ, iC-JRX can generate the flash pulse internally from the clock signal at pin CLK. To this end, NOBLFQ in control word 3 must be set to `1'. The flash period is then calculated from the clocking pulse at CLK by division by 219. Operation without the CLK signal iC-JRX is operable without a clocking pulse at the CLK pin. With NOCLK in control word 3 the clocked filtering for the I/O signals and overcurrent messaging is deactivated. The device remains fully functional with one exception; the PWM cannot be activated, as this is dependent on CLK. The same behavior can be obtained by setting BYPH and BYPL in control word 1 together with BYPSCF in control word 4; all filters are avoided by way of a bypass circuit. This has one disadvantage, namely that interferences in the load lines, for example, can lead to the unwanted display of interrupts. Forced shutdown of output stages The output stages can be forcibly shutdown at input POE. A `1' enables logic access to the drivers; an `0' disables this. With this, a processor-independent watchdog can lock the outputs in the event of error, for example. An integrated pull-down resistor increases safety.
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 22/23 Pulse-width modulation This function can be activated for any chosen I/O stage in output mode. First the duty cycle is determined via the PWM register in 256 steps within one PWM period. Pulse direction and the address for the desired driver stage is selected via control word 5 (PWMPN, PWMADR2..0). The PWM enable bit can now also be set via control word 5. With this enable, the current source and any active flash mode for the selected output are automatically switched off. The set duty cycle is activated when a new PWM period is started. A PWM signal is set at the selected output, whose frequency is determined by the clock signal at CLK and whose duty cycle follows the PWM register.
The following correlations apply: Fig. 5: PWM signal form fPWM ' fCLK 4096 ; tPWM ' 1 ; fPWM x 256 tPWMlo ' (PWMLEN %1) x tPWM
fCLK fPWM tPWM tPWMlo PWMLEN
: Clock frequency CLK : frequency for the PWM signal at IOx : Smallest possible pulse duration `lo' (8 s with a 2 MHz clock) : pulse duration `lo' (Iox = OFF with PWMPN = 1) : Count pulse duration `lo' stored in register PWM7..0
Selectable Pulse-Pause Ratios
PWM7..0 '00'h PWMPN 0 1 0 '01'h .. 'FE'h 1 0 1 Output signal Output stage "ON", Pin Iox = '1' Output stage "OFF", Pin Iox = '0' Output pin IOx goes for (PWMLEN + 1) x tPWM to '0', and then for (255 - PWMLEN) x tPWM to '1' Output pin IOx goes for (PWMLEN + 1) x tPWM to '1', and then for (255 - PWMLEN) x tPWM to '0' Output stage "OFF", Pin Iox = '0' Output stage "ON", Pin Iox = '1' (reset entry)
'FF'h
This specification is for a newly developed product. iC-Haus therefore reserves the right to change or update, without notice, any information contained herein, design and specification; and to discontinue or limit production or distribution of any product versions. Please contact iC-Haus to ascertain the current data. Copying - even as an excerpt - is only permitted with iC-Haus approval in writing and precise reference to source. iC-Haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
iC-JRX
P INTERFACE WITH 2x4 24V HIGH-SIDE DRIVERS
Rev A1, Page 23/23 ORDERING INFORMATION
Type iC-JRX
Package PLCC44
Order designation iC-JRX PLCC44
For information about prices, terms of delivery, options for other case types, etc., please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel +49-6135-9292-0 Fax +49-6135-9292-192 http://www.ichaus.com

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