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Data Sheet, Rev. 1.2, April 2009
TLE7273-2
Low Dropout Voltage Regulator
Automotive Power
Low Dropout Voltage Regulator
TLE7273-2
1
Features * * * * * * * * * * * * *
Overview
Output Voltage 5 V, 3.3 V or 2.6 V Output Voltage Tolerance 2% Up To 180mA Ultra Low Quiescent Current Consumption < 36 A Enable Function Very Low Dropout Voltage Reset With Adjustable Power-On delay Window Watchdog With Current Dependent Deactivation Output Current Limitation Wide Operation Range Up To 45 V Wide Temperature Range From -40 C To 150 C Overtemperature Shutdown Green Product (RoHS compliant) AEC Qualified
PG-DSO-14
Description
PG-SSOP-14 Exposed Pad
The TLE7273-2 is a monolithic voltage regulator with integrated window watchdog and reset dedicated for microcontroller supplies under harsh automotive environment conditions. Due to its ultra low quiescent current, the TLE7273-2 is perfectly suited for applications that are permanently connected to battery. In addition, the regulator can be shut down via the Enable input causing the current consumption to drop below 3 A. The TLE7273-2 is equipped with an output current limitation and an overtemperature shutdown, protecting the device against overload, short circuit and over-temperature. It operates in the wide junction temperature range from -40 C to 150 C.
Type TLE7273-2GV50 TLE7273-2GV33 TLE7273-2GV26 TLE7273-2EV50 Data Sheet
Package PG-DSO-14 PG-DSO-14 PG-DSO-14 PG-SSOP-14 Exposed Pad 2
Marking TLE7273-2GV50 TLE7273-2GV33 TLE7273-2GV26 7273 V50 Rev. 1.2, 2009-04-28
TLE7273-2
Block Diagram
2
Block Diagram
I
TLE7273-2
Q
Overtemperature shutdown RO Bandgap Reference 1 Reset Generator and Window Watchdog
WDI
Charge Pump
WM1 WM2
EN
Enable
GND
Figure 1
Block Diagram
Data Sheet
3
Rev. 1.2, 2009-04-28
TLE7273-2
Pin Configuration
3
3.1
Pin Configuration
Pin Assignment (PG-DSO-14)
RO GND GND GND GND WM2 WM1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 EN I GND GND GND Q WDI
AEP02113_7273
Figure 2
Pin Assignment PG-DSO-14 (top view)
3.2
Table 1 Pin No. 1
Pin Definitions and Functions (PG-DSO-14)
Pin Definitions and Functions Symbol RO Function Reset Output TLE7273-2GV33, TLE7273-2GV26: open drain output; TLE7273-2GV50: integrated 20 k pull-up resistor to output Q; leave open if not needed Ground connect pin 2 and 3 to GND; connect pin 4-5 and 10-12 to heat sink area with GND potential Watchdog Mode Bit 1 watchdog and reset mode selection, see "Window Watchdog State Diagram, Watchdog and Reset Modes" on Page 9; connect to Q or GND Watchdog Mode Bit 2 watchdog and reset mode selection, see "Window Watchdog State Diagram, Watchdog and Reset Modes" on Page 9; connect to Q or GND Watchdog Input trigger input for watchdog pulses; to turn off watchdog connect to GND and connect pin WM1 and WM2 to Q Output Voltage block to GND with a ceramic capacitor close to the IC terminals, respecting the values given for its capacitance and ESR in "Functional Range" on Page 7 Input Voltage block to ground directly at the IC with a 100 nF ceramic capacitor Enable Input low level disables the IC; integrated pull-down resistor to GND
2-5, 10-12
GND
7
WM1
6
WM2
8
WDI
9
Q
13 14
I EN
Data Sheet
4
Rev. 1.2, 2009-04-28
TLE7273-2
Pin Configuration
3.3
Pin Assignments (PG-SSOP-14 Exposed Pad)
Figure 3
Pin Assignment PG-SSOP-14 Exposed Pad (top view)
3.4
Table 2 Pin No. 1
Pin Definitions and Functions (PG-SSOP-14 Exposed Pad)
Pin Definitions and Functions Symbol RO Function Reset Output integrated 20 k pull-up resistor (TLE7273-2EV50); leave open if not needed Ground connect to GND not connected leave open or connect to GND Watchdog Mode Bit 2 watchdog and reset mode selection, see Figure 5; connect to VQ or GND Watchdog Mode Bit 1 watchdog and reset mode selection, see Figure 5; connect to VQ or GND Watchdog Input trigger input for watchdog pulses; pull down to GND if not needed and turn off the watchdog with WM1 and WM2 pin Output Voltage block to GND with a ceramic capacitor CQ 470 nF close to IC terminal Input Voltage block to ground directly at the IC with a 100 nF ceramic capacitor Enable Input low level disables the IC; integrated pull-down resistor Exposed Pad connect to heatsink area; connect with GND on PCB
2, 5 3, 4, 10, 11, 12 6
GND n.c. WM2
7
WM1
8
WDI
9 13 14
Q I EN
Pad
-
Data Sheet
5
Rev. 1.2, 2009-04-28
TLE7273-2
General Product Characteristics
4
4.1
Table 3 Pos. Input I 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9
General Product Characteristics
Absolute Maximum Ratings
Absolute Maximum Ratings1) Parameter Symbol Limit Values Min. Voltage Voltage Voltage Voltage Current Voltage Voltage Voltage Current Max. 45 5.5 6.2 45 1 7 5.5 6.2 5 3 1.5 150 150 V V V V mA V V V mA kV kV C C - permanent Unit Remarks
-40 C < Tj < 150 C
VI VQ VQ VEN IEN VRO VWM1 VWM1 IWM1
-0.3 -0.3 -0.3 -1 -1 -1 -0.3 -0.3 -5
Output Q, Reset Output RO, Watchdog Mode 2
t < 10 s2)
- - permanent permanent
Enable Input EN
Watchdog Input WDI Watchdog Mode 1
t < 10 s2)
- - - - -
ESD Susceptibility 4.1.10 Human Body Model (HBM)3) 4.1.11 Charged Device Model (CDM) Temperatures 4.1.12 Junction Temperature 4.1.13 Storage Temperature
1) 2) 3) 4)
4)
Voltage Voltage -
Tj Tstg
-40 -50
not subject to production test, specified by design exposure to these absolute maximum ratings for extended periods (t > 10 s) may affect device reliability ESD HBM Test according JEDEC JESD22-A114 ESD CDM Test according AEC/ESDA ESD-STM5.3.1-1999
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Integrated protection functions are designed to prevent IC destruction under fault conditions. Fault conditions are considered as outside normal operating range. Protections functions are not designed for continuous repetitive operation.
Data Sheet
6
Rev. 1.2, 2009-04-28
TLE7273-2
General Product Characteristics
4.2
Pos. 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5
Functional Range
Parameter Input Voltage Symbol Limit Values Min. Max. 45 45 45 - 3 V V V nF TLE7273-2GV50, TLE7273-2EV50 TLE7273-2GV33 TLE7273-2GV26 -1) -2) 5.5 4.2 4.5 Output Capacitor's Requirements for Stability Unit Remarks
VI
CQ 470 ESR(CQ) -
1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30% 2) relevant ESR value at f = 10 kHz
Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Pos.
Thermal Resistances
Parameter Symbol Min. Limit Values Typ. 30 53 105 74 65 Max. - - - - - K/W measured to group of pins 3, 4, 5, 10, 11, 12 K/W
2)
Unit Remarks
Package PG-DSO-14 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 Package PG-SSOP-14 Exposed Pad 4.3.6 4.3.7 4.3.8 4.3.9 4.3.10 Junction to Case1) Junction to Ambient
1)
Junction to Soldering Point1) Junction to Ambient1)
RthJSP RthJA
- - - - -
K/W footprint only3) K/W 300 mm2 heatsink area on PCB3) K/W 600 mm2 heatsink area on PCB3) K/W measured to exposed pad K/W
2)
RthJSP RthJA
- - - - -
14 47 141 66 56
- - - - -
K/W footprint only3) K/W 300 mm2 heatsink area on PCB3) K/W 600 mm2 heatsink area on PCB3)
1) not subject to production test, specified by design 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70m Cu, 2 x 35m Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm3 board with 1 copper layer (1 x 70m Cu).
Data Sheet
7
Rev. 1.2, 2009-04-28
TLE7273-2
Block Description and Electrical Characteristics
5
5.1 5.1.1
Block Description and Electrical Characteristics
Description Power On Reset and Reset Output
For an output voltage level of VQ 1 V, the reset output is held low. When the level of VQ reaches the reset threshold VRT, the signal at RO remains low for the power-up reset delay time tRD. The reset function and timing is illustrated in Figure 4. The reset reaction time tRR avoids wrong triggering caused by short "glitches" on the VQline. In case of VQ power down (VQ < VRT for t > tRR) a logic low signal is generated at the pin RO to reset an external microcontroller. The TLE7273-2GV50 and TLE7273-2EV50 feature an integrated pull-up resistor on the reset output while the TLE7273-2GV33 and TLE7273-2GV26 have an open drain output requiring an external pull-up resistor. When connected to a voltage level of 5 V, a recommended value for this external resistor is 5.6 k. But it's also possible calculating its value by using the following formula, based on the reset sink current (Example: external pull-up resistor connected to Vext = 5 V):
Rextmin = V / IRO = (Vext - VROmin) / IRO = (5 V - 0.25 V) / 1.0 mA = 4.75 k At low output voltage levels VQ < 1 V the integrated pull-up resistor of the TLE7273-2GV50 is switched off setting
the reset output high ohmic.
VI
VRTI
t
VQ < tRR
VRT
VRO VROH VROL
tRD
t RR
tRR
t
t
AET03526NEW.VSD
Figure 4
Reset Function and Timing Diagram
5.1.2
Watchdog Operation
The watchdog uses a fraction of the charge pump oscillator's clock signal as timebase. The watchdog timebase can be adjusted using the pins WM1 and WM2 (see Figure 5). The watchdog can be turned off setting WM1 and WM2 to high level. The timing values refer to typ. values with WM1 and WM2 connected to GND (fast watchdog and reset timing). Figure 5 shows the state diagram of the window watchdog (WWD) and the watchdog and reset mode selection. After power-on, the reset output signal at the RO pin (microcontroller reset) is kept LOW for the reset delay time tRD of typ. 16 ms. With the LOW to HIGH transition of the signal at RO the device starts the ignore window time tCW (32 ms). During this window the signal at the WDI pin is ignored. Next the WWD starts the open window which
Data Sheet
8
Rev. 1.2, 2009-04-28
TLE7273-2
Block Description and Electrical Characteristics is in the very first turn after power up a long open window with tmax = 4 * tOW. In the following turns, the timing corresponds to the standard timing setting as described in the specification. When a valid trigger signal is detected during the open window a closed window is initialized immediately. A trigger signal within the closed window is interpreted as a pretrigger failure and results in a reset. After the closed window the open window with the duration tOW is started again. The open window lasts at minimum until the trigger process has occurred, at maximum tOW is 32 ms (typ. value with fast timing). A HIGH to LOW transition of the watchdog trigger signal at pin WDI is considered as a valid trigger pulse. See Figure 7: To avoid wrong triggering due to parasitic glitches two HIGH samples followed by two LOW samples (sample period tsam typ. 0.5 ms) are decoded as a valid trigger . A reset is generated (RO goes LOW) if there is no trigger pulse during the open window or if a pretrigger occurs during the closed window. The triggering is correct also, if the first three samples (two HIGH one LOW) of the trigger pulse at pin WDI are inside the closed window and only the fourth sample (the second LOW sample) is taken in the open window. After turning OFF the Watchdog by output current reduction, RO remains high. (see also the signal diagram in Figure 6). After turning ON the WWD again by exceeding the current threshold, the logic cycle starts again with the Ignore Window and goes then into the "1st. long open window". This 1st long OW is maximum 4 * tOW long and allows the re-synchronisation between the micro controller and the WWD timing. The 1st. long OW is closed by the first valid trigger on WDI from the mirco controller. This trigger ensures the synchronisation. As soon as this trigger is done, the micro controller timing must be stable and correspondent to tWD.
Reset Trigger
Always
Ignore Window IQ > 5mA
No Trigger During Open Window Always Trigger During Closed Window Watchdog OFF
Trigger Closed Window No Trigger Open Window
IQ < 0.5mA Always
WM1 WM2 Window Watchdog Mode Reset Mode
L L Fast Fast
L H Slow Slow
H L Fast Slow
H H Off Slow
AEA03527_1.VSD
Figure 5
Window Watchdog State Diagram, Watchdog and Reset Modes
Data Sheet
9
Rev. 1.2, 2009-04-28
TLE7273-2
Block Description and Electrical Characteristics
Vi/V t VQ/V VRT t IQ/A IQ, WD_OFF VRO/V TRD
Normal operation
IQ, WD_ON t
TRD
TRD
No Reset during Current shut down
Power Fail
trr
trr t
Wnd Ingnore Wnd
Don't care WDI during IW
1. long OW
CW
OW
CW
OW
1. long OW
CW
(Wrong) Trigger in CW
1. long OW
1. long OW
1st long open window to synchronize WD Current Controlled WD-turn off
OW
CW t
1. Correct Trigger
WDI/V
tWD,p
No Trigger in OW
t
Figure 6
Window Watchdog Signal Diagram
Closed window
Open window
Watchdog trigger signal
Open window
Closed window
WDI
Valid
WDI
Not valid
t ECW t EOW
AET02952
= Watchdog decoder sample point
Figure 7
Window Watchdog Definitions
Data Sheet
10
Rev. 1.2, 2009-04-28
TLE7273-2
Block Description and Electrical Characteristics
5.2
Electrical Characteristics
Electrical Characteristics VI =13.5 V; - 40 C < Tj < 150 C; unless otherwise specified Pos. Parameter Symbol Limit Values Min. Output Q 5.2.1 Output Voltage
Typ. Max.
Unit Test Condition
VQ
4.90
5.00
5.10
V
TLE7273-2GV50, TLE7273-2EV50 1 mA < IQ < 180 mA 6 V < VI < 16 V TLE7273-2GV50, TLE7273-2EV50 IQ = 10 mA 6 V < VI < 45 V TLE7273-2GV33 1 mA < IQ < 180 mA 4.5 V < VI < 16 V TLE7273-2GV33 IQ = 10 mA 4.5 V < VI < 45 V TLE7273-2GV26 1 mA < IQ < 180 mA 4.5 V < VI < 16 V TLE7273-2GV26 IQ = 10 mA 4.5 V < VI < 45 V
5.2.2
Output Voltage
VQ
4.90
5.00
5.10
V
5.2.3
Output Voltage
VQ
3.234 3.30
3.366 V
5.2.4
Output Voltage
VQ
3.234 3.30
3.366 V
5.2.5
Output Voltage
VQ
2.548 2.60
2.652 V
5.2.6
Output Voltage
VQ
2.548 2.60
2.652 V
5.2.7 5.2.8 5.2.9
Output Current Limitation Dropout Voltage VDR = VI - VQ
1)
IQ VDR
200 200 -
- - 250
500 600 500
mA mV
VQ = 2.0 V VQ = 0 V IQ = 180 mA
TLE7273-2GV50, TLE7273-2EV50
5.2.10 5.2.11 5.2.12 5.2.13
Load Regulation Line Regulation Power Supply Ripple Rejection Reverse Output Current Clamping
VQ,Lo VQ,Li
- - - -
50 10 60 -
90 50 - 5.5
mV mV dB V
1 mA < IQ < 180 mA;
PSRR VQ
IQ = 1 mA; 10 V < VI < 32 V fr = 100 Hz; Vr = 0.5 VPP IQ = -1 mA, VEN = 0 V IQ = 100 A; Tj < 80C VEN= 0V; Tj < 80C VQ on
Current Consumption 5.2.14 5.2.15 Quiescent Current Iq = II - IQ Quiescent Current Disabled High Level Input Voltage
Iq Iq
- -
28 1
36 3
A A
Enable Input EN 5.2.16
VEN,H
3.0
-
-
V
Data Sheet
11
Rev. 1.2, 2009-04-28
TLE7273-2
Block Description and Electrical Characteristics Electrical Characteristics VI =13.5 V; - 40 C < Tj < 150 C; unless otherwise specified Pos. 5.2.17 5.2.18 5.2.19 5.2.20 5.2.21 5.2.22 5.2.23 5.2.24 5.2.25 5.2.26 5.2.27 5.2.28 5.2.29 5.2.30 5.2.31 5.2.32 5.2.33 5.2.34 5.2.35 5.2.36 5.2.37 5.2.38 5.2.39 5.2.40 5.2.41 5.2.42 5.2.43 Window Watchdog Trigger Time
2)
Parameter Low Level Input Voltage
Symbol Limit Values Min.
Typ. Max.
Unit Test Condition 0.5 0.3 4 - - - 0.80 - - - 0.80 - - - 0.80 4 1 0.60 1.20 38.4 76.8 38.4 76.8 38.4 76.8 - - V V A V V V V V V V V V V V V A A ms ms ms ms ms ms ms ms ms ms
VWDI = 5 V VWDI = 0 V
VEN,L
- -
- - 3 - - - - - - - - - - - - 3 0.5 0.50 1.00 32.0 64.0 32.0 64.0 32.0 64.0 48 96
High Level Input Current High Level Input Voltage
IEN,H VWM1,H
- 4.00 2.65 2.30
VQ = 0.02 V; IQ = 5 mA; Tj < 125 C VQ = 0.02 V; IQ = 5 mA VEN = 5 V
TLE7273-2GV50, TLE7273-2EV50 TLE7273-2GV33 TLE7273-2GV26
Watchdog Mode Bit 1
Low Level Input Voltage High Level Input Voltage
VWM1,L VWM2,H
- 4.00 2.65 2.30
Watchdog Mode Bit 2 TLE7273-2GV50, TLE7273-2EV50 TLE7273-2GV33 TLE7273-2GV26
Low Level Input Voltage High Level Input Voltage
VWM2,L
VWDI,H
- 4.00 2.65 2.30
Watchdog Input WDI TLE7273-2GV50, TLE7273-2EV50 TLE7273-2GV33 TLE7273-2GV26
Low Level Input Voltage High Level Input Current Low Level Input Current Watchdog Sampling Time Ignore Window Time Open Window Time Closed Window Time
VWDI,L
IWDI,H IWD,IL
- - - 0.40 0.80 25.6 51.2 25.6 51.2 25.6 51.2 - -
Tj < 80 C
tsam
tIW
Fast Watchdog Timing Slow Watchdog Timing Fast Watchdog Timing Slow Watchdog Timing Fast Watchdog Timing Slow Watchdog Timing Fast Watchdog Timing Slow Watchdog Timing Fast Watchdog Timing Slow Watchdog Timing
tOW tCW
tWD
Data Sheet
12
Rev. 1.2, 2009-04-28
TLE7273-2
Block Description and Electrical Characteristics Electrical Characteristics VI =13.5 V; - 40 C < Tj < 150 C; unless otherwise specified Pos. 5.2.44 Parameter Watchdog Deactivation Current Threshold Symbol Limit Values Min.
Typ. Max.
Unit Test Condition - mA
IQ,WD_off 0.50
-
IQ decreasing VI > 5.5V for
TLE7273-2GV50, TLE7273-2EV50
VI > 4.5V for TLE72732GV33, TLE7273-2GV26 5.2.45 Watchdog Activating Current Threshold IQ,WD_on - - 5 mA
IQ increasing VI > 5.5V for
TLE7273-2GV50, TLE7273-2EV50
VI > 4.5V for TLE72732GV33, TLE7273-2GV26 Reset Output RO 5.2.46 Output Undervoltage Reset Switching Threshold
VRT
4.50
4.60
4.70
V
TLE7273-2GV50, TLE7273-2EV50 VQ decreasing TLE7273-2GV333) VI > 4.5V; VQ decreasing TLE7273-2GV263) VI > 4.5V; VQ decreasing TLE7273-2GV263) TLE7273-2GV333) VQ > VRT; VI decreasing TLE7273-2GV26 TLE7273-2GV33 TLE7273-2GV50, TLE7273-2EV50 TLE7273-2GV50, TLE7273-2EV50 VQ = 4.5 V; VRO=0.25 V TLE7273-2GV33 VQ = 3.0 V; VRO = 0.25 V TLE7273-2GV26 VQ = 2.35V; VRO = 0.25V
5.2.47
3.00
3.07
3.13
V
5.2.48
2.35
2.38
2.45
V
5.2.49 5.2.50 5.2.51 5.2.52 5.2.53 5.2.54 5.2.55
Input Undervoltage Reset Switching VRTI Threshold
-
3.9
4.0
V
Output Undervoltage Reset Hysteresis Output Undervoltage Reset Hysteresis Maximum Reset Sink Current
VRH VRH
- - -
45 60 90 -
- - - -
mV mV mV mA
IRO,max
1.75
5.2.56
1.3
-
-
mA
5.2.57
1.0
-
-
mA
Data Sheet
13
Rev. 1.2, 2009-04-28
TLE7273-2
Block Description and Electrical Characteristics Electrical Characteristics VI =13.5 V; - 40 C < Tj < 150 C; unless otherwise specified Pos. 5.2.58 5.2.59 5.2.60 5.2.61 Parameter Reset Output Low Level Voltage Reset Output High Level Voltage Reset High Level Leakage Current Integrated Reset Pull Up Resistor Symbol Limit Values Min.
Typ. Max.
Unit Test Condition 0.25 - 1 40 V V A k
VROL VROH IROLK RRO
- 4.5 - 10
0.15 - - 20
VQ 1 V; IRO < 200 A
TLE7273-2GV50, TLE7273-2EV50 TLE7273-2GV33 TLE7273-2GV26 TLE7273-2GV50, TLE7273-2EV50 internally connected to VQ Fast Reset Timing Slow Reset Timing
5.2.62 5.2.63 5.2.64
Power-On Reset Delay Time Reset Reaction Time
tRD tRR
12.8 25.6 -
16.0 32.0 4
19.2 38.4 12
ms ms s
1) measured when the output voltage has dropped 100 mV from the nominal value obtained at VI = 13.5 V 2) recommendation for typical trigger time; tWD = tCW + 1/2*tOW 3) reset output triggered when output voltage VQ is lower than output voltage reset switching threshold VRT or is also triggered, when input voltage is decreasing to VI < 4.0 V and VQ > VRT
Data Sheet
14
Rev. 1.2, 2009-04-28
TLE7273-2
Typical Performance Characteristics Current Consumption Iq versus Junction Temperature Tj (EN=ON)
1_Iq-Tj.vsd
Current Consumption Iq versus Output Current IQ (EN=ON)
2 _ IQ -IQ .V S D
Iq [A] VI = 13.5V
100
45
T j = 2 5 C
40 35
T j = -4 0 C
IQ = 100 A
30
10
I q [A]
25 20 15
1
10 5 0
0.01 -40 -20
0
20 40 60 80 100 120 140
0 ,1
1
10
100
1000
Tj [C]
I Q [m A ]
Current Consumption Iq versus Input Voltage VI at Tj=-40C (EN=ON)
Current Consumption Iq versus Input Voltage VI at Tj=25C (EN=ON)
200
3A_IQ-VI_25.VSD
200
3A_IQ-VI_-40.VSD
Iq [A]
150
Tj = 25 C
Iq [A]
150
Tj = -40C
100
100
IQ = 100mA I Q = 10mA
50
IQ = 100mA I Q = 10mA
50
IQ = 0.2mA
IQ = 0.2mA
0
10
20
30
40
0
10
20
30
40
VI [V]
VI [V]
Data Sheet
15
Rev. 1.2, 2009-04-28
TLE7273-2
Typical Performance Characteristics (contd) Load Regulation dVQ versus Output Current Change dIQ
0
18b_dVQ-dIQ_Vi135V.vsd
Load Regulation dVQ versus Output Current Change dIQ
0
18a_dVQ-dIQ_Vi6V.vsd
VQ
[mV]
VI = 13.5V
VQ
[mV]
VI = 6V
-2
Tj = 25 C Tj = -40 C Tj = 150 C
-2
Tj = 150 C Tj = -40 C Tj = 25 C
-3
-3
-4
-4
-5
-5
-6
0
100
200
-6
0
100
200
IQ [mA]
IQ [mA]
Power Supply Ripple Rejection PSRR
80
13_PSRR.VSD
Load Regulation dVQ versus Output Current Change dIQ
0
18c_dVQ-dIQ_Vi28V.vsd
PSRR
[dB]
IQ = 0.1 mA IQ = 10 mA IQ = 100 mA
VQ
[mV]
Tj = 25 C
VI = 28
60
-2
Tj = -40 C Tj = 150 C
50
-3
40
-4
30
VRIPPLE = 1 V VIN = 13.5 V CQ = 470nF Ceramics Tj = 25 C
100 1k 10k 100k
-5
10
-6
0
100
200
f [Hz]
IQ [mA]
Data Sheet
16
Rev. 1.2, 2009-04-28
TLE7273-2
Typical Performance Characteristics (contd) Line Regulation dVQ versus Input Voltage Change dVI
6
19_dVQ-dVI_-40C.vsd
Line Regulation dVQ versus Input Voltage Change dVI
Tj = -40 C
6
19_dVQ-dVI_25C_.vsd
VQ
[mV]
VQ
[mV]
Tj = 25 C IQ = 1mA IQ = 10mA
2
2
IQ = 100mA
0
IQ = 100mA
0
IQ = 10mA IQ = 1mA
-2
-2
-4
-4
-6
0
5
10 15 20 25 30 35 40 45
-6
0
5
10 15 20 25 30 35 40 45
VI [V]
VI [V]
Line Regulation dVQ versus Input Voltage Change dVI
6
19_dVQ-dVI__150C.vsd
Enable Input Current IEN versus Enable Input Voltage VEN
24_IINH vs VINH.vsd
VQ
[mV]
IQ = 10mA
Tj = 150 C
[A] 50
IEN
Tj = 150C Tj = 25C Tj = -40C
2
IQ = 1mA
40
0
30
-2
20
-4
10
-6
0
5
10 15 20 25 30 35 40 45
10
20
30
40
VI [V]
VEN [V]
Data Sheet
17
Rev. 1.2, 2009-04-28
TLE7273-2
Typical Performance Characteristics (contd) Enable Input Current IEN versus Input Voltage VI, EN=Off
25_IINH vs VIN INH_off.vsd
Enable High Level / Low Level Input Voltage VEN,H / VEN,L versus Junction Temperature Tj
25a_VINH_Tj_ INH_on.vsd
[A] 1.0
IEN
VEN EN = OFF
[V] 2.5
VI = 13.5V
0.8
2.0
VEN increasing
0.6
1.5
Tj = 150C
0.4 1.0
VEN decreasing
0.2
Tj = 25C Tj = -40C
10 20 30 40
0.5
-40 -20
0
20 40 60 80 100 120 140
VIN [V]
Tj [C]
Reset Threshold VRT versus Junction Temperature Tj (5V-Version)
26_VRT_VS_TEMP_5V.VSD
Reset Hysteresis versus Junction Temperature Tj (5V-Version)
120 [mV]
29_VRT_HYSTERESIS-_VS_TEMP_5V.VSD
VQ [V]
VI = 13.5 V
V
VI = 13.5 V
4.90
80
4.80 Reset Release Threshold 4.70
60
40
4.60 Reset Trigger Threshold -40 -20 0 20 40 60 80 100 120 140
20
-40 -20
0
20 40 60 80 100 120 140
Tj [C]
Tj [C]
Data Sheet
18
Rev. 1.2, 2009-04-28
TLE7273-2
Typical Performance Characteristics (contd) Reset Threshold VRT versus Junction Temperature Tj (3.3V-Version)
26_VRT_VS_TEMP_33V.VSD
Reset Hysteresis versus Junction Temperature Tj (3.3V-Version)
120 [mV]
29_VRT_HYSTERESIS-_VS_TEMP_33V.VSD
VQ [V]
VI = 13.5 V
V
VI = 13.5 V
3.20 Reset Release Threshold 3.10
80
60
3.00
Reset Trigger Threshold
40
2.90
20
-40 -20
0
20 40 60 80 100 120 140
-40 -20
0
20 40 60 80 100 120 140
Tj [C]
Tj [C]
Reset Threshold VRT versus Junction Temperature Tj (2.6V-Version)
26_VRT_VS_TEMP_26V.VSD
Reset Hysteresis versus Junction Temperature Tj (2.6V-Version)
120 [mV]
29_VRT_HYSTERESIS-_VS_TEMP_26V.VS D
VQ [V]
VI = 13.5 V
V
VI = 13.5 V
2.50
Reset Release Threshold
80
2.40 Reset Trigger Threshold
60
2.30
40
2.20
20
-40 -20
0
20 40 60 80 100 120 140
-40 -20
0
20 40 60 80 100 120 140
Tj [C]
Tj [C]
Data Sheet
19
Rev. 1.2, 2009-04-28
TLE7273-2
Typical Performance Characteristics (contd) Reset Reaction Time trr versus Junction Temperature Tj
12 [s]
28_RESETREACTION_VS_TEMP.VSD
Reset Delay tRD Time versus Junction Temperature Tj
VI = 13.5 V
60 [ms]
27_RESETDELAY VS TEMP.VSD
tRR
tRD
VI = 13.5 V
8
40 SLOW Timing
6
30
4
20
FAST Timing
2
10
-40 -20
0
20 40 60 80 100 120 140
-40 -20
0
20 40 60 80 100 120 140
Tj [C]
Tj [C]
Reset Output Sink Current IRO versus Junction Temperature Tj
4,40 [mA]
30_IRO_VS_TEMP.VSD
Watchdog Timing tWD versus Junction Temperature Tj
80 [ms]
44_TWD_VS_TEMP.VSD
IRO
VI = 13.5 V
tWD
Timing for Ignore-, Open- Closed- Window
VI = 13.5 V
3,60
60
SLOW Timing
3,20
50
2,80
40
2,40
30
FAST Timing
-40 -20
0
20 40 60 80 100 120 140
-40 -20
0
20 40 60 80 100 120 140
Tj [C]
Tj [C]
Data Sheet
20
Rev. 1.2, 2009-04-28
TLE7273-2
Typical Performance Characteristics (contd) Region of Stability ESR(CQ) versus Output Current IQ
100
12_ESR-IQ.VSD
ESRCQ
[]
CQ = 470nF Tj = -40...150 C
10
1 Stable Region 0.1
0.01
0
100
200
IQ [mA]
Data Sheet
21
Rev. 1.2, 2009-04-28
TLE7273-2
Package Outlines
6
Package Outlines
0.35 x 45
1.75 MAX.
0.175 0.07 (1.47)
C
4 -0.2
1.27 0.41+0.10 2) -0.06 14
B
0.1
0.2 M A B 14x
8 60.2
0.64 0.25
0.2 M C
1 7 1) 8.75 -0.2
A
Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area GPS01230
gps01230.eps
Figure 8
PG-DSO-14
Data Sheet
22
Rev. 1.2, 2009-04-28
8MAX.
1)
0.19 +0.06
TLE7273-2
Package Outlines
0.35 x 45
Stand Off (1.45)
1.7 MAX.
3.9 0.11)
0.1 C D
0 ... 0.1
0.19 +0.06
0.08 C 6 0.2
0.65 0.25 0.05 2)
C
0.64 0.25
D 0.2
8 MAX.
M
0.15 M C A-B D 14x
D 8x
A
14 8
Bottom View 3 0.2
1 7
1
7
B 0.1 C A-B 2x
Exposed Diepad
14
8
4.9 0.11)
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion
PG-SSOP-14-1,-2,-3-PO V02
Figure 9
PG-SSOP-14 Exposed Pad
Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. Data Sheet 23
Rev. 1.2, 2009-04-28
2.65 0.2
Dimensions in mm
TLE7273-2
Revision History
7
Revision 1.2
Revision History
Date 2009-04-28 Changes 2.6V version, 5V version in PG-SSOP-14 package and all related description added: In "Features" on Page 2 "or 2.6 V" added In "Features" on Page 2 package drawing for PG-DSO-14 updated, package drawing for PG-SSOP-14 added In "Overview" on Page 2 in table at the bottom type "TLE7273-2GV26" and "TLE7273-2EV50" added In "Pin Definitions and Functions (PG-DSO-14)" on Page 4 in description for Pin 1 ", TLE7273-2GV26" added "Pin Assignments (PG-SSOP-14 Exposed Pad)" on Page 5 and "Pin Definitions and Functions (PG-SSOP-14 Exposed Pad)" on Page 5 added; In "Functional Range" on Page 7 Item 4.2.3 added, in Item 4.2.1 ", TLE72732EV50" added; In "Thermal Resistances" on Page 7 values for PG-SSOP-14 package added: Item 4.3.6, Item 4.3.7, Item 4.3.8, Item 4.3.9 and Item 4.3.10 added In "Power On Reset and Reset Output" on Page 8 "TLE7273-2EV50" in description added In "Electrical Characteristics" on Page 11 all specific Items for 2.6V version added: Item 5.2.5, Item 5.2.6, Item 5.2.22, Item 5.2.26, Item 5.2.30, Item 5.2.48, Item 5.2.52 and Item 5.2.57 added; In Item 5.2.44, Item 5.2.45, Item 5.2.49, Item 5.2.50, Item 5.2.51 and Item 5.2.60 Conditions for 2.6V version added; In Item 5.2.1, Item 5.2.2, Item 5.2.9, Item 5.2.20, Item 5.2.24, Item 5.2.28, Item 5.2.44, Item 5.2.45, Item 5.2.46, Item 5.2.54, Item 5.2.55, Item 5.2.59 and Item 5.2.61 ", TLE7273-2EV50" added In "Typical Performance Characteristics" on Page 15 Graphs "Reset Threshold VRT versus Junction Temperature Tj (3.3V-Version)" on Page 19, "Reset Threshold VRT versus Junction Temperature Tj (3.3V-Version)" on Page 19, "Reset Threshold VRT versus Junction Temperature Tj (2.6VVersion)" on Page 19 and "Reset Hysteresis versus Junction Temperature Tj (3.3V-Version)" on Page 19 added In "Package Outlines" on Page 22 Oulines for PG-SSOP-14 added: Figure 9
Data Sheet
24
Rev. 1.2, 2009-04-28
TLE7273-2
Revision History Revision 1.1 Date 2008-07-25 Changes 3.3V version and all related description added: In "Features" on Page 2 "3.3V" added In "Overview" on Page 2 in table at the bottom type "TLE7273-2GV33" added In "Pin Definitions and Functions (PG-DSO-14)" on Page 4 in description for Pin 1 "TLE7273-2GV33: open drain output;" added In "Functional Range" on Page 7 Item 4.2.2 added In "Power On Reset and Reset Output" on Page 8 description for dimensioning external pull-up resistor at RO added; In "Electrical Characteristics" on Page 11 all specific Items for 3.3V version added: Item 5.2.3, Item 5.2.4, Item 5.2.21, Item 5.2.25, Item 5.2.29, Item 5.2.47, Item 5.2.49, Item 5.2.50, Item 5.2.51, Item 5.2.53, Item 5.2.56 and Item 5.2.60 added; In Item 5.2.44 and Item 5.2.45 Conditions for 3.3V version added; 1.0 2008-04-10 final version data sheet
Data Sheet
25
Rev. 1.2, 2009-04-28
Edition 2009-04-28 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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