View EP910I_4968207.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Classic
(R)
EPLD Family
Data Sheet
May 1999, ver. 5
Features
s s s s
s s s s
s
s
Complete device family with logic densities of 300 to 900 usable gates (see Table 1) Device erasure and reprogramming with non-volatile EPROM configuration elements Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz 24 to 68 pins available in dual in-line package (DIP), plastic J-lead chip carrier (PLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages Programmable security bit for protection of proprietary designs 100% generically tested to provide 100% programming yield Programmable registers providing D, T, JK, and SR flipflops with individual clear and clock controls Software design support featuring the Altera(R) MAX+PLUS(R) II development system on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000 workstations, and third-party development systems Programming support with Altera's Master Programming Unit (MPU); programming hardware from Data I/O, BP Microsystems, and other third-party programming vendors Additional design entry and simulation support provided by EDIF, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
Table 1. Classic Device Features
Feature
Usable gates Macrocells Maximum user I/O pins t PD (ns) f CNT (MHz)
EP610 EP610I
300 16 22 10 100
EP910 EP910I
450 24 38 12 76.9
EP1810
900 48 64 20 50
Altera Corporation
A-DS-CLASSIC-05
745
Classic EPLD Family Data Sheet
General Description
The Altera ClassicTM device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology, Classic devices also have a Turbo-only version, which is described in this data sheet. Classic devices support 100% TTL emulation and can easily integrate multiple PAL- and GAL-type devices with densities ranging from 300 to 900 usable gates. The Classic family provides pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz. Classic devices are available in a wide range of packages, including ceramic dual in-line package (CerDIP), plastic dual in-line package (PDIP), plastic J-lead chip carrier (PLCC), ceramic J-lead chip carrier (JLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages. EPROM-based Classic devices can reduce active power consumption without sacrificing performance. This reduced power consumption makes the Classic family well suited for a wide range of low-power applications. Classic devices are 100% generically tested devices in windowed packages and can be erased with ultra-violet (UV) light, allowing design changes to be implemented quickly. Classic devices use sum-of-products logic and a programmable register. The sum-of-products logic provides a programmable-AND/fixed-OR structure that can implement logic with up to eight product terms. The programmable register can be individually programmed for D, T, SR, or JK flipflop operation or can be bypassed for combinatorial operation. In addition, macrocell registers can be individually clocked either by a global clock or by any input or feedback path to the AND array. Altera's proprietary programmable I/O architecture allows the designer to program output and feedback paths for combinatorial or registered operation in both active-high and active-low modes. These features make it possible to implement a variety of logic functions simultaneously. Classic devices are supported by Altera's MAX+PLUS II development system, a single, integrated package that offers schematic, text--including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)--and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and workstationbased EDA tools. The MAX+PLUS II software runs on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. These devices also contain on-board logic test circuitry to allow verification of function and AC specifications during standard production flow.
746
Altera Corporation
Classic EPLD Family Data Sheet
f Functional Description
For more information, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet. The Classic architecture includes the following elements:
s s s s
Macrocells Programmable registers Output enable/clock select Feedback select
Macrocells
Classic macrocells, shown in Figure 1, can be individually configured for both sequential and combinatorial logic operation. Eight product terms form a programmable-AND array that feeds an OR gate for combinatorial logic implementation. An additional product term is used for asynchronous clear control of the internal register; another product term implements either an output enable or a logic-array-generated clock. Inputs to the programmable-AND array come from both the true and complement signals of the dedicated inputs, feedbacks from I/O pins that are configured as inputs, and feedbacks from macrocell outputs. Signals from dedicated inputs are globally routed and can feed the inputs of all device macrocells. The feedback multiplexer controls the routing of feedback signals from macrocells and from I/O pins. For additional information on feedback select configurations, see Figure 3 on page 749.
Figure 1. Classic Device Macrocell
Logic Array Global Clock
VCC
Output Enable/Clock Select
OE CLK
Q
CLR
Programmable Register
Input, I/O, and Macrocell Feedbacks To Logic Array Feedback Select
Asynchronous Clear
Altera Corporation
747
Classic EPLD Family Data Sheet
The eight product terms of the programmable-AND array feed the 8-input OR gate, which then feeds one input to an XOR gate. The other input to the XOR gate is connected to a programmable bit that allows the array output to be inverted. Altera's MAX+PLUS II software uses the XOR gate to implement either active-high or active-low logic, or De Morgan's inversion to reduce the number of product terms needed to implement a function.
Programmable Registers
To implement registered functions, each macrocell register can be individually programmed for D, T, JK, or SR operation. If necessary, the register can be bypassed for combinatorial operation. During design compilation, the MAX+PLUS II software selects the most efficient register operation for each registered function to minimize the logic resources needed by the design. Registers have an individual asynchronous clear function that is controlled by a dedicated product term. These registers are cleared automatically during power-up. In addition, macrocell registers can be individually clocked by either a global clock or any input or feedback path to the AND array. Altera's proprietary programmable I/O architecture allows the designer to program output and feedback paths for combinatorial or registered operation in both active-high and active-low modes. These features make it possible to simultaneously implement a variety of logic functions.
Output Enable/Clock Select
Figure 2 shows the two operating modes (Modes 0 and 1) provided by the output enable/clock (OE/CLK) select. The OE/CLK select, which is controlled by a single programmable bit, can be individually configured for each macrocell. In Mode 0, the tri-state output buffer is controlled by a single product term. If the output enable is high, the output buffer is enabled. If the output enable is low, the output has a high-impedance value. In Mode 0, the macrocell flipflop is clocked by its global clock input signal. In Mode 1, the output enable buffer is always enabled, and the macrocell register can be triggered by an array clock signal generated by a product term. This mode allows registers to be individually clocked by any signal on the AND array. With both true and complement signals in the AND array, the register can be configured to trigger on a rising or falling edge. This product-term-controlled clock configuration also supports gated clock structures.
748
Altera Corporation
Classic EPLD Family Data Sheet
Figure 2. Classic Output Enable/Clock Select
Mode 0
Global Clock AND Array CLK VCC OE
Output Enable/Clock Select
In Mode 0, the register is clocked by the global clock signal. The output is enabled by the logic from the product term.
Data
Q
OE = Product Term CLK = Global
CLR
Macrocell Output Buffer
Mode 1
Global Clock VCC OE
Output Enable/Clock Select
In Mode 1, the output AND is permanently enabled Array and the register is clocked by the product term, which allows gated clocks to be generated. OE = Enabled
CLK = Product Term
CLK
Data
Q
CLR
Macrocell Output Buffer
Feedback Select
Each macrocell in a Classic device provides feedback selection that is controlled by the feedback multiplexer. This feedback selection allows the designer to feed either the macrocell output or the I/O pin input associated with the macrocell back into the AND array. The macrocell output can be either the Q output of the programmable register or the combinatorial output of the macrocell. Different devices have different feedback multiplexer configurations. See Figure 3.
Figure 3. Classic Feedback Multiplexer Configurations
Global Feedback Multiplexer Global
EP610 EP610I EP910 EP910I Q I/O
Quadrant Feedback Multiplexer Quadrant
EP1810 Q I/O
Dual Feedback Multiplexer Quadrant Global
EP1810 Q I/O
Altera Corporation
749
Classic EPLD Family Data Sheet
EP610, EP610I, EP910, and EP910I devices have a global feedback configuration; either the macrocell output (Q) or the I/O pin input (I/O) can feed back to the AND array so that it is accessible to all other macrocells. EP1810 macrocells can have either of two feedback configurations: quadrant or dual. Most macrocells in EP1810 devices have a quadrant feedback configuration; either the macrocell output or I/O pin input can feed back to other macrocells in the same quadrant. Selected macrocells in EP1810 devices have a dual feedback configuration: the output of the macrocell feeds back to other macrocells in the same quadrant, and the I/O pin input feeds back to all macrocells in the device. If the associated I/O pin is not used, the macrocell output can optionally feed all macrocells in the device. In this case, the output of the macrocell passes through the tri-state buffer and uses the feedback path between the buffer and the I/O pin.
Design Security
Classic devices contain a programmable security bit that controls access to the data programmed into the device. When this bit is programmed, a proprietary design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security because data within configuration elements is invisible. The security bit that controls this function and other program data is reset only when the device is erased. Device timing can be analyzed with the MAX+PLUS II software, with a variety of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure 4. Devices have fixed internal delays that allow the user to determine the worst-case timing for any design. The MAX+PLUS II software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for systemlevel performance evaluation.
Timing Model
Figure 4. Classic Timing Model
Global Clock Delay tICS Input Delay tIN Array Clock Delay tIC Logic Array Delay tLAD tCLR I/O Delay tIO Feedback Delay tFD Register tSU tH Output Delay tOD tXZ tZX
750
Altera Corporation
Classic EPLD Family Data Sheet
Timing information can be derived from the timing model and parameters for a particular device. External timing parameters represent pin-to-pin timing delays, and can be calculated from the sum of internal parameters. Figure 5 shows the internal timing relationship for internal and external delay parameters.
f
For more information on device timing, refer to Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book.
Altera Corporation
751
Classic EPLD Family Data Sheet
Figure 5. Classic Switching Waveforms
t R and t F < 3 ns. Inputs are driven at 3 V for a logic high and 0 V for a logic low. All timing characteristics are measured at 1.5 V.
Input Mode
tIO
I/O Pin tPD1 = tIN + tLAD + tOD tPD2 = tIO + tIN + tLAD + tOD
tIN
Input Pin
tLAD
Logic Array Input
tCLR
Logic Array Output
tOD
Output Pin
Global Clock Mode
tR Global Clock Pin tCH tCL tF
tIN
Global Clock at Register
tICS
tSU
Data from Logic Array
tH
Array Clock Mode
tR Clock Pin tACH tACL tF
tIN
Clock into Logic Array
tIC
Clock from Logic Array
tASU
Data from Logic Array
tAH
tFD
Register Output to Logic Array
Output Mode
Clock from Logic Array
tOD
Data from Logic Array
tXZ
Output Pin
tZX
High-Impedance Tri-State
752
Altera Corporation
Classic EPLD Family Data Sheet
Turbo Bit Option
Many Classic devices contain a programmable Turbo BitTM option to control the automatic power-down feature that enables the low-standbypower mode. When the Turbo Bit option is turned on, the low-standbypower mode is disabled. All AC values are tested with the Turbo Bit option turned on. When the device is operating with the Turbo Bit option turned off (non-Turbo mode), a non-Turbo adder must be added to the appropriate AC parameter to determine worst-case timing. The nonTurbo adder is specified in the "AC Operating Conditions" tables for each Classic device that supports the Turbo mode. Classic devices are fully functionally tested. Complete testing of each programmable EPROM configuration element and all internal logic elements before and after packaging ensures 100% programming yield. See Figure 6 for AC test measurement conditions. These devices also contain on-board logic test circuitry to allow verification of function and AC specifications during standard production flow.
Generic Testing
Figure 6. AC Test Conditions
Power-supply transients can affect AC measurements. Simultaneous transitions of R1 multiple outputs should be avoided for 885 accurate measurement. Threshold tests Device must not be performed under AC conditions. Large-amplitude, fast ground- Output current transients normally occur as the device outputs discharge the load R2 capacitances. When these transients flow 340 through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result.
VCC
To Test System
C1 (includes JIG capacitance)
Device Programming
Classic devices can be programmed on 486- and Pentium-based PCs with the MAX+PLUS II Programmer, an Altera Logic Programmer card, the MPU, and the appropriate device adapter. The MPU performs continuity checking to ensure adequate electrical contact between the adapter and the device. Data I/O, BP Microsystems, and other programming hardware manufacturers also offer programming support for Altera devices. See Programming Hardware Manufacturers for more information.
Altera Corporation
753
Notes:
EP610 EPLD
Features
s
s s s s s
High-performance, 16-macrocell Classic EPLD - Combinatorial speeds with tPD as fast as 10 ns - Counter frequencies of up to 100 MHz - Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins EP610 and EP610I devices are pin-, function-, and programming file-compatible Programmable clock option for independent clocking of all registers Macrocells individually programmable as D, T, JK, or SR flipflops, or for combinatorial operation Available in the following packages (see Figure 7): - 24-pin small-outline integrated circuit (plastic SOIC only) - 24-pin ceramic and plastic dual in-line package (CerDIP and PDIP) - 28-pin plastic J-lead chip carrier (PLCC)
Figure 7. EP610 Package Pin-Out Diagrams
Package outlines not drawn to scale. Windows in ceramic packages only.
INPUT CLK1 INPUT CLK1 INPUT I/O I/O I/O I/O I/O I/O I/O I/O INPUT GND
1 2 3 4 5 6 24 23 22 21 20 19
VCC
VCC
1 2 3 4 5 6
24 23 22 21 20 19
VCC I/O INPUT I/O I/O I/O I/O I/O I/O I/O I/O INPUT CLK2 I/O I/O I/O I/O I/O I/O NC
5 6 7 8 9 10 11 12
INPUT
27
CLK1
7 8 9 10 11 12
18 17 16 15 14 13
VCC INPUT I/O I/O I/O I/O I/O I/O I/O I/O INPUT CLK2
I/O I/O I/O I/O I/O I/O I/O I/O INPUT GND
4
3
2
1
28
26 25 24 23 22
I/O I/O I/O I/O I/O I/O I/O NC
21 20 19 18
EP610
7 8 9 10 11 12
18 17 16 15 14 13
I/O
INPUT
GND
GND
CLK2
24-Pin SOIC EP610
24-Pin DIP EP610 EP610I
28-Pin PLCC EP610 EP610I
Altera Corporation
INPUT
I/O
EP610
EP610
13
14
15
16
17
755
Classic EPLD Family Data Sheet
General Description
EP610 devices have 16 macrocells, 4 dedicated input pins, 16 I/O pins, and 2 global clock pins (see Figure 8). Each macrocell can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of either the output of the macrocell or the I/O input. The CLK1 signal is a dedicated global clock input for the registers in macrocells 9 through 16. The CLK2 signal is a dedicated global clock input for registers in macrocells 1 through 8.
Figure 8. EP610 Block Diagram
Numbers without parentheses are for DIP and SOIC packages. Numbers in parentheses are for J-lead packages.
2 (3) 1 (2) INPUT CLK1 INPUT (27) 23 CLK2 (16) 13
3 4 5 6 7 8 9 10 11 (13)
(4) (5) (6) (7) (8) (9) (10) (12)
Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 Macrocell 13 Macrocell 14 Macrocell 15 Macrocell 16
Global Bus
Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 Macrocell 8
(26) (25) (24) (23) (22) (21) (20) (18)
22 21 20 19 18 17 16 15
INPUT
INPUT (17) 14
Figure 9 shows the typical supply current (ICC) versus frequency of EP610 devices.
Figure 9. ICC vs. Frequency of EP610 Devices
100
Turbo
10
Typical ICC Active (mA)
1.0
VCC = 5.0 V TA = 25 C
Non-Turbo
0.1 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 80 MHz
Frequency
756
Altera Corporation
Classic EPLD Family Data Sheet
Figure 10 shows the typical output drive characteristics of EP610 devices.
Figure 10. Output Drive Characteristics of EP610 Devices
Drive characteristics may exceed shown curves.
EP610-15 & EP610-20 EPLDs
200
EP610-25, EP610-30 & EP610-35 EPLDs
80
150
IOL VCC = 5.0 V TA = 25 C Typical ICC Output Current (mA)
IOL
60
Typical ICC Output Current (mA)
100
40
VCC = 5.0 V TA = 25 C IOH
50
IOH
20
0.45
1
2
3
4
5
0.45 1
2
3
4
5
VO Output Voltage (V)
VO Output Voltage (V)
EP610I EPLDs
100
80
IOL Typical ICC Output Current (mA)
60
VCC = 5.0 V TA = 25 C
40
20
IOH
1
2
3
4
5
VO Output Voltage (V)
Altera Corporation
757
Classic EPLD Family Data Sheet
Operating Conditions
Tables 2 through 7 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for EP610 and EP610I devices.
Table 2. EP610 & EP610I Device Absolute Maximum Ratings
Symbol Parameter Conditions
Notes (1), (2)
EP610 Min Max
7.0 7.0 175 25 150 135 150 135 -65 -65 150 135 150 135
EP610I Min
-2.0 -0.5
Unit
Max
7.0 VCC + 0.5 V V mA mA C C C C
VCC VI IMAX IOUT TSTG TAMB TJ
Supply voltage DC input voltage DC VCC or ground current DC output current, per pin Storage temperature Ambient temperature Junction temperature
With respect to ground (3)
-2.0 -2.0 -175 -25
No bias Under bias Ceramic packages, under bias Plastic packages, under bias
-65 -65
Table 3. EP610 & EP610I Device Recommended Operating Conditions
Symbol Parameter Conditions EP610 Min
VCC VI VO TA tR tF Supply voltage Input voltage Output voltage Operating temperature Input rise time Input fall time For commercial use For industrial use
Note (2)
EP610I Min
4.75 -0.3 0 0 -40
Unit
Max
VCC + 0.3 VCC 70 85 100 (50) 100 (50)
Max
5.25 V CC + 0.3 V CC 70 85 500 500 V V V C C ns ns
(4)
4.75 (4.5) 5.25 (5.5) -0.3 0 0 -40
(5) (5)
Table 4. EP610 & EP610I Device DC Operating Conditions
Symbol
VIH VIL VOH VOL II IOZ
Note (6)
Min
2.0 -0.3
Parameter
High-level input voltage Low-level input voltage High-level TTL output voltage High-level CMOS output voltage Low-level output voltage
Conditions
Max
VCC + 0.3 0.8
Unit
V V V V
IOH = -4 mA DC (7) IOH = -0.6 mA DC (7), (8) IOL = 4 mA DC (7)
2.4 3.84 0.45 -10 -10 10 10
V A A
I/O pin leakage current of dedicated input VI = VCC or ground pins Tri-state output leakage current VO = VCC or ground
758
Altera Corporation
Classic EPLD Family Data Sheet
Table 5. EP610 & EP610I Device Capacitance
Symbol Parameter
Note (9)
EP610-15 EP610-20 Min Max
10 12 20 20
Conditions
EP610-25 EP610-30 EP610-35 Min Max
20 20 20 50
EP610I
Unit
Min
Max
8 8 10 12 pF pF pF pF
CIN CI/O CCLK1 CCLK2
Input pin capacitance I/O pin capacitance CLK1 pin capacitance CLK2 pin capacitance
VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz
Table 6. EP610 Device ICC Supply Current
Symbol Parameter
Notes (2), (10)
Conditions Speed Grade EP610 Min Typ
20 5 60 45
Unit Max
150 10 (15) 90 (115) 60 (75) A mA mA mA
ICC1 ICC2 ICC3
VCC supply current (non-Turbo, standby) VCC supply current (non-Turbo, active) VCC supply current (Turbo, active)
VI = VCC or ground, no load (11), (12) VI = VCC or ground, no load, f = 1.0 MHz (11), (12) VI = VCC or ground, no load, -15, -20 f = 1.0 MHz (12) -25, -30, -35
Table 7. EP610I Device ICC Supply Current
Symbol Parameter
Note (10)
Conditions Min EP610I Typ
20 3 65
Unit Max
150 8 105 A mA mA
ICC1 ICC2 ICC3
VCC supply current (non-Turbo, standby) VCC supply current (non-Turbo, active) VCC supply current (Turbo, active)
VI = VCC or ground, no load, (11), (12) VI = VCC or ground, no load, f = 1.0 MHz (11), (12) VI = VCC or ground, no load, f = 1.0 MHz (12)
Altera Corporation
759
Classic EPLD Family Data Sheet Notes to tables:
(1) (2) (3) See the Operating Requirements for Altera Devices Data Sheet in this data book. Numbers in parentheses are for industrial-temperature-range devices. The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2.0 V (EP610) or -0.5 V (EP610I) or overshoot to 7.0 V (EP610) or VCC + 0.5 V (EP610I) for input currents less than 100 mA and periods less than 20 ns. (4) For EP610 devices, maximum VCC rise time is 50 ms. For EP610I devices, maximum VCC rise time is unlimited with monotonic rise. (5) For EP610-15 and EP610-20 devices: tR and tF = 40 ns. For EP610-15 and EP610-20 clocks: tR and tF = 20 ns. (6) These values are specified in Table 3 on page 758. (7) The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL output current. (8) This parameter does not apply to EP610I devices. (9) The device capacitance is measured at 25 C and is sample-tested only. (10) Typical values are for TA = 25 C and VCC = 5 V. (11) When the Turbo Bit option is not set (non-Turbo mode), EP610 devices enter standby mode if no logic transitions occur for 100 ns after the last transition. When the Turbo Bit option is not set, EP610I devices enter standby mode if no logic transitions occur for 75 ns after the last transition. (12) Measured with a device programmed as a 16-bit counter.
760
Altera Corporation
Classic EPLD Family Data Sheet
Tables 8 and 9 show the timing parameters for EP610-15 and EP610-20 devices.
Table 8. EP610-15 & EP610-20 External Timing Parameters
Symbol Parameter Conditions
Notes (1), (2)
EP610-15 EP610-20 Non-Turbo Adder
(3)
20.0 20.0 20.0 20.0 20.0 0.0 20.0 0.0 0.0 0.0 13.0 16.0 62.5 8.0 8.0 9.0 9.0 1.0 15.0 14.0 20.0 18.0 55.6 0.0 0.0 0.0 20.0 0.0 0.0 0.0 1.0 20.0 0.0 0.0 ns ns ns ns ns MHz ns ns ns ns ns ns MHz ns ns ns ns ns ns ns MHz
Unit
Min Max Min Max
tPD1 tPD2 tPZX tPXZ tCLR fMAX tSU tH tCH tCL tCO1 tCNT fCNT tASU tAH tACH tACL tODH tACO1 tACNT fACNT Input to non-registered output I/O input to non-registered output Input to output enable Input to output disable Asynchronous output clear time Maximum clock frequency Global clock input setup time Global clock input hold time Global clock high time Global clock low time Global clock to output delay Global clock minimum period Maximum internal global clock frequency Array clock input setup time Array clock input hold time Array clock high time Array clock low time Output data hold time after clock Array clock to output delay Array clock minimum period Array clock internal maximum frequency C1 = 35 pF (7) C1 = 35 pF C1 = 35 pF C1 = 35 pF C1 = 5 pF (4) C1 = 35 pF 15.0 17.0 15.0 15.0 15.0 83.3 9.0 0.0 6.0 6.0 11.0 12.0 62.5 11.0 0.0 8.0 8.0 20.0 22.0 20.0 20.0 20.0
(5)
(6)
83.3 6.0 6.0 7.0 7.0 1.0
(6)
71.4
Table 9. EP610-15 & EP610-20 Internal Timing Parameters (Part 1 of 2)
Symbol Parameter Conditions EP610-15 EP610-20 Min Max Min Max
tIN tIO tLAD tOD tZX tXZ
Input pad and buffer delay I/O input pad and buffer delay Logic array delay Output buffer and pad delay Output buffer enable delay Output buffer disable delay C1 = 35 pF C1 = 35 pF C1 = 5 pF 4.0 2.0 6.0 5.0 5.0 5.0 4.0 2.0 11.0 5.0 5.0 5.0 ns ns ns ns ns ns
Unit
Altera Corporation
761
Classic EPLD Family Data Sheet
Table 9. EP610-15 & EP610-20 Internal Timing Parameters (Part 2 of 2)
Symbol Parameter Conditions EP610-15 EP610-20 Min Max Min Max
tSU tH tIC tICS tFD tCLR
Register setup time Register hold time Array clock delay Global clock delay Feedback delay Register clear time 5.0 4.0 6.0 2.0 1.0 6.0 4.0 7.0 11.0 4.0 1.0 11.0 ns ns ns ns ns ns
Unit
Tables 10 and 11 show the timing parameters for EP610-25, EP610-30 and EP610-35 devices.
Table 10. EP610-25, EP610-30 & EP610-35 External Timing Parameters
Symbol Parameter Conditions EP610-25 EP610-30
Notes (1), (2)
EP610-35 Non-Turbo Unit Adder
(3)
30.0 30.0 30.0 30.0 30.0 0.0 30.0 0.0 0.0 0.0 20.0 35.0 28.6 8.0 12.0 12.0 12.0 1.0 0.0 0.0 0.0 30.0 0.0 0.0 0.0 37.0 35.0 28.6 30.0 0.0 0.0 ns ns ns ns ns MHz ns ns ns ns ns ns MHz ns ns ns ns ns ns ns MHz
Min Max Min Max Min Max
tPD1 tPD2 tPZX tPXZ tCLR fMAX tSU tH tCH tCL tCO1 tCNT fCNT tASU tAH tACH tACL tODH tACO1 tACNT fACNT Input to non-registered output I/O input to non-registered output Input to output enable Input to output disable Asynchronous output clear time Maximum frequency Global clock input setup time Global clock input hold time Global clock high time Global clock low time Global clock to output delay Global clock minimum period Maximum internal global clock frequency Array clock input setup time Array clock input hold time Array clock high time Array clock low time Output data hold time after clock Array clock to output delay Array clock minimum period Maximum internal global clock frequency C1 = 35 pF (7) C1 = 5 pF (4) C1 = 35 pF C1 = 35 pF 25.0 27.0 25.0 25.0 27.0 47.6 21.0 0.0 10.0 10.0 15.0 25.0 41.7 24.0 0.0 11.0 11.0 17.0 30.0 33.3 8.0 12.0 11.0 11.0 1.0 27.0 25.0 32.0 30.0 33.3 30.0 32.0 30.0 30.0 32.0 37.0 27.0 0.0 12.0 12.0 35.0 37.0 35.0 35.0 37.0
(5)
(6)
40.0 8.0 12.0 10.0 10.0 1.0
(6)
40.0
762
Altera Corporation
Classic EPLD Family Data Sheet
Table 11. EP610-25, EP610-30 & EP610-35 Internal Timing Parameters
Symbol Parameter Condition EP610-25 Min
tIN tIO tLAD tOD tZX tXZ tSU tH tIC tICS tFD tCLR
Input pad and buffer delay I/O input pad and buffer delay Logic array delay Output buffer and pad delay Output buffer enable delay Output buffer disable delay Register setup time Register hold time Array clock delay Global clock delay Feedback delay Register clear time C1 = 35 pF C1 = 35 pF C1 = 5 pF 11.0 10.0 13.0 1.0 3.0 13.0
EP610-30 Min Max
9.0 2.0 14.0 7.0 7.0 7.0 11.0 10.0 16.0 1.0 5.0 16.0
EP610-35 Min Max
11.0 2.0 15.0 9.0 9.0 9.0 12.0 10.0 17.0 0.0 8.0 17.0
Unit
Max
8.0 2.0 11.0 6.0 6.0 6.0
ns ns ns ns ns ns ns ns ns ns ns ns
Notes to tables:
(1) (2) (3) (4) (5) (6) (7) These values are specified in Table 3 on page 758. See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for information on internal timing parameters. The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. Sample-tested only for an output change of 500 mV. The fMAX values represent the highest frequency for pipelined data. Measured with a device programmed as a 16-bit counter. Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter applies for both global and array clocking.
Altera Corporation
763
Classic EPLD Family Data Sheet
Tables 12 and 13 show the timing parameters for EP610I devices.
Table 12. EP610I External Timing Parameters
Symbol Parameter
Notes (1), (2)
Non-Turbo Unit Adder
Conditions EP610I-10 EP610I-12 EP610I-15 Min Max Min Max Min Max
(3)
25.0 25.0 25.0 25.0 25.0 0.0 25 0.0 0.0 0.0 ns ns ns ns ns MHz ns ns ns ns ns ns MHz ns ns ns ns ns
tPD1 tPD2 tPZX tPXZ tCLR fMAX tSU tH tCH tCL tCO1 tCNT fCNT tASU tAH tACH tACL tODH tACO1 tACNT fACNT
Input to non-registered output I/O input to non-registered output Input to output enable Input to output disable Asynchronous output clear time Maximum frequency Global clock input setup time Global clock input hold time Global clock high time Global clock low time Global clock to output delay Global clock minimum period Maximum internal global clock frequency Array clock input setup time Array clock input hold time Array clock high time Array clock low time Output data hold time after clock Array clock to output delay Array clock minimum period Maximum internal array clock frequency
C1 = 35 pF
10.0 10.0 15.0
12.0 12.0 15.0 15.0 15.0 100. 0 9.0 0.0 5.0 5.0 83.3 12.0 0.0 5.0 5.0 8.0 12.0 83.3 3.0 6.0 5.0 5.0 1.0 66.0 4.0 6.0 6.0 6.0 1.0 14.0 12.0 83.3 66.0
15.0 15.0 18.0 18.0 18.0
C1 = 5 pF (4) C1 = 35 pF
13.0 13.0 125.0 7.0 0.0 5.0 5.0 6.5 10.0
(5)
8.0 15.0
0.0 25.0 0.0 25.0 0.0 0.0 0.0
(6)
100.0 1.5 5.5 5.0 5.0
C1 = 35 pF (7)
1.0 12.0 10.0
16.0 15.0
25.0 25.0 0.0
ns ns MHz
(6)
100.0
764
Altera Corporation
Classic EPLD Family Data Sheet
Table 13. EP610 Internal Timing Parameters
Symbol Parameter Conditions EP610I-10 Min
tIN tIO tLAD tOD tZX tXZ tSU tH tIC tICS tFD tCLR
Input pad and buffer delay I/O input pad and buffer delay Logic array delay Output buffer and pad delay Output buffer enable delay Output buffer disable delay Register setup time Register hold time Array clock delay Global clock delay Feedback delay Register clear time C1 = 35 pF C1 = 35 pF C1 = 5 pF 3.5 3.5 7.5 2.0 1.0 8.5
EP610I-12 Min Max
4.0 0.0 6.0 2.0 5.0 5.0 5.0 4.0 8.0 2.0 1.0 9.0
EP610I-15 Min Max
4.0 0.0 9.0 2.0 6.0 6.0 5.0 7.0 10.0 2.0 1.0 12.0
Unit
Max
1.5 0.0 5.5 3.0 8.0 6.0
ns ns ns ns ns ns ns ns ns ns ns ns
Notes to tables:
(1) (2) (3) (4) (5) (6) (7) These values are specified in Table 3 on page 758. See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for more information on Classic timing parameters. The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. Sample-tested only for an output change of 500 mV. The fMAX values represent the highest frequency for pipelined data. Measured with a device programmed as a 16-bit counter. Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter applies for both global and array clocking.
Altera Corporation
765
Notes:
EP910 EPLD
Features
s
s s s s s
High-performance, 24-macrocell Classic EPLD - Combinatorial speeds with tPD as fast as 12 ns - Counter frequencies of up to 76.9 MHz - Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs EP910 and EP910I devices are pin-, function-, and programming filecompatible Programmable clock option for independent clocking of all registers Macrocells individually programmable as D, T, JK, or SR flipflops, or for combinatorial operation Available in the following packages (see Figure 11) - 44-pin plastic J-lead chip carrier (PLCC) - 40-pin ceramic and plastic dual in-line packages (CerDIP and PDIP)
Figure 11. EP910 Package Pin-Out Diagrams
Package outlines are not drawn to scale. Windows in ceramic packages only.
CLK1 INPUT INPUT INPUT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O INPUT INPUT INPUT GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
6
5
4
3
2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
VCC INPUT INPUT INPUT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O INPUT INPUT INPUT CLK2
I/O INPUT INPUT INPUT GND GND CLK2 INPUT INPUT INPUT I/O
I/O INPUT INPUT INPUT CLK1 VCC VCC INPUT INPUT INPUT I/O
44-Pin PLCC
EP910 EP910I
40-Pin DIP
EP910 EP910I
Altera Corporation
767
Classic EPLD Family Data Sheet
General Description
Altera EP910 devices can implement up to 450 usable gates of SSI and MSI logic functions. EP910 devices have 24 macrocells, 12 dedicated input pins, 24 I/O pins, and 2 global clock pins (see Figure 12). Each macrocell can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of either the output of the macrocell or the I/O input. The CLK1 and CLK2 signals are the dedicated clock inputs for the registers in macrocells 13 through 24 and 1 through 12, respectively.
Figure 12. EP910 Block Diagram
Numbers without parentheses are for DIP packages. Numbers in parentheses are for J-lead packages.
2 3 4 1 (3) INPUT (4) INPUT (5) INPUT (2) 5 6 7 8 9 10 11 12 13 14 15 16 CLK1 (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (18) Macrocell 13 Macrocell 14 Macrocell 15 Macrocell 16 Macrocell 17 Macrocell 18 Macrocell 19 Macrocell 20 Macrocell 21 Macrocell 22 Macrocell 23 Macrocell 24 Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 Macrocell 8 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 INPUT INPUT INPUT CLK2 (40) (38) (37) (36) (35) (34) (33) (32) (31) (30) (29) (28) INPUT INPUT INPUT (43) 39 (42) 38 (41) 37 (24) 21 36 35 34 33 32 31 30 29 28 27 26 25 (27) 24 (26) 23 (25) 22
Global Bus
17 (19) INPUT 18 (20) INPUT 19 (21) INPUT
768
Altera Corporation
Classic EPLD Family Data Sheet
Figure 13 shows the typical supply current (ICC) versus frequency of EP910 devices.
Figure 13. I CC vs. Frequency of EP910 Devices
100
Turbo
10
Typical ICC Active (mA)
1.0
VCC = 5.0 V TA = 25 C
Non-Turbo
0.1 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 40 MHz
Frequency
Figure 14 shows the typical output drive characteristics of EP910 devices.
Figure 14. Output Drive Characteristics of EP910 Devices
Drive characteristics may exceed shown curves.
EP910 EPLDs
60
EP910I EPLDs
120
50
100
IOL
40 80
Typical IO Output Current (mA)
30
VCC = 5.0 V TA = 25 C IOH
Typical IO Output Current (mA)
IOL
60
20
40
VCC = 5.0 V TA = 25 C IOH
10
20
0 0.45 1 2 3 4 5 0.45 1 2 3 4 5
VO Output Voltage (V)
VO Output Voltage (V)
Altera Corporation
769
Classic EPLD Family Data Sheet
Operating Conditions
Tables 14 through 18 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for EP910 and EP910I devices.
Table 14. EP910 & EP910I Device Absolute Maximum Ratings
Symbol Parameter Conditions
Notes (1), (2)
EP910 Min Max
7.0 7.0 250 25 150 135 150 135 -65 -65 150 135 150 135
EP910I Min
-2.0 -0.5
Unit
Max
7.0 VCC + 0.5 V V mA mA C C C C
VCC VI IMAX IOUT TSTG TAMB TJ
Supply voltage DC input voltage DC VCC or ground current DC output current, per pin Storage temperature Ambient temperature Junction temperature
With respect to ground (3)
-2.0 -2.0 -250 -25
No bias Under bias Ceramic packages, under bias Plastic packages, under bias
-65 -65
Table 15. EP910 & EP910I Device Recommended Operating Conditions
Symbol Parameter Conditions EP910 Min
VCC VI VO TA tR tF Supply voltage Input voltage Output voltage Operating temperature Input rise time Input fall time For commercial use For industrial use
Note (2)
EP910I Min
4.75 -0.3 0 0
Unit
Max
VCC + 0.3 VCC 70 85 100 (50) 100 (50)
Max
5.25 VCC + 0.3 VCC 70 500 500 V V V C C ns ns
(4)
4.75 (4.5) 5.25 (5.5) -0.3 0 0 -40
(5) (5)
Table 16. EP910 & EP910I Device DC Operating Conditions
Symbol
VIH VIL VOH VOL II IOZ
Notes (6), (7)
Min
2.0 -0.3
Parameter
High-level input voltage Low-level input voltage High-level TTL output voltage High-level CMOS output voltage Low-level output voltage Tri-state output leakage current
Conditions
Max
VCC + 0.3 0.8
Unit
V V V V
IOH = -4 mA DC (8) IOH = -0.6 mA DC (8), (9) IOL = 4 mA DC (8)
2.4 3.84 0.45 -10 -10 10 10
V A A
I/O leakage current of dedicated input pins VI = VCC or ground VO = VCC or ground
770
Altera Corporation
Classic EPLD Family Data Sheet
Table 17. EP910 & EP910I Device Capacitance
Symbol Parameter
Note (6)
EP910 Min Max
20 20 20 60
Conditions
EP910I Min Max
8 8 10 12
Unit
CIN CI/O CCLK1 CCLK2
Input pin capacitance I/O pin capacitance CLK1 pin capacitance CLK2 pin capacitance
VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz
pF pF pF pF
Table 18. EP910 & EP910I Device ICC Supply Current
Symbol Parameter Conditions
Notes (2), (6), (7)
EP910 Min Typ
20 6 45
EP910I Max
150 20 80 (100)
Unit Max
150 12 150 A mA mA
Min
Typ
60 4 120
ICC1 ICC2 ICC3
VCC supply current (non-Turbo, standby) VCC supply current (non-Turbo, active) VCC supply current (Turbo, active)
VI = VCC or ground, no load (10), (11) VI = VCC or ground, no load, f = 1.0 MHz (10), (11) VI = VCC or ground, no load, f = 1.0 MHz (11)
Notes to tables:
(1) (2) (3) See the Operating Requirements for Altera Devices Data Sheet in this data book. Numbers in parentheses are for industrial-temperature-range devices. The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2.0 V (EP910) or -0.5 V (EP910I) or overshoot to 7.0 V (EP910) or VCC + 0.5 V (EP910I) for input currents less than 100 mA and periods less than 20 ns. (4) Maximum VCC rise time for EP910 devices = 50 ms; for EP910I devices, maximum VCC rise time is unlimited with monotonic rise. (5) For all clocks: tR and tF = 100 ns (50 ns for the industrial-temperature-range version). (6) These values are specified in Table 15 on page 770. (7) The device capacitance is measured at 25 C and is sample-tested only. (8) The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL output current. (9) This parameter does not apply to EP910I devices. (10) When the Turbo Bit option is not set (non-Turbo mode), an EP910 device will enter standby mode if no logic transitions occur for 100 ns after the last transition, and an EP910I device will enter standby mode if no logic transitions occur for 75 ns after the last transition. (11) Measured with a device programmed as a 24-bit counter.
Altera Corporation
771
Classic EPLD Family Data Sheet
Tables 19 and 20 show the timing parameters for EP910 devices.
Table 19. EP910 External Timing Parameters
Symbol Parameter
Notes (1), (2)
NonUnit Turbo Min Max Min Max Min Max Adder (3)
30.0 33.0 30.0 30.0 33.0 41.7 24.0 0.0 12.0 12.0 37.0 27.0 0.0 13.0 13.0 18 30.0 33.3 10.0 15.0 15.0 15.0 28.6 10.0 15.0 16.0 16.0 1.0 33.0 30.0 33.3 28.6 38.0 35.0 25.0 21.0 35.0 25.0 10.0 15.0 17.0 17.0 1.0 43.0 40.0 30.0 0.0 0.0 35.0 38.0 35.0 35.0 38.0 32.3 31.0 0.0 15.0 15.0 24.0 40.0 40.0 43.0 40.0 40.0 43.0 30.0 30.0 30.0 30.0 30.0 0.0 30.0 0.0 0.0 0.0 0.0 0.0 0.0 30.0 0.0 0.0 0.0 ns ns ns ns ns MHz ns ns ns ns ns ns MHz ns ns ns ns ns ns ns MHz
Conditions
EP910-30
EP910-35
EP910-40
tPD1 tPD2 tPZX tPXZ tCLR fMAX tSU tH tCH tCL tCO1 tCNT fCNT tASU tAH tACH tACL tODH tACO1 tACNT fACNT
Input to non-registered output I/O input to non-registered output Input to output enable Input to output disable Asynchronous output clear time Maximum frequency Global clock input setup time Global clock input hold time Global clock high time Global clock low time Global clock to output delay Global clock minimum clock period Maximum internal global clock frequency Array clock input setup time Array clock input hold time Array clock high time Array clock low time Output data hold time after clock Array clock to output delay Array clock minimum clock period Maximum internal array clock frequency
C1 = 35 pF C1 = 35 pF C1 = 35 pF C1 = 5 pF (4) C1 = 35 pF
(5)
C1 = 35 pF
(6) (6)
C1 = 35 pF (7) C1 = 35 pF
1.0
(6)
772
Altera Corporation
Classic EPLD Family Data Sheet
Table 20. EP910 Internal Timing Parameters
Symbol
tIN tIO tLAD tOD tZX tXZ tSU tH tIC tICS tFD tCLR
Parameter
Input pad and buffer delay I/O input pad and buffer delay Logic array delay Output buffer and pad delay Output buffer enable delay Output buffer disable delay Register setup time Register hold time Array clock delay Global clock delay Feedback delay Register clear time
Condition
EP910-30 Min Max
9.0 3.0 14.0
EP910-35 Min Max
10.0 3.0 16.0 9.0 9.0 9.0 13.0 12.0
EP910-40 Min Max
13.0 3.0 17.0 10.0 10.0 10.0 15.0 12.0
Unit
ns ns ns ns ns ns ns ns
C1 = 35 pF C1 = 35 pF C1 = 5 pF 12.0 12.0
7.0 7.0 7.0
17.0 2.0 4.0 17.0
19.0 2.0 6.0 19.0
20.0 1.0 8.0 20.0
ns ns ns ns
Notes to tables:
(1) (2) (3) (4) (5) (6) (7) These values are specified in Table 15 on page 770. See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for more information on Classic timing parameters. The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. Sample-tested only for an output change of 500 mV. The fMAX values represent the highest frequency for pipelined data. Measured with a device programmed as a 24-bit counter. Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both global and array clocking.
Altera Corporation
773
Classic EPLD Family Data Sheet
Tables 21 and 22 show the timing parameters for EP910I devices.
Table 21. EP910I External Timing Parameters
Symbol Parameter
Notes (1), (2)
Conditions EP910I-12 EP910I-15 EP910I-25 Non-Turbo Unit Adder Min Max Min Max Min Max
(3)
40.0 40.0 40.0 40.0 40.0 0.0 40.0 0.0 0.0 0.0 14.0 25.0 40.0 8.0 8.0 12.5 12.5 1.0 18.0 15.0 66.6 40.0 22.0 25.0 40.0 40.0 0.0 40.0 0.0 40.0 ns ns ns ns ns MHz ns ns ns ns ns ns MHz ns ns ns ns ns ns ns MHz
tPD1 tPD2 tPZX tPXZ tCLR fMAX tSU tH tCH tCL tCO1 tCNT fCNT tASU tAH tACH tACL tODH tACO1 tACNT fACNT
Input to non-registered output I/O input to non-registered output Input to output enable Input to output disable Asynchronous output clear time Global clock maximum frequency Global clock input setup time Global clock input hold time Global clock high time Global clock low time Global clock to output delay Global clock minimum clock period Maximum internal global clock frequency Array clock input setup time Array clock input hold time Array clock high time Array clock low time Output data hold time after clock Array clock to output delay Array clock minimum clock period Maximum internal array clock frequency
C1 = 35 pF C1 = 35 pF C1 = 35 pF C1 = 35 pF (4) C1 = 35 pF
12.0 12.0 15.0 15.0 15.0 125.0 8.0 0.0 5.0 5.0 8.0 100.0 11.0 0.0 6.0 6.0
15.0 15.0 18.0 18.0 18.0 62.5 16.0 0.0 10.0 10.0 9.0 15.0 66.6 4.0 7.0 7.5 7.5 1.0
25.0 25.0 28.0 28.0 28.0
(5)
C1 = 35 pF
13.0 76.9 3.0 6.0 6.0 6.0
(6)
C1 = 35 pF (7) C1 = 35 pF
1.0 16.0 13.0 76.9
(6)
774
Altera Corporation
Classic EPLD Family Data Sheet
Table 22. EP910I Internal Timing Parameters
Symbol Parameter Condition EP910I-12 Min
tIN tIO tLAD tOD tZX tXZ tSU tH tIC tICS tFD tCLR
Input pad and buffer delay I/O input pad and buffer delay Logic array delay Output buffer and pad delay Output buffer enable delay Output buffer disable delay Register setup time Register hold time Array clock delay Global clock delay Feedback delay Register clear time C1 = 35 pF C1 = 35 pF C1 = 5 pF 4.0 4.0 12.0 4.0 1.0 11.0
EP910I-15 Min Max
3.0 0.0 9.0 3.0 6.0 6.0 5.0 6.0 12.0 3.0 1.0 12.0
EP910I-25 Min Max
2.0 0.0 17.0 6.0 9.0 9.0 5.0 11.0 14.0 6.0 3.0 20.0
Unit
Max
2.0 0.0 8.0 2.0 5.0 5.0
ns ns ns ns ns ns ns ns ns ns ns ns
Notes to tables:
(1) (2) (3) (4) (5) (6) (7) These values are specified in Table 15 on page 770. See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for information on internal timing parameters. The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. Sample-tested only for an output change of 500 mV. The fMAX values represent the highest frequency for pipelined data. Measured with the device programmed as a 24-bit counter. Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both global and array clocking.
Altera Corporation
775
Notes:
EP1810 EPLD
Features
s
s s s s
High-performance, 48-macrocell Classic EPLD - Combinatorial speeds with tPD as fast as 20 ns - Counter frequencies of up to 50 MHz - Pipelined data rates of up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs Programmable clock option for independent clocking of all registers Macrocells individually programmable as D, T, JK, or SR flipflops, or for combinatorial operation Available in the following packages (see Figure 15) - 68-pin ceramic pin-grid array (PGA) - 68-pin plastic J-lead chip carrier (PLCC)
Figure 15. EP1810 Package Pin-Out Diagrams
Package outlines not drawn to scale. See Table 32 on page 785 of this data sheet for PGA package pin-out information. Windows in ceramic packages only.
I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O
L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11
Bottom View
I/O I/O I/O I/O INPUT INPUT INPUT CLK1/INPUT VCC CLK2/INPUT INPUT INPUT INPUT INPUT INPUT INPUT I/O
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
I/O I/O I/O I/O INPUT INPUT INPUT CLK4/INPUT VCC CLK3/INPUT INPUT INPUT INPUT I/O I/O I/O I/O
68-Pin PGA
EP1810
Altera Corporation
I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O
68-Pin PLCC
EP1810
777
Classic EPLD Family Data Sheet
General Description
Altera EP1810 devices offer LSI density, TTL-equivalent speed, and lowpower consumption. EP1810 devices have 48 macrocells, 16 dedicated input pins, and 48 I/O pins (see Figure 16). EP1810 devices are divided into four quadrants, each containing 12 macrocells. Of the 12 macrocells in each quadrant, 8 have quadrant feedback and are "local" macrocells (see "Feedback Select" on page 749 of this data sheet for more information). The remaining 4 macrocells in the quadrant are "global" macrocells. Both local and global macrocells can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of the feedbacks from the global macrocells. EP1810 devices also have four dedicated inputs (one in each quadrant) that can be used as quadrant clock inputs. If the dedicated input is used as a clock pin, the input feeds the clock input of all registers in that particular quadrant.
778
Altera Corporation
Classic EPLD Family Data Sheet
Figure 16. EP1810 Block Diagram
Pin numbers are for J-lead packages. Pin numbers in parentheses are for PGA packages.
Quadrant A 2 (F1) 3 (G2) 4 (G1) 5 (H2) 6 (H1) 7 (J2) 8 (J1) 9 (K1) 10 (K2) 1 (L2) 1 12 (K3) 13 (L3) Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 Macrocell 8 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 Quadrant D Macrocell 48 Macrocell 47 Macrocell 46 Macrocell 45 Macrocell 44 Macrocell 43 Macrocell 42 Macrocell 41 Macrocell 40 Macrocell 39 Macrocell 38 Macrocell 37 (E1) 68 (E2) 67 (D1) 66 (D2) 65 (C1) 64 (C2) 63 (B1) 62 (B2) 61 (A2) 60 (A3) 59 (B3) 58 (A4) 57
14 (K4) 15 (L4) 16 (K5) 17 (L5) 19 (L6) 20 (K7) 21 (L7) 22 (K8)
INPUT INPUT INPUT INPUT/CLK1 INPUT/CLK2 INPUT INPUT INPUT Quadrant B
Local Bus--Quadrant D
Local Bus--Quadrant A
INPUT INPUT INPUT
(B4) 56 (A5) 55 (B5) 54 (A6) 53 (A7) 51 (B7) 50 (A8) 49 (B8) 48
Global Bus
INPUT/CLK4 INPUT/CLK3 INPUT INPUT INPUT Quadrant C Macrocell 36 Macrocell 35 Macrocell 34 Macrocell 33 Macrocell 32 Macrocell 31 Macrocell 30 Macrocell 29 Macrocell 28 Macrocell 27 Macrocell 26 Macrocell 25 Global Macrocells Local Macrocells
23 (L8) 24 (K9) 25 (L9) 26 (L10) 27 (K10) 1 28 (K1 ) 29 (J10) 1 30 (J1 ) 31(H10) 1 32 (H1 ) 33(G10) 1 34 (G1)
Macrocell 13 Macrocell 14 Macrocell 15 Macrocell 16 Macrocell 17 Macrocell 18 Macrocell 19 Macrocell 20 Macrocell 21 Macrocell 22 Macrocell 23 Macrocell 24
(A9) 47 (B9) 46 (A10) 45 (B10) 44 (B11) 43 (C11) 42 (C10) 41 (D11) 40 (D10) 39 (E11) 38 (E10) 37 (F11) 36
Altera Corporation
Local Bus--Quadrant C
Local Bus--Quadrant B
779
Classic EPLD Family Data Sheet
Figure 17 shows the typical supply current (ICC) versus frequency for EP1810 EPLDs.
Figure 17. I CC vs. Frequency of EP1810 Devices
EP1810
100
Typical ICC Active (mA)
10
VCC = 5.0 V TA = 25 C
1.0
0.1
10 kHz
100 kHz
1 MHz
10 MHz
60 MHz
Frequency
Figure 18 shows the output drive characteristics of EP1810 devices.
Figure 18. Output Drive Characteristics of EP1810 Devices
Drive characteristics may exceed shown curves.
EP1810-20 & EP1810-25 EPLDs
200
EP1810-35 & EP1810-45 EPLDs
80
IOL
150
IOL VCC = 5.0 V TA = 25 C Typical IO Output Current (mA)
60
Typical I O Output Current (mA)
100
40
VCC = 5.0 V TA = 25 C
50
IOH
20
IOH
1
2
3
4
5
1
2
3
4
5
VO Output Voltage (V)
VO Output Voltage (V)
780
Altera Corporation
Classic EPLD Family Data Sheet
Operating Conditions
Tables 23 through 27 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for EP1810 devices.
Table 23. EP1810 Device Absolute Maximum Ratings
Symbol
VCC VI IMAX IOUT TSTG TAMB TJ
Notes (1), (2)
Min
-2.0 (-0.5) -2.0 (-0.5) -300 (-400) -25
Parameter
Supply voltage DC input voltage DC V CC or ground current DC output current, per pin Storage temperature Ambient temperature Junction temperature No bias Under bias
Conditions
With respect to ground (3) With respect to ground (3)
Max
7.0 7.0 300 (400) 25 150 135 150 135
Unit
V V mA mA C C C C
-65 -65
Ceramic packages, under bias Plastic packages, under bias
Table 24. EP1810 Device Recommended Operating Conditions
Symbol
VCC VI VO TA tR tF
Note (2)
Min
4.75 (4.5) -0.3 0
Parameter
Supply voltage Input voltage Output voltage Operating temperature Input rise time Input fall time
Conditions
(4)
Max
5.25 (5.5) VCC + 0.3 VCC 70 85 50 50
Unit
V V V C C ns ns
For commercial use For industrial use
0 -40
(5) (5)
Table 25. EP1810 Device DC Operating Conditions
Symbol
VIH VIL VOH VOL II IOZ
Notes (6), (7)
Min
2.0 -0.3
Parameter
High-level input voltage Low-level input voltage High-level TTL output voltage High-level CMOS output voltage Low-level output voltage
Conditions
Max
VCC + 0.3 0.8
Unit
V V V V
IOH = -4 mA DC (8) IOH = -0.6 mA DC (8) IOL = 4 mA DC (8)
2.4 3.84 0.45 -10 -10 10 10
V A A
I/O pin leakage current of dedicated VI = VCC or ground input pins Tri-state output leakage current VO = VCC or ground
Altera Corporation
781
Classic EPLD Family Data Sheet
Table 26. EP1810 Device Capacitance
Symbol
CIN CIO CCLK1 CCLK2
Note (9)
Conditions
VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz
Parameter
Input pin capacitance I/O pin capacitance CCLK1 pin capacitance CCLK2 pin capacitance
Min
Max
20 20 25 160
Unit
pF pF pF pF
Table 27. EP1810 Device ICC Supply Current
Symbol
ICC1 ICC2 ICC3
Notes (2), (6), (7)
Conditions Speed Grade Min Typ
50 35 20 10 180 100
Parameter
VCC supply current (non-Turbo, standby) VCC supply current (non-Turbo, active) VCC supply current (Turbo, active)
Max
150 150 40 30 (40) 225 (250) 180 (240)
Unit
A A mA mA mA mA
VI = VCC or ground, no load, -20, -25 (10) -35, -45 VI = VCC or ground, no load, -20, -25 f = 1.0 MHz (10) -35, -45 VI = VCC or ground, no load f = 1.0 MHz (10) -20, -25 -35, -45
Notes to tables:
See the Operating Requirements for Altera Devices Data Sheet in this data book. Numbers in parentheses are for industrial-temperature-range devices. The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods less than 20 ns. (4) Maximum VCC rise time is 50 ms. (5) For EP1810 clocks: tR and tF = 100 ns (50 ns for industrial-temperature-range versions). (6) Typical values are for TA = 25 C and VCC = 5 V. (7) These values are specified in Table 24 on page 781. (8) The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL output current. (9) The device capacitance is measured at 25 C and is sample-tested only. (10) Measured with a device programmed as four 12-bit counters. (1) (2) (3)
782
Altera Corporation
Classic EPLD Family Data Sheet
Tables 28 through 31 show the timing parameters for EP1810-20, EP1810-25, EP1810-35, and EP1810-45 devices.
Table 28. EP1810-20 & EP1810-25 External Timing Parameters
Symbol Parameter Conditions
Note (1)
EP1810-20 EP1810-25 Non-Turbo Adder Min Max Min Max
(2)
25.0 25.0 25.0 0.0 0.0 0.0 18.0 25.0 40.0 10.0 10.0 20.0 1.0 20.0 50.0 62.5 40.0 50.0 1.0 25.0 25.0 0.0 0.0 0.0 25.0 0.0 25.0 0.0 0.0 0.0 0.0 ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns MHz
Unit
tPD1 tPD2 tSU tH tCH tCL tCO1 tCNT fCNT tASU tAH tACO1 tODH tACNT fACNT fMAX
Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock high time Global clock low time Global clock to output delay Minimum global clock period Maximum internal frequency Array clock setup time Array clock hold time Array clock to output delay Output data hold time after clock Array clock maximum clock period Maximum internal array clock frequency Maximum clock frequency
C1 = 35 pF C1 = 35 pF 13.0 0.0 8.0 8.0 C1 = 35 pF
20.0 22.0 17.0 0.0 10.0 10.0 15.0 20.0 50.0 8.0 8.0
25.0 28.0
(3) (3)
C1 = 35 pF C1 = 35 pF (4)
(3) (3) (5)
Table 29. EP1810-20 and EP1810-25 Internal Timing Parameters
Symbol Parameter Conditions EP1810-20 EP1810-25 Non-Turbo Adder Min Max Min Max
tIN tIO tLAD tOD tZX tXZ tSU tH tIC tICS tFD tCLR
Input pad and buffer delay I/O input pad and buffer delay Logic array delay Output buffer and pad delay Output buffer enable delay Output buffer disable delay Register setup time Register hold time Array clock delay Global clock delay Feedback delay Register clear time C1 = 35 pF C1 = 35 pF C1 = 5 pF (6) 8.0 5.0 9.0 4.0 3.0 9.0 5.0 2.0 9.0 6.0 6.0 6.0 10.0 10.0 12.0 5.0 3.0 12.0 7.0 3.0 12.0 6.0 6.0 6.0
Unit
(2)
0.0 0.0 25.0 0.0 0.0 0.0 0.0 0.0 25.0 0.0 -25.0 25.0 ns ns ns ns ns ns ns ns ns ns ns ns
Altera Corporation
783
Classic EPLD Family Data Sheet
Table 30. EP1810-35 & EP1810-45 External Timing Parameters
Symbol Parameter Conditions
Note (1)
EP1810-35 EP1810-45 Non-Turbo Adder Min Max Min Max Unit
(2)
30.0 30.0 30.0 0.0 0.0 0.0 ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns MHz
tPD1 tPD2 tSU tH tCH tCL tCO1 tCNT fCNT tASU tAH tACO1 tODH tACNT fACNT fMAX
Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock high time Global clock low time Global clock to output delay Minimum global clock period Maximum internal frequency Array clock setup time Array clock hold time Array clock to output delay Output data hold time after clock Array clock maximum clock period Maximum internal array clock frequency Maximum clock frequency
C1 = 35 pF C1 = 35 pF 25.0 0.0 12.0 12.0 C1 = 35 pF
35.0 40.0 30.0 0.0 15.0 15.0 20.0 35.0 28.6 10.0 15.0 22.2 11.0 18.0 35.0 1.0 35.0 28.6 40 22.2 33.3 1.0
45.0 50.0
25.0 45.0
0.0 0.0 0.0 30.0 0.0
(3) (3)
C1 = 35 pF C1 = 35 pF (4)
45.0 45.0
30.0 0.0 0.0 0.0
(3) (3) (5)
Table 31. EP1810-35 & EP1810-45 Internal Timing Parameters
Symbol Parameter Conditions EP1810-35 EP1810-45 Non-Turbo Adder Min Max Min Max
tIN tIO tLAD tOD tZX tXZ tSU tH tIC tICS tFD tCLR
Input pad and buffer delay I/O input pad and buffer delay Logic array delay Output buffer and pad delay Output buffer enable delay Output buffer disable delay Register setup time Register hold time Array clock delay Global clock delay Feedback delay Register clear time C1 = 35 pF C1 = 35 pF C1 = 5 pF (6) 10.0 15.0 19.0 4.0 6.0 24.0 7.0 5.0 19.0 9.0 9.0 9.0 10.0 18.0 28.0 8.0 7.0 32.0 6.0 5.0 28.0 11.0 11.0 11.0
Unit
(2)
0.0 0.0 30.0 0.0 0.0 0.0 0.0 0.0 30.0 0.0 -30.0 30.0 ns ns ns ns ns ns ns ns ns ns ns ns
784
Altera Corporation
Classic EPLD Family Data Sheet Notes to tables:
(1) (2) (3) (4) (5) (6) These values are specified in Table 24 on page 781. The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. Measured with a device programmed as four 12-bit counters. Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter applies for both global and array clocking. The fMAX values represent the highest frequency for pipelined data. Sample-tested only for an output change of 500 mV.
Pin-Out Information
Table 32 provides pin-out information for EP1810 devices in 68-pin PGA packages.
Table 32. EP1810 PGA Pin-Outs
Pin
A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8
Function
I/O I/O I/O INPUT CLK4/INPUT INPUT I/O I/O I/O I/O I/O INPUT INPUT VCC INPUT INPUT
Pin
B9 B10 B11 C1 C2 C11 D1 D2 D10 D11 E1 E2 E10 E11 F1 F2
Function
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND
Pin
F10 F11 G1 G2 G10 G11 H1 H2 H10 H11 J1 J2 J10 J11 K1 K2 K3
Function
GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Pin
K4 K5 K6 K7 K8 K9
Function
INPUT INPUT VCC INPUT INPUT I/O
CLK3/INPUT C10
K10 I/O K11 I/O L2 L3 L4 L5 L6 L7 L8 L9 L10 I/O I/O INPUT CLK1/INPUT CLK2/INPUT INPUT I/O I/O I/O
Altera Corporation
785
Notes:

▲Up To Search▲

Price & Availability of EP910I

	To Download EP910I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .