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APA0715
3W Mono Fully Differential Audio Power Amplifier
Features
General Description
The APA0715 is a Mono, fully differential Class-AB audio amplifier which can operate with supply voltage from 2.4V to 5V and is available in a MSOP8, MSOP8P, or TDFN3x38 package. High PSRR and fully differential architecture increase immunity to noise and RF rectification. In addition to these features, a short startup time and small package size make the APA0715 an ideal choice for Mobil Phones and Portable Devices. The APA0715 also integrates the de-pop circuitry that reduces the pops and click noises during power on/off and shutdown mode operation. Both Thermal and over-current protections are integrated to avoid the IC being destroyed by over temperature and short-circuit. The APA0715 is capable of driving 3W at 5V into 3 speaker.
* * * * * * * *
Operating Voltage: 2.4V~5.5V Fully Differential Class-AB Amplifier High PSRR and Excellent RF Rectification Immunity Low Crosstalk 3W Output Power into 3 Load at VDD=5V Thermal and Over-Current Protections Low Supply Current :1.5mA Typical Space Saving Package -MSOP-8 -MSOP-8P -TDFN3x3-8 Lead Free and Green Devices Available (RoHS Compliant)
*
Applications
Pin Configuration
SD 1 BYPASS 2 INP 3 MSOP-8 Top View 8 OUTN 7 GND 6 VDD 5 OUTP
* *
Mobil Phones Portable Devices
Simplified Application Circuit
INN 4
SD 1 BYPASS 2 INP 3 INN 4 MSOP-8P Top View
8 OUTN 7 GND 6 VDD 5 OUTP
LINN Input LINP
LOUTP
APA0715
LOUTN
Speaker
SD 1 BYPASS 2 INP 3 INN 4 TDFN3x3-8 TOP View
8 OUTN 7 GND 6 VDD 5 OUTP
=Thermal Pad (connected the Thermal Pad to GND plane for better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 1 www.anpec.com.tw
APA0715
Ordering and Marking Information
APA0715 Assembly Material Handling Code Temperature Range Package Code A0715 XXX XX A0715 XXX XX APA 0715 XXXXX Package Code X : MSOP-8 XA : MSOP-8P QB : TDFN3x3-8 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device
APA0715
X:
XXXXX - Date Code
APA0715
XA :
XXXXX - Date Code
APA0715
QB :
XXXXX - Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight).
Absolute Maximum Ratings
Symbol VDD Supply Voltage
(Note 1)
Rating -0.3 to 6 -0.3 to 6 -0.3 to VDD +0.3 150 -65 to +150 260 Internally Limited Unit V V V
Parameter
Input Voltage (INN, INP, SD to GND) VIN Input Voltage (OUTN, OUTP to GND) TJ TSTG TSDR PD Maximum Junction Temperature Storage Temperature Range Maximum Soldering Temperature Range, 10 Seconds Power Dissipation
C C

C
W
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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APA0715
Thermal Characteristics (Note 2,3)
Symbol Parameter Thermal Resistance -Junction to Ambient MSOP-8 MSOP-8P TDFN3x3-8 Thermal Resistance -Junction to Case Typical Value 200 52 54 Unit
JA JC
C /W
MSOP-8P 10 C /W TDFN3x3-8 11 Note 2: Please refer to " Layout Recommendation", the Thermal Pad on the bottom of the IC should soldered directly to the PCB' s ThermalPad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz copper thickness. Note 3: The case temperature is measured at the center of the Thermal Pad on the underside of the MSOP-8P and TDFN3x3-8 package.
Recommended Operating Conditions
Symbol VDD VIH VIL VIC Supply Voltage High Level Threshold Voltage Low Level Threshold Voltage Common Mode Input Voltage Operating Ambient Temperature Range Operating Junction Temperature Range Speaker Resistance SD SD Parameter 2.4 1.8 0 0.5 -40 -40 3 Range ~ 5.5 ~ VDD ~ 0.35 ~ VDD-0.5 ~ 85 ~ 125 ~

Unit V V V
C C
Electrical Characteristics
VDD=5V, GND=0V, AV=1V/V, TA= 25oC (unless otherwise noted)
Symbol IDD ISD II TSTART-UP RSD Parameter Supply Current Shutdown Current Input Current Start-Up Time from End of Shutdown Resistance from Shutdown to GND SD = 0V SD Cb=0.22F Test Conditions Min. 90 APA0715 Typ. 1.5 0.1 50 100 Max. 3 5 110 Unit mA A A ms k
VDD=5V, TA=25X C RL = 3 RL = 4 RL = 8 RL = 3 THD+N = 10% RL = 4 fin = 1kHz RL = 8 RL = 8 fin = 1kHz PO= 0.9W Cb= 0.22F, RL = 8, VRR=0.2VPP, fin = 217Hz THD+N = 1% 1 2.4 2.1 1.3 3 2.6 1.6 0.035 75 -
PO
Output Power
W
THD+N PSRR
Total Harmonic Distortion Pulse Noise Power Supply Rejection Ratio
% dB
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APA0715
Electrical Characteristics (Cont.)
VDD=5V, GND=0V, TA= 25 C (unless otherwise noted)
Symbol Parameter Test Conditions Min. APA0715 Typ. Max. Unit
o
VDD=5V, TA=25X (CONT.) C CMRR S/N VOS Vn Common-Mode Rejection Ratio Signal to Noise Ratio Output Offset Voltage Noise Output Voltage Cb= 0.22F, RL = 8, VIC=0.2VPP, fin = 217Hz With A-weighting Filter PO = 1.3W, RL = 8 RL = 8 Cb= 0.22F, With A-weighting Filter 85 112 5 8 20 dB dB mV V (rms)
VDD=3.6V, TA=25X C RL = 3 THD+N = 1% PO Output Power THD+N = 10% fin = 1kHz THD+N PSRR CMRR S/N VOS Vn Total Harmonic Distortion Pulse Noise Power Supply Rejection Ratio Common-Mode Rejection Ratio Signal to Noise Ratio Output Offset Voltage Noise Output Voltage RL = 4 RL = 8 RL = 3 RL = 4 RL = 8 RL = 8 fin = 1kHz PO= 0.45W Cb= 0.22F, RL = 8, VRR=0.2VPP, fin = 217Hz Cb= 0.22F, RL = 8, VIC=0.2VPP, fin = 217Hz With A-weighting Filter PO = 0.65W, RL = 8 RL = 8 Cb= 0.22F, With A-weighting Filter 1.2 1 0.65 1.5 1.3 0.8 0.05 85 75 110 5 7 20 mV V (rms) dB % W
VDD=2.4V, TA=25X C RL = 3 THD+N = 1% PO Output Power THD+N = 10% fin = 1kHz THD+N PSRR CMRR S/N VOS Vn Total Harmonic Distortion Pulse Noise Power Supply Rejection Ratio Common-Mode Rejection Ratio Signal to Noise Ratio Output Offset Voltage Noise Output Voltage RL = 4 RL = 8 RL = 3 RL = 4 0. 5 0.45 0.3 0.7 0.6 0.35 0.08 80 65 106 5 7 20 mV V (rms) dB % W
RL = 8 PO = 0.2W, fin = 1kHz RL = 8 Cb= 0.22F, RL = 8, VRR=0.2VPP, fin = 217Hz Cb= 0.22F, RL = 8, VIC=0.2VPP, fin = 217Hz With A-weighting Filter PO = 0.3W, RL = 8 RL = 8 Cb= 0.22F, With A-weighting Filter
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APA0715
Typical Operating Characteristics
THD+N vs. Output Power
10 RL=3 fin=1kHz Ci=0.22F AV=1V/V 1 BW<80kHz VDD=2.4V 0.1 VDD=3.6V VDD=5.0V 1 5
0.01 10m 100m Output Power (W) THD+N (%) 10
THD+N vs. Output Power
RL=4 fin=1kHz Ci=0.22F AV=1V/V BW<80kHz
1
THD+N (%)
VDD=2.4V 0.1 VDD=3.6V
VDD=5.0V 1 5
0.01 10m
100m Output Power (W)
THD+N vs. Output Power
10 RL=8 fin=1kHz Ci=0.22F AV=1V/V BW<80kHz
THD+N vs. Frequency
10 VDD=5.0V RL=8 Ci=0.22F AV=1V/V BW<80kHz
THD+N (%)
THD+N (%)
1
1
0.1
VDD=2.4V
0.1
PO=250mW PO=25mW PO=0.9W
VDD=3.6V 0.01 10m VDD=5.0V 100m Output Power (W) 1 3
0.01 20 100
1k Frequency (Hz)
10k 20k
THD+N vs. Frequency
10 VDD=3.6V RL=8 Ci=0.22F AV=1V/V BW<80kHz PO=250mW 0.1 PO=25mW PO=450mW 0.01
0.01 10
THD+N vs. Frequency
VDD=2.4V RL=8 Ci=0.22F AV=12dB BW<80kHz
THD+N (%)
THD+N (%)
1
1
0.1
PO=75mW PO=15mW PO=350mW
20
100
1k Frequency (Hz)
10k 20k
20
100
1k Frequency (Hz)
10k 20k
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APA0715
Typical Operating Characteristics (Cont.)
Output Power vs. Supply Voltage
3.5 3.0 Output Power (W) 2.5 2.0 1.5 1.0 0.5 0.0 2.4 3.0 RL=8,THD+N=10% RL=8,THD+N=1% 3.5 4.0 Supply Volume (V) 4.5 5.0 fin=1kHz AV=1V/V RL=3,THD+N=10%
Output Power vs. Load Resistance
3.5 VDD=5V,THD+N=1% 3.0 Output Power (W) 2.5 2.0 1.5 VDD=2.4V,THD+N=1% 1.0 0.5 0.0 3 8 13 18 23 Load Resistance () 28 32 VDD=5V,THD+N=10% fin=1kHz AV=1V/V
RL=4,THD+N=10% RL=3,THD+N=1% RL=4,THD+N=1%
VDD=3.6V,THD+N=10% VDD=3.6V,THD+N=1% VDD=2.4V,THD+N=10%
2.0
Power Dissipation vs. Output Power
1.0
Power Dissipation vs. Output Power
Power Dissipation (W)
1.5 RL=3 1.0 RL=4
Power Dissipation (W)
0.8 RL=3 0.6 RL=4 0.4 VDD=3.6V fin=1kHz AV=1V/V 1.2 1.5 1.8
0.5 RL=8 0.0 VDD=5V fin=1kHz AV=1V/V 2.5 3.0
0.2 RL=8 0.0 0.0 0.3 0.6 0.9
0.0
0.5
1.0 1.5 2.0 Output Power (W)
Output Power (W)
Supply Current vs. Output Power
1.0 RL=3 0.8 Supply Current (A)
Supply Current vs. Output Power
0.8 RL=3 0.6 Supply Current (A)
0.6
RL=4
0.4
RL=4
0.4 RL=8 0.2 VDD=5V fin=1kHz AV=1V/V 0.5 1.0 1.5 2.0 2.5 3.0
0.2
RL=8 VDD=3.6V fin=1kHz AV=1V/V
0.0 0.0
0.0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
Output Power (W)
Output Power (W)
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APA0715
Typical Operating Characteristics (Cont.)
Output Noise Voltage vs. Frequency
50u 40u 30u Output Noise Voltage (Vrms) 20u 10u 7u 5u 4u 3u 2u 1u VDD=5.0V RL=8 AV=1V/V Ci=0.22F A-Weighting 20 100 1k Frequency (Hz) 10k 20k
Output Noise Voltage (Vrms)
50u 40u 30u 20u 10u 7u 5u 4u 3u 2u 1u
Output Noise Voltage vs. Frequency
VDD=3.6V RL=8 AV=1V/V Ci=0.22F A-Weighting 20 100 1k Frequency (Hz) 10k 20k
Power Supply Rejection Ratio (dB)
Output Noise Voltage (Vrms)
50u 40u 30u 20u 10u 7u 5u 4u 3u 2u 1u
Output Noise Voltage vs. Frequency
PSRR vs. Frequency
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 VDD=3.6V 100 1k Frequency (Hz) 10k 20k VDD=5.0V VDD=2.4V RL=8 AV=1V/V Cb=0.47F Ci=2.2F Inputs ac-Grounded
VDD=2.4V RL=8 AV=1V/V Ci=0.22F A-Weighting
20
100
1k Frequency (Hz)
10k 20k
PSRR vs. Frequency
+0 Power Supply Rejection Ratio (dB) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 VDD=5.0V VDD=3.6V 100 VDD=2.4V 10k 20k
PSRR vs. Frequency
+0 Power Supply Rejection Ratio (dB) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 Cb=0.47F 100 Cb=0.01F Cb=0.1F Cb=1F 10k 20k R VDD=3.6V RL=8 AV=1V/V Ci=2.2F Inputs ac-Grounded
T RL=8 AV=1V/V Cb=0.47F Ci=2.2F Inputs Floating
1k Frequency (Hz)
1k Frequency (Hz)
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APA0715
Typical Operating Characteristics (Cont.)
CMRR vs. Frequency
Common Mode Rejection Ratio (dB)
Common Mode Rejection Ratio (dB)
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 20
RL=8 AV=1V/V Vin=0.2VPP Ci=0.22F
+0 -10 -20 -30 -40 -50 -60 -70 -80
CMRR vs. Common Mode Input Voltage
RL=8 AV=1V/V Vin=0.2VPP Ci=0.22F
VDD=3.6V
VDD=2.4V
VDD=5.0V
VDD=3.6V 500m 1 1.5
VDD=2.4V
VDD=5.0V 3 3.5 4 4.5 5
100
1k Frequency (Hz)
10k 20k
2 2.5
Common Mode Input Voltage
Frequency Response
+1 Gain +260
Frequency Response
+1 +0
Phase (deg)
+260 Gain +220 Phase (deg)
+0
+220
Gain (dB)
Phase -2 VDD=5.0V AV=1V/V RL=8 Ci=0.22F 10 100 1k 10k Frequency (Hz) 200k +140
Gain (dB)
-1
+180
-1 Phase -2 VDD=3.6V AV=1V/V RL=8 Ci=0.22F 10 100 1k 10k 200k Frequency (Hz)
+180
+140
-3
+100
-3
+100
-4
+60
-4
+60
Frequency Response
+1 +0 Gain +260 +220 Phase (deg)
Supply Current vs. Supply Voltage
3.0 2.5 Supply Current (mA) 2.0 1.5 1.0 0.5 0.0 2.4 AV=1V/V No Load
Gain (dB)
-1 Phase -2 VDD=2.4V AV=1V/V RL=8 Ci=0.22F 10 100 1k 10k Frequency (Hz) 200k
+180
+140
-3
+100
-4
+60
3.0
3.5 4.5 4.0 Supply Voltage (V)
5.0
5.5
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APA0715
Typical Operating Characteristics (Cont.)
Start-up Time vs. Bypass Capacitor
VDD=5.0V AV=1V/V No Load
-40 -80 -120 Output Voltage (dBV) +0 -40 -80 -120 -160 0 400 800 1.2k 1.6k 2k -160
120 Start-up Time (ms)
90
60
30
0
0.0
0.2
0.4
0.6
0.8
1.0
Bypass Capacitor (F)
Frequency (Hz)
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Supply Voltage (dBV)
150
GSM Power Supply Rejection vs. Frequency
+0
APA0715
Operating Waveforms
GSM Power Supply Rejection vs. Time
VDD 1 V DD
Power On
1
VROUT 2
2 VROUT
CH1: VDD, 100mV/Div, DC, VDD Offset =5.0V CH2: VROUT, 20mV/Div, DC TIME: 2ms/Div
CH1: VDD, 2V/Div, DC CH2: VROUT, 50mV/Div, DC TIME: 20ms/Div
Power Off
Shutdown Release
VDD VR S D
1
1 VROUT
2 2 V ROUTN
CH1: VDD, 2V/Div, DC CH2: VROUT, 50mV/Div, DC TIME: 50ms/Div
CH1: VRSD, 2V/Div, DC CH2: VROUTN, 2V/Div, DC TIME: 20ms/Div
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APA0715
Operating Waveforms (Cont.)
Shutdown
V RSD 1
VROUTN 2
CH1: VRSD, 2V/Div, DC CH2: VROUTN, 2V/Div, DC TIME: 20ms/Div
Pin Description
PIN I/O/P NO. 1 2 3 4 5 6 7 8 NAME SD BYPASS INP INN ROUTP VDD GND LOUTN I P I I O P P O Shutdown mode control signal input, place left channel speaker amplifier in shutdown mode when held low. Bypass voltage input pin The non-inverting input of amplifier. INP is via a capacitor to Gnd for single-end (SE) input signal. The inverting input of amplifier. INN is used as audio input terminal, typically. The positive output terminal of speaker amplifier. Supply voltage input pin Ground connection for circuitry. The negative output terminal of speaker amplifier. FUNCTION
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APA0715
Block Diagram
LINN
OUTP
OUTN LINP
SD Bias and Control Circuitrys
BYPASS
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APA0715
Typical Application Circuits
Single-ended input mode
Rf1 10k
VDD
Cs2 0.1F Cs1 10F
6 VDD
Ci1 Input 0.22F Ci2 0.22F
Ri1 10k Ri2 10k
INN 4
5 OUTP 8 OUTN
INP 3
4
SHUTDOWN Control
SD 1
RSD 100k
Bias and Control Circuitrys
2 BYPASS
0.22F Cb
7 GND
Rf2 10k
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APA0715
Typical Application Circuits (Cont.)
Differential input mode
Rf1 10k
VDD
Cs2 0.1F Cs1 10F
6 VDD
Ci1 0.22F Input Ci2 0.22F
Ri1 10k Ri2 10k
INN 4
5 OUTP 8 OUTN
INP 3
4
SHUTDOWN Control
SD 1
RSD 100k
Bias and Control Circuitrys
2 BYPASS
0.22F Cb
7 GND
Rf2 10k
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APA0715
Function Description
Fully Differential Amplifier The power amplifiers are fully differential amplifiers with differential inputs and outputs. The fully differential amplifier has some advantages versus traditional amplifiers. First, don' need the input coupling capacitors because t the common-mode feedback compensates the input bias. The inputs can be biased from 0.5V to VDD-0.5V, and the outputs are still biased at mid-supply of the power amplifier. If the inputs are biased out of the input range, the coupling capacitors are required. Second, the fully differential amplifier has outstanding immunity against supply voltage ripple (217Hz) cuased by the GSM RF transmitters' signal which is better than the typical audio amplifier. Thermal Protection The over-temperature circuit limits the junction temperature of the APA0715. When the junction temperature exceeds T J = +150 oC, a thermal sensor turns off the amplifiers, allowing the device to cool. The thermal sensor allows the amplifiers to start-up after the junction temperature cools down to about 125 oC. The thermal protection is designed with a 25 oC hysteresis to lower the average TJ during continuous thermal overload conditions, increasing lifetime of the IC. Over-Current Protection The APA0715 monitors the output buffers'current. When the over-current occurs, the output buffers'current will be reduced and limited to a fold-back current level. The power amplifier will go back to normal operation until the over-current situation has been removed. In addition, if the over-current period is long enough and the IC' s junction temperature reaches the thermal protection threshold, the IC enters thermal protection mode. Shutdown Function In order to reduce power consumption while not in use, the APA0715 contains a shutdown function to externally turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when logic low is placed on the SD pin for APA0715. The trigger point between a logic high and logic low level is typically 1.8V. It is best to switch between the ground and the supply voltage VDD to provide maximum device performance. By switching the SD pin to a low level, the amplifier enters a low-consumption-current state, IDD for APA0715 is in shutdown mode. Under normal operating, APA0715' SD pin should pull s to a high level to keep the IC out of the shutdown mode. The SD pin should be tied to a definite voltage to avoid unwanted state changing.
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APA0715
Application Information
Input Resistance (Ri) and Feedback Resistance (Rf) The gain for the APA0715 is set by the external input resistors (Ri) and external feedback resistors (Rf). AV = Rf Ri (1) input in most applications because the DC level of the amplifiers' inputs are held at VDD/2. Please note that it is important to confirm the capacitor polarity in the application. Effective Bypass Capacitor (CBYPASS) The BYPASS pin sets the VDD/2 for internal reference by voltage divider. Adding capacitors at this pin to filter the noise and regulator the mid-supply rail will increase the PSRR and noise performance. The capacitors should be as close to the device as possible. The effect of a larger bypass capacitor will improve PSRR due to increased supply stability. The bypass capacitance also affects to the start time. The large capacitors will increase the start time when device in shutdown. Optimizing Depop Circuitry Circuitry has been included in the APA0715 to minimize the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click and pop circuitry. The value of Ci will also affect turn-on pops. The bypass voltage ramp up should be slower than input bias voltage. Although the BYPASS pin current source cannot be modified, the size of CBYPASS can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of CBYPASS, turn-on pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationship between the size of CBYPASS and the turn-on time. A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. Hence, it is advantageous to use low-gain configurations. Power Supply Decoupling Capacitor (Cs) The APA0715 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) is
Ri and Rf should range from 1k to 100k. Ri is 10k recommended. For the performance of a fully differential amplifier, it' better to select matching input resistors Ri1 s and R i2 . Therefore, 1% tolerance resistors are recommended. If the input resistors are not matched, the CMRR and PSRR performance are worse than using matching devices. Input Capacitor (Ci) When the APA0715 is driven by a differential input source, the input capacitor may not be required. In the single-ended input application, an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the input resistance Ri form a high-pass filter with the corner frequency determined in the following equation: FC(highpass) = 1 2R iCi (2)
The value of Ci must be considered carefully because it directly affects the low frequency performance of the circuit. Consider the example where Ri is 10k and the specification that calls for a flat bass response down to 100Hz. The equation is reconfigured as below: Ci = 1 2RiFc (3)
When the input resistance variation is considered, the Ci is 0.16F. Therefore, a value in the range of 0.22F to 0.47F would be chosen. A further consideration for this capacitor is the leakage path from the input source through the input network (Ri + Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input of the amplifier. The offset reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier
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APA0715
Application Information (Cont.)
Power Supply Decoupling Capacitor (Cs) (Cont.) as low as possible. Power supply decoupling also prevents the oscillations being caused by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different types of capacitors that target on different types of noises on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series- resistance (ESR) ceramic capacitor, typically 0.1F, is placed as close as possible to the device VDD lead works best. For filtering lower frequency noise signals, a large aluminum electrolytic capacitor of 10F or greater placed near the audio power amplifier is recommended. Fully Differential Amplifier Efficiency The traditional class AB power amplifier efficiency can be calculated starts out as being equal to the ratio of power from the power supply to the power delivered to the load. The following equations are the basis for calculating the amplifier efficiency. P Efficiency () = O PSUP where: PO = VOrms V =P RL 2RL VP 2 (5)
2 2
less than the dissipation in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a Mono 1W audio system with 8 loads and a 5V supply, the maximum draw on the power supply is almost 1.63W.
R L () P O (W) 0.25 0.50 1 1.6 0.4 1.2 2 2.6 0.5 1 2 3 Efficiency (%) 30.1 43.1 61.5 77.7 27.5 48.1 62.4 74.1 27.5 38.7 55.1 66.8 IDD(A) 0.17 0.23 0.33 0.43 0.29 0.51 0.66 0.70 0.37 0.52 0.74 0.92 P D (W) P SUP (W) 0.58 0.66 0.63 0.46 1.06 1.30 1.21 0.91 1.32 1.58 1.63 1.49 0.83 1.16 1.63 2.06 1.46 2.50 3.21 3.51 1.82 2.58 3.63 4.49
8
4
3
Table 1: Efficiency vs. Output Power in 5-V Differential Amplifier Syetems A final point to remember about linear amplifiers (either SE or Differential) is how to manipulate the terms in the efficiency equation to an utmost advantage when possible. Note that in equation, VDD is in the denominator. This indicates that as VDD goes down, efficiency goes up. In other words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. Layout Recommendation 1. All components should be placed close to the APA0715. For example, the input capacitor (Ci) should be close to APA0715' input pins to avoid causing noise cous pling to APA0715' high impedance inputs; the s decoupling capacitor (Cs ) should be placed by the
(4)
VOrms =
2V V PSUP = VDD XIDD] DD PP AVG RL IDD] AVG) 2VP = RL
So the Efficiency () is:
VP 2PORL Efficiency () = 4VDD 4VDD
(6)
APA0715' power pin to decouple the power rail noise. s 2. The output traces should be short, wide ( >50mil), and symmetric. 3. The input trace should be short and symmetric. 4. The power trace width should greater than 50mil. 5. The MSOP-8P and DFN3x3-8 Thermal PAD should be soldered on PCB, and the ground plane needs soldered mask (to avoid short circuit) except the Thermal PAD area.
Table 1 calculates efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Dec., 2008
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APA0715
Application Information (Cont.)
Layout Recommendation (Cont.)
3.3mm 1.4mm
0.38mm
0.65mm
0.7mm
ThermalVia diameter 0.3mm X 5
Ground plane for Thermal PAD
1.85mm
Solder Mask to Prevent Short Circuit
Figure 1:TDFN3X3-8 Land Pattern Recommendation
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Dec., 2008
1.95mm
18
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APA0715
Package Information
MSOP-8
D
SEE VIEW A
E1 e b
E
c
A2
0.25 VIEW A MSOP-8 INCHES MIN. MAX. 0.043 0.000 0.030 0.009 0.003 0.114 0.185 0.114 0.026 BSC 0.80 8 0.016 0 0.031 8 0.006 0.037 0.015 0.009 0.122 0.201 0.122 MAX. 1.10 0.15 0.95 0.38 0.23 3.10 5.10 3.10
A
A1
S Y M B O L A A1 A2 b c D E E1 e L 0
MILLIMETERS MIN.
0.00 0.75 0.22 0.08 2.90 4.70 2.90 0.65 BSC 0.40 0
Note: 1. Follow JEDEC MO-187 AA. 2. Dimension Ddoes not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension E1does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 5 mil per side.
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Dec., 2008
19
0
L
GAUGE PLANE SEATING PLANE
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APA0715
Package Information
MSOP-8P
D
SEE VIEW A D1
EXPOSED PAD
E2
E1
e
b
E
c
A2
0.25
GAUGE PLANE SEATING PLANE VIEW A MSOP-8P
A1
A
S Y M B O L A A1 A2 b c D D1 E E1 E2 e L 0
0
INCHES MIN.
L
MILLIMETERS MIN. MAX. 1.10 0.00 0.75 0.22 0.08 2.90 1.50 4.70 2.90 1.50 0.65 BSC 0.40 0 0.80 8 0.016 0 0.15 0.95 0.38 0.23 3.10 2.50 5.10 3.10 2.50 0.000 0.030 0.009 0.003 0.114 0.059 0.185 0.114 0.059
MAX. 0.043 0.006 0.037 0.015 0.009 0.122 0.098 0.201 0.122 0.098 0.026 BSC 0.031 8
Note: 1. Follow JEDEC MO-187 AA-T 2. Dimension Ddoes not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not flash or protrusions. 3. Dimension E1 does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 6 mil per side.
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APA0715
Package Information
TDFN3x3-8
D A
E
Pin 1
D2
Pin 1 Corner
e S Y M B O L A A1 A3 b D D2 E E2 e L K 0.30 0.20 0.25 2.90 1.90 2.90 1.40 0.65 BSC 0.50 0.012 0.008 TDFN3*3-8 MILLIMETERS MIN. 0.70 0.00 0.20 REF 0.35 3.10 2.40 3.10 1.75 0.010 0.114 0.075 0.114 0.055 0.026 BSC 0.020 MAX. 0.80 0.05 MIN. 0.028 0.000 0.008 REF 0.014 0.122 0.094 0.122 0.069 INCHES MAX. 0.031 0.002
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Dec., 2008
21
LK
E2
b
A1 A3
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APA0715
Carrier Tape & Reel Dimensions
OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B
d
Application
A 330.0O .00 2
H 50 MIN. P1 8.00O .10 0 H
H A
T1
T1
C
d 1.5 MIN. D1 1.5 MIN. d
D 20.2 MIN. T 0.6+0.00 -0.40 D
W
W
E1
F 5.5O .05 0 K0 1.40O .20 0 F
12.4+2.00 13.0+0.50 -0.00 -0.20 P2 2.00O .05 0 T1 D0 1.5+0.10 -0.00 C
12.0O .30 1.75O .10 0 0 A0 5.30O .20 0 W B0 3.30O .20 0 E1
MSOP-8(P)
P0 4.00O .10 0
Application
A
178.0O .00 50 MIN. 2
TDFN3x3-8 P0 P1
12.4+2.00 13.0+0.50 0 0 -0.00 -0.20 1.5 MIN. 20.2 MIN. 12.0O .30 1.75O .10
P2 D0 D1 T A0 B0
5.5O .05 0
K0
4.0O .10 0
8.0O .10 0
2.0O .05 0
1.5+0.10 -0.00
1.5 MIN.
0.6+0.00 0 0 0 -0.40 3.30O .20 3.30O .20 1.30O .20
(mm)
Devices Per Unit
Package Type MOSP-8(P) TDFN3x3-8 Unit Tape & Reel Tape & Reel Quantity 3000 3000
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APA0715
Taping Dircetion Information
MSOP-8(P)
USER DIRECTION OF FEED
TDFN3x3-8
USER DIRECTION OF FEED
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APA0715
Reflow Condition
TP
(IR/Convection or VPR Reflow)
tp Critical Zone TL to TP Ramp-up
TL
Temperature
tL Tsmax
Tsmin Ramp-down ts Preheat
25
t 25C to Peak
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78
Time
Description 245C, 5 sec 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA
Classification Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Time 25C to Peak Temperature Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds 6C/second max. 6 minutes max. Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds 6C/second max. 8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.
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APA0715
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process - Package Peak Reflow Temperatures Package Thickness <2.5 mm 2.5 mm Volume mm <350 240 +0/-5C 225 +0/-5C
3
Volume mm 350 225 +0/-5C 225 +0/-5C
3
Table 2. Pb-free Process - Package Classification Reflow Temperatures Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level. Package Thickness
3 3 3
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838
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