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MITSUBISHI SEMICONDUCTOR MITSUBISHI SEMICONDUCTOR
PS21661-RZ/FR PS21661-RZ/FR
TRANSFER-MOLD TYPE TRANSFER-MOLD TYPE INSULATED TYPE INSULATED TYPE
PS21661-RZ
PS21661-FR
INTEGRATED POWER FUNCTIONS
* 600V/3A low-loss 5th generation IGBT inverter bridge for 3 phase DC-to-AC power conversion.
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
* * * * For upper-leg IGBTS :Drive circuit, High voltage isolated high-speed level shifting, Control circuit under-voltage protection (UV). For lower-leg IGBTS : Drive circuit, Control circuit under-voltage protection (UV), Short circuit protection (SC). Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a UV fault (Lower-side supply). Input interface : 5V line CMOS/TTL compatible Schmitt Trigger receiver circuit (Active high), Arm-short-through interlock protection.
APPLICATION AC100V~200V, three-phase inverter drive for small power motor control.
Fig. 1 PS21661-RZ PACKAGE OUTLINES
Dimensions in mm
q~#5 : pins numbers. The terminals array, please reference to the Fig.5.
Mar. 2004
MITSUBISHI SEMICONDUCTOR
PS21661-RZ/FR
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 2 PS21661-FR PACKAGE OUTLINES
Dimensions in mm
q~#5 : pins numbers. The terminals array, please reference to the Fig.7.
MAXIMUM RATINGS (Tj = 25C, unless otherwise noted) INVERTER PART
Symbol VCC VCC(surge) VCES IC ICP PC Tj Parameter Supply voltage Supply voltage (surge) Collector-emitter voltage Collector current Collector current (peak) Collector dissipation Junction temperature Condition Applied between P-N Applied between P-N Tf = 25C Tf = 25C, tw 1msec Tf = 25C, per 1 chip (Note 1) Ratings 450 500 600 3 6 13.8 -20~+150 Unit V V V A A W C
Note 1 : The maximum junction temperature rating of the power chips integrated within the SIP-IPM is 150C (@ Tf 100C) however, to insure safe operation of the SIP-IPM, the average junction temperature should be limited to Tj(ave) 125C (@ Tf 100C).
CONTROL (PROTECTION) PART
Symbol VD VDB VIN VFO IFO VSC Parameter Control supply voltage Control supply voltage Input voltage Fault output supply voltage Fault output current Current sensing input voltage Condition Applied between VN1-VNC Applied between VUFB-U (VUFS), VVFB-V (VVFS), VWFB-W (VWFS) Applied between UP, VP, WP-VNC, UN, VN, WN-VNC Applied between FO-VNC Sink current at FO terminal Applied between CIN-VNC Ratings 20 20 -0.5~VD -0.5~VD 10 -0.5~VD Unit V V V V mA V
Mar. 2004
MITSUBISHI SEMICONDUCTOR
PS21661-RZ/FR
TRANSFER-MOLD TYPE INSULATED TYPE
TOTAL SYSTEM
Symbol Parameter VCC(PROT) Self protection supply voltage limit (short circuit protection capability) Heatsink operation temperature Tf Storage temperature Tstg Viso Isolation voltage Condition VD = 13.5~16.5V, Inverter part Tj = 125C start, non-repetitive, less than 2 s (Note 2) 60Hz, Sinusoidal, AC 1 minute, connection pins to heat-sink plate Ratings 400 -20~+100 -40~+125 1500 Unit V C C Vrms
Note 2 : Tf MEASUREMENT POINT
AI Board Specification : Dimensions 50 x 50 x 10mm, finishing 12s, warp -50~+100m
Control Terminals
AI Board SIP-IPM
IGBT Chip Temp. measurement point (inside the AI board) FWD Chip
10.5mm
15mm 1.5mm 10mm
25mm
Temp. measurement point (inside the AI board) 100~200m of evenly applied Silicon-Grease
THERMAL RESISTANCE
Symbol Rth(j-f)Q Rth(j-f)F Parameter Junction to fin thermal resistance Condition Inverter IGBT part (per 1/6 module) Inverter FWD part (per 1/6 module) (Note 3) (Note 3) Min. -- -- Limits Typ. -- -- Max. 9.0 9.0 Unit C/W
Note 3 : Grease with good thermal conductivity should be applied evenly about +100m ~ +200m on the contact surface of SIP-IPM and a heat-sink.
ELECTRICAL CHARACTERISTICS (Tj = 25C, unless otherwise noted) INVERTER PART
Symbol VCE(sat) VEC ton trr tc(on) toff tc(off) ICES Parameter Collector-emitter saturation voltage FWD forward voltage Condition VD = VDB = 15V IC = 3A, Tj = 25C VIN = 5V IC = 3A, Tj = 125C Tj = 25C, -IC = 3A, VIN = 0V VCC = 300V, VD = 15V Switching times IC = 3A, Tj = 125C Inductive load (upper-lower arm) VIN = 0 5V VCE = VCES Tj = 25C Tj = 125C Min. -- -- -- 0.35 -- -- -- -- -- -- Limits Typ. 1.60 1.70 1.55 0.70 0.20 0.35 1.00 0.55 -- -- Max. 2.15 2.30 2.00 1.10 -- 0.55 1.50 1.10 1 10 Unit V V s s s s s mA
Collector-emitter cut-off current
CONTROL (PROTECTION) PART
Symbol ID Circuit current IDB VFOH VFOL IIN VSC(ref) UVDBt UVDBr UVDt UVDr tFO Vth(on) Vth(off) Fault output voltage Input current Short circuit trip level Supply circuit under-voltage protection Fault output pulse width ON threshold voltage OFF threshold voltage Parameter Condition VD = 15V, VIN = 0V Total of VN1-VNC (U, V, W) VD = 15V, VIN = 5V VDB = 15V, VIN = 0V VUFB-U (VUFS), VVFB-V (VVFS), VDB = 15V, VIN = 5V VWFB-W (VWFS) VSC = 0V, FO circuit : 1k to 5V pull-up VSC = 1V, IFO = -10mA VIN = 5V Tj = 25C, VD = 15V (Note 4) Trip level Reset level Tj 125C Trip level Reset level (Note 4) Applied between: UP, VP, WP-VNC, UN, VN, WN-VNC Min. -- -- -- -- 4.9 -- 0.70 0.43 10.0 10.5 10.3 10.8 20 2.10 1.10 Limits Typ. -- -- -- -- -- -- 1.06 0.48 -- -- -- -- 40 2.35 1.40 Max. 3.60 3.90 0.50 0.50 -- 0.95 1.50 0.53 12.0 12.5 12.5 13.0 -- 2.60 1.80 Unit mA mA mA mA V V mA V V V V V s V V
Note 4 : Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC triplevel is less than 5.1A Mar. 2004
MITSUBISHI SEMICONDUCTOR
PS21661-RZ/FR
TRANSFER-MOLD TYPE INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter Mounting torque Weight Heat-sink flatness Mounting screw : (M3) (Note 5) Condition Min. 0.59 -- -50 Limits Typ. 0.69 10 -- Max. 0.78 -- +100 Unit N*m g m
Note 5: Measurement point of heat-sink flatness
SIP-IPM +- Measurement Range 3mm
Heat-sink - + Heat-sink
RECOMMENDED OPERATION CONDITIONS
Symbol VCC VD VDB VD, VDB tdead fPWM IO VNC tXX Parameter Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time PWM input frequency Allowable r.m.s current VNC terminal voltage minimum on pulse width Condition Applied between P-N Applied between VN1-VNC Applied between VUFB-U (VUFS), VVFB-V (VVFS), VWFB-W (VWFS) Relates to corresponding input signal for blocking arm shoot-through Tj 125C, Tf 100C VCC = 300V, VD = 15V, fC = 15kHz, P.F = 0.8, sinusoidal Tj 125C, Tf 100C Applied between VNC-N (include surge voltage) UP, VP, WP, UN, VN, WN terminal Min. 0 13.5 13.0 -1 1.5 -- -- -5 0.7 Limits Typ. 300 15.0 15.0 -- -- 15 -- -- -- Max. 400 16.5 18.5 1 -- -- 1.5 5 -- Unit V V V V/s s kHz Arms V s
Mar. 2004
MITSUBISHI SEMICONDUCTOR
PS21661-RZ/FR
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 3 THE SIP-IPM INTERNAL CIRCUIT
U(VUFS) VUFB
SIP-IPM
P
VN1
VCC
VB HO VS
COM
UP UN
PIN NIN
FO
LO VNO N
CIN
V(VVFS) VVFB
VN1
VCC
VB HO VS
COM
VP VN
PIN NIN
FO
LO VNO
CIN
W(VWFS) VWFB
VN1 VNC WP WN
Fo CIN
VCC
VB HO VS
COM PIN NIN
FO
LO VNO
CIN
Mar. 2004
MITSUBISHI SEMICONDUCTOR
PS21661-RZ/FR
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 4 PS21661-RZ PACKAGE OUTLINES
q~#5 : pins numbers.
Terminals array
Terminal No Symbol N 1 P 2 FO 3 5 VNC 6 CIN 7 VN1 9 WN 10 VWFB 11 WP 12 W(VWFS) 15 17 18 19 20 23 25 26 27 28 VN1 VN VVFB VP V(VVFS) VN1 UN VUFB UP U(VUFS) Description Inverter DC-link negative (GND) terminal Inverter DC-link positive terminal Fault output terminal Control GND terminal Short-circuit trip voltage sensing terminal Control supply terminal W-phase N-side control input terminal W-phase P-side drive supply terminal W-phase P-side control input terminal W-phase inverter output terminal (W-phase P-side drive supply GND terminal) Control supply terminal V-phase N-side control input terminal V-phase P-side drive supply terminal V-phase P-side control input terminal V-phase inverter output terminal (V-phase P-side drive supply GND terminal) Control supply terminal U-phase N-side control input terminal U-phase P-side drive supply terminal U-phase P-side control input terminal U-phase inverter output terminal (U-phase P-side drive supply GND terminal)
qN Pw e FO t VNC CIN y u VN1 o WN VWFB !0 !1 WP M a r k i n g s i d e W(VWFS) !2
!5 VN1 !7 VN VVFB !8 !9 VP V(VVFS) @0
@3 VN1 @5 UN VUFB @6 @7 UP U(VUFS) @8
The following pins are dummy pins are therefore should not be connected. 4,8,13,14,16,21,22,24,29,30~35 (30~35 are the high voltage side pins.)
Fig. 5
Mar. 2004
MITSUBISHI SEMICONDUCTOR
PS21661-RZ/FR
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 6 PS21661-FR PACKAGE OUTLINES
q~#5 : pins numbers.
Terminals array
Terminal No Symbol N 1 P 2 FO 3 5 VNC 6 CIN 7 VN1 9 WN 10 VWFB 11 WP 12 W(VWFS) 15 17 18 19 20 23 25 26 27 28 VN1 VN VVFB VP V(VVFS) VN1 UN VUFB UP U(VUFS) Description Inverter DC-link negative (GND) terminal Inverter DC-link positive terminal Fault output terminal Control GND terminal Short-circuit trip voltage sensing terminal Control supply terminal W-phase N-side control input terminal W-phase P-side drive supply terminal W-phase P-side control input terminal W-phase inverter output terminal (W-phase P-side drive supply GND terminal) Control supply terminal V-phase N-side control input terminal V-phase P-side drive supply terminal V-phase P-side control input terminal V-phase inverter output terminal (V-phase P-side drive supply GND terminal) Control supply terminal U-phase N-side control input terminal U-phase P-side drive supply terminal U-phase P-side control input terminal U-phase inverter output terminal (U-phase P-side drive supply GND terminal)
qN Pw e FO t VNC CIN y u VN1 o WN VWFB !0 !1 WP M a r k i n g s i d e W(VWFS) !2
!5 VN1 !7 VN VVFB !8 !9 VP V(VVFS) @0
@3 VN1 @5 UN VUFB @6 @7 UP U(VUFS) @8
The following pins are dummy pins are therefore should not be connected. 4,8,13,14,16,21,22,24,29,30~35 (30~35 are the high voltage side pins.)
Fig. 7
Mar. 2004
MITSUBISHI SEMICONDUCTOR
PS21661-RZ/FR
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 8 TIMING CHARTS OF THE SIP-IPM PROTECTIVE FUNCTIONS [A] Short-Circuit Protection (Lower-arms only)
a1. Normal operation : IGBT ON and carrying current. a2. Short circuit current detection (SC trigger). a3. Hard IGBT gate interrupt. a4. IGBT turns OFF. a5. FO output (20~80s). a6. Input "L" : IGBT OFF state. a7. Input "H" : IGBT ON state, but during the FO active signal the IGBT doesn't turn ON. a8. IGBT OFF state.
Lower-arms control input Protection circuit state
a6
a7
SET
RESET
Internal IGBT gate
a2 SC a1
a3
a4 a8 SC reference voltage
Output current Ic Sense voltage of the shunt resistance
CR circuit time constant DELAY (Note)
Error output Fo
a5
Note : The CR time constant safe guards against erroneous SC signal resulting from di/dt generated voltages when IGBT turns ON. The optimum setting for the CR circuit time constant is 1.5~2.0s.
[B] Under-Voltage Protection (Lower-arms, UVD)
a1. Control supply voltage rises : After the voltage level reaches UVDr, the circuits start to operate when the next input is applied. a2. Normal operation : IGBT ON and carrying current. a3. Under voltage trip (UVDt). a4. IGBT OFF in spite of control input condition. a5. FO output (20~80s). a6. Under voltage reset (UVDr). a7. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state UVDBr
RESET
SET
RESET
Control supply voltage VD
a1
UVDBt a2
a6 a3 a4 a7
Output current Ic
Fault output Fo
a5
Mar. 2004
MITSUBISHI SEMICONDUCTOR
PS21661-RZ/FR
TRANSFER-MOLD TYPE INSULATED TYPE
[C] Under-Voltage Protection (Upper-arms, UVDB)
a1. Control supply voltage rises : After the voltage level reaches UVDBr, the circuits start to operate when the next input is applied. a2. Normal operation : IGBT ON and carrying current. a3. Under voltage trip (UVDBt). a4. IGBT OFF in spite of control input condition, but there is no FO signal output. a5. Under voltage reset (UVDBr). a6. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state
RESET UVDBr
SET
RESET
Control supply voltage VDB
a1
UVDBt a2
a5 a3 a4 a6
Output current Ic
High-level (no fault output)
Error output Fo
[D] Simultaneous input signal prevention function
a1 a3. Normal operation : IGBT ON and outputing IGBT gate voltage. a2 a4. Normal operation : IGBT ON and outputing IGBT gate voltage. a5. Abnormal pulse input. a6. IGBT OFF state. a7. No fault output.
Upper-arm control input
a1
a5
Lower-arm control input
a2
Internal upper-arm IGBT gate voltage
a3
a6
Internal lower-arm IGBT gate output
a4
SET Protection circuit state
RESET
Fault output
a7
Mar. 2004
MITSUBISHI SEMICONDUCTOR
PS21661-RZ/FR
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 9 TYPICAL SIP-IPM APPLICATION CIRCUIT EXAMPLE
R2
C2 C1
VUFB U(VUFS) IC1 VN1
VCC COM VB HO VS
SIP-IPM
P
C3
UP UN
PIN NIN FO CIN
LO VNO
N R2
C2 C1
A
VVFB IC2 VN1 CIN
VB
M
C3
R1 C4
VCC COM
HO VS
VP
PIN NIN FO CIN
N1
VN
LO VNO
5V line
R2
C2 C1
VWFB W(VWFS) IC3 VN1
VCC COM PIN NIN FO CIN CIN LO VNO VB HO VS
R3 C3
VNC WP WN FO
15V line
Note 1 : Input signal lines are pulled-down with 4.7k (min.) internal resistor. If these input lines are susceptible to noise, an RC coupling at each input is recommended. Input signal voltage is determined by the values of internal pull-down resistor and the external connected resistor. Set the external resistance value so that input signal voltage exceeds the on-threshold voltage. To prevent the input signals oscillation, the wiring of each input should be as short as possible. 2 : By virtue of integrating the specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. 3 : FO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 1k resistance. 4 : Approximately a 0.1~2F by-pass capacitor should be used across each power supply connection terminals. 5 : To prevent errors of the protection function, the wiring of A should be as short as possible. 6 : Each capacitor should be located as close to the pins of the SIP-IPM as possible. 7 : In the recommended protection circuit, please select the R1C4 time constant in the range of 1.5~2s. 8 : To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 pins should be as short as possible. Approximately a 0.1~0.22F snubber capacitor between the P&N1 pins is recommended.
Shunt resistor
V(VVFS)
CPU UNIT
Mar. 2004

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