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| LT3024 Dual 100mA/500mA Low Dropout, Low Noise, Micropower Regulator FEATURES n n n n n n n n n n n n n n DESCRIPTION The LT(R)3024 is a dual, micropower, low noise, low dropout regulator. With an external 0.01F bypass capacitor, output noise drops to 20VRMS over a 10Hz to 100kHz bandwidth. Designed for use in battery-powered systems, the low 30A quiescent current per output makes it an ideal choice. In shutdown, quiescent current drops to less than 0.1A. Shutdown control is independent for each output, allowing for flexibility in power management. The device is capable of operating over an input voltage range of 1.8V to 20V. The device can supply 100mA of output current from Output 2 with a dropout voltage of 300mV. Output 1 can supply 500mA of output current with a dropout voltage of 300mV. Quiescent current is well controlled in dropout. The LT3024 regulator is stable with output capacitors as low as 1F for the 100mA output and 3.3F for the 500mA output. Small ceramic capacitors can be used without the series resistance required by other regulators. Internal protection circuitry includes reverse-battery protection, current limiting, thermal limiting and reverse current protection. The device is available as an adjustable device with a 1.22V reference voltage. The LT3024 regulator is available in the thermally enhanced 16-lead TSSOP and 12-lead, low profile (4mm x 3mm x 0.75mm) DFN packages. Low Noise: 20VRMS (10Hz to 100kHz) Low Quiescent Current: 30A/Output Wide Input Voltage Range: 1.8V to 20V Output Current: 100mA/500mA Very Low Shutdown Current: <0.1A Low Dropout Voltage: 300mV at 100mA/500mA Adjustable Outputs from 1.22V to 20V Stable with 1F/3.3F Output Capacitor Stable with Aluminum, Tantalum or Ceramic Capacitors Reverse Battery Protected No Reverse Current No Protection Diodes Needed Overcurrent and Overtemperature Protected Thermally Enhanced 16-Lead TSSOP and 12-Lead (4mm x 3mm) DFN Packages APPLICATIONS n n n n n Cellular Phones Pagers Battery-Powered Systems Frequency Synthesizers Wireless Modems L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 3.3V/2.5V Low Noise Regulators IN VIN 3.7V TO 20V 1F SHDN1 SHDN2 BYP1 ADJ1 249k 2.5V AT 100mA 20VRMS NOISE VOUT 100V/DIV 20VRMS OUT1 0.01F 422k 10F 3.3V AT 500mA 20VRMS NOISE 10Hz to 100kHz Output Noise LT3024 OUT2 0.01F BYP2 ADJ2 GND 261k 10F 249k 3024 TA01a 3024 TA01b 3024fa 1 LT3024 ABSOLUTE MAXIMUM RATINGS (Note 1) IN Pin Voltage .........................................................20V OUT1, OUT2 Pin Voltage .........................................20V Input-to-Output Differential Voltage ........................20V ADJ1, ADJ2 Pin Voltage ............................................7V BYP1, BYP2 Pin Voltage ........................................0.6V SHDN1, SHDN2 Pin Voltage ...................................20V Output Short-Circut Duration ........................... Indefinite Operating Junction Temperature Range (Note 2) ............................................. -40C to 125C Storage Temperature Range FE Package ........................................ -65C to 150C DE Package ........................................ -65C to 125C Lead Temperature (Soldering, 10 sec) .................. 300C (FE package only) PIN CONFIGURATION TOP VIEW TOP VIEW BYP1 OUT1 OUT1 GND OUT2 BYP2 1 2 3 13 4 5 6 12 ADJ1 11 SHDN1 10 IN 9 8 7 IN SHDN2 ADJ2 GND BYP1 OUT1 OUT1 GND OUT2 BYP2 GND DE12 PACKAGE 12-LEAD (4mm 3mm) PLASTIC DFN TJMAX = 150C, JA = 40C/W, JC = 10C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB 1 2 3 4 5 6 7 8 17 16 GND 15 ADJ1 14 SHDN1 13 IN 12 IN 11 SHDN2 10 ADJ2 9 GND FE PACKAGE 16-LEAD PLASTIC TSSOP TJMAX = 150C, JA = 38C/W, JC = 8C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LT3024EDE#PBF LT3024IDE#PBF LT3024EFE#PBF LT3024IFE#PBF LEAD BASED FINISH LT3024EDE LT3024IDE LT3024EFE LT3024IFE TAPE AND REEL LT3024EDE#TRPBF LT3024IDE#TRPBF LT3024EFE#TRPBF LT3024IFE#TRPBF TAPE AND REEL LT3024EDE#TR LT3024IDE#TR LT3024EFE#TR LT3024IFE#TR PART MARKING* 3024 3024 3024EFE 3024IFE PART MARKING* 3024 3024 3024EFE 3024IFE PACKAGE DESCRIPTION 12-Lead (4mm x 3mm) Plastic DFN 12-Lead (4mm x 3mm) Plastic DFN 16-Lead Plastic TSSOP 16-Lead Plastic TSSOP PACKAGE DESCRIPTION 12-Lead (4mm x 3mm) Plastic DFN 12-Lead (4mm x 3mm) Plastic DFN 16-Lead Plastic TSSOP 16-Lead Plastic TSSOP TEMPERATURE RANGE -40C to 125C -40C to 125C -40C to 125C -40C to 125C TEMPERATURE RANGE -40C to 125C -40C to 125C -40C to 125C -40C to 125C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3024fa 2 LT3024 ELECTRICAL CHARACTERISTICS PARAMETER Minimum Input Voltage (Notes 3, 11) ADJ1, ADJ2 Pin Voltage (Note 3, 4) Line Regulation (Note 3) Load Regulation (Note 3) CONDITIONS Output 2, ILOAD = 100mA Output 1, ILOAD = 500mA VIN = 2V, ILOAD = 1mA Output 2, 2.3V < VIN < 20V, 1mA < ILOAD < 100mA Output 1, 2.3V < VIN < 20V, 1mA < ILOAD < 500mA VIN = 2V to 20V, ILOAD = 1mA Output 2, VIN = 2.3V, ILOAD = 1mA to 100mA VIN = 2.3V, ILOAD = 1mA to 100mA Output 1, VIN = 2.3V, ILOAD = 1mA to 500mA VIN = 2.3V, ILOAD = 1mA to 500mA Dropout Voltage (Output 2) VIN = VOUT(NOMINAL) (Notes 5, 6, 11) ILOAD = 1mA ILOAD = 1mA ILOAD = 10mA ILOAD = 10mA ILOAD = 50mA ILOAD = 50mA ILOAD = 100mA ILOAD = 100mA Dropout Voltage (Output 1) VIN = VOUT(NOMINAL) (Notes 5, 6, 11) ILOAD = 10mA ILOAD = 10mA ILOAD = 50mA ILOAD = 50mA ILOAD = 100mA ILOAD = 100mA ILOAD = 500mA ILOAD = 500mA GND Pin Current (Output 2) VIN = VOUT(NOMINAL) (Notes 5, 7) ILOAD = 0mA ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA ILOAD = 100mA ILOAD = 0mA ILOAD = 1mA ILOAD = 50mA ILOAD = 100mA ILOAD = 250mA ILOAD = 500mA COUT = 10F CBYP = 0.01F ILOAD = Full Current, , , BW = 10Hz to 100kHz ADJ1, ADJ2 (Notes 3, 8) VOUT = Off to On VOUT = On to Off VSHDN1, VSHDN2 = 0V VSHDN1, VSHDN2 = 20V VIN = 6V, VSHDN1 = 0V, VSHDN2 = 0V VIN = 2.72V (Avg), VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz, ILOAD = Full Current 55 l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2) MIN TYP 1.8 1.8 1.205 1.190 1.190 1.220 1.220 1.220 1 1 1 0.10 0.17 0.24 0.30 0.13 0.17 0.20 0.30 20 55 230 1 2.2 30 65 1.1 2 5 11 20 30 0.25 0.8 0.65 0 1 0.01 65 100 1.4 0.5 3 0.1 MAX 2.3 2.3 1.235 1.250 1.250 10 12 25 12 25 0.15 0.19 0.22 0.29 0.31 0.40 0.35 0.45 0.19 0.25 0.22 0.32 0.34 0.44 0.35 0.45 45 90 400 2 4 75 120 1.6 3 8 16 UNITS V V V V V mV mV mV mV mV V V V V V V V V V V V V V V V V A A A mA mA A A mA mA mA mA VRMS nA V V A A A dB GND Pin Current (Output 1) VIN = VOUT(NOMINAL) (Notes 5, 7) Output Voltage Noise ADJ Pin Bias Current Shutdown Threshold SHDN1/SHDN2 Pin Current (Note 9) Quiescent Current in Shutdown Ripple Rejection 3024fa 3 LT3024 ELECTRICAL CHARACTERISTICS PARAMETER Current Limit CONDITIONS Output 2, VIN = 7V, VOUT = 0V VIN = 2.3V, VOUT = -0.1V Output 1, VIN = 7V, VOUT = 0V VIN = 2.3V, VOUT = -0.1V Input Reverse Leakage Current VIN = -20V, VOUT = 0V Reverse Output Current (Notes 3,10) VOUT = 1.22V, VIN < 1.22V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3024 is tested and specified under pulse load conditions such that TJ TA. The LT3024E is 100% tested at TA = 25C. Performance at - 40C and 125C is assured by design, characterization and correlation with statistical process controls. The LT3024I is guaranteed over the full -40C to 125C operating junction temperature range. Note 3: The LT3024 is tested and specified for these conditions with the ADJ1/ADJ2 pin connected to the corresponding OUT1/OUT2 pin. Note 4: Operating conditions are limited by maximum junction temperature. The regulated output voltage specification will not apply for all possible combinations of input voltage and output current. When operating at maximum input voltage, the output current range must be limited. When operating at maximum output current, the input voltage range must be limited. Note 5: To satisfy requirements for minimum input voltage, the LT3024 is tested and specified for these conditions with an external resistor divider (two 250k resistors) for an output voltage of 2.44V. The external resistor divider will add a 5A DC load on the output. l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2) MIN 110 700 520 1 5 10 TYP 200 MAX UNITS mA mA mA mA mA A Note 6: Dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output current. In dropout, the output voltage will be equal to: VIN - VDROPOUT. Note 7: GND pin current is tested with VIN = 2.44V and a current source load. This means the device is tested while operating in its dropout region or at the minimum input voltage specification. This is the worst-case GND pin current. The GND pin current will decrease slightly at higher input voltages. Total GND pin current is equal to the sum of GND pin currents from Output 1 and Output 2. Note 8: ADJ1 and ADJ2 pin bias current flows into the pin. Note 9: SHDN1 and SHDN2 pin current flows into the pin. Note 10: Reverse output current is tested with the IN pin grounded and the OUT pin forced to the rated output voltage. This current flows into the OUT pin and out the GND pin. Note 11: For the LT3024 dropout voltage will be limited by the minimum input voltage specification under some output voltage/load conditions. See the curve of Minimum Input Voltage in the Typical Performance Characteristics. 3024fa 4 LT3024 TYPICAL PERFORMANCE CHARACTERISTICS Output 2 Typical Dropout Voltage 500 450 DROPOUT VOLTAGE (mV) DROPOUT VOLTAGE (mV) 400 350 300 250 200 150 100 50 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT CURRENT (mA) 3024 G01 Output 2 Guaranteed Dropout Voltage 500 450 DROPOUT VOLTAGE (mV) 400 350 300 250 200 150 100 50 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT CURRENT (mA) 3024 G02 Output 2 Dropout Voltage 500 450 400 350 300 250 200 150 100 50 0 -50 -25 IL = 50mA IL = 10mA IL = 1mA IL = 100mA = TEST POINTS TJ = 125C TJ 125C TJ 25C TJ = 25C 50 25 0 75 TEMPERATURE (C) 100 125 3024 G03 Output 1 Typical Dropout Voltage 500 GUARANTEED DROPOUT VOLTAGE (mV) 450 DROPOUT VOLTAGE (mV) 400 350 300 250 200 150 100 50 0 0 50 100 150 200 250 300 350 400 450 500 OUTPUT CURRENT (mA) 3024 G04 Output 1 Guaranteed Dropout Voltage 500 450 DROPOUT VOLTAGE (mV) 400 350 300 250 200 150 100 50 0 0 50 100 150 200 250 300 350 400 450 500 OUTPUT CURRENT (mA) 3024 G05 Output 1 Dropout Voltage 500 450 400 350 300 250 200 150 100 50 0 -50 -25 IL = 10mA 50 25 0 75 TEMPERATURE (C) IL = 1mA IL = 50mA IL = 250mA IL = 100mA IL = 500mA = TEST POINTS TJ = 125C TJ 125C TJ 25C TJ = 25C 100 125 3024 G06 Quiescent Current (Per Output) 50 45 QUIESCENT CURRENT (A) 40 35 30 25 20 15 10 5 VIN = 6V RL = 250k, IL = 5A 0 0 25 -50 -25 1.205 50 75 100 125 VSHDN = VIN ADJ PIN VOLTAGE (V) 1.240 1.235 1.230 1.225 1.220 1.215 1.210 ADJ1 or ADJ2 Pin Voltage IL = 1mA 1.200 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) 3024 G07 TEMPERATURE (C) 3024 G08 3024fa 5 LT3024 TYPICAL PERFORMANCE CHARACTERISTICS Quiescent Current (Per Output) 40 TJ = 25C 35 RL = 250k QUIESCENT CURRENT (A) GND PIN CURRENT (mA) 30 25 20 15 10 5 0 0 2 4 VSHDN = 0V 6 8 10 12 14 16 18 20 INPUT VOLTAGE (V) 3024 G09 Output 2 GND Pin Current 2.50 2.25 TJ = 25C *FOR VOUT = 1.22V GND PIN CURRENT (mA) RL = 12.2 IL = 100mA* 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 0 1 2 34567 INPUT VOLTAGE (V) 8 9 10 Output 2 GND Pin Current vs ILOAD VIN = VOUT(NOMINAL) + 1V VSHDN = VIN 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 RL = 24.4 IL = 50mA* RL = 1.22k IL = 1mA* RL = 122 IL = 10mA* 0 10 20 30 40 50 60 70 80 90 100 OUTPUT CURRENT (mA) 3024 G11 3024 G10 Output 1 GND Pin Current 1200 1000 GND PIN CURRENT (A) 800 600 400 200 0 RL = 122 IL = 10mA* RL = 1.22k IL = 1mA* 0 1 2 34567 INPUT VOLTAGE (V) 8 9 10 TJ = 25C VIN = VSHDN *FOR VOUT = 1.22V RL = 24.4 IL = 50mA* 12 10 GND PIN CURRENT (mA) 8 6 4 2 0 Output 1 GND Pin Current 12 TJ = 25C VIN = VSHDN *FOR VOUT = 1.22V RL = 2.44 IL = 500mA* RL = 4.07 IL = 300mA* GND PIN CURRENT (mA) 10 8 6 4 2 0 Output 1 GND Pin Current vs ILOAD VIN = VOUT(NOMINAL) + 1V RL = 12.2 IL = 100mA* 0 1 2 34567 INPUT VOLTAGE (V) 8 9 10 0 50 100 150 200 250 300 350 400 450 500 OUTPUT CURRENT (mA) 3024 G14 3024 G12 3024 G13 SHDN1 or SHDN2 Pin Threshold (On-to-Off) 1.0 0.9 SHDN PIN THRESHOLD (V) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 IL = 1mA SHDN PIN THRESHOLD (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 SHDN1 or SHDN2 Pin Threshold (Off-to-On) IL = FULL IL = 1mA 0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 3024 G15 3024 G16 3024fa 6 LT3024 TYPICAL PERFORMANCE CHARACTERISTICS SHDN1 or SHDN2 Pin Input Current 1.0 0.9 SHDN PIN INPUT CURRENT (A) SHDN PIN INPUT CURRENT (A) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 345678 SHDN PIN VOLTAGE (V) 9 10 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 ADJ PIN BIAS CURRENT (nA) 50 25 0 75 TEMPERATURE (C) 125 SHDN1 or SHDN2 Pin Input Current VSHDN = 20V 100 90 80 70 60 50 40 30 20 10 -25 100 ADJ1 or ADJ2 Pin Bias Current 0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 3024 G17 3024 G18 3024 G19 Output 2 Current Limit 350 SHORT-CIRCUIT CURRENT (mA) 300 250 200 150 100 50 0 0 1 VOUT = 0V TJ = 25C CURRENT LIMIT (mA) 350 300 250 200 150 100 50 Output 2 Current Limit VIN = 7V VOUT = 0V 1.0 0.9 0.8 CURRENT LIMIT (A) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 -25 50 25 0 75 TEMPERATURE (C) 100 125 0 Output 1 Current Limit VOUT = 0V 4 3 2 5 INPUT VOLTAGE (V) 6 7 3024 G20 0 -50 0 1 4 3 2 5 INPUT VOLTAGE (V) 6 7 3024 G22 3024 G21 Output 1 Current Limit 1.2 1.0 CURRENT LIMIT (A) 0.8 0.6 0.4 0.2 0 -50 REVERSE OUTPUT CURRENT (A) VIN = 7V VOUT = 0V 100 Reverse Output Current TA = 25C 90 VIN = 0V = VADJ V 80 OUT CURRENT FLOWS 70 INTO OUTPUT PIN 60 50 40 30 20 10 -25 50 25 0 75 TEMPERATURE (C) 100 125 0 0 1 2 345678 OUTPUT VOLTAGE (V) 9 10 3024 G23 3024 G24 3024fa 7 LT3024 TYPICAL PERFORMANCE CHARACTERISTICS Reverse Output Current 18 REVERSE OUTPUT CURRENT (A) 15 12 9 6 3 0 -50 -25 VIN = 0V VOUT = VADJ = 1.22V RIPPLE REJECTION (dB) 80 70 RIPPLE REJECTION (dB) 60 50 COUT = 10F 40 30 20 COUT = 1F Output 2 Input Ripple Rejection 80 70 60 50 40 30 20 Output 2 Input Ripple Rejection CBYP = 0.01F CBYP = 1000pF CBYP = 100pF 50 25 75 0 TEMPERATURE (C) 100 125 IL = 100mA 10 V = 2.3V + 50mV IN RMS RIPPLE CBYP = 0 0 0.1 0.01 1 10 FREQUENCY (kHz) 100 1000 3024 G26 IL = 100mA 10 V = 2.3V + 50mV IN RMS RIPPLE COUT = 10F 0 0.1 0.01 1 10 FREQUENCY (kHz) 100 1000 3024 G27 3024 G25 Output 2 Input Ripple Rejection 80 70 RIPPLE REJECTION (dB) RIPPLE REJECTION (dB) 60 50 40 30 20 VIN = VOUT (NOMINAL) + 1V + 0.5VP-P RIPPLE 10 AT f = 120Hz IL = 50mA 0 0 50 25 -50 -25 80 70 Output 1 Input Ripple Rejection 80 Output 1 Input Ripple Rejection 70 CBYP = 0.01F RIPPLE REJECTION (dB) 60 50 CBYP = 1000pF 40 30 20 I = 500mA L VIN = VOUT(NOMINAL) + 10 1V + 50mVRMS RIPPLE COUT = 10F 0 100 10 1k 10k FREQUENCY (Hz) CBYP = 100pF 60 50 40 30 20 I = 500mA L COUT = 4.7F VIN = VOUT(NOMINAL) + 10 1V + 50mV RMS RIPPLE CBYP = 0 0 100 100k 10 1k 10k 1M FREQUENCY (Hz) 3024 G29 COUT = 10F 75 100 125 100k 1M 3024 G30 TEMPERATURE (C) 3024 G28 Output 1 Ripple Rejection 68 66 MINIMUM INPUT VOLTAGE (V) RIPPLE REJECTION (dB) 64 62 60 58 56 54 VIN = VOUT (NOMINAL) + 1V + 0.5VP-P RIPPLE AT f = 120Hz IL = 500mA -25 0 25 50 75 100 125 TEMPERATURE (C) 3024 G31 Output 2 Minimum Input Voltage 2.5 VOUT = 1.22V 2.0 IL = 100mA 1.5 IL = 50mA 1.0 0.5 52 -50 0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 3024 G32 3024fa 8 LT3024 TYPICAL PERFORMANCE CHARACTERISTICS Output 1 Minimum Input Voltage 2.50 2.25 MINIMUM INPUT VOLTAGE (V) 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 IL = 1mA IL = 500mA CHANNEL-TO-CHANNEL ISOLATION (dB) VOUT = 1.22V 100 90 80 70 CHANNEL 1 60 50 40 30 GIVEN CHANNEL IS TESTED WITH 50mVRMS SIGNAL ON OPPOSING CHANNEL, BOTH 10 CHANNELS DELIVERING FULL CURRENT 0 100 1k 10k 10 FREQUENCY (Hz) 20 VOUT2 20mV/DIV CHANNEL 2 VOUT1 20mV/DIV Channel-to-Channel Isolation Channel-to-Channel Isolation 100k 1M 3024 G34 3024 G33 50s/DIV COUT1 = 22F COUT2 = 10F CBYP1 = CBYP2 = 0.01F IL1 = 50mA TO 500mA IL2 = 10mA TO 100mA VIN = 6V, VOUT1 = VOUT2 = 5V 3024 G50 Output 2 Load Regulation 0 -1 LOAD REGULATION (mV) LOAD REGULATION (mV) -2 -3 -4 -5 -6 -7 -8 -9 IL = 1mA TO 100mA -10 0 50 75 -50 -25 25 TEMPERATURE (C) 5 Output 1 Load Regulation IL = 1mA TO 500mA OUTPUT NOISE SPECTRAL DENSITY (V/Hz) 10 Output Noise Spectral Density COUT = 10F CBYP = 0 IL = FULL LOAD VOUT SET FOR 5V VOUT =VADJ 0.1 0 1 -5 100 125 -10 -50 -25 0 25 50 75 100 125 0.01 0.01 0.1 TEMPERATURE (C) 3024 G35 3024 G36 1 10 FREQUENCY (kHz) 100 3024 G37 Output Noise Spectral Density OUTPUT NOISE SPECTRAL DENSITY (V/Hz) 10 COUT = 10F IL = FULL LOAD OUTPUT NOISE (VRMS) VOUT SET FOR 5V 1 CBYP = 1000pF CBYP = 100pF VOUT =VADJ 0.1 CBYP = 0.01F 140 120 100 RMS Output Noise vs Bypass Capacitor VOUT = 5V COUT = 10F IL = FULL LOAD fBW = 10Hz TO 100kHz CHANNEL 2 80 CHANNEL 1 60 40 CHANNEL 1 20 VOUT = 1.22V CHANNEL 2 0.01 0.01 0 0.1 1 10 FREQUENCY (kHz) 100 3023 G38 10 100 CBYP (pF) 1000 10000 3024 G39 3024fa 9 LT3024 TYPICAL PERFORMANCE CHARACTERISTICS Output 2 RMS Output Noise vs Load Current (10Hz to 100kHz) 160 COUT = 10F CBYP = 0F 140 CBYP = 0.01F OUTPUT NOISE (VRMS) VOUT SET FOR 5V OUTPUT NOISE (VRMS) 120 100 80 60 40 20 0 0.01 VOUT SET FOR 5V VOUT =VADJ 0.1 1 10 LOAD CURRENT (mA) 100 3024 G40 Output 1 RMS Output Noise vs Load Current (10Hz to 100kHz) 160 140 120 VOUT SET FOR 5V 100 80 60 40 20 0 0.01 0.1 VOUT SET FOR 5V VOUT = VADJ 10 100 1 LOAD CURRENT (mA) 1000 3024 G41 10Hz to 100kHz Output Noise CBYP = 0pF COUT = 10F CBYP = 0 CBYP = 0.01F VOUT 100V/DIV VOUT =VADJ VOUT = VADJ 1ms/DIV COUT = 10F IL = 100mA VOUT SET FOR 5V 3024 G42 10Hz to 100kHz Output Noise CBYP = 100pF 10Hz to 100kHz Output Noise CBYP = 1000pF 10Hz to 100kHz Output Noise CBYP = 0.01F VOUT 100V/DIV VOUT 100V/DIV VOUT 100V/DIV 1ms/DIV COUT = 10F IL = 100mA VOUT SET FOR 5V 3024 G43 1ms/DIV COUT = 10F IL = 100mA VOUT SET FOR 5V 3024 G44 1ms/DIV COUT = 10F IL = 100mA VOUT SET FOR 5V 3024 G45 3024fa 10 LT3024 TYPICAL PERFORMANCE CHARACTERISTICS Output 2 Transient Response CBYP = 0pF OUTPUT VOLTAGE DEVIATION (V) OUTPUT VOLTAGE DEVIATION (V) VIN = 6V, VOUT SET FOR 5V 0.2 CIN = 10F COUT = 10F 0.1 0 -0.1 -0.2 Output 2 Transient Response CBYP = 0.01F VIN = 6V, VOUT SET FOR 5V 0.04 CIN = 10F COUT = 10F 0.02 0 -0.02 -0.04 LOAD CURRENT (mA) 100 50 0 0 400 800 1200 TIME (s) 1600 2000 3024 G46 LOAD CURRENT (mA) 100 50 0 0 20 40 60 80 100 120 140 160 180 200 TIME (s) 3024 G47 Output 1 Transient Response CBYP = 0pF OUTPUT VOLTAGE DEVIATION (V) OUTPUT VOLTAGE DEVIATION (V) VIN = 6V, VOUT SET FOR 5V 0.4 CIN = 10F COUT = 10F 0.2 0 -0.2 -0.4 Output 1 Transient Response CBYP = 0.01F VIN = 6V, VOUT SET FOR 5V 0.10 CIN = 10F COUT = 10F 0.05 0 -0.05 -0.10 LOAD CURRENT (mA) 600 400 200 0 0 200 400 600 TIME (s) 800 1000 3024 G48 LOAD CURRENT (mA) 600 400 200 0 0 10 20 30 40 50 60 70 80 90 100 TIME (s) 3024 G49 3024fa 11 LT3024 PIN FUNCTIONS (DFN/TSSOP) GND (Pins 4, 13)/(Pins 1, 5, 8, 9, 16, 17): Ground. The Exposed Pad must be soldered to PCB ground for optimum thermal performance. ADJ1/ADJ2 (Pins 12/7)/(Pins 15/10): Adjust Pin. These are the input to the error amplifiers. These pins are internally clamped to 7V. They have a bias current of 30nA which flows into the pin (see curve of ADJ1/ADJ2 Pin Bias Current vs Temperature in the Typical Performance Characteristics section). The ADJ1 and ADJ2 pin voltage is 1.22V referenced to ground and the output voltage range is 1.22V to 20V. BYP1/BYP2 (Pins 1/6)/(Pins 2/7): Bypass. The BYP1/ BYP2 pins are used to bypass the reference of the LT3024 regulator to achieve low noise performance from the regulator. The BYP1/BYP2 pins are clamped internally to 0.6V (one VBE) from ground. A small capacitor from the corresponding output to this pin will bypass the reference to lower the output voltage noise. A maximum value of 0.01F can be used for reducing output voltage noise to a typical 20VRMS over a 10Hz to 100kHz bandwidth. If not used, this pin must be left unconnected. OUT1/OUT2 (Pins 2, 3/5)/(Pins 3, 4/6): Output. The outputs supply power to the loads. A minimum output capacitor of 1F is required to prevent oscillations on Output 2; Output 1 requires a minimum of 3.3F Larger output capacitors . will be required for applications with large transient loads to limit peak voltage transients. See the Applications Information section for more information on output capacitance and reverse output characteristics. SHDN1/SHDN2 (Pins 11/8)/(Pins 14/11): Shutdown. The SHDN1/SHDN2 pins are used to put the corresponding output of the LT3024 regulator into a low power shutdown state. The output will be off when the pin is pulled low. The SHDN1/SHDN2 pins can be driven either by 5V logic or open-collector logic with pull-up resistors. The pull-up resistors are required to supply the pull-up current of the open-collector gates, normally several microamperes, and the SHDN1/SHDN2 pin current, typically 1A. If unused, the pin must be connected to VIN. The device will not function if the SHDN1/SHDN2 pins are not connected. IN (Pins 9, 10)/(Pins 12, 13): Input. Power is supplied to the device through the IN pin. A bypass capacitor is required on this pin if the device is more than six inches away from the main input filter capacitor. In general, the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in batterypowered circuits. A bypass capacitor in the range of 1F to 10F is sufficient. The LT3024 regulator is designed to withstand reverse voltages on the IN pin with respect to ground and the OUT pin. In the case of a reverse input, which can happen if a battery is plugged in backwards, the device will act as if there is a diode in series with its input. There will be no reverse current flow into the regulator and no reverse voltage will appear at the load. The device will protect both itself and the load. 3024fa 12 LT3024 APPLICATIONS INFORMATION The LT3024 is a dual 100mA/500mA low dropout regulator with micropower quiescent current and shutdown. The device is capable of supplying 100mA from Output 2 at a dropout voltage of 300mV. Output 1 delivers 500mA at a dropout voltage of 300mV. The two regulators have common VIN and GND pins and are thermally coupled, however, the two outputs of the LT3024 operate independently. They can be shut down independently and a fault condition on one output will not affect the other output electrically. Output voltage noise can be lowered to 20VRMS over a 10Hz to 100kHz bandwidth with the addition of a 0.01F reference bypass capacitor. Additionally, the reference bypass capacitor will improve transient response of the regulator, lowering the settling time for transient load conditions. The low operating quiescent current (30A per output) drops to less than 1A in shutdown. In addition to the low quiescent current, the LT3024 regulator incorporates several protection features which make it ideal for use in battery-powered systems. The device is protected against both reverse input and reverse output voltages. In battery backup applications where the output can be held up by a backup battery when the input is pulled to ground, the LT3024 acts like it has a diode in series with its output and prevents reverse current flow. Additionally, in dual supply applications where the regulator load is returned to a negative supply, the output can be pulled below ground by as much as 20V and still allow the device to start and operate. Adjustable Operation The LT3024 has an output voltage range of 1.22V to 20V. The output voltage is set by the ratio of two external resistors as shown in Figure 1. The device servos the output to maintain the corresponding ADJ pin voltage at 1.22V referenced to ground. The current in R1 is then equal to 1.22V/R1 and the current in R2 is the current in R1 plus the ADJ pin bias current. The ADJ pin bias current, 30nA at 25C, flows through R2 into the ADJ pin. The output voltage can be calculated using the formula in Figure 1. The IN VIN OUT1/OUT2 VOUT + LT3024 ADJ1/ADJ2 GND R1 3024 F01 R2 R2 VOUT = 1.22V 1 + + IADJ R2 R1 VADJ = 1.22V IADJ = 30nA AT 25C ( )( ) OUTPUT RANGE = 1.22V TO 20V Figure 1. Adjustable Operation value of R1 should be no greater than 250k to minimize errors in the output voltage caused by the ADJ pin bias current. Note that in shutdown the output is turned off and the divider current will be zero. Curves of ADJ Pin Voltage vs Temperature and ADJ Pin Bias Current vs Temperature appear in the Typical Performance Characteristics. The device is tested and specified with the ADJ pin tied to the corresponding OUT pin for an output voltage of 1.22V. Specifications for output voltages greater than 1.22V will be proportional to the ratio of the desired output voltage to 1.22V: VOUT/1.22V. For example, load regulation on Output 2 for an output current change of 1mA to 100mA is -1mV typical at VOUT = 1.22V. At VOUT = 12V, load regulation is: (12V/1.22V)(-1mV) = -9.8mV Bypass Capacitance and Low Noise Performance The LT3024 regulator may be used with the addition of a bypass capacitor from VOUT to the corresponding BYP pin to lower output voltage noise. A good quality low leakage capacitor is recommended. This capacitor will bypass the reference of the regulator, providing a low frequency noise pole. The noise pole provided by this bypass capacitor will lower the output voltage noise to as low as 20VRMS with the addition of a 0.01F bypass capacitor. Using a bypass capacitor has the added benefit of improving transient response. With no bypass capacitor and a 10F output capacitor, a 10mA to 100mA load step on Output 2 will settle to within 1% of its final value in less than 100s. With the addition of a 0.01F bypass capacitor, the output will stay 3024fa 13 LT3024 APPLICATIONS INFORMATION within 1% for the same load step. Both outputs exhibit this improvement in transient response (see Transient Reponse in Typical Performance Characteristics section). However, regulator start-up time is proportional to the size of the bypass capacitor, slowing to 15ms with a 0.01F bypass capacitor and 10F output capacitor. Output Capacitance and Transient Response The LT3024 regulator is designed to be stable with a wide range of output capacitors. The ESR of the output capacitor affects stability, most notably with small capacitors. A minimum output capacitor of 1F with an ESR of 3 or less is recommended for Output 2 to prevent oscillations. A minimum output capacitor of 3.3F with an ESR of 3 or less is recommended for Output 1. The LT3024 is a micropower device and output transient response will be a function of output capacitance. Larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. Bypass capacitors, used to decouple individual components powered by the LT3024, will increase the effective output capacitor value. With larger capacitors used to bypass the reference (for low noise operation), larger values of output capacitors are needed. For 100pF of bypass capacitance on Output 2, 2.2F of output capacitor is recommended. With a 330pF bypass capacitor or larger on this output, a 3.3F output capacitor is recommended. For Output 1, 4.7F of output capacitor is recommended for 100pF of bypass capacitance. With 1000pF or larger bypass capacitor on this output, a 6.8F output capacitor is recommended. The 4.0 3.5 3.0 STABLE REGION 2.5 ESR () 2.0 1.5 1.0 0.5 0 1 3 2 4 5 6 7 8 9 10 OUTPUT CAPACITANCE (F) 3024 F02 shaded region of Figures 2 and 3 define the regions over which the LT3024 regulator is stable. The minimum ESR needed is defined by the amount of bypass capacitance used, while the maximum ESR is 3. Extra consideration must be given to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics used are specified with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are good for providing high capacitances in a small package, but they tend to have strong voltage and temperature coefficients as shown in Figures 4 and 5. When used with a 5V regulator, a 16V 10F Y5V capacitor can exhibit an effective value as low as 1F to 2F for the DC bias voltage applied and over the operating temperature range. The X5R and X7R dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and is available in higher values. Care still must be exercised when using X5R and X7R capacitors; the X5R and X7R codes only specify operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC bias with X5R and X7R capacitors is better than Y5V and Z5U capacitors, but can still be significant enough to drop capacitor values below appropriate levels. Capacitor DC bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be verified. 4.0 3.5 3.0 STABLE REGION 2.5 ESR () 2.0 1.5 1.0 0.5 0 1 3 2 4 5 6 7 8 9 10 OUTPUT CAPACITANCE (F) 3024 F03 CBYP = 0 CBYP = 100pF CBYP = 330pF CBYP > 3300pF CBYP = 0 CBYP = 100pF CBYP = 330pF CBYP 1000pF Figure 2. Output 2 Stability Figure 3. Output 1 Stability 3024fa 14 LT3024 APPLICATIONS INFORMATION 20 0 CHANGE IN VALUE (%) CHANGE IN VALUE (%) X5R -20 -40 -60 Y5V -80 -100 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10F 40 20 0 -20 -40 -60 -80 Y5V X5R 0 2 4 8 6 10 12 DC BIAS VOLTAGE (V) 14 16 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10F -100 50 25 75 -50 -25 0 TEMPERATURE (C) 100 125 3024 F04 3024 F05 Figure 4. Ceramic Capacitor DC Bias Characteristics Figure 5. Ceramic Capacitor Temperature Characteristics Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or microphone works. For a ceramic capacitor the stress can be induced by vibrations in the system or thermal transients. The resulting voltages produced can cause appreciable amounts of noise, especially when a ceramic capacitor is used for noise bypassing. A ceramic capacitor produced Figure 6's trace in response to light tapping from a pencil. Similar vibration induced behavior can masquerade as increased output voltage noise. COUT = 10F CBYP = 0.01F ILOAD = 100mA Thermal Considerations The power handling capability of the device will be limited by the maximum rated junction temperature (125C). The power dissipated by the device will be made up of two components for each output: 1. Output current multiplied by the input/output voltage differential: (IOUT)(VIN - VOUT), and 2. GND pin current multiplied by the input voltage: (IGND)(VIN). The ground pin current can be found by examining the GND Pin Current curves in the Typical Performance Characteristics section. Power dissipation will be equal to the sum of the two components listed above. The LT3024 regulator has internal thermal limiting designed to protect the device during overload conditions. For continuous normal conditions, the maximum junction temperature rating of 125C must not be exceeded. It is important to give careful consideration to all sources of thermal resistance from junction to ambient. Additional heat sources mounted nearby must also be considered. VOUT 500V/DIV 100ms/DIV 3024 F06 Figure 6. Noise Resulting from Tapping on a Ceramic Capacitor For surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the PC board 3024fa 15 LT3024 APPLICATIONS INFORMATION and its copper traces. Copper board stiffeners and plated through-holes can also be used to spread the heat generated by power devices. The following tables list thermal resistance for several different board sizes and copper areas. All measurements were taken in still air on 3/32" FR-4 board with one ounce copper. Table 1. FE Package, 16-Lead TSSOP COPPER AREA TOPSIDE* 2500mm2 1000mm2 225mm2 100mm2 BACKSIDE 2500mm2 2500mm2 2500mm2 2500mm2 THERMAL RESISTANCE BOARD AREA (JUNCTION-TO-AMBIENT) 2500mm2 2500mm2 2500mm2 2500mm2 38C/W 43C/W 48C/W 60C/W The power dissipated by each output will be equal to: IOUT(MAX)(VIN(MAX) - VOUT) + IGND(VIN(MAX)) Where for Output 1: IOUT(MAX) = 500mA VIN(MAX) = 5V IGND at (IOUT = 500mA, VIN = 5V) = 9mA For Output 2: IOUT(MAX) = 100mA VIN(MAX) = 5V IGND at (IOUT = 100mA, VIN = 5V) = 2mA So for Output 1: P = 500mA (5V - 3.3V) + 9mA (5V) = 0.90W For Output 2: P = 100mA (5V - 2.5V) + 2mA (5V) = 0.26W The thermal resistance will be in the range of 35C/W to 55C/W depending on the copper area. So the junction temperature rise above ambient will be approximately equal to: (0.90W + 0.26W) 50C/W = 57.8C The maximum junction temperature will then be equal to the maximum junction temperature rise above ambient plus the maximum ambient temperature or: TJMAX = 50C + 57.8C = 107.8C Protection Features The LT3024 regulator incorporates several protection features which make it ideal for use in battery-powered circuits. In addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the device is protected against reverse input voltages, reverse output voltages and reverse voltages from output to input. The two regulators have common *Device is mounted on topside. Table 2. UE Package, 12-Lead DFN COPPER AREA TOPSIDE* 2500mm2 1000mm2 225mm2 100mm2 BACKSIDE 2500mm2 2500mm2 2500mm2 2500mm2 THERMAL RESISTANCE BOARD AREA (JUNCTION-TO-AMBIENT) 2500mm2 2500mm2 2500mm2 2500mm2 40C/W 45C/W 50C/W 62C/W *Device is mounted on topside. The thermal resistance junction-to-case (JC), measured at the Exposed Pad on the back of the die is 10C/W for the DFN package and 8C/W for the TSSOP package. Calculating Junction Temperature Example: Given Output 1 set for an output voltage of 3.3V, Output 2 set for an output voltage of 2.5V, an input voltage range of 3.8V to 5V, an output current range of 0mA to 500mA for Output 1, an output current range of 0mA to 100mA for Output 2 and a maximum ambient temperature of 50C, what will the maximum junction temperature be? 3024fa 16 LT3024 APPLICATIONS INFORMATION VIN and GND pins and are thermally coupled, however, the two outputs of the LT3024 operate independently. They can be shut down independently and a fault condition on one output will not affect the other output electrically. Current limit protection and thermal overload protection are intended to protect the device against current overload conditions at the output of the device. For normal operation, the junction temperature should not exceed 125C. The input of the device will withstand reverse voltages of 20V. Current flow into the device will be limited to less than 1mA (typically less than 100A) and no negative voltage will appear at the output. The device will protect both itself and the load. This provides protection against batteries which can be plugged in backward. The output of the LT3024 can be pulled below ground without damaging the device. If the input is left open circuit or grounded, the output can be pulled below ground by 20V. The output will act like an open circuit; no current will flow out of the pin. If the input is powered by a voltage source, the output will source the short-circuit current of the device and will protect itself by thermal limiting. In this case, grounding the SHDN1/SHDN2 pins will turn off the device and stop the output from sourcing the shortcircuit current. The ADJ pins can be pulled above or below ground by as much as 7V without damaging the device. If the input is left open circuit or grounded, the ADJ pins will act like an open circuit when pulled below ground and like a large resistor (typically 100k) in series with a diode when pulled above ground. In situations where the ADJ pins are connected to a resistor divider that would pull the pins above their 7V clamp voltage if the output is pulled high, the ADJ pin input current must be limited to less than 5mA. For example, a resistor divider is used to provide a regulated 1.5V output from the 1.22V reference when the output is forced to 20V. The top resistor of the resistor divider must be chosen to limit the current into the ADJ pin to less than 5mA when the ADJ pin is at 7V. The 13V difference between output and ADJ pin divided by the 5mA maximum current into the ADJ pin yields a minimum top resistor value of 2.6k. In circuits where a backup battery is required, several different input/output conditions can occur. The output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left open circuit. Current flow back into the output will follow the curve shown in Figure 7. When the IN pin of the LT3024 is forced below either OUT pin or either OUT pin is pulled above the IN pin, input current for the corresponding regulator will typically drop to less than 2A. This can happen if the input of the device is connected to a discharged (low voltage) battery and the output is held up by either a backup battery or a second regulator circuit. The state of the SHDN1/SHDN2 pin will have no effect on the reverse output current when the output is pulled above the input. 100 REVERSE OUTPUT CURRENT (A) TA = 25C 90 VIN = 0V = VADJ V 80 OUT CURRENT FLOWS 70 INTO OUTPUT PIN 60 50 40 30 20 10 0 0 1 2 345678 OUTPUT VOLTAGE (V) 9 10 3024 F07 Figure 7. Reverse Output Current 3024fa 17 LT3024 PACKAGE DESCRIPTION DE/UE Package 12-Lead Plastic DFN (4mm x 3mm) (Reference LTC DWG # 05-08-1695 Rev D) 0.70 0.05 3.30 0.05 1.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.50 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 (2 SIDES) R = 0.05 TYP 3.00 0.10 (2 SIDES) 3.30 0.10 1.70 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 x 45 CHAMFER 1 0.50 BSC 2.50 REF 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD (UE12/DE12) DFN 0806 REV D 3.60 0.05 2.20 0.05 7 R = 0.115 TYP 0.40 0.10 12 PIN 1 TOP MARK (NOTE 6) 0.200 REF 0.75 0.05 6 0.25 0.05 NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3024fa 18 LT3024 PACKAGE DESCRIPTION FE Package 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation BB 3.58 (.141) 4.90 - 5.10* (.193 - .201) 3.58 (.141) 16 1514 13 12 1110 6.60 0.10 4.50 0.10 SEE NOTE 4 9 2.94 (.116) 0.45 0.05 1.05 0.10 0.65 BSC 2.94 6.40 (.116) (.252) BSC RECOMMENDED SOLDER PAD LAYOUT 12345678 1.10 (.0433) MAX 0 - 8 4.30 - 4.50* (.169 - .177) 0.25 REF 0.09 - 0.20 (.0035 - .0079) 0.50 - 0.75 (.020 - .030) 0.65 (.0256) BSC NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 0.195 - 0.30 (.0077 - .0118) TYP 0.05 - 0.15 (.002 - .006) FE16 (BB) TSSOP 0204 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3024fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LT3024 RELATED PARTS PART NUMBER LT1129 LT1175 LT1185 LT1761 LT1762 LT1763 LT1764/LT1764A LTC1844 LT1962 LT1963/LT1963A LT1964 LT3023 LTC3407 DESCRIPTION 700mA, Micropower, LDO 500mA, Micropower Negative LDO 3A, Negative LDO 100mA, Low Noise Micropower, LDO 150mA, Low Noise Micropower, LDO 500mA, Low Noise Micropower, LDO 3A, Low Noise, Fast Transient Response, LDO 150mA, Very Low Drop-Out LDO 300mA, Low Noise Micropower, LDO COMMENTS VIN: 4.2V to 30V, VOUT(MIN) = 3.75V, IQ = 50A, ISD = 16A, DD, SOT-223, S8,TO220, TSSOP20 Packages Guaranteed Voltage Tolerance and Line/Load Regulation, VIN: -20V to -4.3V, VOUT(MIN) = -3.8V, IQ = 45A, ISD = 10A, DD,SOT-223, S8 Packages Accurate Programmable Current Limit, Remote Sense, VIN: -35V to -4.2V, VOUT(MIN) = -2.40V, IQ = 2.5mA, ISD <1A, TO220-5 Package Low Noise < 20VRMS, Stable with 1F Ceramic Capacitors, VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, IQ = 20A, ISD <1A, ThinSOT Package Low Noise < 20VRMS, VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, IQ = 25A, ISD <1A, MS8 Package Low Noise < 20VRMS, VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, IQ = 30A, ISD <1A, S8 Package Low Noise < 40VRMS, "A" Version Stable with Ceramic Capacitors, VIN: 2.7V to 20V, VOUT(MIN) = 1.21V, IQ = 1mA, ISD <1A, DD, TO220 Packages Low Noise < 30VRMS, Stable with 1F Ceramic Capacitors, VIN: 1.6V to 6.5V, VOUT(MIN) = 1.25V, IQ = 40A, ISD <1A, ThinSOT Package Low Noise < 20VRMS, VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, IQ = 30A, ISD <1A, MS8 Package 1.5A, Low Noise, Fast Transient Response, LDO Low Noise < 40VRMS, "A" Version Stable with Ceramic Capacitors, VIN: 2.1V to 20V, VOUT(MIN) = 1.21V, IQ = 1mA, ISD <1A, DD, TO220, SOT-223, S8 Packages 200mA, Low Noise Micropower, Negative LDO Dual 100mA, Low Noise, Micropower LDO Dual 600mA. 1.5MHz Synchronous Step Down DC/DC Converter Low Noise < 30VRMS, Stable with Ceramic Capacitors, VIN: -0.9V to -20V, VOUT(MIN) = -1.21V, IQ = 30A, ISD = 3A, ThinSOT Package Low Noise < 20VRMS, Stable with 1F Ceramic Capacitors, VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, IQ = 40A, ISD <1A, MS10E, DFN Packages VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6 V, IQ = 40A, ISD <1A, MSE Package 3024fa 20 Linear Technology Corporation (408) 432-1900 FAX: (408) 434-0507 LT 0208 REV A * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2004 |
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