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240pin DDR3 SDRAM Registered DIMM
DDR3 SDRAM Unbuffered DIMMs Based on 1Gb T-Die
HMT112U6TFR8C HMT112U7TFR8C HMT125U6TFR8C HMT125U7TFR8C
* Hynix Semiconductor reserves the right to change products or specifications without notice.
Rev. 1.0 / Nov. 2009 1
Revision History
Revision No. 1.0 History Initial Release Draft Date Nov. 2009 Remark Web posting
Rev. 1.0 / Nov. 2009
2
Description
Hynix Unbuffered DDR3 SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use Hynix DDR3 SDRAM devices. These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems such as PCs and workstations.
Features
* VDD=1.5V +/- 0.075V * VDDQ=1.5V +/- 0.075V * VDDSPD=3.0V to 3.6V * Functionality and operations comply with the DDR3 SDRAM datasheet * 8 internal banks * Data transfer rates: PC3-10600, PC3-8500, or PC3-6400 * Bi-directional Differential Data Strobe * 8 bit pre-fetch * Burst Length (BL) switch on-the-fly: BL 8 or BC (Burst Chop) 4 * Supports ECC error correction and detection * On Die Termination (ODT) supported * Temperature sensor with integrated SPD (Serial Presence Detect) EEPROM * RoHS compliant
* This product is in compliance with the RoHS directive.
Ordering Information
Part Number HMT112U6TFR8C-G7/H9/PB HMT112U7TFR8C-G7/H9/PB HMT125U6TFR8C-G7/H9/PB HMT125U7TFR8C-G7/H9/PB
Rev. 1.0 / Nov. 2009
Density 1GB 1GB 2GB 2GB
Organization 128Mx64 128Mx72 256Mx64 256Mx72
Component Composition 128Mx8(H5TQ1G83TFR)*8 128Mx8(H5TQ1G83TFR)*9 128Mx8(H5TQ1G83TFR)*16 128Mx8(H5TQ1G83TFR)*18
# of ranks 1 1 2 2
FDHS X X X X
3
Key Parameters
MT/s DDR3-1066 DDR3-1333 DDR3-1600 Grade -G7 -H9 -PB tCK (ns) 1.875 1.5 1.25 CAS Latency (tCK) 7 9 11 tRCD (ns) 13.125 13.5 13.75 tRP (ns) 13.125 13.5 13.75 tRAS (ns) 37.5 36 35 tRC (ns) 50.625 49.5 48.75 CL-tRCD-tRP 7-7-7 9-9-9 11-11-11
Speed Grade
Frequency [MHz] Grade CL6 -G7 -H9 -PB 800 800 800 CL7 1066 1066 1066 CL8 1066 1066 1066 1333 1333 1333 1333 1600 CL9 CL10 CL11 Remark
Address Table
1GB(1Rx8) Refresh Method Row Address Column Address Bank Address Page Size 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 1GB(1Rx8) 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 2GB(2Rx8) 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 2GB(2Rx8) 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB
Rev. 1.0 / Nov. 2009
4
Pin Descriptions
Pin Name A0-A15 BA0-BA2 RAS CAS WE S0-S1 CKE0-CKE1 ODT0-ODT1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 DQS0-DQS8 DM0-DM8 CK0-CK1 CK0-CK1 Description SDRAM address bus SDRAM bank select SDRAM row address strobe SDRAM column address strobe SDRAM write enable DIMM Rank Select Lines SDRAM clock enable lines On-die termination control lines DIMM memory data bus DIMM ECC check bits SDRAM data strobes (positive line of differential pair) SDRAM data strobes (negative line of differential pair) SDRAM data masks/high data strobes (x8-based x72 DIMMs) SDRAM clocks (positive line of differential pair) SDRAM clocks (negative line of differential pair) Pin Name SCL SDA SA0-SA2 VDD* VDDQ* VREFDQ VREFCA VSS VDDSPD NC TEST RESET VTT RSVD Description I2C serial bus clock for EEPROM I2C serial bus data line for EEPROM I2C slave address select for EEPROM SDRAM core power supply SDRAM I/O Driver power supply SDRAM I/O reference supply SDRAM command/address reference supply Power supply return (ground) Serial EEPROM positive power supply Spare pins (no connect) Memory bus analysis tools (unused on memory DIMMS) Set DRAMs to Known State SDRAM I/O termination supply Reserved for future use -
*The VDD and VDDQ pins are tied common to a single power-plane on these designs
Rev. 1.0 / Nov. 2009
5
Input/Output Functional Descriptions
Symbol CK0-CK1 CK0-CK1 Type Polarity Differential crossing Function CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing). Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. This signal provides for external rank selection on systems with multiple ranks. RAS, CAS, and WE (ALONG WITH S) define the command being entered. When high, termination resistance is enabled for all DQ, DQS, DQS and DM pins, assuming this function is enabled in the Mode Register 1 (MR1). Reference voltage for SSTL15 I/O inputs. Reference voltage for SSTL 15 command/address inputs. Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. -- Selects which SDRAM bank of eight is activated. During a Bank Activate command cycle, Address input defines the row address (RA0-RA15). During a Read or Write command cycle, Address input defines the column address. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to define which bank to precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed (HIGH, no burst chop; LOW, burst chopped). Data and Check Bit Input/Output pins. DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Power and ground for the DDR3 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules.
SSTL
CKE0-CKE1
SSTL
Active High
S0-S1
SSTL
Active Low
RAS, CAS, WE ODT0-ODT1 VREFDQ VREFCA VDDQ BA0-BA2
SSTL SSTL Supply Supply Supply SSTL
Active Low Active High
A0-A15
SSTL
--
DQ0-DQ63, CB0-CB7
SSTL
--
DM0-DM8
SSTL
Active High
VDD, VSS
Supply
Rev. 1.0 / Nov. 2009
6
Symbol DQS0-DQS8 DQS0-DQS8 SA0-SA2
Type SSTL
Polarity Differential crossing --
Function Data strobe for input and output data. These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected from the SDA bus line to VDDSPD to act as a pullup on the system board. This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL bus time to VDDSPD to act as a pullup on the system board. Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 3.0V to 3.6V.
SDA
--
SCL
--
VDDSPD
Supply
Pin Assignments
Front Side(left 1-60) Pin x64 # Non-ECC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VREFDQ VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 x72 ECC VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 Back Side(right 121-180) Pin x64 # Non-ECC VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 x72 ECC VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS Front Side(left 61-120) Back Side(right 181-240) Pin # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 x64 Non-ECC A2 VDD CK1 CK1 VDD VDD VREFCA NC VDD A10 BA02 VDD WE CAS VDD S1 x72 ECC A2 VDD CK1 CK1 VDD VDD VREFCA NC VDD A10 BA02 VDD WE CAS VDD S1 Pin # 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 x64 Non-ECC A1 VDD VDD CK0 CK0 VDD NC A0 VDD BA12 VDD RAS S0 VDD ODT0 A13 x72 ECC A1 VDD VDD CK0 CK0 VDD NC A0 VDD BA12 VDD RAS S0 VDD ODT0 A13
VREFDQ 121
NC = No Connect; RFU = Reserved Future Use 1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group. 2. Address pins A3-A8 and BA0 and BA1 can be mirrored or not mirrored.
Rev. 1.0 / Nov. 2009 7
Front Side(left 1-60) Pin x64 # Non-ECC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 VSS NC NC VSS NC NC VSS NC NC VSS x72 ECC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8 DQS8 VSS CB2 CB3 VSS
Back Side(right 121-180) Pin x64 # Non-ECC 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS NC NC VSS DM8 NC VSS NC NC VSS NC x72 ECC DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 NC VSS CB6 CB7 VSS NC
Front Side(left 61-120) Back Side(right 181-240) Pin # 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 x64 Non-ECC ODT1 VDD NC VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS x72 ECC ODT1 VDD NC VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS Pin # 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 x64 Non-ECC VDD NC VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 x72 ECC VDD NC VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 NC VSS DQ54 DQ55 VSS DQ60
NC = No Connect; RFU = Reserved Future Use 1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group. 2. Address pins A3-A8 and BA0 and BA1 can be mirrored or not mirrored.
Rev. 1.0 / Nov. 2009
8
Front Side(left 1-60) Pin x64 # Non-ECC 48 49 50 51 52 53 54 55 56 57 58 59 60 NC KEY NC CKE0 VDD BA2 NC VDD All A72 VDD A52 A42 VDD NC CKE0 VDD BA2 NC VDD All A72 VDD A52 A42 VDD x72 ECC NC
Back Side(right 121-180) Pin x64 # Non-ECC 168 169 170 171 172 173 174 175 176 177 178 179 180 Reset KEY CKE1/NC VDD NC NC VDD A12 A9 VDD A82 A62 VDD A32 CKE1/NC VDD NC NC VDD A12 A9 VDD A82 A62 VDD A32 x72 ECC Reset
Front Side(left 61-120) Back Side(right 181-240) Pin # 108 109 110 111 112 113 114 115 116 117 118 119 120 x64 Non-ECC DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SA0 SCL SA2 VTT x72 ECC DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SA0 SCL SA2 VTT Pin # 228 229 230 231 232 233 234 235 236 237 238 239 240 x64 Non-ECC DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT x72 ECC DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT
NC = No Connect; RFU = Reserved Future Use 1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group. 2. Address pins A3-A8 and BA0 and BA1 can be mirrored or not mirrored.
Rev. 1.0 / Nov. 2009
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On DIMM Thermal Sensor
The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal sensor comply with JEDEC "TSE2002av, Serial Presence Detect with Temperature Sensor".
Connection of Thermal Sensor
EVENT SCL SDA SA0 SA1 SA2 SA0 SPD with SA1 Integrated SA2 TS
EVENT SCL SDA
Temperature-to-Digital Conversion Performance
Parameter Condition Active Range, 75C < TA < 95C Temperature Sensor Accuracy (Grade B) Monitor Range, 40C < TA < 125C -20C < TA < 125C Min Typ 0.5 1.0 2.0 Max 1.0 2.0 3.0 Unit C C C C
Resolution
0.25
Rev. 1.0 / Nov. 2009
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Functional Block Diagram
1GB, 128Mx64 Module(1Rank of x8)
DQS0 DQS0 DM0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
S0
DQS4 DQS4 DM4
I/O I/O I/O I/O I/O I/O I/O I/O DM CS DQS DQS 0 1 D0 2 3 4 5 6 ZQ 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS
D4
ZQ
DQS1 DQS1 DM1
DQS5 DQS5 DM5
DQS2 DQS2 DM2
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DM CS DQS DQS I/O 0 I/O 1 D1 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7
DQS6 DQS6 DM6
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D5
ZQ
DQS3 DQS3 DM3
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
I/O I/O I/O I/O I/O I/O I/O I/O
DM CS DQS DQS 0 1 D2 2 3 4 5 6 7 ZQ
DQS7 DQS7 DM7
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D6
ZQ
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DM CS DQS DQS I/O 0 I/O 1 D3 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D7
ZQ
Serial PD WP A0 SDA A1 SA1 A2 SA2
SCL
BA0-BA2 A0-A15 RAS CAS CKE0 WE ODT0 CK0 CK0 RESET
BA0-BA2: SDRAMs D0-D7 A0-A15: SDRAMs D0-D7 RAS: SDRAMs D0-D7 CAS: SDRAMs D0-D7 CKE: SDRAMs D0-D7 WE: SDRAMs D0-D7 ODT: SDRAMs D0-D7 CK: SDRAMs D0-D7 CK: SDRAMs D0-D7 RESET: SDRAMs D0-D7
SA0
VDDSPD VDD/VDDQ VREFDQ VSS VREFCA
SPD D0-D7 D0-D7 D0-D7 D0-D7
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,DM,DQS/DQS resistors;Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document. 5. Refer to Section 3.1 of this document for details on address mirroring. 6. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 7. One SPD exists per module.
Rev. 1.0 / Nov. 2009
11
1GB, 128Mx72 Module(1Rank of x8)
DQS0 DQS0 DM0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
S0
DQS4 DQS4 DM4
CS DQS DQS
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
ZQ
DQS1 DQS1 DM1
DQS5 DQS5 DM5
CS DQS DQS
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
DQS DQS
D4
ZQ
DQS2 DQS2 DM2
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
ZQ
DQS6 DQS6 DM6
CS DQS DQS
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D5
ZQ
DQS3 DQS3 DM3
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D2
ZQ
DQS7 DQS7 DM7
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
DQS DQS
D6
ZQ
DQS8 DQS8 DM8
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
DQS DQS
D3
ZQ
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
DQS DQS
D7
ZQ
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
SPD(TS integrated) SCL
D8
EVENT
ZQ
EVENT
A0 SA0
SDA A1 SA1
A2
SA2
BA0-BA2 A0-A15 RAS CAS CKE0 WE ODT0 CK0 CK0 RESET
BA0-BA2: SDRAMs D0-D8 A0-A15: SDRAMs D0-D8 VDDSPD RAS: SDRAMs D0-D8 VDD/VDDQ CAS: SDRAMs D0-D8 CKE: SDRAMs D0-D8 VREFDQ WE: SDRAMs D0-D8 VSS ODT: SDRAMs D0-D8 CK: SDRAMs D0-D8 VREFCA CK: SDRAMs D0-D8 RESET: SDRAMs D0-D8
SPD D0-D8 D0-D8 D0-D8 D0-D8
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,CB,DM,DQS/DQS resistors;Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document. 5. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 6. One SPD exists per module.
Rev. 1.0 / Nov. 2009
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2GB, 256Mx64 Module(2Rank of x8)
S0 DQS0 DQS0 DM0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS
S1 DQS4 DQS4 DM4
DM CS DQS DQS I/O 0 I/O 1 D8 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 ZQ I/O 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS DQS DQS I/O 0 I/O 1 D4 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 D12 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
DQS1 DQS1 DM1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
ZQ
DQS5 DQS5 DM5
DM CS DQS DQS I/O 0 I/O 1 D9 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
ZQ
ZQ
CS DQS DQS
D1
DQS2 DQS2 DM2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
ZQ
DM CS DQS DQS I/O 0 I/O 1 D5 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQS6 DQS6 DM6
ZQ
DM CS DQS DQS I/O 0 I/O 1 D13 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ
CS DQS DQS
D2
DQS3 DQS3 DM3
ZQ
DM CS DQS DQS I/O 0 I/O 1 D10 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DM CS DQS DQS I/O 0 I/O 1 D6 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
ZQ
DM CS DQS DQS I/O 0 I/O 1 D14 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ
DQS7 DQS7 DM7
DM CS DQS DQS I/O 0 I/O 1 D11 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 ZQ I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS DQS DQS I/O 0 I/O 1 D7 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 D15 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D3
ZQ
ZQ
ZQ
Serial PD BA0-BA2 A0-A15 CKE1 CKE0 RAS CAS WE ODT0 ODT1 CK0 CK0 CK1 CK1 BA0-BA2: SDRAMs D0-D15 SCL A0-A15: SDRAMs D0-D15 WP CKE: SDRAMs D8-D15 A0 CKE: SDRAMs D0-D7 SA0 RAS: SDRAMs D0-D15 CAS: SDRAMs D0-D15 VDDSPD WE: SDRAMs D0-D15 VDD/VDDQ ODT: SDRAMs D0-D7 VREFDQ ODT: SDRAMs D8-D15 CK: SDRAMs D0-D7 CK: SDRAMs D0-D7 CK: SDRAMs D8-D15 CK: SDRAMs D8-D15 VSS VREFCA
A1 SA1
A2
SA2
Notes: 1. DQ-to-I/O wiring is shown as recomSDA mended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,DM,DQS,DQS resistors;Refer to associated topology diagram. SPD 4. Refer to Section 3.1 of this document for D0-D15 details on address mirroring. 5. For each DRAM, a unique ZQ resistor is D0-D15 connected to ground.The ZQ resistor is D0-D15 240ohm+-1% 6. One SPD exists per module. D0-D15
RESET
RESET: SDRAMs D0-D3
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2GB, 256Mx72 Module(2Rank of x8)
DQS0 DQS0 DM0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
S0
S1 DQS4 DQS4 DM4
DM CS DQS DQS I/O 0 I/O 1 D0 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS
D9
ZQ
DQS1 DQS1 DM1
DQS5 DQS5 DM5
CS DQS DQS
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DM CS DQS DQS I/O 0 I/O 1 D4 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
ZQ
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D13
ZQ
DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D1
DQS2 DQS2 DM2
ZQ
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D10
ZQ
DQS6 DQS6 DM6
CS DQS DQS
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DM CS DQS DQS I/O 0 I/O 1 D5 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
ZQ
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D14
ZQ
DQS3 DQS3 DM3
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DM CS DQS DQS I/O 0 I/O 1 D2 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D11
ZQ
DQS7 DQS7 DM7
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DM CS DQS DQS I/O 0 I/O 1 D6 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D15
ZQ
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DM CS DQS DQS I/O 0 I/O 1 D3 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D12
DQS8 DQS8 DM8
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
ZQ
ZQ
SCL
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DM CS DQS DQS I/O 0 I/O 1 D7 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D16
ZQ
SPD
VDDSPD
SPD(TS integrated)
DM CS DQS DQS I/O 0 I/O 1 D8 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS
VDD/VDDQ
D0-D17 D0-D17 D0-D17 D0-D17
EVENT
EVENT
A0 SA0
SDA A1 SA1
VREFDQ Vss VREFCA
D17
A2
SA2
ZQ
ZQ
ODT: SDRAMs D0-D8 ODT: SDRAMs D9-D17 CK: SDRAMs D0-D8 CK: SDRAMs D0-D8 CK: SDRAMs D9-D17 CK: SDRAMs D9-D17 RESET: SDRAMs D0-D17
BA0-BA2 A0-A15 CKE0 CKE1 RAS CAS WE
BA0-BA2: SDRAMs D0-D17 A0-A15: SDRAMs D0-D17 CKE: SDRAMs D0-D8 CKE: SDRAMs D9-D17 RAS: SDRAMs D0-D17 CAS: SDRAMs D0-D17 WE: SDRAMs D0-D17
ODT0 ODT1 CK0 CK0 CK1 CK1 RESET
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,CB,DM/DQS/DQS resistors;Refer to associated topology diagram. 4. Refer to Section 3.1 of this document for details on address mirroring. 5. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 6. One SPD exists per module.
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Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol VDD VDDQ Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Rating - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V -55 to +100 Units V V V
o
Notes 1, 1, 1 1, 2
VIN, VOUT Voltage on any pin relative to Vss TSTG Notes: Storage Temperature
C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Temperature Range
Symbol TOPER Notes: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 s. It is also possible to specify a component with 1X refresh (tREFI to 7.8s) in the Extended Temperature Range. Please refer to the DIMM SPD for option availability b. Hynix DDR3 SDRAMs support Auto Self-Refresh and Extended Temperature Range and please refer to Hynix component datasheet and/or the DIMM SPD for tREFI requirement in the Extended Temperature Range. Parameter Normal Operating Temperature Range Extended Temperature Range Rating 0 to 85 85 to 95 Units
oC oC
Notes 1,2 1,3
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AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions
Symbol VDD VDDQ Supply Voltage Supply Voltage for Output Parameter Rating Min. 1.425 1.425 Typ. 1.500 1.500 Max. 1.575 1.575 Units V V Notes 1,2 1,2
Notes: 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
AC & DC Input Measurement Levels
AC and DC Logic Input Levels for Single-Ended Signals AC and DC Input Levels for Signal-Ended Command and Address Signals
Single Ended AC and DC Input Levels for Command and Address
DDR3-800/1066/1333/1600 Symbol VIH.CA(DC100) VIL.CA(DC100) VIH.CA(AC175) VIL.CA(AC175) VIH.CA(AC150) VIL.CA(AC150) VRefCA(DC) Parameter Min DC input logic high DC input logic low AC input logic high AC input logic low AC Input logic high AC input logic low Reference Voltage for ADD, CMD inputs Vref + 0.100 VSS Vref + 0.175 Note2 Vref + 0.150 Note2 0.49 * VDD Max VDD Vref - 0.100 Note2 Vref - 0.175 Note2 Vref - 0.150 0.51 * VDD V V V V V V V 1 1 1, 2 1, 2 1, 2 1, 2 3, 4 Unit Notes
Notes: 1. For input only pins except RESET, Vref = VrefCA (DC). 2. Refer to "Overshoot and Undershoot Specifications" on page 29. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV.
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AC and DC Input Levels for Signal-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in the table below. DDR3 SDRAM will also support corresponding tDS values (Table 41 and Table 47 in "DDR3 Device Operation") as well as derating tables in Table 44 of "DDR3 Device Operation" depending on Vih/Vil AC levels.
Single Ended AC and DC Input Levels for DQ and DM
DDR3-800/1066 Symbol VIH.CA(DC100) VIL.CA(DC100) VIH.CA(AC175) VIL.CA(AC175) VIH.CA(AC150) VIL.CA(AC150) VRefDQ(DC) Parameter Min DC input logic high Vref + 0.100 DC input logic low VSS AC input logic high Vref + 0.175 AC input logic low Note2 AC Input logic high Vref + 0.150 AC input logic low Note2 Reference Voltage for DQ, 0.49 * VDD DM inputs Max VDD Vref - 0.100 Note2 Vref - 0.175 Note2 Vref - 0.150 0.51 * VDD Min Vref + 0.100 VSS Vref + 0.150 Note2 0.49 * VDD Max VDD Vref - 0.100 Note2 Vref - 0.150 0.51 * VDD V V V V V V V 1 1 1, 2 1, 2 1, 2 1, 2 3, 4 DDR3-1333/1600 Unit Notes
Notes: 1. Vref = VrefDQ (DC). 2. Refer to "Overshoot and Undershoot Specifications" on page 29. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV.
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Vref Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure below. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise). VRef (DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in the table "Differential Input Slew Rate Definition" on page24. Furthermore VRef (t) may temporarily deviate from VRef (DC) by no more than +/- 1% VDD.
voltage
VDD
VRef ac-noise VRef(DC)
VRef(t) VRef(DC)max VDD/2 VRef(DC)min
VSS
time
Illustration of VRef(DC) tolerance and VRef ac-noise limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on VRef. "VRef " shall be understood as VRef(DC), as defined in figure above. This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VRef(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRefac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.
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AC and DC Logic Input Levels for Differential Signals
Differential signal definition
tDVAC VIL.DIFF.AC.MIN Differential Input Voltage(i.e.DQS - DQS#, CK - CK#)
VIL.DIFF.MIN
0 half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX tDVAC time Definition of differential ac-swing and "time above ac-level" tDVAC
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Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
Differential AC and DC Input Levels
DDR3-800, 1066, 1333, & 1600 Symbol VIHdiff VILdiff VIHdiff (ac) VILdiff (ac) Notes: 1. Used to define a differential signal slew-rate. 2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL (ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level applies also here. 3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 29. Parameter Min Differential input high Differential input logic low Differential input high ac Differential input low ac + 0.200 Note 3 2 x (VIH (ac) - Vref) Note 3 Max Note 3 - 0.200 Note 3 2 x (VIL (ac) - Vref) V V V V 1 1 2 2 Unit Notes
Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
Slew Rate [V/ns] > 4.0 4.0 3.0 2.0 1.8 1.6 1.4 1.2 1.0 < 1.0 tDVAC [ps] @ |VIH/Ldiff (ac)| = 350mV min 75 57 50 38 34 29 22 13 0 0 max tDVAC [ps] @ |VIH/Ldiff (ac)| = 300mV min 175 170 167 163 162 161 159 155 150 150 max -
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Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH (ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac) / VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ's might be different per speed-bin etc. E.g., if VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the singleended signals CK and CK.
VDD or VDDQ
VSEHmin VSEH
VDD/2 or VDDQ/2 CK or DQS VSELmax
VSS or VSSQ
VSEL time
Single-ended requirements for differential signals. Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.
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Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
DDR3-800, 1066, 1333, & 1600 Symbol VSEH VSEL Notes: 1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac) of DQs. 2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 29. Parameter Min Single-ended high level for strobes Single-ended high level for Ck, CK Single-ended low level for strobes Single-ended low level for CK, CK (VDD / 2) + 0.175 (VDD /2) + 0.175 Note 3 Note 3 Max Note 3 Note 3 (VDD / 2) = 0.175 (VDD / 2) = 0.175 V V V V 1,2 1,2 1,2 1,2 Unit Notes
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in table below. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS
VDD CK, DQS
VIX VDD/2 VIX VIX
CK, DQS VSS
Vix Definition
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Cross point voltage for differential input signals (CK, DQS)
DDR3-800, 1066, 1333, & 1600 Symbol VIX VIX Parameter Min Differential Input Cross Point Voltage relative to VDD/2 for CK, CK Differential Input Cross Point Voltage relative to VDD/2 for DQS, DQS -150 -175 -150 Max 150 175 150 mV mV mV 1 Unit Notes
Notes: 1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK - CK is larger than 3 V/ns. 2. Refer to the table "Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU" on page 22 for VSEL and VSEH standard values.
Slew Rate Definitions for Single-Ended Input Signals
See 7.5 "Address / Command Setup, Hold and Derating" on page 137 in "DDR3 Device Operation" for single-ended slew rate definitions for address and command signals. See 7.6 "Data Setup, Hold and Slew Rate Derating" on page 144 in "DDR3 Device Operation" for singleended slew rate definition for data signals.
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Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table and Figure below.
Differential Input Slew Rate Definition
Measured Description Min
Max
Defined by
Differential input slew rate for rising edge (CK-CK and DQS-DQS) Differential input slew rate for falling edge (CK-CK and DQS-DQS) Notes:
VILdiffmax VIHdiffmin
VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
Differential Input Voltage (i.e. DQS-DQS; CK-CK)
Delta TRdiff vIHdiffmin
0
vILdiffmax Delta TFdiff
Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
Differential Input Slew Rate Definition for DQS, DQS and CK, CK
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AC & DC Output Measurement Levels
Single Ended AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Single-ended AC and DC Output Levels
Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output SR) AC output low measurement level (for output SR) DDR3-800, 1066, 1333 and 1600 0.8 x VDDQ 0.5 x VDDQ 0.2 x VDDQ VTT + 0.1 x VDDQ VTT - 0.1 x VDDQ Unit V V V V V 1 1 Notes
Notes: 1. The swing of 0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT = VDDQ / 2.
Differential AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Differential AC and DC Output Levels
Symbol VOHdiff (AC) VOLdiff (AC) Parameter AC differential output high measurement level (for output SR) AC differential output low measurement level (for output SR) DDR3-800, 1066, 1333 and 1600 + 0.2 x VDDQ - 0.2 x VDDQ Unit V V Notes 1 1
Notes: 1. The swing of 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT = VDDQ/2 at each of the differential outputs.
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Single Ended Output Slew Rate
When the Reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and Figure below.
Single-ended Output slew Rate Definition
Measured Description From Single-ended output slew rate for rising edge Single-ended output slew rate for falling edge VOL(AC) VOH(AC) To VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / DeltaTRse [VOH(AC)-VOL(AC)] / DeltaTFse Defined by
Notes: 1. Output slew rate is verified by design and characterisation, and may not be subject to production test.
Delta TRse Single Ended Output Voltage(l.e.DQ)
vOH(AC)
V
vOl(AC)
Delta TFse
Single Ended Output Slew Rate Definition
Single Ended Output slew Rate Definition
Output Slew Rate (single-ended)
DDR3-800 Parameter Single-ended Output Slew Rate Symbol SRQse Min 2.5 Max 5 DDR3-1066 Min 2.5 Max 5 DDR3-1333 Min 2.5 Max 5 DDR3-1600 Min TBD Max 5
Units
V/ns
Description: SR; Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting
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Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and Figure below.
Differential Output Slew Rate Definition
Measured Description From Differential output slew rate for rising edge Differential output slew rate for falling edge VOLdiff (AC) VOHdiff (AC) To VOHdiff (AC) VOLdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTRdiff [VOHdiff (AC)-VOLdiff (AC)] / DeltaTFdiff Defined by
Notes: 1. Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output Voltage(i.e. DQS-DQS)
Delta TRdiff vOHdiff(AC)
O
vOLdiff(AC) Delta TFdiff
Differential Output Slew Rate Definition
Differential Output slew Rate Definition
Differential Output Slew Rate
DDR3-800 Parameter Differential Output Slew Rate Symbol SRQdiff Min 5 Max 10 DDR3-1066 Min 5 Max 10 DDR3-1333 Min 5 Max 10 DDR3-1600 Min TBD Max 10
Units
V/ns
Description: SR; Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting
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Reference Load for AC Timing and Output Slew Rate
Figure Below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
VDDQ
CK, CK
DUT
DQ DQS DQS
25 Ohm VTT = VDDQ/2
Reference Load for AC Timing and Output Slew Rate
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Overshoot and Undershoot Specifications
Address and Control Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Address and Control Pins
Parameter Maximum peak amplitude allowed for overshoot area. (See Figure below) Maximum peak amplitude allowed for undershoot area. (See Figure below) Maximum overshoot area above VDD (See Figure below) Maximum undershoot area below VSS (See Figure below) DDR3- DDR3- DDR3- DDR3800 0.4 0.4 0.67 0.67 1066 0.4 0.4 0.5 0.5 1333 0.4 0.4 0.4 0.4 1600 0.4 0.4 0.33 0.33 Units V V V-ns V-ns
(A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT) See figure below for each parameter definition
M axim um A m plitude O vershoot A rea
V olts (V)
VDD V SS
U ndershoot Area M axim um A m plitud e Tim e (ns) Add ress and Control O vershoot and U ndershoot D efinition
Address and Control Overshoot and Undershoot Definition
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Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask
Parameter Maximum peak amplitude allowed for overshoot area. (See Figure below) Maximum peak amplitude allowed for undershoot area. (See Figure below) Maximum overshoot area above VDD (See Figure below) Maximum undershoot area below VSS (See Figure below) DDR3- DDR3- DDR3- DDR3800 0.4 0.4 0.25 0.25 1066 0.4 0.4 0.19 0.19 1333 0.4 0.4 0.15 0.15 1600 0.4 0.4 0.13 0.13 Units V V V-ns V-ns
(CK, CK, DQ, DQS, DQS, DM) See figure below for each parameter definition
M a x im u m A m p litu d e O v e rs h o o t A re a
V o lts (V )
VDDQ VSSQ
U n d e rs h o o t A re a M a x im u m A m p litu d e T im e (n s ) C lo c k , D a ta S tro b e a n d M a s k O v e rs h o o t a n d U n d e rs h o o t D e fin itio n
Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
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Refresh parameters by device density
Refresh parameters by device density
Parameter REF command ACT or REF command time Average periodic refresh interval RTT_Nom Setting tRFC tREFI 0 C TCASE 85 C 85 C < TCASE 95 C 512Mb 90 7.8 3.9 1Gb 110 7.8 3.9 2Gb 160 7.8 3.9 4Gb 300 7.8 3.9 8Gb 350 7.8 3.9 Units Notes ns us us
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Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-800 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 36.
Speed Bin CL - nRCD - nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CL = 6 CWL = 5 CWL = 5 Supported CL Settings Supported CWL Settings Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) 2.5 6 5 min 15 15 15 52.5 37.5 Reserved 3.3 DDR3-800E 6-6-6 max 20 -- -- -- 9 * tREFI ns ns ns ns ns ns ns nCK nCK 1, 2, 3, 4 1, 2, 3 Unit Notes
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DDR3-1066 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 36.
Speed Bin CL - nRCD - nRP Parameter Symbol Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CL = 6 CL = 7 CL = 8 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 min 13.125 13.125 13.125 50.625 37.5 Reserved Reserved 2.5 Reserved Reserved 1.875 Reserved 1.875 6, 7, 8 5, 6 < 2.5 < 2.5 3.3 DDR3-1066F 7-7-7 max 20 -- -- -- 9 * tREFI ns ns ns ns ns ns ns ns ns ns ns ns ns 1, 2, 3, 4, 5 4 1, 2, 3, 5 1, 2, 3, 4 4 1, 2, 3, 4 4 1, 2, 3 Unit Note
tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG)
Supported CL Settings Supported CWL Settings
nCK nCK
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DDR3-1333 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 36.
Speed Bin CL - nRCD - nRP Parameter Symbol Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6, 7 CWL = 5 CL = 6 CWL = 6 CWL = 7 CWL = 5 CL = 7 CWL = 6 CWL = 7 CWL = 5 CL = 8 CWL = 6 CWL = 7 CL = 9 CWL = 5, 6 CWL = 7 CWL = 5, 6 CL = 10 CWL = 7 min 13.5 (13.125)8 13.5 (13.125)8 13.5 (13.125)8 49.5 (49.125)8 36 Reserved Reserved 2.5 Reserved Reserved Reserved 1.875 Reserved Reserved Reserved 1.875 Reserved Reserved 1.5 Reserved 1.5 Reserved 6, 8, (7), 9, (10) 5, 6, 7 <1.875 <1.875 < 2.5 < 2.5 3.3 DDR3-1333H 9-9-9 max 20 -- -- -- 9 * tREFI ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1,2, 3,4, 6 4 1, 2, 3, 6 1, 2, 3, 4, 6 4 4 1, 2, 3, 4, 6 1, 2, 3, 4 4 1, 2, 3, 6 1, 2, 3, 4 4 1, 2, 3, 4 4 1, 2, 3 Unit Note
tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG)
Supported CL Settings Supported CWL Settings
nCK nCK
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DDR3-1600 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 36.
Speed Bin CL - nRCD - nRP Parameter Symbol Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6, 7 CWL = 5 CL = 6 CWL = 6 CWL = 7 CWL = 5 CL = 7 CWL = 6 CWL = 7 CWL = 8 CWL = 5 CL = 8 CWL = 6 CWL = 7 CWL = 8 CWL = 5, 6 CL = 9 CWL = 7 CWL = 8 CWL = 5, 6 CL = 10 min 13.75 (13.125)8 13.75 (13.125)8 13.75 (13.125)8 48.75 (48.125)8 35 Reserved Reserved 2.5 Reserved Reserved Reserved 1.875 Reserved Reserved Reserved 1.875 Reserved Reserved Reserved 1.5 Reserved Reserved 1.5 Reserved Reserved 1.25 5, 6, 7, 8 <1.5 6, (7), 8, (9), 10, 11 <1.875 <1.875 < 2.5 < 2.5 3.3 DDR3-1600K 11-11-11 max 20 -- -- -- 9 * tREFI ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1, 2, 3, 4, 7 4 1, 2, 3, 7 1, 2, 3, 4, 7 4 4 1, 2, 3, 4, 7 1, 2, 3, 4, 7 4 4 1, 2, 3, 7 1, 2, 3, 4, 7 1, 2, 3, 4 4 1, 2, 3, 4, 7 1, 2, 3, 4 4 1, 2, 3, 7 1,2,3,4 4 1, 2, 3 Unit Note
tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG)
tCK(AVG) tCK(AVG) CWL = 7 tCK(AVG) CWL = 8 CWL = 5, 6,7 tCK(AVG) CL = 11 tCK(AVG) CWL = 8
Supported CL Settings Supported CWL Settings
nCK nCK
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Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
Notes: 1, The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK (AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK (AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK (AVG) [ns], rounding up to the next `Supported CL'. 3. tCK(AVG).MAX limits: Calculate tCK (AVG) = tAA.MAX / CLSELECTED and round the resulting tCK (AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CLSE LECTED. 4. `Reserved' settings are not allowed. User must program a different value. 5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 8. Hynix DDR3 SDRAM devices support down binning to CL=7 and CL=9, and tAA/tRCD/tRP satisfy minimum value of 13.125ns. SPD settings are also programmed to match. For example, DDR3 1333H devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to DDR3-1333H or DDR3 1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.
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Environmental Parameters
Symbol
TOPR HOPR TSTG HSTG PBAR
Parameter
Operating temperature (ambient) Operating humidity (relative) Storage temperature Storage humidity (without condensation) Barometric Pressure (operating & storage)
Rating
0 to +55 10 to 90 -50 to +100 5 to 95 105 to 69
Units
oC
Notes
3
%
o
C
1 1 1, 2
% K Pascal
Note: 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended periods may affect reliablility. 2. Up to 9850 ft. 3. The component maximum case Temperature (TCASE) shall not exceed the value specified in the DDR3 DRAM component specification.
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Pin Capacitance (VDD=1.5V, VDDQ=1.5V)
1GB: HMT112U67TFR8C
Pin CK0, CK0 CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF
CCK CCTRL CI CIO
TBD TBD TBD TBD
TBD TBD TBD TBD
1GB: HMT112U7TFR8C
Pin CK0, CK0 CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF
CCK CCTRL CI CIO
TBD TBD TBD TBD
TBD TBD TBD TBD
2GB: HMT125U6TFR8C
Pin CK0, CK0 CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF
CCK CCTRL CI CIO
TBD TBD TBD TBD
TBD TBD TBD TBD
2GB: HMT125U7TFR8C
Pin CK0, CK0 CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF
CCK CCTRL CI CIO
TBD TBD TBD TBD
TBD TBD TBD TBD
Note: 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only.
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IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure below (Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements) shows the setup and test load for IDD and IDDQ measurements. * IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents. IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in the Figure below (Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement). In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using on merged-power layer in Module PCB.
*
For IDD and IDDQ measurements, the following definitions apply: * * * * * * * "0" and "LOW" is defined as VIN <= VILAC(max). "1" and "HIGH" is defined as VIN >= VIHAC(max). "MID_LEVEL" is defined as inputs are VREF = VDD/2. Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1. Basic IDD and IDDQ Measurement Conditions are described in Table 2. Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10. IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 Ohm in MR1); RTT_Wr = RZQ/2 (120 Ohm in MR2); TDQS Feature disabled in MR1 Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.
*
* Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW} Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
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IDD
IDDQ (optional)
VDD
RESET CK/CK CKE CS RAS, CAS, WE A, BA ODT ZQ
VDDQ
DDR3 SDRAM
DQS, DQS DQ, DM, TDQS, TDQS
RTT = 25 Ohm VDDQ/2
VSS
VSSQ
Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements [Note: DIMM level Output test load condition may be different from above
Application specific memory channel environment
IDDQ Test Load
Channel IO Power Simulation
IDDQ Simulation
IDDQ Simulation
Correction Channel IO Power Number Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement
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Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Symbol DDR3-1066 7-7-7 1.875 7 7 27 20 7 1KB page size 2KB page size 1KB page size 2KB page size 20 27 4 6 48 59 86 160 187 DDR3-1333 9-9-9 1.5 9 9 33 24 9 20 30 4 5 60 74 107 200 234 DDR3-1600 11-11-11 1.25 11 11 39 28 11 24 32 5 6 72 88 128 240 280 Unit ns nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK
tCK
CL
nRCD nRC nRAS nRP nFAW nRRD nRFC-1 Gb nRFC- 2 Gb nRFC- 4 Gb nRFC- 8 Gb
nRFC -512Mb
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and Description
IDD0
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3. Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT,
IDD1
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.
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Symbol Precharge Standby Current
Description
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2N
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5. Precharge Standby ODT Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2NT Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6; Pattern Details: see Table 6.
IDDQ2NT Precharge Standby ODT IDDQ Current
(optional) Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current Precharge Power-Down Current Slow Exit CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2P0 Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc) Precharge Power-Down Current Fast Exit
IDD2P1
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc) Precharge Quiet Standby Current
IDD2Q
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 Active Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD3N
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5.
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Symbol Active Power-Down Current
Description
IDD3P
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
IDDQ4R Operating Burst Read IDDQ Current
(optional) Same definition like for IDD4R, however measuring IDDQ current instead of IDD current Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address,
IDD4R
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7. Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, Address,
IDD4W
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8. Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Command,
IDD5B
Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9. Self-Refresh Current: Normal Temperature Range
TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE: IDD6
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
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Symbol
Description Self-Refresh Current: Extended Temperature Range
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede); IDD6ET
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Auto Self-Refresh Current
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale); CKE: IDD6TC Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a),f); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table
IDD7
10; Data IO: read data burst with different data between one burst and the next one according to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 10.
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
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Table 3 - IDD0 Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0
0
1,2 3,4 ... nRAS ... 1*nRC+0 1*nRC+1, 2
ACT D, D D, D PRE ACT D, D D, D PRE
CS
Datab)
0 1 1 0 0 1 1 0
0 0 1 0 0 0 1 0
1 0 1 1 1 0 1 1
1 0 1 0 1 0 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
00 00 00 00 00 00 00 00
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 F F F F
-
repeat pattern 1...4 until nRAS - 1, truncate if necessary repeat pattern 1...4 until nRC - 1, truncate if necessary
Static High
toggling
1*nRC+3, 4 ... 1*nRC+nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary repeat pattern 1...4 until 2*nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL.
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Table 4 - IDD1 Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0 0 0 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0
0
1,2 3,4 ... nRCD ... nRAS ... 1*nRC+0 1*nRC+1,2
ACT D, D D, D RD PRE ACT D, D D, D RD PRE
CS
Datab)
0 1 1 0 0 0 1 1 0 0
0 0 1 1 0 0 0 1 1 0
1 0 1 0 1 1 0 1 0 1
1 0 1 1 0 1 0 1 1 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
00 00 00 00 00 00 00 00 00 00
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 F F F F F
00000000 00110011 -
repeat pattern 1...4 until nRCD - 1, truncate if necessary repeat pattern 1...4 until nRAS - 1, truncate if necessary repeat pattern 1...4 until nRC - 1, truncate if necessary
Static High
toggling
1*nRC+3,4 ... 1*nRC+nRCD ... 1*nRC+nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC
repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MIDLEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL.
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Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0
0
1 2 3
D D D D
CS
Datab)
1 1 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 F F
-
Static High
toggling
1 2 3 4 5 6 7
4-7 8-11 12-15 16-19 20-23 24-17 28-31
repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL.
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0
0
1 2 3
D D D D
CS
Datab)
1 1 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 F F
-
Static High
toggling
1 2 3 4 5 6 7
4-7 8-11 12-15 16-19 20-23 24-17 28-31
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL.
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Table 7 - IDD4R and IDDQ24RMeasurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0
0
1 2,3 4 5
RD D D,D RD D D,D
CS
Datab)
0 1 1 0 1 1
1 0 1 1 0 1
0 0 1 0 0 1
1 0 1 1 0 1
0 0 0 0 0 0
0 0 0 0 0 0
00 00 00 00 00 00
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 F F F
00000000 00110011 -
Static High
toggling
6,7 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63
repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Table 8 - IDD4W Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
0
0
1 2,3 4 5 6,7 8-15 16-23 24-31 32-39 40-47 48-55 56-63
1 2 3 4 5 6 7
WR D D,D WR D D,D repeat repeat repeat repeat repeat repeat repeat
0 1 1 0 1 1 0 1 1 0 1 1 Sub-Loop Sub-Loop Sub-Loop Sub-Loop Sub-Loop Sub-Loop Sub-Loop
0, 0, 0, 0, 0, 0, 0,
0 0 1 0 0 1 but but but but but but but
0 0 1 0 0 1 BA[2:0] BA[2:0] BA[2:0] BA[2:0] BA[2:0] BA[2:0] BA[2:0]
WE
CS
Datab) 00000000 00110011 -
1 1 1 1 1 1 = = = = = = =
Static High
toggling
0 0 0 0 0 0 1 2 3 4 5 6 7
00 00 00 00 00 00
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 F F F
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.0 / Nov. 2009
48
Table 9 - IDD5B Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0 1
0
1.2 3,4 5...8
REF D, D D, D
CS
Datab)
0 1 1
0 0 1
0 0 1
1 0 1
0 0 0
0 0 0
0 00 00
0 0 0
0 0 0
0 0 F
-
repeat cycles 1...4, but BA[2:0] = 1 repeat cycles 1...4, but BA[2:0] = 2 repeat cycles 1...4, but BA[2:0] = 3 repeat cycles 1...4, but BA[2:0] = 4 repeat cycles 1...4, but BA[2:0] = 5 repeat cycles 1...4, but BA[2:0] = 6 repeat cycles 1...4, but BA[2:0] = 7 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
Static High
toggling
9...12 13...16 17...20 21...24 25...28 29...32 2 33...nRFC-1
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL.
Rev. 1.0 / Nov. 2009
49
Table 10 - IDD7 Measurement-Loop Patterna)
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9 Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
0 0 0 0 0 0 0
A[10]
ODT
RAS
CKE
CAS
0
1 2 3 4 5 6 7 8 Static High toggling 9
0 1 2 ... nRRD nRRD+1 nRRD+2 ... 2*nRRD 3*nRRD 4*nRRD nFAW nFAW+nRRD nFAW+2*nRRD nFAW+3*nRRD nFAW+4*nRRD 2*nFAW+0 2*nFAW+1 2&nFAW+2 2*nFAW+nRRD 2*nFAW+nRRD+1 2&nFAW+nRRD+2
10
11 12 13 14 15 16 17 18 19
2*nFAW+2*nRRD 2*nFAW+3*nRRD 2*nFAW+4*nRRD 3*nFAW 3*nFAW+nRRD 3*nFAW+2*nRRD 3*nFAW+3*nRRD 3*nFAW+4*nRRD
ACT 0 0 1 1 0 0 00 0 0 0 RDA 0 1 0 1 0 0 00 1 0 0 D 1 0 0 0 0 0 00 0 0 0 repeat above D Command until nRRD - 1 ACT 0 0 1 1 0 1 00 0 0 F RDA 0 1 0 1 0 1 00 1 0 F D 1 0 0 0 0 1 00 0 0 F repeat above D Command until 2* nRRD - 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 1, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 F Assert and repeat above D Command until nFAW - 1, if necessary repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 1, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 1, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 F Assert and repeat above D Command until 2* nFAW - 1, if necessary ACT 0 0 1 1 0 0 00 0 0 F RDA 0 1 0 1 0 0 00 1 0 F D 1 0 0 0 0 0 00 0 0 F Repeat above D Command until 2* nFAW + nRRD - 1 ACT 0 0 1 1 0 1 00 0 0 0 RDA 0 1 0 1 0 1 00 1 0 0 D 1 0 0 0 0 1 00 0 0 0 Repeat above D Command until 2* nFAW + 2* nRRD - 1 repeat Sub-Loop 10, but BA[2:0] = 2 repeat Sub-Loop 11, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 0 Assert and repeat above D Command until 3* nFAW - 1, if necessary repeat Sub-Loop 10, but BA[2:0] = 4 repeat Sub-Loop 11, but BA[2:0] = 5 repeat Sub-Loop 10, but BA[2:0] = 6 repeat Sub-Loop 11, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 0 Assert and repeat above D Command until 4* nFAW - 1, if necessary
WE
CS
Datab)
00000000 00110011 -
-
0 0 0 0 0 0 0
00110011 00000000 -
0
-
0
-
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.0 / Nov. 2009
50
IDD Specifications (Tcase: 0 to 95oC)
* Module IDD values in the datasheet are only a calculation based on the component IDD spec. The actual measurements may vary according to DQ loading cap.
1GB, 128M x 64 U-DIMM: HMT112U6TFR8C
Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 DDR3 1066 360 480 240 280 80 200 240 280 160 720 720 1080 80 96 96 1040 DDR3 1333 400 520 280 320 80 280 280 320 200 840 840 1120 80 96 96 1280 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
1GB, 128M x 72 U-DIMM: HMT112U7TFR8C
Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7
Rev. 1.0 / Nov. 2009
DDR3 1066 405 540 270 315 90 225 270 315 180 810 810 1215 90 108 108 1170
DDR3 1333 450 585 315 360 90 315 315 360 225 945 945 1260 90 108 108 1440
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
note
51
2GB, 256M x 64 U-DIMM: HMT125U6TFR8C
Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDDET IDD6TC IDD7 DDR3 1066 600 720 480 560 160 400 480 560 320 960 960 1320 160 192 192 1280 DDR3 1333 680 800 560 640 160 560 560 640 400 1120 1120 1400 160 192 192 1560 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
2GB, 256M x 72 U-DIMM: HMT125U7TFR8C
Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDDET IDD6TC IDD7 DDR3 1066 675 810 540 630 180 450 540 630 360 1080 1080 1485 180 216 216 1140 DDR3 1333 765 900 630 720 180 630 630 720 450 1260 1260 1575 180 216 216 1755 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
Rev. 1.0 / Nov. 2009
52
Module Dimensions
128Mx64 - HMT112U6TFR8C
Front
2.10 0.15 Min 1.45 SPD 4x3.00 0.10 17.30 DETAIL-A 2x2.30 0.10 5.175 47.00 128.95 133.35 71.00 DETAIL-B 2x2.50 0.10 9.50 Max R0.70 30.00
Back
Side
3.18
Detail - A
0.80 0.05
Detail - B
2.50 FULL R
2.50 0.20
1.27 0.10
1.00
0.3 0.15
0.35 0.05
3.80
0.3~1.0
1.50 0.10
5.00
Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters
Rev. 1.0 / Nov. 2009
53
128Mx72 - HMT112U7TFR8C
Front
2.10 0.15 Min 1.45 SPD Max R0.70 30.00
4x3.00 0.10 17.30 DETAIL-A 2x2.30 0.10 5.175 47.00 128.95 133.35 71.00 DETAIL-B 2x2.50 0.10 9.50
Back
Side
3.18
Detail - A
0.80 0.05
Detail - B
2.50 FULL R
2.50 0.20
1.27 0.10
1.00
0.3 0.15
0.35 0.05
3.80
0.3~1.0
1.50 0.10
5.00
Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters
Rev. 1.0 / Nov. 2009
54
256Mx64 - HMT125U6TFR8C
Front
2.10 0.15 Min 1.45 SPD 4x3.00 0.10 17.30 DETAIL-A 2x2.30 0.10 5.175 47.00 128.95 133.35 71.00 DETAIL-B 2x2.50 0.10 9.50 Max R0.70 30.00
Back
Side
4.00
Detail - A
0.80 0.05
Detail - B
2.50 FULL R
2.50 0.20
1.27 0.10
1.00
0.3 0.15
0.35 0.05
3.80
0.3~1.0
1.50 0.10
5.00
Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters
Rev. 1.0 / Nov. 2009
55
256Mx72 - HMT125U7TFR8C
Front
2.10 0.15 Min 1.45 SPD Max R0.70 30.00
4x3.00 0.10 17.30 DETAIL-A 2x2.30 0.10 5.175 47.00 128.95 133.35 71.00 DETAIL-B 2x2.50 0.10 9.50
Back
Side
4.00
Detail - A
0.80 0.05
Detail - B
2.50 FULL R
2.50 0.20
1.27 0.10
1.00
0.3 0.15
0.35 0.05
3.80
0.3~1.0
1.50 0.10
5.00
Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters
Rev. 1.0 / Nov. 2009
56

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