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EL5421T
Data Sheet September 25, 2009 FN6922.0
12MHz Rail-to-Rail Input-Output Buffer
The EL5421T is a high voltage rail-to-rail input-output buffer with low power consumption. The EL5421T contains four buffers. Each buffer exhibits beyond the rail input capability, rail-to-rail output capability and is unity gain stable. The maximum operating voltage range is from 4.5V to 19V. It can be configured for single or dual supply operation, and typically consumes only 500A per buffer. The EL5421T has an output short circuit capability of 200mA and a continuous output current capability of 70mA. The EL5421T features a slew rate of 12V/s. Also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a bandwidth of 12MHz (-3dB). This enables the buffers to offer maximum dynamic range at any supply voltage. These features make the EL5421T an ideal buffer solution for use in TFT-LCD panels as a VCOM or static gamma buffer, and in high speed filtering and signal conditioning applications. Other applications include battery power and portable devices, especially where low power consumption is important. The EL5421T is available in a space saving 10 Ld MSOP package and operates over an ambient temperature range of -40C to +85C.
Features
* 12MHz -3dB bandwidth * 4 Unity Gain Buffers * 4.5V to 19V Maximum Supply Voltage Range * 12V/s Slew Rate * 500A Supply Current (per buffer) * 70mA Continuous Output Current * 200mA Output Short Circuit Current * Unity-gain Stable * Beyond the Rails Input Capability * Rail-to-rail Output Swing * Built-in Thermal Protection * -40C to +85C Ambient Temperature Range * Pb-free (RoHS compliant)
Applications
* TFT-LCD Panels * VCOM Buffers * Electronics Notebooks
Ordering Information
PART NUMBER (Note) EL5421TIYZ* PART MARKING BBBLA PACKAGE (Pb-Free) 10 Ld MSOP PKG. DWG. # M10.118A
* Electronics Games * Personal Communication Devices * Personal Digital Assistants (PDA) * Portable Instrumentation * Wireless LANs * Office Automation * Active Filters * ADC/DAC Buffers
*Add "-T7" or "-T13" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
EL5421T (10 LD MSOP) TOP VIEW
VOUTA 1 VINA 2 VS+ 3 VINB 4 VOUTB 5 10 VOUTD 9 VIND 8 VS7 VINC 6 VOUTC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Elantec is a registered trademark of Elantec Semiconductor, Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5421T
Absolute Maximum Ratings (TA = +25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . +19.8V Input Voltage Range (VINx) . . . . . . . . . . . .(VS-)-0.5V to (VS+)+0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . 70mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3000V
Thermal Information
Thermal Resistance Junction-to-Ambient (Typical) JA (C/W) 10 Ld MSOP (Note 1). . . . . . . . . . . . . . . . . . . . . . . . 160 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . .See Figure 27 and 28 Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV
VS+ = +5V, VS- = -5V, RL = 10k to 0V, TA = +25C unless otherwise specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
Input Offset Voltage Average Offset Voltage Drift (Note 2) Input Bias Current Input Impedance Input Capacitance Voltage Gain
VCM = 0V
3 4
13
mV V/C
VCM = 0V
2 1 2
50
nA G pF
-4.5V VOUTx 4.5V
0.992
1.008
V/V
OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short Circuit Current Output Current IL = -5mA IL = +5mA VCM = 0V, Source: VOUTx short to VS-, Sink: VOUTx short to VS+ 4.85 -4.94 4.94 200 70 -4.85 V V mA mA
POWER SUPPLY PERFORMANCE (VS+) - (VS-) IS PSRR Supply Voltage Range Supply Current (Per Buffer) Power Supply Rejection Ratio VCM = 0V, No load Supply is moved from 2.25V to 9.5V 60 4.5 500 75 19 750 V A dB
DYNAMIC PERFORMANCE SR tS BW CS Slew Rate (Note 3) Settling to +0.1% (Note 4) -3dB Bandwidth Channel Separation -4.0V VOUTx 4.0V, 20% to 80% AV = +1, VOUTx = 2V step, RL= 10k, CL= 8pF RL= 10k, CL= 8pF f = 5MHz 12 500 12 75 V/s ns MHz dB
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB
VS+ = +5V, VS- = 0V, RL = 10k to 2.5V, TA = +25C unless otherwise specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
Input Offset Voltage Average Offset Voltage Drift (Note 2) Input Bias Current
VCM = 2.5V
3 4
13
mV V/C
VCM = 2.5V
2
50
nA
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FN6922.0 September 25, 2009
EL5421T
Electrical Specifications
PARAMETER RIN CIN AV Input Impedance Input Capacitance Voltage Gain 0.5 VOUTx 4.5V 0.992 VS+ = +5V, VS- = 0V, RL = 10k to 2.5V, TA = +25C unless otherwise specified. (Continued) CONDITION MIN TYP 1 2 1.008 MAX UNIT GW pF V/V
DESCRIPTION
OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short Circuit Current Output Current IL = -2.5mA IL = +2.5mA VCM = 0V, Source: VOUTx short to VS-, Sink: VOUTx short to VS+ 4.85 30 4.97 125 70 150 mV V mA mA
POWER SUPPLY PERFORMANCE (VS+) - (VS-) IS PSRR Supply Voltage Range Supply Current (Per Buffer) Power Supply Rejection Ratio VCM = 2.5V, No load Supply is moved from 4.5V to 19V 60 4.5 500 75 19 750 V A dB
DYNAMIC PERFORMANCE SR tS BW CS Slew Rate (Note 3) Settling to +0.1% (Note 4) -3dB Bandwidth Channel Separation 1V VOUTx 4V, 20% to 80% AV = +1, VOUTx = 2V step, RL= 10k, CL= 8pF RL= 10k, CL= 8pF f = 5MHz 12 500 12 75 V/s ns MHz dB
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV
VS+ = +18V, VS- = 0V, RL = 10k to 9V, TA = +25C unless otherwise specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
Input Offset Voltage Average Offset Voltage Drift (Note 2) Input Bias Current Input Impedance Input Capacitance Voltage Gain
VCM = 9V
4 5
15
mV V/C
VCM = 9V
2 1 2
50
nA G pF
0.5 VOUTx 17.5V
0.992
1.008
V/V
OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short Circuit Current Output Current IL = -9mA IL = +9mA VCM = 9V, Source: VOUTx short to VS-, Sink: VOUTx short to VS+ 17.85 100 17.90 200 70 150 mV V mA mA
POWER SUPPLY PERFORMANCE (VS+) - (VS-) IS PSRR Supply Voltage Range Supply Current (Per Buffer) Power Supply Rejection Ratio VCM = 9V, No load Supply is moved from 4.5V to 19V 60 4.5 550 75 19 750 V A dB
DYNAMIC PERFORMANCE SR Slew Rate (Note 3) 1V VOUTx 14V, 20% to 80% 12 V/s
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FN6922.0 September 25, 2009
EL5421T
Electrical Specifications
PARAMETER tS BW CS NOTES: 2. Measured over -40C to +85C ambient operating temperature range. See the typical TCVOS production distribution shown in the "Typical Performance Curves" on page 5 3. Typical slew rate is an average of the slew rates measured on the rising (20% to 80%) and the falling (80% to 20%) edges of the output signal. 4. Settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the output level settles within a 0.1% error band. The range of the error band is determined by: Final Value(V)[Full Scale(V)*0.1%] VS+ = +18V, VS- = 0V, RL = 10k to 9V, TA = +25C unless otherwise specified. CONDITION AV = +1, VOUTx = 2V step, RL= 10k, CL= 8pF RL= 10k, CL= 8pF f = 5MHz MIN TYP 500 12 75 MAX UNIT ns MHz dB
DESCRIPTION Settling to +0.1% (Note 4) -3dB Bandwidth Channel Separation
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FN6922.0 September 25, 2009
EL5421T Typical Performance Curves
2200 2000 1800 1600 1400 1200 1000 800 600 400 200 0 QUANTITY (AMPLIFIERS) QUANTITY (AMPLIFIERS) VS = 5V TA = +25C 28 TYPICAL PRODUCTION DISTRIBUTION 24 20 16 12 8 4 0 1 3 5 7 9 11 13 INPUT OFFSET VOLTAGE DRIFT (|V|/C) 15 VS = 5V -40C TO +85C TYPICAL PRODUCTION DISTRIBUTION
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 INPUT OFFSET VOLTAGE (mV)
FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION
FIGURE 2. INPUT OFFSET VOLTAGE DRIFT
10 INPUT OFFSET VOLTAGE (mV) INPUT BIAS CURRENT (nA) VS = 5V 5
2 VS = 5V 1
0
0
-1
-5 -50
0
50 100 TEMPERATURE (C)
150
-2 -50
0
50 100 TEMPERATURE (C)
150
FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
4.95 OUTPUT HIGH VOLTAGE (V) OUTPUT LOW VOLTAGE (V) VS = 5V IOUT = 5mA 4.93
-4.91 -4.92 -4.93 -4.94 -4.95 -4.96 -50 VS = 5V IOUT = -5mA
4.91
4.89 -50
0
50 100 TEMPERATURE (C)
150
0
50 100 TEMPERATURE (C)
150
FIGURE 5. OUTPUT HIGH VOLTGE vs TEMPERATURE
FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE
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FN6922.0 September 25, 2009
EL5421T Typical Performance Curves (Continued)
1.0018 1.0016 1.0014 1.0012 1.0010 1.0008 -50 VS = 5V RL = 10k SLEW RATE (V/s) 13 14 VS = 5V RL = 10k
VOLTAGE GAIN (V/V)
12
0
50 100 TEMPERATURE (C)
150
11 -50
0
50 100 TEMPERATURE (C)
150
FIGURE 7. VOLTAGE GAIN vs TEMPERATURE
FIGURE 8. SLEW RATE vs TEMPERATURE
550 SUPPLY CURRENT (A) SUPPLY CURRENT (A) VS = 5V NO LOAD INPUTS AT GND
650 TA = +25C 600 550 500 450 400 350 2 4 6 8 SUPPLY VOLTAGE (V) 10
525
500
475
450 -50
0
50 100 TEMPERATURE (C)
150
FIGURE 9. SUPPLY CURRENT PER CHANNEL vs TEMPERATURE
FIGURE 10. SUPPLY CURRENT PER CHANNEL vs SUPPLY VOLTAGE
20
SLEW RATE (V/s)
16
TA = +25C AV = 1 RL = 10k CL = 8pF GAIN (dB)
5 10k 0 1k 560 -5 150 VS = 5V AV = 1 CL = 8pF 1M 10M FREQUENCY (Hz) 100M
12
8
-10
4 2
4 6 SUPPLY VOLTAGE (V)
8
10
-15 100k
FIGURE 11. SLEW RATE vs SUPPLY VOLTAGE
FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS RL
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FN6922.0 September 25, 2009
EL5421T Typical Performance Curves (Continued)
20 OUTPUT IMPEDANCE () 100pF 10 GAIN (dB) 0 -10 1000pF -20 VS = 5V AV = 1 RL = 10k -30 100k 50pF 200 160 120 80 40 0 VS = 5V AV = 1 RL = OPEN VOUTx = +13dBm
8pF
1M
10M
100M
1k
10k
FREQUENCY (Hz)
100k 1M FREQUENCY (Hz)
10M
FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS CL
FIGURE 14. OUTPUT IMPEDANCE vs FREQUENCY
MAXIMUM OUTPUT SWING (VP-P)
12 10 PSRR (dB) 8 6 4 2 0
0 -10 -20 -30 -40 -50 -60 -70 100k 1M FREQUENCY (Hz) 10M -80 1k PSRR+ PSRR10k 100k FREQUENCY (Hz) 1M 10M VS = 5V TA = +25C
VS = 5V TA = +25C AV = 1 RL = 10k CL = 8pF
10k
FIGURE 15. MAXIMUM OUTPUT SWING vs FREQUENCY
FIGURE 16. PSRR vs FREQUENCY
1000 VOLTAGE NOISE (nV/Hz) TA = +25C
0.050 0.045 0.040 THD+N (%) VS = 5V RL = 10k AV = 1 VIN = 1.4VRMS
100
0.035 0.030 0.025 0.020 0.015 0.010
10
1 100
1k
10k
100k
1M
10M
100M
0.005 100
1k
FREQUENCY (Hz)
10k FREQUENCY (Hz)
100k
FIGURE 17. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY
FIGURE 18. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
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FN6922.0 September 25, 2009
EL5421T Typical Performance Curves (Continued)
-60 MEASURED CH A TO D, OR B TO C OTHER COMBINATIONS YIELD IMPROVED REJECTION OVERSHOOT (%) 100 80 60 40 20 0 10
-70 XTALK(dB)
-80
VS = 5V AV = 1 VINx = 0dBm
-90
VS = 5V TA = +25C AV = 1 RL = 10k VINx = 50mV 100 LOAD CAPACITANCE (pF) 1000
-100
10k
100k 1M FREQUENCY (Hz)
10M
FIGURE 19. CHANNEL SEPARATION vs FREQUENCY RESPONSE
FIGURE 20. SMALL SIGNAL OVERSHOOT vs LOAD CAPACITANCE
5 4 3 STEP SIZE (V) 2 1 0 -1 -2 -3 -4 -5 100
0.1%
0.1% 6V STEP 200 300 400 500 SETTLING TIME (ns) 600 700 1s/DIV
FIGURE 21. STEP SIZE vs SETTLING TIME
1V/DIV
VS = 5V TA = +25C AV = 1 RL = 10k CL = 8pF
VS = 5V TA = +25C AV = 1 RL= 10k CL =8pF
FIGURE 22. LARGE SIGNAL TRANSIENT RESPONSE
50mV/DIV
VS = 5V TA = +25C AV = 1 RL= 10k CL =8pF
200ns/DIV 100mV STEP
FIGURE 23. SMALL SIGNAL TRANSIENT RESPONSE
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FN6922.0 September 25, 2009
EL5421T Typical Performance Curves (Continued)
EL5421T (10LD MSOP shown) VOUTA
C LA RLA 1 VOUTA VOUTD 10 R LD C LD
VOUTD
VINA+
49.9
2
VINA
VIND
9 49.9
VIND+
VS+
+ 4.7F 0.1F
3
Vs+
Vs-
8 0.1F +
V S4.7F
VINB+
49.9
4
VINB
VINC
7 49.9
VINC+
VOUTB
C LB RLB
5
VOUTB
VOUTC
6 R LC C LC
VOUTC
FIGURE 24. BASIC TEST CIRCUIT
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 PIN NAME VOUTA VINA VS+ VINB VOUTB VOUTC VINC VSVIND VOUTD Buffer A Output Buffer A Input Positive Power Supply Buffer B Input Buffer B Output Buffer C Output Buffer C Input Negative Power Supply Buffer D Input Buffer D Output (Reference Circuit 1) (Reference Circuit 2) (Reference Circuit 2) (Reference Circuit 1) (Reference Circuit 1) (Reference Circuit 2) FUNCTION EQUIVALENT CIRCUIT (Reference Circuit 1) (Reference Circuit 2)
VS+
VS+
VOUTx VINx VSVS-
GND
CIRCUIT 1
CIRCUIT 2
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FN6922.0 September 25, 2009
EL5421T Applications Information
VS = 2.5V, TA = +25C, VINx = 6VP-P, RL = 10k to GND
Product Description
The EL5421T is a high voltage rail-to-rail input-output buffer with low power consumption. The EL5421T contains four buffers. Each buffer exhibits beyond the rail input capability, rail-to-rail output capability and is unity gain stable. The EL5421T features a slew rate of 12V/s. Also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a bandwidth of 12MHz (-3dB). This enables the buffers to offer maximum dynamic range at any supply voltage.
1V/DIV
OUTPUT
INPUT
100s/DIV
Operating Voltage, Input and Output Capability
The EL5421T can operate on a single supply or dual supply configuration. The EL5421T operating voltage ranges from a minimum of 4.5V to a maximum of 19V. This range allows for a standard 5V (or 2.5V) supply voltage to dip to -10%, or a standard 18V (or 9V) to rise by +5.5% without affecting performance or reliability. The input common-mode voltage range of the EL5421T extends 500mV beyond the supply rails. Also, the EL5421T is immune to phase reversal. However, if the common mode input voltage exceeds the supply voltage by more than 0.5V, electrostatic protection diodes in the input stage of the device begin to conduct. Even though phase reversal will not occur, to maintain optimal reliability it is suggested to avoid input overvoltage conditions. Figure 25 shows the input voltage driven 500mV beyond the supply rails and the device output swinging between the supply rails. The EL5421T output typically swings to within 50mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 26 shows the input and output waveforms for the device in a unity-gain configuration. Operation is from 5V supply with a 10k load connected to GND. The input is a 10VP-P sinusoid and the output voltage is approximately 9.9VP-P. Refer to the "Electrical Specifications" Table beginning on page 2 for specific device parameters. Parameter variations with operating voltage, loading and/or temperature are shown in the "Typical Performance Curves" on page 5.
FIGURE 25. OPERATION WITH BEYOND-THE-RAILS INPUT
VS = 5V, TA = +25C, VINx = 10VP-P, RL = 10k to GND
100s/DIV
FIGURE 26. OPERATION WITH RAIL-TO-RAIL INPUT AND
Output Current
The EL5421T is capable of output short circuit currents of 200mA (source and sink), and the device has built-in protection circuitry which limits the short circuit current to 200mA (typical). To maintain maximum reliability the continuous output current should never exceed 70mA. This 70mA limit is determined by the characteristics of the internal metal interconnects. Also, see "Power Dissipation" on page 11 for detailed information on ensuring proper device operation and reliability for temperature and load conditions.
Unused Buffers
It is recommended that any unused buffers have their inputs tied to the ground plane.
Driving Capacitive Loads
As load capacitance increases, the -3dB bandwidth will decrease and peaking can occur. Depending on the application, it may be necessary to reduce peaking and to improve device stability. To improve device stability a snubber circuit or a series resistor may be added to the output of the EL5421T. A snubber is a shunt load consisting of a resistor in series with a capacitor. An optimized snubber can improve the
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FN6922.0 September 25, 2009
OUTPUT
5V/DIV
INPUT
EL5421T
phase margin and the stability of the EL5421T. The advantage of a snubber circuit is that it does not draw any DC load current or reduce the gain. Another method to reduce peaking is to add a series output resistor (typically between 1 to 10). Depending on the capacitive loading, a small value resistor may be the most appropriate choice to minimize any reduction in gain. Where: * i = 1 to 4 (1, 2, 3, 4 corresponds to Channel A, B, C, D respectively) * VS = Total supply voltage (VS+ - VS-) * VS+ = Positive supply voltage * VS- = Negative supply voltage * ISMAX = Maximum supply current per buffer (ISMAX = EL5421T quiescent current / 4) * VOUT = Output voltage * ILOAD = Load current Device overheating can be avoided by calculating the minimum resistive load condition, RLOAD, resulting in the highest power dissipation. To find RLOAD set the two PDMAX equations equal to each other and solve for VOUT/ILOAD. Reference the package power dissipation curves, Figures 27 and 28, for further information.
8 POWER DISSIPATION (W) JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 625mW MSOP10 JA = +200C/W
Power Dissipation
With the high-output drive capability of the EL5421T buffers, it is possible to exceed the +150C absolute maximum junction temperature under certain load current conditions. It is important to calculate the maximum power dissipation of the EL5421T in the application. Proper load conditions will ensure that the EL5421T junction temperature stays within a safe operating region. The maximum power dissipation allowed in a package is determined according to Equation 1:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA (EQ. 1)
where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation allowed The total power dissipation produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power dissipation in the IC due to the loads, or:
P DMAX = i [ V S x I SMAX + ( V S + - V OUT i ) x I LOAD i ] (EQ. 2)
7 6 5 4 3 2 1 0 0
25 50 75 85 100 125 AMBIENT TEMPERATURE (C)
150
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE POWER DISSIPATION (W)
when sourcing, and:
P DMAX = i [ V S x I SMAX + ( V OUT i - V S - ) x I LOAD i ] (EQ. 3)
1.0 THERMAL CONDUCTIVITY TEST BOARD 0.9 781mW 0.8 MSOP10 JA = +160C/W 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0
when sinking.
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN6922.0 September 25, 2009
EL5421T
Thermal Shutdown
The EL5421T has a built-in thermal protection which ensures safe operation and prevents internal damage to the device due to overheating. When the die temperature reaches +165C (typical) the device automatically shuts OFF the outputs by putting them in a high impedance state. When the die cools by +15C (typical) the device automatically turns ON the outputs by putting them in a low impedance or (normal) operating state. performance. Ground plane construction is highly recommended, trace lengths should be as short as possible and the power supply pins must be well bypassed to reduce any risk of oscillation. For normal single supply operation (the VS- pin is connected to ground) a 4.7F capacitor should be placed from VS+ to ground, then a parallel 0.1F capacitor should be connected as close to the device as possible. One 4.7F capacitor may be used for multiple devices. For dual supply operation the same capacitor combination should be placed at each supply pin to ground.
Power Supply Bypassing and Printed Circuit Board Layout
The EL5421T can provide gain at high frequency, so good printed circuit board layout is necessary for optimum
Revision History
DATE 9/10/09 REVISION FN6922.0 CHANGE Issued File Number FN6922. Initial release of Datasheet with file number FN6922 making this a Rev 0.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN6922.0 September 25, 2009
EL5421T
Package Outline Drawing
M10.118A (JEDEC MO-187-BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP) Rev 0, 9/09
A 3.0 0.1 10 0.25 CAB DETAIL "X"
1.10 Max
PIN# 1 ID 1 2
B
4.9 0.15
SIDE VIEW 2
0.18 0.05
3.0 0.1
0.95 BSC 0.5 BSC TOP VIEW
Gauge H 0.86 0.09 C SEATING PLANE 0.55 0.15 0.10 0.05 0.23 +0.07/ -0.08 0.08 C A B SIDE VIEW 1 0.10 C DETAIL "X" 33 Plane 0.25
5.80 4.40 3.00 NOTES: 1. 2. 0.50 0.30 1.40 TYPICAL RECOMMENDED LAND PATTERN 3. 4. 5. 6. Dimensions are in millimeters. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Plastic or metal protrusions of 0.15mm max per side are not included. Plastic interlead protrusions of 0.25mm max per side are not included. Dimensions "D" and "E1" are measured at Datum Plane "H". This replaces existing drawing # MDP0043 MSOP10L.
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FN6922.0 September 25, 2009

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