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800 MHz, 4:1 Analog Multiplexer ADV3221/ADV3222
FEATURES
Excellent ac performance -3 dB bandwidth 800 MHz (200 mV p-p) 750 MHz (2 V p-p) Slew rate: 2400 V/s Low power: 75 mW, VS = 5 V Excellent video performance 100 MHz, 0.1 dB gain flatness 0.02% differential gain error/0.02 differential phase error (RL = 150 ) ADV3221 is a pin-for-pin upgrade to the HA4344 Gain = +1 (ADV3221) or gain = +2 (ADV3222) Low all hostile crosstalk of -85 dB @ 5 MHz, and -58 dB @ 100 MHz Latched control lines for synchronous switching High impedance output disable allows connection of multiple devices without loading the output bus 16-lead SOIC
CS D
FUNCTIONAL BLOCK DIAGRAM
Q D Q ENABLE LATCH A0 D Q LATCH D Q
DECODE
LATCH A1 CK1 CK2 100k D Q
LATCH D Q
IN0 IN1 IN2 IN3
G = +1 (G = +2)
OUT
LATCH
LATCH
100k
Figure 1.
APPLICATIONS
Routing of high speed signals including Video (NTSC, PAL, S, SECAM, YUV, RGB) Compressed video (MPEG, wavelet) 3-level digital video (HDB3) Data communications Telecommunications
GENERAL DESCRIPTION
The ADV3221 and ADV3222 are high speed, high slew rate, buffered 4:1 analog multiplexers. They offer a -3 dB signal bandwidth greater than 800 MHz and channel switch times of less than 20 ns with 1% settling. With lower than -58 dB of crosstalk and -67 dB isolation (at 100 MHz), the ADV3221 and ADV3222 are useful in many high speed applications. The differential gain error of less than 0.02% and differential phase error of less than 0.02, together with 0.1 dB gain flatness out to 100 MHz while driving a 75 back terminated load, make the ADV3221 and ADV3222 ideal for all types of signal switching. The ADV3221/ADV3222 include an output buffer that can be placed into a high impedance state. This allows multiple outputs to be connected together for cascading stages without the off channels loading the output bus. The ADV3221 has a gain of +1, and the ADV3222 has a gain of +2; they both operate on 5 V supplies while consuming less than 7.5 mA of idle current. The channel switching is performed via latched control lines, allowing synchronous updating in a multiple ADV3221/ADV3222 environment. The ADV3221/ADV3222 are offered in a 16-lead SOIC package and are available over the extended industrial temperature range of -40C to +85C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved.
08652-001
ADV3221/ADV3222 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing and Logic Characteristics .............................................. 4 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 Power Dissipation ......................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ..............................................8 Circuit Diagrams ............................................................................ 16 Theory of Operation ...................................................................... 17 Applications Information .............................................................. 18 CK1/CK2 Operation .................................................................. 18 Circuit Layout ............................................................................. 18 Termination................................................................................. 18 Capacitive Load .......................................................................... 18 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19
REVISION HISTORY
3/10--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADV3221/ADV3222 SPECIFICATIONS
VS = 5 V, TA = 25C, RL = 150 , CL = 2 pF, ADV3221 at G = +1, ADV3222 at G = +2, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Gain Flatness Propagation Delay Settling Time Slew Rate NOISE/DISTORTION PERFORMANCE Differential Gain Error Differential Phase Error Crosstalk, All Hostile Off Isolation, Input to Output Input Second-Order Intercept (ADV3222 Only) Input Third-Order Intercept (ADV3222 Only) Output 1 dB Compression Point (ADV3222 Only) Input Voltage Noise DC PERFORMANCE Gain Error Gain Matching OUTPUT CHARACTERISTICS Output Impedance Output Disable Capacitance Output Leakage Current Output Voltage Range Short-Circuit Current INPUT CHARACTERISTICS Input Offset Voltage Input Offset Voltage Drift Input Voltage Range Input Capacitance Input Resistance Input Bias Current SWITCHING CHARACTERISTICS Enable On Time Switching Time, 2 V Step Switching Transient (Glitch) Test Conditions/Comments 200 mV p-p 2 V p-p 0.1 dB, 200 mV p-p 0.1 dB, 2 V p-p 2 V p-p 1%, 2 V step 2 V step, peak NTSC or PAL NTSC or PAL f = 100 MHz f = 5 MHz f = 100 MHz, one channel f = 70 MHz, RL = 100 f = 70 MHz, RL = 100 f = 70 MHz, RL = 100 10 MHz to 100 MHz No load RL = 150 Channel-to-channel, no load DC, enabled Disabled Disabled Disabled No load RL = 150 Min ADV3221 Typ Max 1000 750 100 100 700 5 2400 0.01 0.01 -87 -100 -67 Min ADV3222 Typ Max 800 750 100 100 650 5 2700 0.02 0.02 -58 -85 -72 54 17 18.5 17 1 0.75 1 0.02 1 2.8 2 3 3 50 5 10 3 1.8 10 5 15 20 28 21 1 3 2 3 3 50 5 10 1.5 1.8 10 6 15 20 55 21 0.75 1 0.04 1 Unit MHz MHz MHz MHz ps ns V/s % Degrees dB dB dB dBm dBm dBm nV/Hz % % % M pF A V V mA mV V/C V pF M A ns ns mV p-p
16
2.9 2.8
2.9 2.75
Worst case (all configurations)
Any switch configuration Output enabled Output enabled
1
1 12
12
50% A0 to 1% settling IN0 to IN1 switching
Rev. 0 | Page 3 of 20
ADV3221/ADV3222
Parameter POWER SUPPLIES Supply Current Test Conditions/Comments V+, output enabled, no load V+, output disabled (CS high) V-, output enabled, no load V-, output disabled (CS high) Supply Voltage Range Power Supply Rejection (PSR) TEMPERATURE Operating Temperature Range Junction-to-Ambient Thermal Impedance (JA) 4.5 f = 100 kHz f = 1 MHz Still air Operating (still air) -40 81 -70 -60 +85 -40 81 Min ADV3221 Typ Max 7 1.6 7 1.6 8 2.0 8 2.0 5.5 4.5 -65 -55 +85 Min ADV3222 Typ Max 7.5 1.8 7.5 1.8 9 2.2 9 2.2 5.5 Unit mA mA mA mA V dB dB C C/W
TIMING AND LOGIC CHARACTERISTICS
Table 2.
Parameter A0, A1, CS Setup Time CK1 Pulse Width CK1 to CK2 Pulse Separation CK2 Pulse Width A0, A1, CS Hold Time Symbol t1 t2 t3 t4 t5 Min 20 40 40 40 20 Typ Max Unit ns ns ns ns ns
Table 3. Logic Levels
VIH A0, A1, CK1, CK2, CS +2.0 V min VIL A0, A1, CK1, CK2, CS +0.8 V max IIH A0, A1, CS 2 A max IIL A0, A1, CS 2 A max IIH CK1, CK2 +60 A max IIL CK1, CK2 +10 A max
Rev. 0 | Page 4 of 20
ADV3221/ADV3222
Timing and Programming Diagrams
t1
1 CK1 0
t2
t3
t4
1 CK2 0 1 A0, A1, CS 0
t5
08652-002
Figure 2. Timing Diagram
CK1
CK2
A0
A1 CS
08652-003
OUTPUT
XX
IN0
IN1
HIGH-Z
Figure 3. Programming Example
Rev. 0 | Page 5 of 20
ADV3221/ADV3222 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Supply Voltage (V+ - V-) Analog Input Voltage Digital Input Voltage Output Voltage (Disabled Output) Output Short-Circuit Duration Output Short-Circuit Current Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 12 V V- to V+ 0 V to V+ (V+ - 1 V) to (V- + 1 V) Momentary 50 mA -65C to +150C -40C to +85C 300C 150C
POWER DISSIPATION
The ADV3221/ADV3222 are operated with 5 V supplies and can drive loads down to 150 , resulting in a wide range of possible power dissipations. For this reason, extra care must be taken to adjust the operating conditions based on ambient temperature. Packaged in a 16-lead narrow-body SOIC, the ADV3221 and ADV3222 junction-to-ambient thermal impedance (JA) is 81C/W. For long-term reliability, the maximum allowed junction temperature of the die, TJ, should not exceed 125C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in stresses exerted on the die by the package. Figure 4 shows the range of the allowed internal die power dissipations that meet these conditions over the -40C to +85C ambient temperature range. When using Figure 4, do not include the external load power in the maximum power calculation, but do include the load current through the die output transistors.
1.50 TJ = 125C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance
Package Type 16-Lead Narrow-Body SOIC JA 81 JC 43 Unit C/W
MAXIMUM POWER (W)
THERMAL RESISTANCE
1.25
1.00
0.75
25
35
45
55
65
75
85
AMBIENT TEMPERATURE (C)
Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. 0 | Page 6 of 20
08652-004
0.50 15
ADV3221/ADV3222 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN0 1 GND 2 IN1 3 GND 4
16 15
V+ A0 A1
CS TOP VIEW IN2 5 (Not to Scale) 12 OUT 11 CK2 GND 6
13
ADV3221/ ADV3222
14
GND 8
9
V-
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic IN0 GND IN1 GND IN2 GND IN3 GND V- CK1 CK2 OUT CS A1 A0 V+ Description Analog Input Ground Analog Input Ground Analog Input Ground Analog Input Ground Negative Power Supply First Rank Clock Second Rank Clock Analog Output Chip Select (Output Enable) Select Address Most Significant Bit Select Address Least Significant Bit Positive Power Supply
Table 7. Truth Table
CS 0 0 0 0 1
1
A1 0 0 1 1 X1
A0 0 1 0 1 X1
CK1 0 0 0 0 0
CK2 0 0 0 0 0
08652-005
IN3 7
10
CK1
Output IN0 IN1 IN2 IN3 High-Z
X is don't care.
Rev. 0 | Page 7 of 20
ADV3221/ADV3222 TYPICAL PERFORMANCE CHARACTERISTICS
4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1
GAIN (dB)
0pF 2pF 4.7pF 10pF
08652-012
GAIN (dB)
0pF 2pF 4.7pF 10pF 10 100 FREQUENCY (MHz) 1k 10k
08652-015 08652-017 08652-016
10
100 FREQUENCY (MHz)
1k
10k
Figure 6. ADV3221 Small Signal Response vs. Capacitive Load, 200 mV p-p
4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1
Figure 9. ADV3222 Small Signal Response vs. Capacitive Load, 200 mV p-p
4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1
GAIN (dB)
0pF 2pF 4.7pF 10pF 10 100 FREQUENCY (MHz) 1k 10k
08652-013
GAIN (dB)
0pF 2pF 4.7pF 10pF 10 100 FREQUENCY (MHz) 1k 10k
Figure 7. ADV3221 Large Signal Response vs. Capacitive Load, 2 V p-p
0.2
Figure 10. ADV3222 Large Signal Response vs. Capacitive Load, 2 V p-p
0.2
0pF 2pF 4.7pF 10pF
0pF 2pF 4.7pF 10pF
0.1
0.1
VOUT (V)
0
VOUT (V)
0
-0.1
-0.1
0
5
10 TIME (ns)
15
20
08652-014
-0.2
-0.2 0 5 10 TIME (ns) 15 20
Figure 8. ADV3221 Small Signal Pulse Response vs. Capacitive Load, 200 mV p-p
Figure 11. ADV3222 Small Signal Pulse Response vs. Capacitive Load, 200 mV p-p
Rev. 0 | Page 8 of 20
ADV3221/ADV3222
2 0pF 2pF 4.7pF 10pF 2 0pF 2pF 4.7pF 10pF
1
1
VOUT (V)
0
VOUT (V)
08652-018
0
-1
-1
0
5
10 TIME (ns)
15
20
0
5
10 TIME (ns)
15
20
Figure 12. ADV3221 Large Signal Pulse Response vs. Capacitive Load, 2 V p-p
3000 1.5
Figure 15. ADV3222 Large Signal Pulse Response vs. Capacitive Load, 2 V p-p
4000 3000 1.5
2000
1.0 2000
1.0
SLEW RATE (V/s)
SLEW RATE (V/s)
1000 dv/dt 0
0.5
VOUT (V)
0.5 1000 0 -1000 -0.5 -2000 VOUT -3000 dv/dt 0
VOUT (V) VOUT (V)
08652-023 08652-022
0
-1000 VOUT
-0.5
-2000
-1.0
-1.0
08652-019
-3000 0 1 2 TIME (ns) 3 4
-1.5
-4000 0 1 2 TIME (ns) 3 4
-1.5
Figure 13. ADV3221 Large Signal Rising Slew Rate with 3 pF Load, 2 V p-p
3000 VOUT 1.5
Figure 16. ADV3222 Large Signal Rising Slew Rate with 3 pF Load, 2 V p-p
4000 3000 1.5
2000
1.0 2000
VOUT
SLEW RATE (V/s)
1.0
SLEW RATE (V/s)
1000 dv/dt 0
0.5
VOUT (V)
0.5 1000 0 -1000 -0.5 -2000 dv/dt 0
0
-1000
-0.5
-2000
-1.0 -3000
-1.0
08652-020
-3000 0 1 2 TIME (ns) 3 4
-1.5
-4000 0 1 2 TIME (ns) 3 4
-1.5
Figure 14. ADV3221 Large Signal Falling Slew Rate with 3 pF Load, 2 V p-p
Figure 17. ADV3222 Large Signal Falling Slew Rate with 3 pF Load, 2 V p-p
Rev. 0 | Page 9 of 20
08652-021
-2
-2
ADV3221/ADV3222
1.5 VOUT FALLING EDGE 2.1 1.9 1.7 0.5
VOUT (V) A0 (V)
1.5 VOUT FALLING EDGE
2.1 1.9 1.7
1.0
1.0
0.5
A0 (V) CS (V) CS (V)
08652-029 08652-028 08652-027
A0 0
VOUT (V)
1.5 1.3
A0 0
1.5 1.3
-0.5 1.1 -1.0 VOUT RISING EDGE 0.9 0.7 0 10 TIME (ns) 20 30
-0.5 1.1 -1.0 VOUT RISING EDGE 0.9 0.7 0 10 TIME (ns) 20 30
Figure 18. ADV3221 Switching Time
100 80 5 60 40 OUTPUT
VOUT (mV) CS (V)
08652-024
-1.5
-1.5
Figure 21. ADV3222 Switching Time
6 100 80 OUTPUT 60 4 3 2 1 0 -80
08652-025
6 5 4 3 2 1 0 -1 0 10 20 TIME (ns) 30 40 50
40
VOUT (mV)
20 0 -20 -40 -60 -80 -100 0 10 20 TIME (ns) 30 40 50 CS
20 0 -20 -40 -60 CS
-1
-100
Figure 19. ADV3221 Enable Glitch
3 2.1 1.9 CS 1
VOUT (V)
Figure 22. ADV3222 Enable Glitch
3 2.1 1.9 CS 1
VOUT (V) CS (V)
2 INPUT +1V
2 INPUT +0.5V
1.7 1.5
1.7 1.5
0 1.3 -1 INPUT -1V 1.1 -2 0.9 0.7 0 10 20 TIME (ns) 30 40
0 1.3 -1 INPUT -0.5V 1.1 -2 0.9 0.7 0 10 20 TIME (ns) 30 40
Figure 20. ADV3221 Enable On Timing
08652-026
-3
-3
Figure 23. ADV3222 Enable On Timing
Rev. 0 | Page 10 of 20
ADV3221/ADV3222
1.5 2.1 1.9 INPUT +1V 1.7 0.5
VOUT (V) CS (V)
0.5 1.5 2.1 1.9 INPUT +0.5V 1.7 1.5 1.3 -0.5 1.1 0.9 0.7 0 10 20 TIME (ns) 30 40
1.0
1.0
0 1.3 -0.5 INPUT -1V -1.0 1.1 0.9 0.7 0 10 20 TIME (ns) 30 40
0
INPUT -0.5V -1.0
Figure 24. ADV3221 Disable Timing
100 80 60 40
VOUT (mV)
Figure 27. ADV3222 Disable Timing
6 5
60 100 80 6 5 4 3 2 1 0 -80
08652-034
08652-031
A0
A0
4 3 2 1 0
VOUT (mV)
40 20 OUTPUT 0 -20 -40 -60
20 OUTPUT 0 -20 -40 -60 -80 -100 0 10 20 TIME (ns) 30 40 50
A0 (V)
-1
-100 0 10 20 TIME (ns) 30 40 50
-1
Figure 25. ADV3221 Switching Glitch Rising Edge
100 80 5 60 40 4 60 40
Figure 28. ADV3222 Switching Glitch Rising Edge
6 5 4 3 OUTPUT -20 -40 -60 2 1 0 -1 0 10 20 TIME (ns) 30 40 50
100 80
6
VOUT (mV)
A0 (V)
0 OUTPUT -20 -40 -60 -80 -100 0 10 20 TIME (ns) 30 40 50 A0 0 -1 2 1
0
-80
08652-032
A0
Figure 26. ADV3221 Switching Glitch Falling Edge
Figure 29. ADV3222 Switching Glitch Falling Edge
Rev. 0 | Page 11 of 20
08652-035
-100
A0 (V)
3
VOUT (mV)
20
20
A0 (V)
08652-033
08652-030
-1.5
-1.5
CS (V)
CS
VOUT (V)
1.5
CS
ADV3221/ADV3222
5 INPUT 4 3 2 1.00 0.75 0.50 4 3 2 INPUT 1.25 5 OUTPUT 1.00 0.75 0.50 0.25 ERROR 0 -1 -2 -3 -4
08652-036
1.25
OUTPUT (V)
ERROR (%)
ERROR 0 -1 OUTPUT -2 -3 -4 -5 0 1 2 3 4 5 TIME (ns) 6 7 8 9 10 -0.50 -0.75 -1.00 -1.25 0 -0.25
ERROR (%)
1
0.25
1
0 -0.25 -0.50 -0.75 -1.00
0
1
2
3
4
5 TIME (ns)
6
7
8
9
10
Figure 30. ADV3221 Settling Time, 2 V Step
10 0 -10 -20 10 0 -10 -20
Figure 33. ADV3222 Settling Time, 2 V Step
PSR (dB)
PSR (dB)
-30 PSR (V-) -40 PSR (V+) -50 -60 -70 -80
08652-037
-30 PSR (V-) -40 PSR (V+) -50 -60 -70 -80
08652-040
-90 0.1
1
10
100
1k
10k
-90 0.1
1
10
100
1k
10k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 31. ADV3221 PSR
200 180 160 140 NOISE (nV/ Hz) NOISE (nV/ Hz) 120 100 80 60 40 20
08652-038
Figure 34. ADV3222 PSR
200 180 160 140 120 100 80 60 40 20
08652-041
0 1k
10k
100k
1M
10M
100M
0 1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 32. ADV3221 Output Noise vs. Frequency
Figure 35. ADV3222 Output Noise vs. Frequency
Rev. 0 | Page 12 of 20
08652-039
-5
-1.25
OUTPUT (V)
ADV3221/ADV3222
-20 -30 -40
CROSSTALK (dB) CROSSTALK (dB)
08652-042
-20 -30 -40 -50 -60 -70 -80 -90 -100 1 10 100 FREQUENCY (MHz) 1k 10k
-50 -60 -70 -80 -90 -100 -110 1 10 100 FREQUENCY (MHz) 1k 10k
Figure 36. ADV3221 All Hostile Crosstalk
-20 -30 -40
CROSSTALK (dB) CROSSTALK (dB)
Figure 39. ADV3222 All Hostile Crosstalk
-20 -30 -40 -50 -60 -70 -80 -90 -100
08652-043 08652-046 08652-047
-50 -60 -70 -80 -90 -100 -110 1 10 100 FREQUENCY (MHz) 1k 10k
-110 1 10 100 FREQUENCY (MHz) 1k 10k
Figure 37. ADV3221 Crosstalk, Adjacent Channel
0 -10 -20
FEEDTHROUGH (dB) FEEDTHROUGH (dB)
Figure 40. ADV3222 Crosstalk, Adjacent Channel
0 -10 -20 -30 -40 -50 -60 -70 -80 -90
08652-044
-30 -40 -50 -60 -70 -80 -90 -100 1 10 100 FREQUENCY (MHz) 1k 10k
-100 1 10 100 FREQUENCY (MHz) 1k 10k
Figure 38. ADV3221 Off Isolation
Figure 41. ADV3222 Off Isolation
Rev. 0 | Page 13 of 20
08652-045
ADV3221/ADV3222
1M 0 -5 100k -10 -15 10k
INPUT IMPEDANCE ()
INPUT S11 (dB)
08652-048
-20 -25 -30 -35
1k
100
-40 -45
08652-051 08652-053 08652-052
10 0.1
1
10
100
1k
-50 0.1
1
10
100
1k
10k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 42. ADV3221/ADV3222 Input Impedance
1M
Figure 45. ADV3221/ADV3222 S11 (Including Evaluation Board)
1M
DISABLED OUTPUT IMPEDANCE ()
100k
DISABLED OUTPUT IMPEDANCE ()
08652-049
100k
10k
10k
1k
1k
100
100
10
10
1 0.1
1
10
100
1k
1 0.1
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 43. ADV3221 Disabled Output Impedance
10k 10k
Figure 46. ADV3222 Disabled Output Impedance
ENABLED OUTPUT IMPEDANCE ()
1k
ENABLED OUTPUT IMPEDANCE ()
1 10 100 1k 10k
08652-050
1k
100
100
10
10
1
1
0.1
0.1
0.01 0.1
0.01 0.1
1
10
100
1k
10k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 44. ADV3221 Enabled Output Impedance
Figure 47. ADV3222 Enabled Output Impedance
Rev. 0 | Page 14 of 20
ADV3221/ADV3222
5 INPUT 4 3 4 3 5
5 INPUT 4 3 OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2.5 2.0 1.5 OUTPUT INPUT VOLTAGE (V)
08652-059 08652-058
OUTPUT VOLTAGE (V)
2 1 0 -1 -2 -3 -4 -5 100
OUTPUT
2 1 0 -1 -2 -3 -4
2 1 0 -1 -2 -3 -4
1.0 0.5 0 -0.5 -1.0 -1.5 -2.0
08652-054
120
140
160 TIME (ns)
180
0
20
40 TIME (ns)
60
80
Figure 48. ADV3221 Overdrive Recovery
0 -10 HD3 10dBm -20 HD2 10dBm -30 -40 -50 HD3 0dBm -60 -70 -80
08652-055
Figure 51. ADV3222 Overdrive Recovery
70 60 50 40 30 20 10 0 10
HD2 0dBm
-90 10
100 INPUT FREQUENCY (MHz)
1k
SECOND-ORDER INTERCEPT (dBm)
HARMONIC DISTORTION (dBc)
100 INPUT FREQUENCY (MHz)
1k
Figure 49. ADV3222 Harmonic Distortion, RL = 100 , CL = 4 pF
30
Figure 52. ADV3222 Input Second-Order Intercept, RL = 100 , CL = 4 pF
20 18
P1dB GAIN COMPRESSION (dBm)
THIRD-ORDER INTERCEPT (dBm)
25
16 14 12 10 8 6 4 2
20
15
10
5
100 INPUT FREQUENCY (MHz)
1k
08652-056
0 10
0 10
100 FREQUENCY (MHz)
1k
Figure 50. ADV3222 Input Third-Order Intercept, RL = 100 , CL = 4 pF
Figure 53. ADV3222 Output P1dB, RL = 100 , CL = 4 pF
Rev. 0 | Page 15 of 20
08652-057
-5 200
-5
-2.5 100
ADV3221/ADV3222 CIRCUIT DIAGRAMS
V+
IN 1.8pF
08652-006
V-
Figure 54. ADV3221/ADV3222 Analog Input
Figure 57. ADV3221/ADV3222 Disabled Output
V+
OUT
A0, A1, CS CK1, CK2 100k (CK1, CK2 ONLY)
08652-007
1k
GND
Figure 55. ADV3221 Enabled Analog Output
Figure 58. ADV3221/ADV3222 Logic Input
V+
OUT
A0, A1, CK1, CK2, CS
1k
IN, OUT
08652-008
GND
V-
GND
Figure 56. ADV3222 Enabled Analog Output
Figure 59. ADV3221/ADV3222 ESD Schematic
Rev. 0 | Page 16 of 20
08652-011
1k
08652-010
V-
08652-009
OUT 2.8pF (ADV3221) 3.0pF (ADV3222)
ADV3221/ADV3222 THEORY OF OPERATION
The ADV3221/ADV3222 are dual-supply, high performance 4:1 analog multiplexers, optimized for switching between multiple video sources. High peak slew rates enable wide bandwidth operation for large input signals. Internal compensation provides for high phase margin, allowing low overshoot and fast settling for pulsed inputs. Low enabled and disabled power consumption make the ADV3221 and ADV3222 ideal for constructing larger arrays. The ADV3221/ADV3222 are organized as four input transconductance stages tied in parallel with a single output transimpedance stage followed by a unity-gain buffer. Internal voltage feedback sets the gain. The ADV3221 is configured as a gain of 1, while the ADV3222 uses a resistive feedback network and ground buffer to realize gain-of-two operation (see Figure 60).
V+ IN0 x1 V- V+ IN1 OUT
When not in use, the output can be placed in a low power, high impedance disabled mode via the CS logic input. This is useful when paralleling multiple ADV3221/ADV3222 devices in a system to create larger switching arrays. Switching between the inputs is controlled with the A0, A1, and CS logic inputs, which are latched through two stages of asynchronous latches. CK1 controls the first stage latch, and CK2 controls the second stage latch. The latch state is dependent on the level of the CK1 and CK2 signals, and it is not edge triggered. When using multiple ADV3221/ADV3222 devices in a switch design, this double buffered logic allows the use of the CK2 signal to simultaneously update all ADV3221/ADV3222 devices in a system. The A0 and A1 logic inputs select which input is connected to the output (A1 is the most significant bit, A0 is the least significant bit), and the CS logic input determines whether the output is enabled or disabled.
V- (2 MORE INPUTS) V+ GND 1k
08652-060
1k
V-
Figure 60. Conceptual Diagram of ADV3222
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ADV3221/ADV3222 APPLICATIONS INFORMATION
The ADV3221 and ADV3222 are high speed multiplexers used to switch video or RF signals. The low output impedance of the ADV3221/ADV3222 allows the output environment to be optimized for use in 75 or 50 systems by choosing the appropriate series termination resistor. For composite video applications, the ADV3222 (gain of +2) is typically used to provide compensation for the loss of the output termination.
TERMINATION
For a controlled impedance situation, termination resistors are required at the inputs and output of the device. The input termination should be a shunt resistor to ground with a value matching the characteristic impedance of the input trace. To reduce reflections, place the input termination resistor as close to the device input pin as possible. To minimize the input-toinput crosstalk, it is important to utilize a low inductance shield between input traces to isolate each input. Consideration of ground current paths must be taken to minimize loop currents in the shields to prevent them from providing a coupling medium for crosstalk. For proper matching, the output series termination resistor should be the same value as the characteristic impedance of the output trace and placed as close to the output of the device as possible. This placement reduces the high frequency effect of series parasitic inductance, which can affect gain flatness and -3 dB bandwidth.
CK1/CK2 OPERATION
The ADV3221/ADV3222 provide a double latched architecture for the A0, A1 (channel selection) and CS (output enable) logic. This allows for simultaneous update of multiple devices in bank switching applications or large multiplexer systems consisting of multiple devices connected to common output busses. Holding CK1 and CK2 low places the ADV3221/ADV3222 in a transparent mode. In transparent mode, all logic changes to A0, A1, and CS immediately affects the input selection and output enable/disable.
CIRCUIT LAYOUT
Use of proper high speed design techniques is important to ensure optimum performance. Use a low inductance ground plane for power supply bypassing and to provide high quality return paths for the input and output signals. For best performance, it is recommended that power supplies be bypassed with 0.1 F ceramic capacitors as close to the body of the device as possible. To provide stored energy for lower frequency, high current output driving, place 10 F tantalum capacitors farther from the device. The input and output signal paths should be stripline or microstrip controlled impedance. Video systems typically use 75 characteristic impedance, whereas RF systems typically use 50 . Various calculators are available to calculate the trace geometry required to produce the proper characteristic impedance.
CAPACITIVE LOAD
A high frequency output can have difficulties when driving a large capacitive load, usually resulting in peaking in the frequency domain or overshoot in the time domain. If these effects become too large, oscillation can result. The response of the device under various capacitive loads is shown in Figure 6 through Figure 12, and in Figure 15. If a condition arises where excessive load capacitance is encountered and the overshoot is too great or the device oscillates, a small series resistor of a few tens of ohms can be used to improve the performance.
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ADV3221/ADV3222 OUTLINE DIMENSIONS
10.00 (0.3937) 9.80 (0.3858)
16 1 9 8
4.00 (0.1575) 3.80 (0.1496)
6.20 (0.2441) 5.80 (0.2283)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
1.75 (0.0689) 1.35 (0.0531) SEATING PLANE
0.50 (0.0197) 0.25 (0.0098) 8 0 1.27 (0.0500) 0.40 (0.0157)
45
0.25 (0.0098) 0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
060606-A
Figure 61. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body [R-16] Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model 1 ADV3221ARZ ADV3221ARZ-RL ADV3221ARZ-R7 ADV3222ARZ ADV3222ARZ-RL ADV3222ARZ-R7 ADV3221-EVALZ ADV3222-EVALZ
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 16-Lead SOIC_N 16-Lead SOIC_N, 13" Reel 16-Lead SOIC_N, 7" Reel 16-Lead SOIC_N 16-Lead SOIC_N, 13" Reel 16-Lead SOIC_N, 7" Reel Evaluation Board Evaluation Board
Package Option R-16 R-16 R-16 R-16 R-16 R-16
Z = RoHS Compliant Part.
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ADV3221/ADV3222 NOTES
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08652-0-3/10(0)
Rev. 0 | Page 20 of 20

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