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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
MITSUBISHI 4-BIT SINGLE-CHIP MICROCOMPUTER 4500 SERIES
4513/4514
Group
User's Manual
keep safety first in your circuit designs ! q Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials q These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. q Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. q All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. q Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. q The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. q If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of JAPAN and/or the country of destination is prohibited. q Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Preface
This user's manual describes the hardware and instructions of Mitsubishi's 4513/4514 Group CMOS 4-bit microcomputer. After reading this manual, the user should have a through knowledge of the functions and features of the 4513/4514 Group and should be able to fully utilize the product. The manual starts with specifications and ends with application examples. In this manual, the 4514 Group is mainly described. The differences from the 4513 Group are described at the related points.
BEFORE USING THIS USER'S MANUAL
This user's manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development.
1. Organization
CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. CHAPTER 3 APPENDIX This chapter includes precautions for systems development using the microcomputer, the mask ROM confirmation forms (mask ROM version), and mark specification forms which are to be submitted when ordering. Be sure to refer to this chapter because this chapter also includes necessary information for systems development. Note: In this manual, the 4514 Group is mainly described. The differences from the 4513 Group are described at the related points.
Table of contents
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-3 FEATURES ...................................................................................................................................... 1-3 APPLICATION ................................................................................................................................ 1-3 PIN CONFIGURATION .................................................................................................................. 1-4 BLOCK DIAGRAM ......................................................................................................................... 1-6 PERFORMANCE OVERVIEW ....................................................................................................... 1-8 PIN DESCRIPTION ........................................................................................................................ 1-9 MULTIFUNCTION ................................................................................................................... 1-10 CONNECTIONS OF UNUSED PINS ................................................................................... 1-10 PORT FUNCTION .................................................................................................................. 1-11 DEFINITION OF CLOCK AND CYCLE ............................................................................... 1-11 PORT BLOCK DIAGRAMS ................................................................................................... 1-12 FUNCTION BLOCK OPERATIONS ........................................................................................... 1-17 CPU .......................................................................................................................................... 1-17 PROGRAM MEMOY (ROM) .................................................................................................. 1-20 DATA MEMORY (RAM) ......................................................................................................... 1-21 INTERRUPT FUNCTION ....................................................................................................... 1-22 EXTERNAL INTERRUPTS .................................................................................................... 1-26 TIMERS ................................................................................................................................... 1-29 WATCHDOG TIMER .............................................................................................................. 1-35 SERIAL I/O.............................................................................................................................. 1-36 A-D CONVERTER .................................................................................................................. 1-41 VOLTAGE COMPARATOR.................................................................................................... 1-47 RESET FUNCTION ................................................................................................................ 1-49 VOLTAGE DROP DETECTION CIRCUIT ........................................................................... 1-52 RAM BACK-UP MODE .......................................................................................................... 1-53 CLOCK CONTROL ................................................................................................................. 1-57 ROM ORDERING METHOD ....................................................................................................... 1-58 LIST OF PRECAUTIONS ............................................................................................................ 1-59 SYMBOL ........................................................................................................................................ 1-62 LIST OF INSTRUCTION FUNCTION ........................................................................................ 1-63 INSTRUCTION CODE TABLE.................................................................................................... 1-66 MACHINE INSTRUCTIONS ........................................................................................................ 1-70 CONTROL REGISTERS .............................................................................................................. 1-84 BUILT-IN PROM VERSION ........................................................................................................ 1-88
4513/4514 Group User's Manual
i
Table of contents CHAPTER 2 APPLICATION
2.1 I/O pins .................................................................................................................................... 2-2 2.1.1 I/O ports .......................................................................................................................... 2-2 2.1.2 Related registers ............................................................................................................ 2-4 2.1.3 Port application examples ............................................................................................. 2-7 2.1.4 Notes on use .................................................................................................................. 2-9 2.2 Interrupts ............................................................................................................................... 2-11 2.2.1 Interrupt functions ........................................................................................................ 2-11 2.2.2 Related registers .......................................................................................................... 2-13 2.2.3 Interrupt application examples.................................................................................... 2-16 2.2.4 Notes on use ................................................................................................................ 2-25 2.3 Timers .................................................................................................................................... 2-26 2.3.1 Timer functions ............................................................................................................. 2-26 2.3.2 Related registers .......................................................................................................... 2-27 2.3.3 Timer application examples ........................................................................................ 2-30 2.3.4 Notes on use ................................................................................................................ 2-39 2.4 Serial I/O ................................................................................................................................ 2-40 2.4.1 Carrier functions ........................................................................................................... 2-40 2.4.2 Related registers .......................................................................................................... 2-41 2.4.3 Operation description ................................................................................................... 2-42 2.4.4 Serial I/O application example ................................................................................... 2-45 2.4.5 Notes on use ................................................................................................................ 2-48 2.5 A-D converter ....................................................................................................................... 2-49 2.5.1 Related registers .......................................................................................................... 2-50 2.5.2 A-D converter application examples .......................................................................... 2-51 2.5.3 Notes on use ................................................................................................................ 2-52 2.6 Voltage comparator ............................................................................................................. 2-54 2.6.1 Voltage comparator function ....................................................................................... 2-54 2.6.2 Related registers .......................................................................................................... 2-54 2.6.3 Notes on use ................................................................................................................ 2-55 2.7 Reset....................................................................................................................................... 2-56 2.7.1 Reset circuit .................................................................................................................. 2-56 2.7.2 Internal state at reset .................................................................................................. 2-57 2.8 Voltage drop detection circuit.......................................................................................... 2-58 2.9 RAM back-up ........................................................................................................................ 2-59 2.9.1 RAM back-up mode ..................................................................................................... 2-59 2.9.2 Related register ............................................................................................................ 2-60 2.9.3 Notes on use ................................................................................................................ 2-62 2.10 Oscillation circuit .............................................................................................................. 2-63 2.10.1 Oscillation circuit ........................................................................................................ 2-63 2.10.2 Oscillation operation .................................................................................................. 2-64 2.10.3 Notes on use .............................................................................................................. 2-64
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4513/4514 Group User's Manual
Table of contents CHAPTER 3 APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2 3.1.1 Absolute maximum ratings ............................................................................................ 3-2 3.1.2 Recommended operating conditions ............................................................................ 3-3 3.1.3 Electrical characteristics ................................................................................................ 3-5 3.1.4 A-D converter recommended operating conditions.................................................... 3-6 3.1.5 Voltage drop detection circuit characteristics............................................................. 3-6 3.1.6 Voltage comparator characteristics .............................................................................. 3-7 3.1.7 Basic timing diagram ..................................................................................................... 3-7 3.2 Typical characteristics ......................................................................................................... 3-8 3.2.1 VDD-IDD characteristics ................................................................................................. 3-8 3.2.2 VOL-IOL characteristics ................................................................................................ 3-11 3.2.3 VOH-IOH characteristics (Port P5) ............................................................................. 3-13 3.2.4 VDD-RPU characteristics (Ports P0, P1) ................................................................... 3-13 3.2.5 A-D converter typical characteristics ......................................................................... 3-14 3.2.6 Analog input current characteristics pins AIN0-AIN7 ............................................................ 3-17 3.2.7 VDD-VIH/VIL characteristics ......................................................................................... 3-19 3.2.8 Detection voltage temperature characteristics of voltage drop detection circuit . 3-20 3.3 List of precautions .............................................................................................................. 3-21 3.4 Notes on noise ..................................................................................................................... 3-24 3.4.1 Shortest wiring length .................................................................................................. 3-24 3.4.2 Connection of bypass capacitor across VSS line and VDD line ............................ 3-26 3.4.3 Wiring to analog input pins ........................................................................................ 3-27 3.4.4 Oscillator concerns....................................................................................................... 3-27 3.4.5 Setup for I/O ports ....................................................................................................... 3-28 3.4.6 Providing of watchdog timer function by software .................................................. 3-28 3.5 Mask ROM order confirmation form ............................................................................... 3-30 3.6 Mark specification form ..................................................................................................... 3-36 3.7 Package outline ................................................................................................................... 3-39
4513/4514 Group User's Manual
iii
List of figures
List of figures
CHAPTER 1 HARDWARE
PIN CONFIGURATION (TOP VIEW) 4513 Group ..................................................................... 1-4 PIN CONFIGURATION (TOP VIEW) 4514 Group ..................................................................... 1-5 BLOCK DIAGRAM (4513 Group) ................................................................................................. 1-6 BLOCK DIAGRAM (4514 Group) ................................................................................................. 1-7 PORT BLOCK DIAGRAMS ......................................................................................................... 1-12 External interrupt circuit structure .............................................................................................. 1-16 Fig. 1 AMC instruction execution example ............................................................................... 1-17 Fig. 2 RAR instruction execution example ............................................................................... 1-17 Fig. 3 Registers A, B and register E ........................................................................................ 1-17 Fig. 4 TABP p instruction execution example .......................................................................... 1-17 Fig. 5 Stack registers (SKs) structure ....................................................................................... 1-18 Fig. 6 Example of operation at subroutine call ....................................................................... 1-18 Fig. 7 Program counter (PC) structure ..................................................................................... 1-19 Fig. 8 Data pointer (DP) structure ............................................................................................. 1-19 Fig. 9 SD instruction execution example .................................................................................. 1-19 Fig. 10 ROM map of M34514M8/E8 ......................................................................................... 1-20 Fig. 11 Page 1 (addresses 008016 to 00FF16) structure ....................................................... 1-20 Fig. 12 RAM map ......................................................................................................................... 1-21 Fig. 13 Program example of interrupt processing ................................................................... 1-23 Fig. 14 Internal state when interrupt occurs ............................................................................ 1-23 Fig. 15 Interrupt system diagram ............................................................................................... 1-23 Fig. 16 Interrupt sequence .......................................................................................................... 1-25 Fig. 17 External interrupt circuit structure ................................................................................ 1-26 Fig. 18 Auto-reload function ....................................................................................................... 1-29 Fig. 19 Timers structure .............................................................................................................. 1-31 Fig. 20 Watchdog timer function ................................................................................................ 1-35 Fig. 21 Program example to enter the RAM back-up mode when using the watchdog timer .... 1-35 Fig. 22 Serial I/O structure ......................................................................................................... 1-36 Fig. 23 Serial I/O register state when transferring.................................................................. 1-37 Fig. 24 Serial I/O connection example...................................................................................... 1-38 Fig. 25 Timing of serial I/O data transfer ................................................................................. 1-39 Fig. 26 A-D conversion circuit structure ................................................................................... 1-41 Fig. 27 A-D conversion timing chart.......................................................................................... 1-44 Fig. 28 Setting registers .............................................................................................................. 1-44 Fig. 29 Comparator operation timing chart............................................................................... 1-45 Fig. 30 Definition of A-D conversion accuracy ........................................................................ 1-46 Fig. 31 Voltage comparator structure ........................................................................................ 1-47 Fig. 32 Reset release timing ...................................................................................................... 1-49 Fig. 33 RESET pin input waveform and reset operation ....................................................... 1-49 Fig. 34 Power-on reset circuit example .................................................................................... 1-50 Fig. 35 Internal state at reset .................................................................................................... 1-51 Fig. 36 Voltage drop detection reset circuit ............................................................................. 1-52 Fig. 37 Voltage drop detection circuit operation waveform.................................................... 1-52 Fig. 38 State transition ................................................................................................................ 1-55 Fig. 39 Set source and clear source of the P flag ................................................................. 1-55 Fig. 40 Start condition identified example using the SNZP instruction ................................ 1-55 Fig. 41 Clock control circuit structure ....................................................................................... 1-57
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4513/4514 Group User's Manual
List of figures
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 42 43 44 45 46 47 48 49 50 51 52 Ceramic resonator external circuit ............................................................................... 1-58 External clock input circuit ............................................................................................ 1-58 External 0 interrupt program example ......................................................................... 1-59 External 1 interrupt program example ......................................................................... 1-59 A-D converter operating mode program example ...................................................... 1-60 Analog input external circuit example-1 ...................................................................... 1-60 Analog input external circuit example-2 ...................................................................... 1-60 Pin configuration of built-in PROM version of 4513 Group...................................... 1-88 Pin configuration of built-in PROM version of 4514 Group...................................... 1-88 PROM memory map ....................................................................................................... 1-89 Flow of writing and test of the product shipped in blank......................................... 1-89
CHAPTER 2 APPLICATION
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 Key input by key scan................................................................................................. 2-7 2.1.2 Key scan input timing .................................................................................................. 2-8 2.2.1 INT0 interrupt operation example ............................................................................ 2-17 2.2.2 INT0 interrupt setting example ................................................................................. 2-18 2.2.3 INT1 interrupt operation example ............................................................................ 2-19 2.2.4 INT1 interrupt setting example ................................................................................. 2-20 2.2.5 Timer 1 constant period interrupt setting example................................................ 2-21 2.2.6 Timer 2 constant period interrupt setting example................................................ 2-22 2.2.7 Timer 3 constant period interrupt setting example................................................ 2-23 2.2.8 Timer 4 constant period interrupt setting example................................................ 2-24 2.3.1 Peripheral circuit example ......................................................................................... 2-30 2.3.2 Watchdog timer function............................................................................................ 2-31 2.3.3 Constant period measurement setting example ..................................................... 2-32 2.3.4 CNTR0 output setting example ................................................................................ 2-33 2.3.5 CNTR1 input setting example .................................................................................. 2-34 2.3.6 CNTR0 output control setting example ................................................................... 2-35 2.3.7 Timer start by external input setting example (1) ................................................. 2-36 2.3.8 Timer start by external input setting example (2) ................................................. 2-37 2.3.9 Watchdog timer setting example .............................................................................. 2-38 2.4.1 Serial I/O block diagram ........................................................................................... 2-40 2.4.2 Serial I/O connection example ................................................................................. 2-42 2.4.3 Serial I/O register state when transmitting/receiving ............................................ 2-42 2.4.4 Serial I/O transfer timing ........................................................................................... 2-43 2.4.5 Master serial I/O setting example ............................................................................ 2-46 2.4.6 Slave serial I/O example ........................................................................................... 2-47 2.4.7 Input waveform of external clock ............................................................................. 2-48 2.5.1 A-D converter structure ............................................................................................. 2-49 2.5.2 A-D conversion mode setting example ................................................................... 2-51 2.5.3 Analog input external circuit example-1 .................................................................. 2-52 2.5.4 Analog input external circuit example-2 .................................................................. 2-52 2.5.5 A-D converter operating mode program example.................................................. 2-52 2.7.1 Power-on reset circuit example ................................................................................ 2-56 2.7.2 Oscillation stabilizing time after system is released from reset .......................... 2-56 2.7.3 Internal state at reset ................................................................................................ 2-57 2.8.1 Voltage drop detection reset circuit ......................................................................... 2-58 2.8.2 Voltage drop detection circuit operation waveform ............................................... 2-58 2.9.1 Start condition identified example ............................................................................ 2-60 2.10.1 Oscillation circuit example connecting ceramic resonator externally................ 2-63 2.10.2 Structure of clock control circuit ............................................................................ 2-64
4513/4514 Group User's Manual
v
List of figures CHAPTER 3 APPENDIX
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.2.1 A-D conversion characteristics data ........................................................................ 3-14 44 External 0 interrupt program example ......................................................................... 3-21 45 External 1 interrupt program example ......................................................................... 3-21 46 A-D converter operating mode program example ...................................................... 3-22 47 Analog input external circuit example-1 ...................................................................... 3-22 48 Analog input external circuit example-2 ...................................................................... 3-22 3.4.1 Selection of packages ............................................................................................... 3-24 3.4.2 Wiring for the RESET input pin ............................................................................... 3-24 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-25 3.4.4 Wiring for CNVSS pin ................................................................................................. 3-25 3.4.5 Wiring for the VPP pin of the One Time PROM version ...................................... 3-26 3.4.6 Bypass capacitor across the VSS line and the VDD line ...................................... 3-26 3.4.7 Analog signal line and a resistor and a capacitor ................................................ 3-27 3.4.8 Wiring for a large current signal line ...................................................................... 3-27 3.4.9 Wiring to a signal line where potential levels change frequently ....................... 3-28 3.4.10 VSS pattern on the underside of an oscillator ..................................................... 3-28 3.4.11 Watchdog timer by software ................................................................................... 3-29
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4513/4514 Group User's Manual
List of tables
List of tables
CHAPTER 1 HARDWARE
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Selection of system clock ................................................................................................ 1-11 1 ROM size and pages .................................................................................................... 1-20 2 RAM size ........................................................................................................................ 1-21 3 Interrupt sources ............................................................................................................ 1-22 4 Interrupt request flag, interrupt enable bit and skip instruction.............................. 1-22 5 Interrupt enable bit function ......................................................................................... 1-22 6 Interrupt control registers ............................................................................................. 1-24 7 External interrupt activated conditions........................................................................ 1-26 8 External interrupt control registers .............................................................................. 1-28 9 Function related timers ................................................................................................. 1-30 10 Timer control registers ................................................................................................ 1-32 11 Serial I/O pins .............................................................................................................. 1-36 12 Serial I/O mode register ............................................................................................. 1-36 13 Processing sequence of data transfer from master to slave ................................ 1-40 14 A-D converter characteristics ..................................................................................... 1-41 15 A-D control registers ................................................................................................... 1-42 16 Change of successive comparison register AD during A-D conversion .............. 1-43 17 Voltage comparator characteristics ........................................................................... 1-47 18 Voltage comparator control register Q3 ................................................................... 1-48 19 Port state at reset ....................................................................................................... 1-50 20 Functions and states retained at RAM back-up ..................................................... 1-53 21 Return source and return condition .......................................................................... 1-54 22 Key-on wakeup control register, pull-up control register, and interrupt control . 1-56 23 Clock control register MR .......................................................................................... 1-57 24 Maximum value of external clock oscillation frequency ......................................... 1-58 25 Product of built-in PROM version ............................................................................. 1-88 26 Programming adapters ................................................................................................ 1-89
CHAPTER 2 APPLICATION
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.2.1 2.2.2 2.2.3 2.2.4 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.4.1 2.4.2 Pull-up control register PU0 .................................................................................... 2-4 Key-on wakeup control register K0 ........................................................................ 2-5 A-D control register Q2 ............................................................................................ 2-5 Direction register FR0 .............................................................................................. 2-6 Timer control register W6 ........................................................................................ 2-6 connections of unused pins ................................................................................... 2-10 Interrupt control register V1................................................................................... 2-14 Interrupt control register V2................................................................................... 2-14 Interrupt control register I1 .................................................................................... 2-15 Interrupt control register I2 .................................................................................... 2-15 Interrupt control register V1................................................................................... 2-27 Interrupt control register V2................................................................................... 2-27 Timer control register W1 ...................................................................................... 2-28 Timer control register W2 ...................................................................................... 2-28 Timer control register W3 ...................................................................................... 2-29 Timer control register W4 ...................................................................................... 2-29 Serial I/O mode register J1 ................................................................................... 2-41 Recommended operating conditions (serial I/O) ................................................. 2-48
4513/4514 Group User's Manual
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List of tables
Table Table Table Table Table Table Table Table Table Table Table Table 2.5.1 A-D control register Q1 .......................................................................................... 2-50 2.5.2 A-D control register Q2 .......................................................................................... 2-50 2.5.3 Recommended operating conditions (when using A-D converter) ................... 2-53 2.6.1 Voltage comparator control register Q3 ............................................................... 2-54 2.9.1 Functions and states retained at RAM back-up mode ...................................... 2-59 2.9.2 Return source and return condition ...................................................................... 2-60 2.9.3 Start condition identification................................................................................... 2-60 2.9.4 Key-on wakeup control register K0 ...................................................................... 2-60 2.9.5 Pull-up control register PU0 .................................................................................. 2-61 2.9.6 Interrupt control register I1 .................................................................................... 2-61 2.9.7 Interrupt control register I2 .................................................................................... 2-62 2.10.1 Maximum value of oscillation frequency and supply voltage ......................... 2-63
CHAPTER 3 APPENDIX
Table Table Table Table Table Table Table Table Table 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 3.1.9 Absolute maximum ratings ....................................................................................... 3-2 Recommended operating conditions 1 ................................................................... 3-3 Recommended operating conditions 2 ................................................................... 3-4 Electrical characteristics ........................................................................................... 3-5 A-D converter recommended operating conditions............................................... 3-6 A-D converter characteristics .................................................................................. 3-6 Voltage drop detection circuit characteristics........................................................ 3-6 Voltage comparator recommended operating conditions ..................................... 3-7 Voltage comparator characteristics ......................................................................... 3-7
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4513/4514 Group User's Manual
CHAPTER 1 HARDWARE
DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION BLOCK DIAGRAM PERFORMANCE OVERVIEW PIN DESCRIPTION FUNCTION BLOCK OPERATIONS ROM ORDERING METHOD LIST OF PRECAUTIONS SYMBOL LIST OF INSTRUCTION FUNCTION INSTRUCTION CODE TABLE MACHINE INSTRUCTIONS CONTROL REGISTERS BUILT-IN PROM VERSION
HARDWARE
1-2
4513/4514 Group User's Manual
HARDWARE
DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION
DESCRIPTION
The 4513/4514 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with serial I/O, four 8-bit timers (each timer has a reload register), and 10-bit A-D conver ter. The various microcomputers in the 4513/4514 Group include variations of the built-in memory type and package as shown in the table below.
FEATURES
qMinimum instruction execution time ................................ 0.75 s (at 4.0 MHz oscillation frequency, in high-speed mode, VDD = 4.0 V to 5.5 V) qSupply voltage * Middle-speed mode ...... 2.5 V to 5.5 V (at 4.2 MHz oscillation frequency, for Mask ROM version and One Time PROM version) ...... 2.0 V to 5.5 V (at 3.0 MHz oscillation frequency, for Mask ROM version) (Operation voltage of A-D conversion: 2.7 V to 5.5 V) * High-speed mode ...... 4.0 V to 5.5 V (at 4.2 MHz oscillation frequency, for Mask ROM version and One Time PROM version) ...... 2.5 V to 5.5 V (at 2.0 MHz oscillation frequency, for Mask ROM version and One Time PROM version) ...... 2.0 V to 5.5 V (at 1.5 MHz oscillation frequency, for Mask ROM version) (Operation voltage of A-D conversion: 2.7 V to 5.5 V) ROM (PROM) size (! 10 bits) 2048 words 4096 words 4096 words 6144 words 8192 words 8192 words 6144 words 8192 words 8192 words
qTimers Timer 1 ...................................... 8-bit timer with a reload register Timer 2 ...................................... 8-bit timer with a reload register Timer 3 ...................................... 8-bit timer with a reload register Timer 4 ...................................... 8-bit timer with a reload register qInterrupt ........................................................................ 8 sources qSerial I/O ....................................................................... 8 bit-wide qA-D converter .................. 10-bit successive comparison method qVoltage comparator ........................................................ 2 circuits qWatchdog timer ................................................................. 16 bits qVoltage drop detection circuit qClock generating circuit (ceramic resonator) qLED drive directly enabled (port D)
APPLICATION
Electrical household appliance, consumer electronic products, office automation equipment, etc.
Product M34513M2-XXXSP/FP M34513M4-XXXSP/FP M34513E4SP/FP (Note) M34513M6-XXXFP M34513M8-XXXFP M34513E8FP (Note) M34514M6-XXXFP M34514M8-XXXFP M34514E8FP (Note)
Note: shipped in blank
RAM size (! 4 bits) 128 words 256 words 256 words 384 words 384 words 384 words 384 words 384 words 384 words
Package SP: 32P4B FP: 32P6B-A SP: 32P4B FP: 32P6B-A SP: 32P4B FP: 32P6B-A 32P6B-A 32P6B-A 32P6B-A 42P2R-A 42P2R-A 42P2R-A
ROM type Mask ROM Mask ROM One Time PROM Mask ROM Mask ROM One Time PROM Mask ROM Mask ROM One Time PROM
4513/4514 Group User's Manual
1-3
HARDWARE
PIN CONFIGURATION
PIN CONFIGURATION (TOP VIEW) 4513 Group
D0 D1 D2 D3 D4 D5 D6/CNTR0 D7/CNTR1 P20/SCK P21/SOUT P22/SIN RESET CNVSS XOUT XIN VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
P13 P12 P11 P10 P03 P02 P01 P00 AIN3/CMP1+ AIN2/CMP1AIN1/CMP0+ AIN0/CMP0P31/INT1 P30/INT0 VDCE VDD
M34513Mx-XXXSP
29 P13 26 P10 28 P12 25 P03 27 P11
Outline 32P4B
D3 1 D4 2 D5 3 D6/CNTR0 4 D7/CNTR1 5 P20/SCK 6 P21/SOUT 7 P22/SIN 8
P30/INT0 16
11
31 D1
30 D0
M34513E4SP
32 D2
24 P02 23 P01 22 P00 21 20 19 18
M34513Mx-XXXFP M34513ExFP
AIN3/CMP1+ AIN2/CMP1AIN1/CMP0+
AIN0/CMP017 P31/INT1
VDD 14 VSS 13 XIN 12 CNVSS 10 RESET 9 VDCE 15
Outline 32P6B-A
1-4
4513/4514 Group User's Manual
XOUT
HARDWARE
PIN CONFIGURATION
PIN CONFIGURATION (TOP VIEW) 4514 Group
P13 1 D0 2 D1 3 D2 4 D3 5 D4 6
42 P12 41 P11 40 P10 39 P03 38 P02 37 P01 36 P00 35 P43/AIN7 34 P42/AIN6 33 P41/AIN5 32 P40/AIN4 31 AIN3/CMP1+ 30 AIN2/CMP129 AIN1/CMP0+ 28 AIN0/CMP027 P33 26 P32 25 P31/INT1 24 P30/INT0 23 VDCE 22 VDD
M34514Mx-XXXFP
M34514E8FP
D5 7 D6/CNTR0 8 D7/CNTR1 9 P50 10 P51 11 P52 12 P53 13 P20/SCK P21/SOUT
14 15
P22/SIN 16 RESET 17 CNVSS 18 XOUT
19
XIN 20 VSS 21
Outline 42P2R-A
4513/4514 Group User's Manual
1-5
1-6
4 3 2 8 4 Port P0 | [ Port P1 go 1 Port P2 Port P3 Port D Voltage comparator (2 circuits) System clock generating circuit XIN-XOUT
BLOCK DIAGRAM
HARDWARE
I/O port
Internal peripheral functions
BLOCK DIAGRAM (4513 Group)
Timer
Timer 1 (8 bits)
Timer 2 (8 bits)
Timer 3 (8 bits) Voltage drop detection circuit
Timer 4 (8 bits)
Watchdog timer (16 bits)
Memory
ROM
2048, 4096,6144, 8192 words x 10 bits
4513/4514 Group User's Manual
A-D converter (10 bits ! 4 ch)
4500 Series CPU core
ALU (4 bits)
Serial I/O (8 bits ! 1)
RAM
128, 256, 384 words x 4 bits
Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level)
4 4 4 4 8 3
4
I/O port
Port P1 Port P2 Port P3 Port P4 Port P5 Port D
Port P0
Internal peripheral functions
Voltage comparator (2 circuits) System clock generating circuit XIN--XOUT
BLOCK DIAGRAM (4514 Group)
Timer
Timer 1 (8 bits)
Timer 2 (8 bits)
Timer 3 (8 bits) Voltage drop detection circuit
Timer 4 (8 bits)
Watchdog timer (16 bits)
Memory
ROM
6144, 8192 words x 10 bits
4513/4514 Group User's Manual
A-D converter (10 bits ! 8 ch)
4500 Series CPU core
ALU (4 bits)
Serial I/O (8 bits ! 1)
RAM
384 words x 4 bits
Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level)
BLOCK DIAGRAM
HARDWARE
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HARDWARE
PERFORMANCE OVERVIEW
PERFORMANCE OVERVIEW
Parameter 4513 Group Number of 4514 Group basic instructions Minimum instruction execution time M34513M2 Memory sizes ROM M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 RAM M34513M2 M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 I/O (Input is Input/Output D0-D7 examined by ports skip decision) P00-P03 I/O P10-P13 I/O P20-P22 Input P30-P33 I/O P40-P43 P50-P53 CNTR0 CNTR1 INT0 INT1 Timer 1 Timer 2 Timer 3 Timer 4 I/O I/O I/O I/O Input Input Function 123 128 0.75 s (at 4.0 MHz oscillation frequency, in high-speed mode) 2048 words ! 10 bits 4096 words ! 10 bits 6144 words ! 10 bits 8192 words ! 10 bits 6144 words ! 10 bits 8192 words ! 10 bits 128 words ! 4 bits 256 words ! 4 bits 384 words ! 4 bits 384 words ! 4 bits 384 words ! 4 bits 384 words ! 4 bits Eight independent I/O ports; ports D6 and D7 are also used as CNTR0 and CNTR1, respectively. 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. 3-bit input port; ports P20, P21 and P22 are also used as SCK, SOUT and SIN, respectively. 4-bit I/O port (2-bit I/O port for the 4513 Group); ports P30 and P31 are also used as INT0 and INT1, respectively. The 4513 Group does not have ports P32, P33. 4-bit I/O port; The 4513 Group does not have this port. 4-bit I/O port with a direction register; The 4513 Group does not have this port. 1-bit I/O; CNTR0 pin is also used as port D6. 1-bit I/O; CNTR1 pin is also used as port D7. 1-bit input; INT0 pin is also used as port P30 and equipped with a key-on wakeup function. 1-bit input; INT1 pin is also used as port P31 and equipped with a key-on wakeup function. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register is also used as an event counter. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register is also used as an event counter. 10-bit wide, This is equipped with an 8-bit comparator function. 2 circuits (CMP0, CMP1) 8-bit ! 1 8 (two for external, four for timer, one for A-D, and one for serial I/O) 1 level 8 levels CMOS silicon gate 32-pin plastic molded SDIP (32P4B)/LQFP(32P6B-A) 42-pin plastic molded SSOP (42P2R-A) -20 C to 85 C 2.0 V to 5.5 V for Mask ROM version, 2.5 V to 5.5 V for One Time PROM version (Refer to the electrical characteristics because the supply voltage depends on the oscillation frequency.) 1.8 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in middle- speed mode, output transistors in the cut-off state) 3.0 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors in the cut-off state) 0.1 A (at room temperature, VDD = 5 V, output transistors in the cut-off state)
Timers
A-D converter Voltage comparator Serial I/O Sources Interrupt Nesting Subroutine nesting Device structure 4513 Group Package 4514 Group Operating temperature range Supply voltage Active mode Power dissipation (typical value) RAM back-up mode
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HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Pin VDD VSS VDCE Name Input/Output Power supply -- Ground -- Voltage drop detecInput tion circuit enable CNVSS Reset input -- I/O Input Output I/O Function Connected to a plus power supply. Connected to a 0 V power supply. VDCE pin is used to control the operation/stop of the voltage drop detection circuit. When "H" level is input to this pin, the circuit is operating. When "L" level is inpu to this pin, the circuit is stopped. Connect CNVSS to VSS and apply "L" (0V) to CNVSS certainly. An N-channel open-drain I/O pin for a system reset. When the watchdog timer causes the system to be reset or system reset is performed by the voltage drop detection circuit, the RESET pin outputs "L" level. I/O pins of the system clock generating circuit. XIN and XOUT can be connected to ceramic resonator. A feedback resistor is built-in between them. Each pin of port D has an independent 1-bit wide I/O function. Each pin has an output latch. For input use, set the latch of the specified bit to "1." The output structure is N-channel open-drain. Ports D6 and D7 are also used as CNTR0 and CNTR1, respectively. Each of ports P0 and P1 serves as a 4-bit I/O port, and it can be used as inputs when the output latch is set to "1." The output structure is N-channel open-drain. Every pin of the ports has a key-on wakeup function and a pull-up function. Both functions can be switched by software. 3-bit input port. Ports P20, P21 and P22 are also used as SCK, SOUT and SIN, respectively. 4-bit I/O port (2-bit I/O port for the 4513 Group). For input use, set the latch of the specified bit to "1." The output structure is N-channel open-drain. Ports P30 and P31 are also used as INT0 and INT1, respectively. The 4513 Group does not have ports P32, P33. 4-bit I/O port. For input use, set the latch of the specified bit to "1." The output structure is N-channel open-drain. Ports P40-P43 are also used as analog input pins AIN4-AIN7, respectively. The 4513 Group does not have port P4. 4-bit I/O port. Each pin has a direction register and an independent 1-bit wide I/O function. For input use, set the direction register to "0." For output use, set the direction regiser to "1." The output structure is CMOS. The 4513 Group does not have port P5. Analog input pins for A-D converter. AIN0-AIN3 are also used as voltage comparator input pins and AIN4-AIN7 are also used as port P4. The 4513 Group does not have AIN4-AIN7. CNTR0 pin has the function to input the clock for the timer 2 event counter, and to output the timer 1 underflow signal divided by 2. CNTR0 pin is also used as port D6. CNTR1 pin has the function to input the clock for the timer 4 event counter, and to output the timer 3 underflow signal divided by 2. CNTR1 pin is also used as port D7. INT0, INT1 pins accept external interrupts. They also accept the input signal to return the system from the RAM back-up state. INT0, INT1 pins are also used as ports P30 and P31, respectively. SIN pin is used to input serial data signals by software. SIN pin is also used as port P22. SOUT pin is used to output serial data signals by software. SOUT pin is also used as port P21. SCK pin is used to input and output synchronous clock signals for serial data transfer by software. SCK pin is also used as port P20. CMP0-, CMP0+ pins are used as the voltage comparator input pin when the voltage comparator function is selected by software. CMP0-, CMP0+ pins are also used as AIN0 and AIN1. CMP1-, CMP1+ pins are used as the voltage comparator input pin when the voltage comparator function is selected by software. CMP1-, CMP1+ pins are also used as AIN2 and AIN3.
CNVSS RESET
XIN XOUT D0-D7
System clock input System clock output I/O port D (Input is examined by skip decision.) I/O port P0 I/O port P1 Input port P2 I/O port P3
P00-P03 P10-P13 P20-P22 P30-P33
I/O I/O Input I/O
P40-P43
I/O port P4
I/O
P50-P53
I/O port P5
I/O
AIN0-AIN7
Analog input
Input
CNTR0
Timer input/output
I/O
CNTR1
Timer input/output
I/O
INT0, INT1
Interrupt input
Input
SIN SOUT SCK
Serial data input Serial data output Serial I/O clock input/output Voltage comparator input Voltage comparator input
Input Output I/O
CMP0CMP0+ CMP1CMP1+
Input
Input
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HARDWARE
PIN DESCRIPTION
MULTIFUNCTION
Pin D6 D7 P20 P21 P22 P30 P31 Multifunction CNTR0 CNTR1 SCK SOUT SIN INT0 INT1 Pin CNTR0 CNTR1 SCK SOUT SIN INT0 INT1 Multifunction D6 D7 P20 P21 P22 P30 P31 Pin AIN0 AIN1 AIN2 AIN3 P40 P41 P42 P43 Multifunction CMP0CMP0+ CMP1CMP1+ AIN4 AIN5 AIN6 AIN7 Pin CMP0CMP0+ CMP1CMP1+ AIN4 AIN5 AIN6 AIN7 Multifunction AIN0 AIN1 AIN2 AIN3 P40 P41 P42 P43
Notes 1: Pins except above have just single function. 2: The input of D6, D7, P20-P22, CMP0-, CMP0+, CMP1-, CMP1+ and the input/output of P30, P31, P40-P43 can be used even when CNTR0, CNTR1, SCK, SOUT, SIN, INT0, INT1, and AIN0-AIN7 are selected. 3: The 4513 Group does not have P40/AIN4-P43/AIN7.
CONNECTIONS OF UNUSED PINS
Pin XOUT VDCE D0-D5 D6/CNTR0 D7/CNTR1 P20/SCK P21/SOUT P22/SIN P30/INT0 P31/INT1 P32, P33 P40/AIN4-P43/AIN7 P50-P53 (Note 1) Connection Open (when using an external clock). Connect to VSS. Connect to VSS, or set the output latch to "0" and open. Connect to VSS.
Notes 1: After system is released from reset, port P5 is in an input mode (direction register FR0 = 00002) 2: When the P00-P03 and P10-P13 are connected to VSS, turn off their pull-up transistors (register PU0i="0") and also invalidate the key-on wakeup functions (register K0i="0") by software. When these pins are connected to VSS while the key-on wakeup functions are left valid, the system fails to return from RAM back-up state. When these pins are open, turn on their pull-up transistors (register PU0i="1") by software, or set the output latch to "0." Be sure to select the key-on wakeup functions and the pull-up functions with every two pins. If only one of the two pins for the key-on wakeup function is used, turn on their pull-up transistors by software and also disconnect the other pin. (i = 0, 1, 2, or 3.) (Note when the output latch is set to "0" and pins are open) q After system is released from reset, port is in a high-impedance state until it is set the output latch to "0" by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur while the port is in a high-impedance state. q To set the output latch periodically by software is recommended because value of output latch may change by noise or a program run away (caused by noise). (Note when connecting to VSS and VDD) q Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise.
Connect to VSS, or set the output latch to "0" and open. Connect to VSS, or set the output latch to "0" and open. When the input mode is selected by software, pull-up to VDD through a resistor or pull-down to VDD. When selecting the output mode, open. Connect to VSS.
AIN0/CMP0AIN1/CMP0+ AIN2/CMP1AIN3/CMP1+ P00-P03 P10-P13
Open or connect to VSS (Note 2) Open or connect to VSS (Note 2)
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HARDWARE
PIN DESCRIPTION
PORT FUNCTION
Port Port D Pin D0-D5 D6/CNTR0 D7/CNTR1 P00-P03 Input Output I/O (8) I/O (4) Output structure N-channel open-drain I/O unit 1 Control instructions SD, RD SZD CLD OP0A IAP0 Control registers W6 PU0, K0 Built-in programmable pull-up functions Key-on wakeup functions (programmable) Built-in programmable pull-up functions Key-on wakeup functions (programmable) Remark
Port P0
N-channel open-drain
4
Port P1
P10-P13
I/O (4)
N-channel open-drain
4
OP1A IAP1
PU0, K0
Port P2
Port P3 (Note 1) Port P4 (Note 2) Port P5 (Note 2)
P20/SCK P21/SOUT P22/SIN P30/INT0 P31/INT1 P32, P33 P40/AIN4 -P43/AIN7 P50-P53
Input (3) I/O (4) I/O (4) I/O (4) N-channel open-drain
3
IAP2
J1
4
OP3A IAP3 OP4A IAP4 OP5A IAP5
I1, I2
Built-in key-on wakeup function (P30/INT0, P31/INT1)
N-channel open-drain CMOS
4 4
Q2 FR0
Notes 1: The 4513 Group does not have P32 and P33. 2: The 4513 Group does not have these ports.
DEFINITION OF CLOCK AND CYCLE
q System clock The system clock is the basic clock for controlling this product. The system clock is selected by the bit 3 of the clock control register MR. Table Selection of system clock Register MR MR3 0 1
System clock f(XIN) f(XIN)/2
Note: f(XIN)/2 is selected after system is released from reset. q Instruction clock The instruction clock is a signal derived by dividing the system clock by 3. The one instruction clock cycle generates the one machine cycle. q Machine cycle The machine cycle is the standard cycle required to execute the instruction.
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HARDWARE
PIN DESCRIPTION
PORT BLOCK DIAGRAMS
K00
Key-on wakeup input IAP0 instruction Register A
Ai D T Q
Pull-up transistor
PU00
P00,P01
OP0A instruction
K01
Key-on wakeup input IAP0 instruction Register A
Ai D T Q
Pull-up transistor
PU01
P02,P03
OP0A instruction
K02
Key-on wakeup input IAP1 instruction Register A
Ai D T Q
Pull-up transistor
PU02
P10,P11
OP1A instruction
K03
Key-on wakeup input IAP1 instruction Register A
Ai D T Q
Pull-up transistor
PU03
P12,P13
OP1A instruction
* *i
This symbol represents a parasitic diode on the port. represents 0, 1, 2, or 3.
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HARDWARE
PIN DESCRIPTION
PORT BLOCK DIAGRAMS (continued)
IAP2 instruction Register A
Synchronous clock input for serial transfer
J11
0
P20/SCK
Synchronous clock output for serial transfer J10
1
IAP2 instruction Register A
J11
0
P21/SOUT
Serial data output
1
Serial data input IAP2 instruction Register A
P22/SIN
Key-on wakeup input External interrupt circuit IAP3 instruction Register A Ai OP3A instruction D T Q
P30/INT0,P31/INT1
IAP3 instruction Register A Ai OP3A instruction D T Q
P32,P33
This symbol represents a parasitic diode on the port. * * Applied potential to ports P20--P22 must be VDD. * i represents 0, 1, 2, or 3. * The 4513 Group does not have ports P32, P33.
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HARDWARE
PIN DESCRIPTION
PORT BLOCK DIAGRAMS (continued)
Q1
Decoder
Analog input
AIN0/CMP0-
Q30 CMP0
+
Q32 Q1
Decoder
Analog input
AIN1/CMP0+
Q1
Decoder
Analog input
AIN2/CMP1-
Q31 CMP1
+
Q33 Q1
Decoder
Analog input
AIN3/CMP1+
IAP4 instruction Register A Ai OP4A instruction D TQ Q1
P40/AIN4-P43/AIN7
Decoder
Analog input
This symbol represents a parasitic diode on the port. * * i represents 0, 1, 2, or 3. * The 4513 Group does not have port P4.
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4513/4514 Group User's Manual
HARDWARE
PIN DESCRIPTION
PORT BLOCK DIAGRAMS (continued)
Direction register FR0i
Ai D T Q
P50-P53
OP5A instruction
Register A IAP5 instruction
Register Y
Decoder
Skip decision (SZD instruction)
CLD instruction
S
D0-D5
Q
SD instruction RD instruction
R
Skip decision (SZD instruction) Clock input for timer 2 event count Register Y Decoder CLD instruction
S
SD instruction RD instruction Timer 1 underflow signal divided by 2 or signal of AND operation between timer 1 underflow signal divided by 2 and timer 2 underflow signal divided by 2
R Q
W60 0 1
D6/CNTR0
Skip decision (SZD instruction) Clock input for timer 4 event count Register Y Decoder CLD instruction SD instruction RD instruction Timer 3 underflow signal divided by 2 or signal of AND operation between timer 3 underflow signal divided by 2 and timer 4 underflow signal divided by 2
S R Q W62 0 1
D7/CNTR1
This symbol represents a parasitic diode on the port. * * Applied potential to ports D0-D7 must be 12 V. * i represents 0, 1, 2, or 3. * The 4513 Group does not have port P5.
4513/4514 Group User's Manual
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HARDWARE
PIN DESCRIPTION
I12 Falling
0
One-sided edge detection circuit
I11
0
P30/INT0
1 1
EXF0 Both edges detection circuit Wakeup Skip SNZI0
External 0 interrupt
Rising
I22 Falling
0
One-sided edge detection circuit
I21
0
P31/INT1
1 1
EXF1 Both edges detection circuit Wakeup Skip SNZI1
External 1 interrupt
Rising
This symbol represents a parasitic diode on the port.
External interrupt circuit structure
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4513/4514 Group User's Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
FUNCTION BLOCK OPERATIONS CPU
(CY)

(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and bit manipulation.
(M(DP)) Addition (A)
Fig. 1 AMC instruction execution example
ALU
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to "1" when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to "1" with the SC instruction and cleared to "0" with the RC instruction.
SC instruction
RC instruction
CY
A3 A2 A1 A0 RAR instruction
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3).
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
(4) Register D
Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4).
Register B
TAB instruction
Register A
B3 B2 B1 B0
A3 A2 A1 A0
TEAB instruction Register E E7 E6 E5 E4 E3 E2 E1 E0 TABE instruction B3 B2 B1 B0 Register B A3 A2 A1 A0 Register A
TBA instruction
Fig. 3 Registers A, B and register E
TABP p instruction Specifying address
ROM 8 4 0
PCH p6 p5 p4 p3 p2 p1 p0
PCL DR2 DR1DR0 A3 A2 A1 A0
Low-order 4bits Register A (4) Middle-order 4 bits Register B (4)
Immediate field value p
The contents of The contents of register D register A
Fig. 4 TABP p instruction execution example
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HARDWARE
FUNCTION BLOCK OPERATIONS
(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; * branching to an interrupt service routine (referred to as an interrupt service routine), * performing a subroutine call, or * executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call.
Program counter (PC) Executing BM instruction SK0 SK1 SK2 SK3 SK4 SK5 SK6 SK7 Executing RT instruction (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7
Stack pointer (SP) points "7" at reset or returning from RAM back-up mode. It points "0" by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction.
(SP) 0 (SK0) 000116 (PC) SUB1
Main program Address 000016 NOP 000116 BM SUB1 000216 NOP
Subroutine
SUB1 : NOP * * * RT
(7) Skip flag
Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained.
(PC) (SK0) (SP) 7
Note : Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction.
Fig. 6 Example of operation at subroutine call
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HARDWARE
FUNCTION BLOCK OPERATIONS
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PCH (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not specify after the last page of the built-in ROM.
Program counter p6 p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0
PCH Specifying page
PCL Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP) Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9).
Register Y (4) Register X (4)
Specifying RAM digit
Specifying RAM file
Register Z (2)
Specifying RAM file group
Fig. 8 Data pointer (DP) structure
Specifying bit position Set
D7 D6 D5 D4 D0
0
1
0
1
1 Port D output latch
Register Y (4)
Fig. 9 SD instruction execution example
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HARDWARE
FUNCTION BLOCK OPERATIONS
PROGRAM MEMOY (ROM)
The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34514M8/E8. Table 1 ROM size and pages Product M34513M2 M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 ROM size (! 10 bits) 2048 words 4096 words 6144 words 8192 words 6144 words 8192 words Pages 16 (0 to 15) 32 (0 to 31) 48 (0 to 47) 64 (0 to 63) 48 (0 to 47) 64 (0 to 63)
98 000016 007F16 008016 00FF16 010016 017F16 018016
7
6
5
4
3
2
10 Page 0
Interrupt address page Subroutine special page
Page 1 Page 2 Page 3
0FFF16
Page 31
1FFF16
A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction.
Page 63
Fig. 10 ROM map of M34514M8/E8
98765 43210 008016 External 0 interrupt address 008216 008416 008616 008816 008A16 008C16 008E16 External 1 interrupt address Timer 1 interrupt address Timer 2 interrupt address Timer 3 interrupt address Timer 4 interrupt address A-D interrupt address Serial I/O interrupt address
00FF16
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure
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FUNCTION BLOCK OPERATIONS
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Table 2 shows the RAM size. Figure 12 shows the RAM map.
Table 2 RAM size Product M34513M2 M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 128 words 256 words 384 words 384 words 384 words 384 words RAM size ! 4 bits (512 bits) ! 4 bits (1024 bits) ! 4 bits (1536 bits) ! 4 bits (1536 bits) ! 4 bits (1536 bits) ! 4 bits (1536 bits)
RAM 384 words ! 4 bits (1536 bits)
Register Z
0
1 15 0 1 2 3 4 5 6 7
Register X 0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 M34513M6 M34513M8/E8 15 M34514M6 Z=0, X=0 to 15 M34514M8/E8 Z=1, X=0 to 7
Register Y
384 words 256 words 128 words
M34513M4/E4 Z=0, X=0 to 15 M34513M2 Z=0, X=0 to 7
Fig. 12 RAM map
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HARDWARE
FUNCTION BLOCK OPERATIONS
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied. * An interrupt activated condition is satisfied (request flag = "1") * Interrupt enable bit is enabled ("1") * Interrupt enable flag is enabled (INTE = "1") Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.)
Table 3 Interrupt sources Priority Interrupt name level 1 External 0 interrupt 2 3 4 5 6 7 8 External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt A-D interrupt Serial I/O interrupt
Activated condition Level change of INT0 pin Level change of INT1 pin Timer 1 underflow Timer 2 underflow Timer 3 underflow Timer 4 underflow Completion of A-D conversion Completion of serial I/O transfer
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to "1" with the EI instruction and disabled when INTE flag is cleared to "0" with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to "0," so that other interrupts are disabled until the EI instruction is executed.
Interrupt address Address 0 in page 1 Address 2 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Address A in page 1 Address C in page 1 Address E in page 1
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function. Table 4 Interrupt request flag, interrupt enable bit and skip instruction Interrupt name Request flag External 0 interrupt EXF0 EXF1 External 1 interrupt T1F Timer 1 interrupt T2F Timer 2 interrupt T3F Timer 3 interrupt T4F Timer 4 interrupt ADF A-D interrupt SIOF Serial I/O interrupt Skip instruction SNZ0 SNZ1 SNZT1 SNZT2 SNZT3 SNZT4 SNZAD SNZSI Enable bit V10 V11 V12 V13 V20 V21 V22 V23
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to "1." Each interrupt request flag is cleared to "0" when either; * an interrupt occurs, or * the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3.
Table 5 Interrupt enable bit function Interrupt enable bit Occurrence of interrupt Enabled 1 Disabled 0
Skip instruction Invalid Valid
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(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as follows (Figure 14). * Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK). * Interrupt enable flag (INTE) INTE flag is cleared to "0" so that interrupts are disabled. * Interrupt request flag Only the request flag for the current interrupt source is cleared to "0." * Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP).
* Program counter (PC) .............................................................. Each interrupt address * Stack register (SK) The address of main routine to be .................................................................................................... executed when returning * Interrupt enable flag (INTE) .................................................................. 0 (Interrupt disabled) * Interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 * Data pointer, carry flag, registers A and B, skip flag ........ Stored in the interrupt stack register (SDP) automatically Fig. 14 Internal state when interrupt occurs
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13)
INT0 pin (LH or HL input) INT1 pin (LH or HL input)
EXF0
V10
Address 0 in page 1 Address 2 in page 1
EXF1
V11
Timer 1 underflow
T1F
V12
Address 4 in page 1
Main routine Interrupt service routine
Interrupt occurs
Timer 2 underflow
T2F
V13
Address 6 in page 1
Timer 3 underflow
T3F
V20
Address 8 in page 1
* * * *
Timer 4 underflow
T4F
V21
Address A in page 1
EI RTI
Interrupt is enabled
Completion of A-D conversion
ADF
V22
Address C in page 1
Completion of serial I/O transfer Activated condition
SIOF Request flag (state retained)
V23 Enable bit
INTE
Address E in page 1
Enable flag
Fig. 15 Interrupt system diagram : Interrupt enabled state : Interrupt disabled state Fig. 13 Program example of interrupt processing
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(6) Interrupt control registers
* Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A.
* Interrupt control register V2 Interrupt enable bits of timer 3, timer 4, A-D and serial I/O are assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A.
Table 6 Interrupt control registers Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit Interrupt control register V2 V23 V22 V21 V20 Serial I/O interrupt enable bit A-D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W
Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) at reset : 00002 at RAM back-up : 00002 R/W
Interrupt disabled (SNZSI instruction is valid) Interrupt enabled (SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid)
Note: "R" represents read enabled, and "W" represents write enabled.
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(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt enable bits (V10-V13 and V20-V23), and interrupt request flag are "1." The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt oc-
curs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16).
When an interrupt request flag is set after its interrupt is enabled (Note 1)
f (XIN) (middle-speed mode)
f (XIN) (high-speed mode)
1 machine cycle
T1 System clock
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
Interrupt enable flag (INTE)
EI instruction execution cycle Interrupt enabled state
Interrupt disabled state
INT0, INT1 External interrupt EXF0, EXF1 Interrupt activated condition is satisfied. T1F, T2F, T3F, T4F, ADF,SIOF
Retaining level of system clock for 4 periods or more is necessary.
Timer 1, Timer 2, Timer 3, Timer 4, A-D, and Serial I/O interrupts
Flag cleared 2 to 3 machine cycles (Notes 2, 3)
The program starts from the interrupt address.
Notes 1: The 4513/4514 Group operates in the middle-speed mode after system is released from reset. 2: The address is stacked to the last cycle. 3: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
Fig. 16 Interrupt sequence
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EXTERNAL INTERRUPTS
The 4513/4514 Group has two external interrupts (external 0 and external 1). An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupts can be controlled with the interrupt control registers I1 and I2. Table 7 External interrupt activated conditions Name External 0 interrupt Input pin P30/INT0 Activated condition When the next waveform is input to P30/INT0 pin * Falling waveform ("H""L") * Rising waveform ("L""H") * Both rising and falling waveforms When the next waveform is input to P31/INT1 pin * Falling waveform ("H""L") * Rising waveform ("L""H") * Both rising and falling waveforms Valid waveform selection bit I11 I12
External 1 interrupt
P31/INT1
I21 I22
I12 Falling
0
One-sided edge detection circuit
I11
0
P30/INT0
1 1
EXF0 Both edges detection circuit Wakeup Skip SNZI0
External 0 interrupt
Rising
I22 Falling
0
One-sided edge detection circuit
I21
0
P31/INT1
1 1
EXF1 Both edges detection circuit Wakeup Skip SNZI1
External 1 interrupt
Rising
This symbol represents a parasitic diode on the port.
Fig. 17 External interrupt circuit structure
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(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to "1" when a valid waveform is input to P30/INT0 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with the skip instruction. The P30/INT0 pin need not be selected the external interrupt input INT0 function or the normal I/O port P30 function. However, the EXF0 flag is set to "1" when a valid waveform is input even if it is used as an I/O port P30. * External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to P30/INT0 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. Select the valid waveform with the bits 1 and 2 of register I1. Clear the EXF0 flag to "0" with the SNZ0 instruction. Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. Set both the external 0 interrupt enable bit (V10) and the INTE flag to "1." The external 0 interrupt is now enabled. Now when a valid waveform is input to the P30/INT0 pin, the EXF0 flag is set to "1" and the external 0 interrupt occurs.
(2) External 1 interrupt request flag (EXF1)
External 1 interrupt request flag (EXF1) is set to "1" when a valid waveform is input to P31/INT1 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF1 flag can be examined with the skip instruction (SNZ1). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF1 flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with the skip instruction. The P31/INT1 pin need not be selected the external interrupt input INT1 function or the normal I/O port P31 function. However, the EXF1 flag is set to "1" when a valid waveform is input even if it is used as an I/O port P31. * External 1 interrupt activated condition External 1 interrupt activated condition is satisfied when a valid waveform is input to P31/INT1 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 1 interrupt is as follows. Select the valid waveform with the bits 1 and 2 of register I2. Clear the EXF1 flag to "0" with the SNZ1 instruction. Set the NOP instruction for the case when a skip is performed with the SNZ1 instruction. Set both the external 1 interrupt enable bit (V11) and the INTE flag to "1." The external 1 interrupt is now enabled. Now when a valid waveform is input to the P31/INT1 pin, the EXF1 flag is set to "1" and the external 1 interrupt occurs.
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(3) External interrupt control registers
* Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A.
* Interrupt control register I2 Register I2 controls the valid waveform for the external 1 interrupt. Set the contents of this register through register A with the TI2A instruction. The TAI2 instruction can be used to transfer the contents of register I2 to register A.
Table 8 External interrupt control registers Interrupt control register I1 I13 Not used 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT0 pin is recognized with the SNZI0 instruction)/"L" level Rising waveform ("H" level of INT0 pin is recognized with the SNZI0 instruction)/"H" level One-sided edge detected Both edges detected Disabled Enabled at reset : 00002 at RAM back-up : state retained R/W
I12
Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2)
I11 I10
INT0 pin edge detection circuit control bit INT0 pin timer 1 control enable bit Interrupt control register I2
I23
Not used
0 1 0 1 0 1 0 1
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT1 pin is recognized with the SNZI1 instruction)/"L" level Rising waveform ("H" level of INT1 pin is recognized with the SNZI1 instruction)/"H" level One-sided edge detected Both edges detected Disabled Enabled
I22
Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3)
I21 I20
INT1 pin edge detection circuit control bit INT1 pin timer 3 control enable bit
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction. 3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
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TIMERS
The 4513/4514 Group has the programmable timers. * Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to "1," new data is loaded from the reload register, and count continues (auto-reload function).
* Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to "1" after every n count of a count pulse.
FF16 n : Counter initial value Count starts n The contents of counter 1st underflow 2nd underflow Reload Reload
0016 Time n+1 count "1" Timer interrupt "0" request flag An interrupt occurs or a skip instruction is executed. n+1 count
Fig. 18 Auto-reload function
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The 4513/4514 Group timer consists of the following circuits. * Prescaler : frequency divider * Timer 1 : 8-bit programmable timer * Timer 2 : 8-bit programmable timer * Timer 3 : 8-bit programmable timer * Timer 4 : 8-bit programmable timer (Timers 1 to 4 have the interrupt function, respectively) * 16-bit timer Prescaler and timers 1 to 4 can be controlled with the timer control registers W1 to W6. The 16-bit timer is a free counter which is not controlled with the control register. Each function is described below. Table 9 Function related timers Circuit Prescaler Timer 1 Structure Frequency divider 8-bit programmable binary down counter Count source * Instruction clock * Prescaler output (ORCLK) Frequency dividing ratio 4, 16 1 to 256 Use of output signal * Timer 1, 2, 3 and 4 count sources * Timer 2 count source * CNTR0 output * Timer 1 interrupt * Timer 3 count source * Timer 2 interrupt * CNTR0 output * Timer 4 count source * Timer 3 interrupt * CNTR1 output * Timer 4 interrupt * CNTR1 output * Watchdog timer (The 15th bit is counted twice) * Timer 2 count source (16-bit timer underflow) Control register W1 W1 W6 W2 W6
Timer 2
Timer 3
(link to P30/INT0 input) * Timer 1 underflow 8-bit programmable binary down counter * Prescaler output (ORCLK) * CNTR0 input * 16-bit timer underflow * Timer 2 underflow 8-bit programmable * Prescaler output (ORCLK) binary down counter (link to P31/INT1 input) 8-bit programmable * Timer 3 underflow * Prescaler output (ORCLK) binary down counter * CNTR1 input 16-bit fixed dividing frequency * Instruction clock
1 to 256
1 to 256
W3 W6 W4 W6
Timer 4
1 to 256
16-bit timer
65536
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Instruction clock
Prescaler
W12 1/4 1/16
0 1 0
W13 Divistion circuit (divided by 2) XIN MR3
1 0
Internal clock generating circuit (divided by 3) I12
1
Falling 0
One-sided edge detection circuit Both edges detection circuit
I11
0
ORCLK (Note 1) SQ R W10
1 0
P30/INT0
1 Rising
1
I10
W11 (Note 3)
0 1
Timer 1 (8) Reload register R1 (8)
T1AB (TR1AB) T1AB
T1F
Timer 1 interrupt
(TAB1)
Register B Register A Timer 1 underflow signal
W21,W20
00 01 10 Not available 11 0 1
W23(Note 3)
Timer 2 (8) Reload register R2 (8)
(T2AB)
T2F
Timer 2 interrupt
(TAB2) I22 P31/INT1
Register B Register A
I21
0
Falling 0 1 Rising
One-sided edge detection circuit Both edges detection circuit
Timer 2 underflow signal (Note 2) W32 SQ 1
0
1
W31,W30
00 01 10Not available 11Not available
I20 W33(Note 3)
0 1
R
Timer 3 (8) Reload register R3 (8)
T3AB (TR3AB) T3AB
T3F
Timer 3 interrupt
(TAB3)
Register B Register A Timer 3 underflow signal
W41,W40
00 01 10Not available 11Not available
W43(Note 3)
0 1
Timer 4 (8) Reload register R4 (8)
(T4AB)
T4F
Timer 4 interrupt
(TAB4)
Register B Register A
Data is set automatically from each reload 16-bit timer (WDT) register when timer 1, 2, 3, or 4 underflows Instruction clock 1 - - - - - - - - - - - 15 16 (auto-reload function) Notes 1: Timer 1 count start synchronous circuit is set by the valid edge of P30/INT0 pin selected by S WRST instruction bits 1 (I11) and 2 (I12) of register I1. WEF Q Reset signal R 2: Timer 3 count start synchronous circuit is set by the valid edge of P31/INT1 pin selected by bits 1 (I21) and 2 (I22) of register I2. 3: Count source is stopped by clearing to "0."
System reset
WDF1 WDF2
Fig. 19 Timers structure
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Table 10 Timer control registers Timer control register W1 W13 W12 W11 W10 Prescaler control bit Prescaler dividing ratio selection bit Timer 1 control bit Timer 1 count start synchronous circuit control bit Timer control register W2 W23 W22 W21 Timer 2 count source selection bits W20 Timer 2 control bit Not used 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W
Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected at reset : 00002 at RAM back-up : state retained R/W
0 1 0 1 W21 W20 0 0 0 1 1 0 1 1
Stop (state retained) Operating This bit has no function, but read/write is enabled. Count source Timer 1 underflow signal Prescaler output CNTR0 input 16 bit timer (WDT) underflow signal at RAM back-up : state retained R/W
Timer control register W3 W33 W32 W31 Timer 3 count source selection bits W30 Timer 3 control bit Timer 3 count start synchronous circuit control bit
at reset : 00002 0 1 0 1 W31 W30 0 0 0 1 1 0 1 1
Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected Count source Timer 2 underflow signal Prescaler output Not available Not available at RAM back-up : state retained R/W
Timer control register W4 W43 W42 W41 Timer 4 count source selection bits W40 Timer 4 control bit Not used
at reset : 00002 0 1 0 1 W41 W40 0 0 0 1 1 0 1 1
Stop (state retained) Operating This bit has no function, but read/write is enabled. Count source Timer 3 underflow signal Prescaler output CNTR1 input Not available at RAM back-up : state retained R/W
Timer control register W6 W63 W62 W61 W60 CNTR1 output control bit D7/CNTR1 function selection bit CNTR0 output control bit D6/CNTR0 output control bit 0 1 0 1 0 1 0 1
at reset : 00002
Timer 3 underflow signal output divided by 2 CNTR1 output control by timer 4 underflow signal divided by 2 D7(I/O)/CNTR1 input CNTR1 (I/O)/D7(input) Timer 1 underflow signal output divided by 2 CNTR0 output control by timer 2 underflow signal divided by 2 D6(I/O)/CNTR0 input CNTR0 (I/O)/D6(input)
Note: "R" represents read enabled, and "W" represents write enabled.
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(1) Timer control registers
* Timer control register W1 Register W1 controls the count operation of timer 1, the selection of count start synchronous circuit, and the frequency dividing ratio and count operation of prescaler. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. * Timer control register W2 Register W2 controls the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. * Timer control register W3 Register W3 controls the count operation and count source of timer 3 and the selection of count start synchronous circuit. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A. * Timer control register W4 Register W4 controls the count operation and count source of timer 4. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A. * Timer control register W6 Register W6 controls the D6/CNTR0 pin and D7/CNTR1 functions, the selection and operation of the CNTR0 and CNTR1 output. Set the contents of this register through register A with the TW6A instruction. The TAW6 instruction can be used to transfer the contents of register W6 to register A.
(4) Timer 1 (interrupt function)
Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Data can be written to reload register (R1) with the TR1AB instruction. When writing data to reload register R1 with the TR1AB instruction, the downcount after the underflow is started from the setting value of reload register R1. Timer 1 starts counting after the following process; set data in timer 1, and set the bit 1 of register W1 to "1." However, P30/INT0 pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register W1 to "1." When a value set in timer 1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes "0"), the timer 1 interrupt request flag (T1F) is set to "1," new data is loaded from reload register R1, and count continues (auto-reload function). Data can be read from timer 1 with the TAB1 instruction. When reading the data, stop the counter and then execute the TAB1 instruction. Timer 1 underflow signal divided by 2 can be output from D6/CNTR0 pin.
(5) Timer 2 (interrupt function)
Timer 2 is an 8-bit binary down counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload register (R2) with the T2AB instruction. Timer 2 starts counting after the following process; set data in timer 2, select the count source with the bits 0 and 1 of register W2, and set the bit 3 of register W2 to "1." When a value set in timer 2 is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes "0"), the timer 2 interrupt request flag (T2F) is set to "1," new data is loaded from reload register R2, and count continues (auto-reload function). Data can be read from timer 2 with the TAB2 instruction. When reading the data, stop the counter and then execute the TAB2 instruction. The output from D6/CNTR0 pin by timer 2 underflow signal divided by 2 can be controlled.
(2) Precautions
Note the following for the use of timers. * Prescaler Stop the prescaler operation to change its frequency dividing ratio. * Count source Stop timer 1, 2, 3, or 4 counting to change its count source. * Reading the count value Stop timer 1, 2, 3, or 4 counting and then execute the TAB1, TAB2, TAB3, or TAB4 instruction to read its data. * Writing to reload registers R1 and R3 When writing data to reload registers R1 or R3 while timer 1 or timer 3 is operating, avoid a timing when timer 1 or timer 3 underflows.
(3) Prescaler
Prescaler is a frequency divider. Its frequency dividing ratio can be selected. The count source of prescaler is the instruction clock. Use the bit 2 of register W1 to select the prescaler dividing ratio and the bit 3 to start and stop its operation. Prescaler is initialized, and the output signal (ORCLK) stops when the bit 3 of register W1 is cleared to "0."
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(6) Timer 3 (interrupt function)
Timer 3 is an 8-bit binary down counter with the timer 3 reload register (R3). Data can be set simultaneously in timer 3 and the reload register (R3) with the T3AB instruction. Data can be written to reload register (R3) with the TR3AB instruction. When writing data to reload register R3 with the TR3AB instruction, the downcount after the underflow is started from the setting value of reload register R3. Timer 3 starts counting after the following process; set data in timer 3, select the count source with the bits 0 and 1 of register W3, and set the bit 3 of register W3 to "1." However, P31/INT1 pin input can be used as the star t trigger for timer 3 count operation by setting the bit 2 of register W3 to "1." When a value set in timer 3 is n, timer 3 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 3 underflows (the next count pulse is input after the contents of timer 3 becomes "0"), the timer 3 interrupt request flag (T3F) is set to "1," new data is loaded from reload register R3, and count continues (auto-reload function). Data can be read from timer 3 with the TAB3 instruction. When reading the data, stop the counter and then execute the TAB3 instruction. Timer 3 underflow signal divided by 2 can be output from D7/CNTR1 pin.
(9) Timer I/O pin (D6/CNTR0, D7/CNTR1)
D6/CNTR0 pin has functions to input the timer 2 count source, and to output the timer 1 and timer 2 underflow signals divided by 2. D7/ CNTR1 pin has functions to input the timer 4 count source, and to output the timer 3 and timer 4 underflow signals divided by 2. The selection of D6/CNTR0 pin function can be controlled with the bit 0 of register W6. The selection of D7/CNTR1 pin function can be controlled with the bit 2 of register W6. The following signals can be selected for the CNTR0 output signal with the bit 1 of register W6. * timer 1 underflow signal divided by 2 * the signal of AND operation between timer 1 underflow signal divided by 2 and timer 2 underflow signal divide by 2 The following signals can be selected for the CNTR1 output signal with the bit 3 of register W6. * timer 3 underflow signal divided by 2 * the signal of AND operation between timer 3 underflow signal divided by 2 and timer 4 underflow signal divide by 2 Timer 2 counts the rising waveform of CNTR0 input when the CNTR0 input is selected as the count source. Timer 4 counts the rising waveform of CNTR1 input when the CNTR1 input is selected as the count source.
(10) Count start synchronous circuit (timer 1 and 3)
Each of timer 1 and timer 3 has the count start synchronous circuit which synchronizes P30/INT0 pin and P31/INT1 pin, respectively, and can start the timer count operation. Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register W1 to "1." The control by P30/INT0 pin input can be performed by setting the bit 0 of register I1 to "1." The count start synchronous circuit is set by level change ("H""L" or "L""H") of P30/INT0 pin input. This valid waveform is selected by bits 1 (I11) and 2 (I12) of register I1 as follows; * I11 = "0": Synchronized with one-sided edge (falling or rising) * I11 = "1": Synchronized with both edges (both falling and rising) When register I11="0" (synchronized with the one-sided edge), the rising or falling waveform can be selected by bit 2 of register I1; * I12 = "0": Falling waveform * I12 = "1": Rising waveform Timer 3 count start synchronous circuit function is selected by setting the bit 2 of register W3 to "1." The control by P31/INT1 pin input can be performed by setting the bit 0 of register I2 to "1." The count start synchronous circuit is set by level change ("H""L" or "L""H") of P31/INT1 pin input. This valid waveform is selected by bits 1 (I21) and 2 (I22) of register I2 as follows; * I21 = "0": Synchronized with one-sided edge (falling or rising) * I21 = "1": Synchronized with both edges (both falling and rising) When register I21="0" (synchronized with the one-sided edge), the rising or falling waveform can be selected by bit 2 of register I2; * I22 = "0": Falling waveform * I22 = "1": Rising waveform When timer 1 and timer 3 count start synchronous circuits are used, the count start synchronous circuits are set, the count source is input to each timer by inputting valid waveform to P30/INT0 pin and P31/INT1 pin. Once set, the count start synchronous circuit is cleared by clearing the bit I10 or I20 to "0" or reset.
(7) Timer 4 (interrupt function)
Timer 4 is an 8-bit binary down counter with the timer 4 reload register (R4). Data can be set simultaneously in timer 4 and the reload register (R4) with the T4AB instruction. Timer 4 starts counting after the following process; set data in timer 4, select the count source with the bits 0 and 1 of register W4, and set the bit 3 of register W4 to "1." When a value set in timer 4 is n, timer 4 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 4 underflows (the next count pulse is input after the contents of timer 4 becomes "0"), the timer 4 interrupt request flag (T4F) is set to "1," new data is loaded from reload register R4, and count continues (auto-reload function). Data can be read from timer 4 with the TAB4 instruction. When reading the data, stop the counter and then execute the TAB4 instruction. The output from D7/CNTR1 pin by timer 4 underflow signal divided by 2 can be controlled.
(8) Timer interrupt request flags (T1F, T2F, T3F, and T4F)
Each timer interrupt request flag is set to "1" when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3, and SNZT4). Use the interrupt control registers V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with a skip instruction.
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WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a program runs wild. Watchdog timer consists of a 16-bit timer (WDT), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source. The underflow signal is generated when the count value reaches "000016." This underflow signal can be used as the timer 2 count source. When the WRST instruction is executed after system is released from reset, the WEF flag is set to "1". At this time, the watchdog timer starts operating.
When the count value of timer WDT reaches "BFFF16" or "3FFF16," the WDF1 flag is set to "1." If the WRST instruction is never executed while timer WDT counts 32767, WDF2 flag is set to "1," and the RESET pin outputs "L" level to reset the microcomputer. Execute the WRST instruction at each period of 32766 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. To prevent the WDT stopping in the event of misoperation, WEF flag is designed not to initialize once the WRST instruction has been executed. Note also that, if the WRST instruction is never executed, the watchdog timer does not start.
FFFF16
The value of timer (WDT)
0000 16
WEF flag
BFFF16 3FFF16
WDF1 flag WDF2 flag
RESET pin output WRST instruction executed
Fig. 20 Watchdog timer function The contents of WEF, WDF1 and WDF2 flags and timer WDT are initialized at the RAM back-up mode. If WDF2 flag is set to "1" at the same time that the microcomputer enters the RAM back-up state, system reset may be performed. When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back-up state (refer to Figure 21)
WRST instruction executed
System reset
* * * * * *
WRST EPOF POF
; WDF1 flag reset ; POF instruction enabled
Oscillation stop
(RAM back-up state)
Fig. 21 Program example to enter the RAM back-up mode when using the watchdog timer
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SERIAL I/O
The 4513/4514 Group has a built-in clock synchronous serial I/O which can serially transmit or receive 8-bit data. Serial I/O consists of; * serial I/O register SI * serial I/O mode register J1 * serial I/O transmission/reception completion flag (SIOF) * serial I/O counter Registers A and B are used to perform data transfer with internal CPU, and the serial I/O pins are used for external data transfer. The pin functions of the serial I/O pins can be set with the register J1.
Table 11 Serial I/O pins Pin P20/SCK P21/SOUT P22/SIN Pin function when selecting serial I/O Clock I/O (SCK) Serial data output (SOUT) Serial data input (SIN)
Note: Input ports P20-P22 can be used regardless of register J1.
Division circuit (divided by 2) XIN
MR3
1 0
Internal clock generation circuit (divided by 3)
Instruction clock
J12 1/4 1/8
1 0
Serial I/O mode register J1 J13 J12 J11 J10
P20/SCK
SCK
Synchronous circuit
Serial I/O counter (3)
SIOF
Serial I/O interrupt
P21/SOUT
SOUT
P22/SIN
SIN
MSB
Serial I/O register SI (8) TSIAB
LSB TABSI
J11
J10
Register B (4)
Register A (4)
Note: The output structure of SCK and SOUT pins is N-channel open-drain.
Fig. 22 Serial I/O structure Table 12 Serial I/O mode register Serial I/O mode register J1 J13 J12 J11 J10 Not used Serial I/O internal clock dividing ratio selection bit Serial I/O port selection bit Serial I/O synchronous clock selection bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W
This bit has no function, but read/write is enabled. Instruction clock signal divided by 8 Instruction clock signal divided by 4 Input ports P20, P21, P22 selected Serial I/O ports SCK, SOUT, SIN/input ports P20, P21, P22 selected External clock Internal clock (instruction clock divided by 4 or 8)
Note: "R" represents read enabled, and "W" represents write enabled.
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When transmitting (D7-D0 : transfer data)
SIN pin
When receiving
SOUT pin
Serial I/O register (SI)
D7 D6 D5 D4 D3 D2 D1 D0
SOUT pin
SIN pin
Serial I/O register (SI)
D7 D6 D5 D4 D3 D2 D1 D0
Transfer data to be set
D0
D7 D6 D5 D4 D3 D2 D1
Transfer started

D7 D6 D5 D4 D3 D2
D1 D0
Fig. 23 Serial I/O register state when transferring
Transfer completed
D7 D6 D5 D4 D3 D2 D1 D0
(1) Serial I/O register SI
Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and B with the TSIAB instruction. The contents of register A is transmitted to the low-order 4 bits of register SI, and the contents of register B is transmitted to the high-order 4 bits of register SI. During transmission, each bit data is transmitted LSB first from the lowermost bit (bit 0) of register SI, and during reception, each bit data is received LSB first to register SI starting from the topmost bit (bit 7). When register SI is used as a work register without using serial I/O, pull up the SCK pin or set the pin function to an input port P20.
(3) Serial I/O start instruction (SST)
When the SST instruction is executed, the SIOF flag is cleared to "0" and then serial I/O transmission/reception is started.
(4) Serial I/O mode register J1
Register J1 controls the synchronous clock, P20/SCK, P21/SOUT and P22/SIN pin function. Set the contents of this register through register A with the TJ1A instruction. The TAJ1 instruction can be used to transfer the contents of register J1 to register A.
(2) Serial I/O transmission/reception completion flag (SIOF)
Serial I/O transmission/reception completion flag (SIOF) is set to "1" when serial data transmission or reception completes. The state of SIOF flag can be examined with the skip instruction (SNZSI). Use the interrupt control register V2 to select the interrupt or the skip instruction. The SIOF flag is cleared to "0" when the interrupt occurs or when the next instruction is skipped with the skip instruction.
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(5) How to use serial I/O
Figure 24 shows the serial I/O connection example. Serial I/O interrupt is not used in this example. In the actual wiring, pull up the
wiring between each pin with a resistor. Figure 25 shows the data transfer timing and Table 13 shows the data transfer sequence.
Master (clock control)
Slave (external clock)
D5 SCK SOUT SIN
SRDY signal
D5 SCK SIN SOUT
(Bit 3) ! ! 1
(Bit 0) 1 Serial I/O mode register J1 Internal clock selected as a synchronous clock Serial I/O port SCK,SOUT,SIN Instruction clock divided by 8 or 4 selected as a transfer clock
(Bit 3) !
!
1
(Bit 0) 0 Serial I/O mode register J1 External clock selected as a synchronous clock Serial I/O port SCK,SOUT,SIN This bit is not valid when J10="0"
(Bit 3) 0 !
!
(Bit 0) Interrupt control register V2 !
(Bit 3) 0
!
!
(Bit 0) ! Interrupt control register V2
Serial I/O interrupt enable bit (SNZSI instruction is valid)
Serial I/O interrupt enable bit (SNZSI instruction is valid)
! : Set an arbitrary value.
Fig. 24 Serial I/O connection example
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Master
SOUT SIN SST instruction
M7' S7'
M0 S0
M1 S1
M2 S2
M3 S3
M4 S4
M5 S5
M6 S6
M7 S7
SCK
Slave
SST instruction SRDY signal
SOUT SIN
S7' M7'
S0 M0
S1 M1
S2 M2
S3 M3
S4 M4
S5 M5
S6 M6
S7 M7
M0-M7 : the contents of master serial I/O S0-S7 : the contents of slave serial I/O register Rising of SCK : serial input Falling of SCK : serial output
Fig. 25 Timing of serial I/O data transfer
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Table 13 Processing sequence of data transfer from master to slave Master (transmission) [Initial setting] * Setting the serial I/O mode register J1 and interrupt control register V2 shown in Figure 24. TJ1A and TV2A instructions * Setting the port received the reception enable signal (SRDY) to the input mode. (Port D5 is used in this example) SD instruction * [Transmission enable state] * Storing transmission data to serial I/O register SI. TSIAB instruction Slave (reception) [Initial setting] * Setting serial I/O mode register J1, and interrupt control register V2 shown in Figure 24. TJ1A and TV2A instructions * Setting the port transmitted the reception enable signal (SRDY) and outputting "H" level (reception impossible). (Port D5 is used in this example) SD instruction *[Reception enable state] * The SIOF flag is cleared to "0." SST instruction * "L" level (reception possible) is output from port D5. RD instruction [Reception]
[Transmission] *Check port D5 is "L" level. SZD instruction *Serial transfer starts. SST instruction *Check transmission completes. SNZSI instruction *Wait (timing when continuously transferring)
* Check reception completes. SNZSI instruction * "H" level is output from port D5. SD instruction [Data processing]
1-byte data is serially transferred on this process. Subsequently, data can be transferred continuously by repeating the process from *. When an external clock is selected as a synchronous clock, the clock is not controlled internally. Control the clock externally because serial transfer is performed as long as clock is externally input. (Unlike an internal clock, an external clock is not stopped when serial transfer is completed.) However, the SIOF flag is set to "1" when the clock is counted 8 times after executing the SST instruction. Be sure to set the initial level of the external clock to "H."
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A-D CONVERTER
The 4513/4514 Group has a built-in A-D conversion circuit that performs conversion by 10-bit successive comparison method. Table 14 shows the characteristics of this A-D converter. This AD converter can also be used as an 8-bit comparator to compare analog voltages input from the analog input pin with preset values.
Table 14 A-D converter characteristics Parameter Characteristics Conversion format Successive comparison method Resolution 10 bits Relative accuracy Linearity error: 2LSB Non-linearity error: 0.9LSB Conversion speed 46.5 s (High-speed mode at 4.0 MHz oscillation frequency) Analog input pin 4 for 4513 Group 8 for 4514 Group
Register B (4)
Register A (4) 4 TAQ2 TQ2A
Q23 Q22 Q21 Q20
4 4
IAP4 (P40--P43)
TAQ1 TQ1A 2
Q13 Q12 Q11 Q10
4
8 TABAD
8 TADAB
TALA Instruction clock 1/6
OP4A (P40--P43) 3
Q23
0
8-channel multi-plexed analog switch
(Note 3) AIN0/CMP0AIN1/CMP0+ AIN2/CMP1AIN3/CMP1+ P40/AIN4 P41/AIN5 P42/AIN6 P43/AIN7
A-D control circuit
1
ADF (1)
A-D interrupt
1
Comparator
0
Successive comparison register (AD) (10) 10 10
1
Q23 8
0 1 0
Q23
1
DAC operation signal
Q23
8 DA converter (Note 1) VSS Comparator register (8) (Note 2) VDD 8 8
Notes 1: This switch is turned ON only when A-D converter is operating and generates the comparison voltage. 2: Writing/reading data to the comparator register is possible only in the comparator mode (Q23=1). The value of the comparator register is retained even when the mode is switched to the A-D conversion mode (Q23=0) because it is separated from the successive comparison register (AD). Also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits. 3: The 4513 Group does not have ports P40/AIN4-P43/AIN7 and the IAP4 and OP4A instructions.
Fig. 26 A-D conversion circuit structure
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Table 15 A-D control registers
A-D control register Q1 Q13 Not used at reset : 00002 0 1 Q12Q11 Q10 000 001 010 011 100 101 110 111 at RAM back-up : state retained R/W
This bit has no function, but read/write is enabled. Selected pins AIN0 AIN1 AIN2 AIN3 AIN4 (Not available for the 4513 Group) AIN5 (Not available for the 4513 Group) AIN6 (Not available for the 4513 Group) AIN7 (Not available for the 4513 Group) at RAM back-up : state retained R/W
Q12
Q11
Analog input pin selection bits (Note 2)
Q10
A-D control register Q2 Q23 Q22 Q21 Q20 A-D operation mode selection bit P43/AIN7 and P42/AIN6 pin function selection bit (Not used for the 4513 Group) P41/AIN5 pin function selection bit (Not used for the 4513 Group) P40/AIN4 pin function selection bit (Not used for the 4513 Group) 0 1 0 1 0 1 0 1
at reset : 00002
A-D conversion mode Comparator mode P43, P42 (read/write enabled for the 4513 Group) AIN7, AIN6/P43, P42 (read/write enabled for the 4513 Group) P41 (read/write enabled for the 4513 Group) AIN5/P41 P40 AIN4/P40 (read/write enabled for the 4513 Group) (read/write enabled for the 4513 Group) (read/write enabled for the 4513 Group)
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: Select AIN4-AIN7 with register Q1 after setting register Q2.
(1) Operating at A-D conversion mode
The A-D conversion mode is set by setting the bit 3 of register Q2 to "0."
(4) A-D conversion start instruction (ADST)
A-D conversion starts when the ADST instruction is executed. The conversion result is automatically stored in the register AD.
(2) Successive comparison register AD
Register AD stores the A-D conversion result of an analog input in 10-bit digital data format. The contents of the high-order 8 bits of this register can be stored in register B and register A with the TABAD instruction. The contents of the low-order 2 bits of this register can be stored into the high-order 2 bits of register A with the TALA instruction. However, do not execute this instruction during AD conversion. When the contents of register AD is n, the logic value of the comparison voltage Vref generated from the built-in DA converter can be obtained with the reference voltage VDD by the following formula: Logic value of comparison voltage Vref Vref =
(5) A-D control register Q1
Register Q1 is used to select one of analog input pins. The 4513 Group does not have AIN4-AIN7. Accordingly, do not select these pins with register Q1.
(6) A-D control register Q2
Register Q2 is used to select the pin function of P40/AIN4, P41/ AIN5, P42/AIN6, and P43/AIN7. The A-D conversion mode is selected when the bit 3 of register Q2 is "0," and the comparator mode is selected when the bit 3 of register Q2 is "1." After set this register, select the analog input with register Q1. Even when register Q2 is used to set the pins for analog input, P40/AIN4-P43/AIN7 continue to function as P40-P43 I/O. Accordingly, when any of them are used as I/O port P4 and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to "1." Also, for the port input, the port input function of the pin functions as analog input is undefined.
VDD !n 1024
n: The value of register AD (n = 0 to 1023)
(3) A-D conversion completion flag (ADF)
A-D conversion completion flag (ADF) is set to "1" when A-D conversion completes. The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to "0" when the interrupt occurs or when the next instruction is skipped with the skip instruction.
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(7) Operation description
A-D conversion is started with the A-D conversion start instruction (ADST). The internal operation during A-D conversion is as follows: When A-D conversion starts, the register AD is cleared to "00016." Next, the topmost bit of the register AD is set to "1," and the comparison voltage Vref is compared with the analog input voltage VIN. When the comparison result is Vref < VIN, the topmost bit of the register AD remains set to "1." When the comparison result is Vref > VIN, it is cleared to "0."
The 4513/4514 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value. A-D conversion stops after 62 machine cycles (46.5 s when f(XIN) = 4.0 MHz in high-speed mode) from the start, and the conversion result is stored in the register AD. An A-D interrupt activated condition is satisfied and the ADF flag is set to "1" as soon as A-D conversion completes (Figure 27).
Table 16 Change of successive comparison register AD during A-D conversion At starting conversion 1st comparison 2nd comparison 3rd comparison After 10th comparison completes U1: 1st comparison result U3: 3rd comparison result U9: 9th comparison result Change of successive comparison register AD
-------------
Comparison voltage (Vref) value VDD 2 VDD 2 VDD 2 VDD VDD 4 VDD VDD 4

1 U1 U1
0 1 U2
0 0 1
-----------------------------------------------------
0 0 0
0 0 0
0 0 0
---------

-------------

8 VDD 1024
A-D conversion result
-------------
U1
U2
U3
-------------
-----
U8
U9
UA
2
U2: 2nd comparison result U8: 8th comparison result UA: 10th comparison result
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(8) A-D conversion timing chart
Figure 27 shows the A-D conversion timing chart.
ADST instruction 62 machine cycles A-D conversion completion flag (ADF) DAC operation signal
Fig. 27 A-D conversion timing chart
(9) How to use A-D conversion
How to use A-D conversion is explained using as example in which the analog input from P40/AIN4 pin is A-D converted, and the highorder 4 bits of the converted data are stored in address M(Z, X, Y) = (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A-D interrupt is not used in this example. After selecting the AIN4 pin function with the bit 0 of the register Q2, select AIN4 pin and A-D conversion mode with the register Q1 (refer to Figure 28). Execute the ADST instruction and start A-D conversion. Examine the state of ADF flag with the SNZAD instruction to determine the end of A-D conversion. Transfer the low-order 2 bits of converted data to the high-order 2 bits of register A (TALA instruction). Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2). Transfer the high-order 8 bits of converted data to registers A and B (TABAD instruction). Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1). Transfer the contents of register B to register A, and then, store into M(Z, X, Y) = (0, 0, 0).
(Bit 3)
(Bit 0)
0
!
!
1
A-D control register Q2 AIN4 function selected A-D conversion mode
(Bit 3)
(Bit 0)
!
1
0
0
A-D control register Q1
AIN4 pin selected
! : Set an arbitrary value
Fig. 28 Setting registers
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(10) Operation at comparator mode
The A-D converter is set to comparator mode by setting bit 3 of the register Q2 to "1." Below, the operation at comparator mode is described.
(12) Comparison result store flag (ADF)
In comparator mode, the ADF flag, which shows completion of A-D conversion, stores the results of comparing the analog input voltage with the comparison voltage. When the analog input voltage is lower than the comparison voltage, the ADF flag is set to "1." The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to "0" when the interrupt occurs or when the next instruction is skipped with the skip instruction.
(11) Comparator register
In comparator mode, the built-in DA comparator is connected to the comparator register as a register for setting comparison voltages. The contents of register B is stored in the high-order 4 bits of the comparator register and the contents of register A is stored in the low-order 4 bits of the comparator register with the TADAB instruction. When changing from A-D conversion mode to comparator mode, the result of A-D conversion (register AD) is undefined. However, because the comparator register is separated from register AD, the value is retained even when changing from comparator mode to A-D conversion mode. Note that the comparator register can be written and read at only comparator mode. If the value in the comparator register is n, the logic value of comparison voltage Vref generated by the built-in DA converter can be determined from the following formula: Logic value of comparison voltage Vref Vref = VDD 256 !n
(13) Comparator operation start instruction (ADST instruction)
In comparator mode, executing ADST starts the comparator operating. The comparator stops 8 machine cycles after it has started (6 s at f(XIN) = 4.0 MHz in high-speed mode). When the analog input voltage is lower than the comparison voltage, the ADF flag is set to "1."
(14) Notes for the use of A-D conversion 1
Note the following when using the analog input pins also for I/O port P4 functions: * Even when P40/AIN4-P43/AIN7 are set to pins for analog input, they continue to function as P40-P43 I/O. Accordingly, when any of them are used as I/O port P4 and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to "1." Also, the port input function of the pin functions as an analog input is undefined. * TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is "0."
n: The value of register AD (n = 0 to 255)
ADST instruction 8 machine cycles Comparison result store flag(ADF) DAC operation signal
Comparator operation completed. (The value of ADF is determined)
Fig. 29 Comparator operation timing chart
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(15) Notes for the use of A-D conversion 2
Do not change the operating mode (both A-D conversion mode and comparator mode) of A-D converter with bit 3 of register Q2 while A-D converter is operating. When the operating mode of A-D converter is changed from the comparator mode to A-D conversion mode with the bit 3 of register Q2, note the following; * Clear bit 2 of register V2 to "0" to change the operating mode of the A-D converter from the comparator mode to A-D conversion mode with the bit 3 of register Q2. * The A-D conversion completion flag (ADF) may be set when the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode. Accordingly, set a value to register Q2, and execute the SNZAD instruction to clear the ADF flag.
(16) Definition of A-D converter accuracy
The A-D conversion accuracy is defined below (refer to Figure 30). * Relative accuracy Zero transition voltage (V0T) This means an analog input voltage when the actual A-D conversion output data changes from "0" to "1." Full-scale transition voltage (VFST) This means an analog input voltage when the actual A-D conversion output data changes from "1023" to "1022." Linearity error This means a deviation from the line between V0T and VFST of a converted value between V0T and VFST. Differential non-linearity error This means a deviation from the input potential difference required to change a converter value between V0T and VFST by 1 LSB at the relative accuracy. * Absolute accuracy This means a deviation from the ideal characteristics between 0 to VDD of actual A-D conversion characteristics.
Output data
1023 1022
Full-scale transition voltage (VFST)
Differential non-linearity error = b-a [LSB] a Linearity error = c [LSB] a
b a
n+1 n
Actual A-D conversion characteristics c a: 1LSB by relative accuracy b: Vn+1-Vn c: Difference between ideal Vn and actual Vn
Ideal line of A-D conversion between V0-V1022
1 0
V0 V1 Zero transition voltage (V0T)
Vn
Vn+1
V1022 Analog voltage
VDD
Fig. 30 Definition of A-D conversion accuracy Vn: Analog input voltage when the output data changes from "n" to "n+1" (n = 0 to 1022) * 1LSB at relative accuracy VFST-V0T (V) 1022 VDD 1024
* 1LSB at absolute accuracy
(V)
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VOLTAGE COMPARATOR
The 4513/4514 Group has 2 voltage comparator circuits that perform comparison of voltage between 2 pins. Table 17 shows the characteristics of this voltage comparison.
Table 17 Voltage comparator characteristics Parameter Characteristics Voltage comparator function 2 circuits (CMP0, CMP1) Input pin CMP0-, CMP0+ (also used as AIN0, AIN1) CMP1-, CMP1+ Supply voltage Input voltage Comparison check error Response time (also used as AIN2, AIN3) 3.0 V to 5.5 V 0.3 VDD to 0.7 VDD Typ. 20 mV, Max.100 mV Max. 20 s
CMP0-/AIN0 CMP0+/AIN1
- CMP0 +
CMP1-/AIN2 CMP1+/AIN3
- CMP1 +
Q33 Q32 Q31 Q30 Voltage comparator control register Q3 (4) TQ3A TAQ3 Register A (4) Note: Bits 0 and 1 of register Q3 can be only read.
Fig. 31 Voltage comparator structure
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Table 18 Voltage comparator control register Q3
Voltage comparator control register Q3 (Note 2) Q33 Q32 Q31 Q30 Voltage comparator (CMP1) control bit Voltage comparator (CMP0) control bit CMP1 comparison result store bit CMP0 comparison result store bit 0 1 0 1 0 1 0 1 at reset : 00002 Voltage comparator Voltage comparator Voltage comparator Voltage comparator CMP1- > CMP1+ CMP1- < CMP1+ CMP0- > CMP0+ CMP0- < CMP0+ at RAM back-up : state retained (CMP1) (CMP1) (CMP0) (CMP0) invalid valid invalid valid R/W
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: Bits 0 and 1 of register Q3 can be only read.
(1) Voltage comparator control register Q3
Register Q3 controls the function of the voltage comparator. The function of the voltage comparator CMP0 becomes valid by setting bit 2 of register Q3 to "1," and becomes invalid by setting bit 2 of register Q3 to "0." The comparison result of the voltage comparator CMP0 is stored into bit 0 of register Q3. The function of the voltage comparator CMP1 becomes valid by setting bit 3 of register Q3 to "1," and becomes invalid by setting bit 3 of register Q3 to "0." The comparison result of the voltage comparator CMP1 is stored into bit 1 of register Q3.
(3) Precautions
When the voltage comparator is used, note the following; * Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode. Accordingly, be careful about such state because it causes the increase of the operation current in the RAM backup mode. In order to reduce the operation current in the RAM back-up mode, invalidate (bits 2 and 3 of register Q3 = "0") the voltage comparator function by software before the POF instruction is executed. Also, while the voltage comparator function is valid, current is always consumed by voltage comparator. On the system required for the low-power dissipation, invalidate the voltage comparator by software when it is unused. * Register Q3 Bits 0 and 1 of register Q3 can be only read. Note that they cannot be written. * Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time (max. 20 s) is passed from the voltage comparator function becomes valid.
(2) Operation description of voltage comparator
The voltage comparator function becomes valid by setting each control bit of register Q3 to "1" and compares the voltage of the input pin. The comparison result is stored into each comparison result store bit of register Q3. The comparison result is as follows; * When CMP0- > CMP0+, Q30 = "0" When CMP0- < CMP0+, Q30 = "1" * When CMP1- > CMP1+, Q31 = "0" When CMP1- < CMP1+, Q31 = "1"
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RESET FUNCTION
System reset is performed by applying "L" level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when "H" level is applied to RESET pin, software starts from address 0 in page 0.
f(XIN)
RESET
(Note) f(XIN) is counted 16892 to
16895 times.
Software starts (address 0 in page 0)
Note: It depends on the internal state of the microcomputer when reset is performed.
Fig. 32 Reset release timing
Reset input
=
f(XIN) is counted 16892 to
1 machine cycle or more
16895 times.
0.85VDD RESET 0.3VDD
Software starts (address 0 in page 0)
(Note)
Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions.
Fig. 33 RESET pin input waveform and reset operation
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FUNCTION BLOCK OPERATIONS
(1) Power-on reset
Reset can be performed automatically at power on (power-on reset) by connecting resistors, a diode, and a capacitor to RESET pin. Connect RESET pin and the external circuit at the shortest distance.
VDD
VDD RESET pin voltage
Internal reset signal
RESET pin
(Note)
Reset state
Voltage drop detection circuit
Watchdog timer output
WEF
Internal reset signal
Reset released Note: Power-on This symbol represents a parasitic diode. Applied potential to RESET pin must be VDD or less.
Fig. 34 Power-on reset circuit example
(2) Internal state at reset
Table 19 shows port state at reset, and Figure 35 shows internal state at reset (they are the same after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 35 are undefined, so set the initial value to them. Table 19 Port state at reset Name D0-D5 D6/CNTR0, D7/CNTR1 P00-P03 P10-P13 P20/SCK, P21/SOUT, P22/SIN P30/INT0, P31/INT1 P32, P33 (Note 4) P40/AIN4-P43/AIN7 (Note 4) P50-P53 (Note 4) Function D0-D5 D6, D7 P00-P03 P10-P13 P20-P22 P30, P31 P32, P33 P40-P43 P50-P53 High impedance (Note) High impedance (Notes 1, 2) High impedance High impedance (Note 1) High impedance (Note 1) High impedance (Note 3) State
Notes 1: Output latch is set to "1." 2: Pull-up transistor is turned OFF. 3: After system is released from reset, port P5 is in the input mode. (Direction register FR0 = 00002) 4: The 4513 Group does not have these ports.
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* Program counter (PC) .......................................................................................................... 0 00000 Address 0 in page 0 is set to program counter. * Interrupt enable flag (INTE) .................................................................................................. 0 * Power down flag (P) ............................................................................................................. 0 * External 0 interrupt request flag (EXF0) .............................................................................. 0 * External 1 interrupt request flag (EXF1) .............................................................................. 0 * Interrupt control register V1 .................................................................................................. 0 000 * Interrupt control register V2 .................................................................................................. 0 000 * Interrupt control register I1 ................................................................................................... 0 000 * Interrupt control register I2 ................................................................................................... 000 * Timer 1 interrupt request flag (T1F) ..................................................................................... * Timer 2 interrupt request flag (T2F) ..................................................................................... * Timer 3 interrupt request flag (T3F) ..................................................................................... * Timer 4 interrupt request flag (T4F) ..................................................................................... * Watchdog timer flags (WDF1, WDF2) .................................................................................. * Watchdog timer enable flag (WEF) ...................................................................................... * Timer control register W1 ..................................................................................................... 000 * Timer control register W2 ..................................................................................................... 000 * Timer control register W3 ..................................................................................................... 000 * Timer control register W4 ..................................................................................................... 000 * Timer control register W6 ..................................................................................................... 000 * Clock control register MR ..................................................................................................... 100 * Serial I/O transmission/reception completion flag (SIOF) ................................................... * Serial I/O mode register J1 .................................................................................................. 000 !!!!!!! * Serial I/O register SI ............................................................................................................. * A-D conversion completion flag (ADF) ................................................................................. * A-D control register Q1 ......................................................................................................... 000 * A-D control register Q2 ......................................................................................................... 000 * Voltage comparator control register Q3 ............................................................................... 000 !!!!!!!!! * Successive comparison register AD .................................................................................... * Comparator register...........................................................................................................! ! ! ! ! ! ! ... * Key-on wakeup control register K0 ...................................................................................... 000 * Pull-up control register PU0 ................................................................................................. 000 * Direction register FR0 .......................................................................................................... 000 * Carry flag (CY) ...................................................................................................................... * Register A ............................................................................................................................. 000 * Register B ............................................................................................................................. 000 * Register D ............................................................................................................................. !! !!!!!!! * Register E ............................................................................................................................. * Register X ............................................................................................................................. 000 * Register Y ............................................................................................................................. 000 * Register Z ............................................................................................................................. ! * Stack pointer (SP) ................................................................................................................ 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ! 0 0 0 0 ! ! 0 0
0
0
0
0
0
0
0
0
(Interrupt disabled)
(Interrupt disabled) (Interrupt disabled)
(Prescaler and timer 1 stopped) (Timer 2 stopped) (Timer 3 stopped) (Timer 4 stopped)
(External clock selected and serial I/O port not selected)
0 (Port P5: input mode) 0 0 0 ! ! 0 0 ! 1
"!" represents undefined. Fig. 35 Internal state at reset
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FUNCTION BLOCK OPERATIONS
VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value.
RESET pin
Internal reset signal Voltage drop detection circuit Watchdog timer output WEF Note: The output structure of RESET pin is N-channel open-drain.
Fig. 36 Voltage drop detection reset circuit
VDD VRST (detection voltage)
Voltage drop detection circuit output The microcomputer starts operation after f(XIN) is counted 16892 to 16895 times. RESET pin Notes 1: Pull-up RESET pin externally. 2: Refer to the voltage drop detection circuit in the electrical characteristics for the rating value of VRST (detection voltage).
Fig. 37 Voltage drop detection circuit operation waveform
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FUNCTION BLOCK OPERATIONS
RAM BACK-UP MODE
The 4513/4514 Group has the RAM back-up mode. When the EPOF and POF instructions are executed continuously, system enters the RAM back-up state. The POF instruction is equal to the NOP instruction when the EPOF instruction is not executed before the POF instruction. As oscillation stops retaining RAM, the function of reset circuit and states at RAM back-up mode, current dissipation can be reduced without losing the contents of RAM. Table 20 shows the function and states retained at RAM back-up. Figure 38 shows the state transition.
Table 20 Functions and states retained at RAM back-up Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Port level Timer control register W1 Timer control registers W2 to W4, W6 Clock control register MR Interrupt control registers V1, V2 Interrupt control registers I1, I2 Timer 1 function Timer 2 function Timer 3 function Timer 4 function A-D conversion function A-D control registers Q1, Q2 Voltage comparator function Voltage comparator control register Q3 Serial I/O function Serial I/O mode register J1 Pull-up control register PU0 Key-on wakeup control register K0 Direction register FR0 External 0 interrupt request flag (EXF0) External 1 interrupt request flag (EXF1) Timer 1 interrupt request flag (T1F) Timer 2 interrupt request flag (T2F) Timer 3 interrupt request flag (T3F) Timer 4 interrupt request flag (T4F) Watchdog timer flags (WDF1, WDF2) Watchdog timer enable flag (WEF) 16-bit timer (WDT) A-D conversion completion flag (ADF) Serial I/O transmission/reception completion flag (SIOF) Interrupt enable flag (INTE) RAM back-up ! O O ! O ! ! O ! (Note 3) (Note 3) (Note 3) ! O O (Note 5) O ! O O O O ! ! ! (Note 3) (Note 3) (Note 3) ! (Note 4) ! (Note 4) ! (Note 4) ! ! !
(1) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the state of the power down flag (P) with the SNZP instruction.
(2) Warm start condition
When the external wakeup signal is input after the system enters the RAM back-up state by executing the EPOF and POF instructions continuously, the CPU starts executing the program from address 0 in page 0. In this case, the P flag is "1."
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0 when; * reset pulse is input to RESET pin, or * reset by watchdog timer is performed, or * voltage drop detection circuit detects the voltage drop. In this case, the P flag is "0."
Notes 1:"O" represents that the function can be retained, and "!" represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to "7" at RAM back-up. 3: The state of the timer is undefined. 4: Initialize the watchdog timer with the WRST instruction, and then execute the POF instruction. 5: The state is retained when the voltage comparator function is selected with the voltage comparator control register Q3.
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(4) Return signal
An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 21 shows the return condition for each return source.
(5) Ports P0 and P1 control registers
* Key-on wakeup control register K0 Register K0 controls the ports P0 and P1 key-on wakeup function. Set the contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A. * Pull-up control register PU0 Register PU0 controls the ON/OFF of the ports P0 and P1 pull-up transistor. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A.
External wakeup signal
Table 21 Return source and return condition Return source Return condition Ports P0, P1 Return by an external falling edge input ("H""L"). Port P30/INT0 Return by an external "H" level or "L" level input. The EXF0 flag is not set. Return by an external "H" level or "L" level input. The EXF1 flag is not set.
Remarks Set the port using the key-on wakeup function selected with register K0 to "H" level before going into the RAM back-up state because the port P0 shares the falling edge detection circuit with port P1. Select the return level ("L" level or "H" level) with the bit 2 of register I1 according to the external state before going into the RAM back-up state. Select the return level ("L" level or "H" level) with the bit 2 of register I2 according to the external state before going into the RAM back-up state.
Port P31/INT1
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A (Stabilizing time a ) Reset f(XIN) oscillation
POF instruction is executed Return input (Stabilizing time a )
B f(XIN) stop (RAM back-up mode)
Stabilizing time a : Time required to stabilize the f(XIN) oscillation is automatically generated by hardware.
Fig. 38 State transition
Power down flag P POF instruction Reset input or voltage drop detection circuit output S Q Software start P = "1" ? No Cold start Yes
R
q Set source * * * * * * * POF instruction is executed q Clear source * * * * * * Reset input
Warm start
Fig. 39 Set source and clear source of the P flag
Fig. 40 Start condition identified example using the SNZP instruction
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Table 22 Key-on wakeup control register, pull-up control register, and interrupt control register Key-on wakeup control register K0 K03 K02 K01 K00 Pins P12 and P13 key-on wakeup control bit Pins P10 and P11 key-on wakeup control bit Pins P02 and P03 key-on wakeup control bit Pins P00 and P01 key-on wakeup control bit Pull-up control register PU0 PU03 PU02 PU01 PU00 Pins P12 and P13 pull-up transistor control bit Pins P10 and P11 pull-up transistor control bit Pins P02 and P03 pull-up transistor control bit Pins P00 and P01 pull-up transistor control bit Interrupt control register I1 I13 Not used 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W
Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at reset : 00002 at RAM back-up : state retained R/W at RAM back-up : state retained R/W
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT0 pin is recognized with the SNZI0 instruction)/"L" level Rising waveform ("H" level of INT0 pin is recognized with the SNZI0 instruction)/"H" level One-sided edge detected Both edges detected Disabled Enabled at reset : 00002 at RAM back-up : state retained R/W
I12
Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2)
I11 I10
INT0 pin edge detection circuit control bit INT0 pin timer 1 control enable bit Interrupt control register I2
I23
Not used
0 1 0 1 0 1 0 1
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT1 pin is recognized with the SNZI1 instruction)/"L" level Rising waveform ("H" level of INT1 pin is recognized with the SNZI1 instruction)/"H" level One-sided edge detected Both edges detected Disabled Enabled
I22
Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3)
I21 I20
INT1 pin edge detection circuit control bit INT1 pin timer 3 control enable bit
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction. 3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
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CLOCK CONTROL
The clock control circuit consists of the following circuits. * System clock generating circuit * Control circuit to stop the clock oscillation
* Control circuit to switch the middle-speed mode and high-speed mode * Control circuit to return from the RAM back-up state
Division circuit (divided by 2) XIN XOUT
MR3
1 0
System clock Internal clock generation circuit (divided by 3) Instruction clock Counter Wait time (Note) control circuit
Oscillation circuit
POF instruction
R S
Q
RESET Key-on wake up control register K00,K01,K02,K03 Ports P00, P01 MultiPorts P02, P03 Falling detected Ports P10, P11 plexer Ports P12, P13 I12
"L" level
Software start signal
0
P30/INT0
1
"H" level
"L" level
I22
0
P31/INT1
1
"H" level
Note: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation.
Fig. 41 Clock control circuit structure Table 23 Clock control register MR Clock control register MR MR3 MR2 MR1 MR0 System clock selection bit Not used Not used Not used 0 1 0 1 0 1 0 1 at reset : 10002 at RAM back-up : 10002 R/W
f(XIN) (high-speed mode) f(XIN)/2 (middle-speed mode) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled.
Note : "R" represents read enabled, and "W" represents write enabled.
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FUNCTION BLOCK OPERATIONS/ROM ORDERING METHOD
Clock signal f(XIN) is obtained by externally connecting a ceramic resonator. Connect this external circuit to pins XIN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT. When an external clock signal is input, connect the clock source to XIN and leave XOUT open. When using an external clock, the maximum value of external clock oscillating frequency is shown in Table 24. CIN
4513/4514
XIN
Note: Externally connect a damping resistor Rd depending on the oscillation XOUT frequency. (A feedback resistor is built-in.) Rd Use the resonator manufacturer's recommended value because constants COUT such as capacitance depend on the resonator.
Fig. 42 Ceramic resonator external circuit
4513/4514
XIN
XOUT
VDD VSS
External oscillation circuit
Fig. 43 External clock input circuit
Table 24 Maximum value of external clock oscillation frequency Middle-speed mode Mask ROM version High-speed mode Middle-speed mode One Time PROM version High-speed mode Supply voltage VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V Oscillation frequency (duty ratio) 3.0 MHz (40 % to 60 %) 3.0 MHz (40 % to 60 %) 1.0 MHz (40 % to 60 %) 0.8 MHz (40 % to 60 %) 3.0 MHz (40 % to 60 %) 3.0 MHz (40 % to 60 %) 1.0 MHz (40 % to 60 %)
ROM ORDERING METHOD
Please submit the information described below when ordering Mask ROM. (1) Mask ROM Order Confirmation Form ..................................... 1 (2) Data to be written into mask ROM ............................... EPROM (three sets containing the identical data) (3) Mark Specification Form .......................................................... 1
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LIST OF PRECAUTIONS
Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; * connect a bypass capacitor (approx. 0.1 F) between pins VDD and VSS at the shortest distance, * equalize its wiring in width and length, and * use relatively thick wire. In the One Time PROM version, CNVSS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 k in series at the shortest distance. Prescaler Stop the prescaler operation to change its frequency dividing ratio. Timer count source Stop timer 1, 2, 3, or 4 counting to change its count source. Reading the count value Stop timer 1, 2, 3, or 4 counting and then execute the TAB1, TAB2, TAB3, or TAB4 instruction to read its data. Writing to reload registers R1 and R3 When writing data to reload registers R1 or R3 while timer 1 or timer 3 is operating, avoid a timing when timer 1 or timer 3 underflows. P30/INT0 pin When the interrupt valid waveform of the P30/INT0 pin is changed with the bit 2 of register I1 in software, be careful about the following notes. * Clear the bit 0 of register V1 to "0" before the interrupt valid waveform of P30/INT0 pin is changed with the bit 2 of register I1 (refer to Figure 44). * Depending on the input state of the P30/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the interrupt valid waveform is changed. Accordingly, clear bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction (refer to Figure 44)
P31/INT1 pin When the interrupt valid waveform of P31/INT1 pin is changed with the bit 2 of register I2 in software, be careful about the following notes. * Clear the bit 1 of register V1 to "0" before the interrupt valid waveform of P31/INT1 pin is changed with the bit 2 of register I2 (refer to Figure 45). * Depending on the input state of the P31/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the interrupt valid waveform is changed. Accordingly, clear bit 2 of register I2 and execute the SNZ1 instruction to clear the EXF1 flag after executing at least one instruction (refer to Figure 45).
. . .
LA 8 TV1A LA 8 TI2A NOP SNZ1 NOP ; (!!0!2) ; The SNZ1 instruction is valid ........... ; Change of the interrupt valid waveform ........................................................... ; The SNZ1 instruction is executed
. . .
! : this bit is not related to the setting of INT1.
Fig. 45 External 1 interrupt program example One Time PROM version The operating power voltage of the One Time PROM version is 2.5 V to 5.5 V. Multifunction The input of D6, D7, P20-P22, I/O of P30 and P31, input of CMP0-, CMP0+, CMP1-, CMP1+, and I/O of P40-P43 can be used even when CNTR0, CNTR1, SCK, SOUT, SIN, INT0, INT1, AIN0-AIN3 and AIN4-AIN7 are selected.
. . .
LA 4 TV1A LA 4 TI1A NOP SNZ0 NOP ; (!!!02) ; The SNZ0 instruction is valid ........... ; ; Interrupt valid waveform is changed ........................................................... ; The SNZ0 instruction is executed
. . .
! : this bit is not related to the setting of INT0 pin. Fig. 44 External 0 interrupt program example
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LIST OF PRECAUTIONS
A-D converter-1 When the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 in a program, be careful about the following notes. * Clear the bit 2 of register V2 to "0" to change the operating mode of the A-D converter from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 (refer to Figure 46). * The A-D conversion completion flag (ADF) may be set when the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode. Accordingly, set a value to register Q2, and execute the SNZAD instruction to clear the ADF flag. Do not change the operating mode (both A-D conversion mode and comparator mode) of A-D converter with the bit 3 of register Q2 during operating the A-D converter.
Sensor
AIN
Apply the voltage withiin the specifications to an analog input pin.
Fig. 47 Analog input external circuit example-1
. . .
LA 8 TV2A LA 0 TQ2A ; (!0!!2) ; The SNZAD instruction is valid ........ ; (0!!!2) ; Change of the operating mode of the A-D converter from the comparator mode to the A-D conversion mode
About 1k
Sensor
AIN
SNZAD NOP
Fig. 48 Analog input external circuit example-2
12
. . .
!: this bit is not related to the change of the operating mode of the A-D conversion.
Fig. 46 A-D converter operating mode program example
11
A-D converter-2 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A-D accuracy may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 F to 1 F) to analog input pins (Figure 47). When the overvoltage applied to the A-D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 48. In addition, test the application products sufficiently.
POF instruction Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM back-up. Note that system cannot enter the RAM back-up state when executing only the POF instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.
Analog input pins Note the following when using the analog input pins also for I/O port P4 functions: * Even when P40/AIN4-P43/AIN7 are set to pins for analog input, they continue to function as P40-P43 I/O. Accordingly, when any of them are used as I/O port P4 and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to "1." Also, the port input function of the pin functions as an analog input is undefined. * TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is "0."
13 14
Program counter Make sure that the PCH does not specify after the last page of the built-in ROM. Port P3 In the 4513 Group, when the IAP3 instruction is executed, note that the high-order 2 bits of register A is undefined.
15
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Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode. Accordingly, be careful about such state because it causes the increase of the operation current in the RAM backup mode. In order to reduce the operation current in the RAM back-up mode, invalidate (bits 2 and 3 of register Q3 = "0") the voltage comparator function by software before the POF instruction is executed. Also, while the voltage comparator function is valid, current is always consumed by voltage comparator. On the system required for the low-power dissipation, invalidate the voltage comparator when it is unused by software. Register Q3 Bits 0 and 1 of register Q3 can be only read. Note that they cannot be written. Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time (max. 20 s) is passed from the voltage comparator function become valid.
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SYMBOL
SYMBOL
The symbols shown below are used in the following instruction function table and instruction list. Symbol A B DR E Q1 Q2 Q3 AD J1 SI V1 V2 I1 I2 W1 W2 W3 W4 W6 MR K0 PU0 FR0 X Y Z DP PC PCH PCL SK SP CY R1 R2 R3 R4 T1 T2 T3 T4 Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) A-D control register Q1 (4 bits) A-D control register Q2 (4 bits) Voltage comparator control register Q3 (4 bits) Successive comparison register AD (10 bits) Serial I/O mode register J1 (4 bits) Serial I/O register SI (8 bits) Interrupt control register V1 (4 bits) Interrupt control register V2 (4 bits) Interrupt control register I1 (4 bits) Interrupt control register I2 (4 bits) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W3 (4 bits) Timer control register W4 (4 bits) Timer control register W6 (4 bits) Clock control register MR (4 bits) Key-on wakeup control register K0 (4 bits) Pull-up control register PU0 (4 bits) Direction register FR0 (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits ! 8) Stack pointer (3 bits) Carry flag Timer 1 reload register Timer 2 reload register Timer 3 reload register Timer 4 reload register Timer 1 Timer 2 Timer 3 Timer 4 Contents Symbol T1F T2F T3F T4F WDF1 WEF INTE EXF0 EXF1 P ADF SIOF D P0 P1 P2 P3 P4 P5 x y z p n i j A3A2A1A0 Contents Timer 1 interrupt request flag Timer 2 interrupt request flag Timer 3 interrupt request flag Timer 4 interrupt request flag Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag External 1 interrupt request flag Power down flag A-D conversion completion flag Serial I/O transmission/reception completion flag Port D (8 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (3 bits) Port P3 (4 bits) Port P4 (4 bits) Port P5 (4 bits) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before "?" Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x (also same for others)
? () -- M(DP) a p, a C + x
Note : The 4513/4514 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes "1" if the TABP p, RT, or RTS instruction is skipped.
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LIST OF INSTRUCTION FUNCTION
LIST OF INSTRUCTION FUNCTION
GroupMnemonic ing TAB TBA TAY TYA TEAB Register to register transfer Function (A) (B) (B) (A) (A) (Y) (Y) (A) (E7-E4) (B) (E3-E0) (A) (B) (E7-E4) (A) (E3-E0) (DR2-DR0) (A2-A0) (A2-A0) (DR2-DR0) (A3) 0 (A1, A0) (Z1, Z0) (A3, A2) 0 TAX TASP (A) (X) (A2-A0) (SP2-SP0) (A3) 0 Arithmetic operation LXY x, y RAM addresses (X) x, x = 0 to 15 (Y) y, y = 0 to 15 (Z) z, z = 0 to 3 (Y) (Y) + 1 (Y) (Y) - 1 SC TAM j (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1 RC SZC XAM j CMA RAR XAMD j (CY) 1 (CY) 0 (CY) = 0 ? Return operation (A) (A) CY A3A2A1A0 RTI AM AMC RAM to register transfer GroupMnemonic ing XAMI j Function (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1 (M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15 (A) n n = 0 to 15 TABE TABP p (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (PC) (SK(SP)) (SP) (SP) - 1 (A) (A) + (M(DP)) BM a (A) (A) + (M(DP)) + (CY) (CY) Carry An (A) (A) + n n = 0 to 15 (A) (A) AND (M(DP)) (A) (A) OR (M(DP)) Subroutine operation BML p, a (SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) a6-a0 BMLA p (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) (PC) (SK(SP)) (SP) (SP) - 1 RT (PC) (SK(SP)) (SP) (SP) - 1 (PC) (SK(SP)) (SP) (SP) - 1 GroupMnemonic ing SB j Bit operation Function (Mj(DP)) 1 j = 0 to 3 (Mj(DP)) 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (PCL) a6-a0 (PCH) p (PCL) a6-a0 (PCH) p (PCL) (DR2-DR0, A3-A0)
RB j
TMA j
SZB j
Comparison operation Branch operation
LA n
SEAM SEA n
TDA TAD
Ba BL p, a
TAZ
BLA p
LZ z INY DEY
AND OR
RAM to register transfer
RTS
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LIST OF INSTRUCTION FUNCTION
LIST OF INSTRUCTION FUNCTION (continued)
GroupMnemonic ing DI EI SNZ0 Function (INTE) 0 (INTE) 1 (EXF0) = 1 ? After skipping (EXF0) 0 SNZ1 (EXF1) = 1 ? After skipping (EXF1) 0 T1AB SNZI0 Interrupt operation I12 = 1 : (INT0) = "H" ? I12 = 0 : (INT0) = "L" ? I22 = 1 : (INT1) = "H" ? I22 = 0 : (INT1) = "L" ? (A) (V1) T2AB TV1A TAV2 TV2A TAI1 TI1A TAI2 TI2A TAW1 TW1A TAW2 Timer operation TW2A TAW3 TW3A (V1) (A) Timer operation (A) (V2) (V2) (A) (A) (I1) (I1) (A) (A) (I2) (I2) (A) (A) (W1) T4AB (W1) (A) (A) (W2) (W2) (A) (A) (W3) TR3AB (W3) (A) (R37-R34) (B) (R33-R30) (A) SD TR1AB (R47-R44) (B) (T47-T44) (B) (R43-R40) (A) (T43-T40) (A) (R17-R14) (B) (R13-R10) (A) TAB4 (R27-R24) (B) (T27-T24) (B) (R23-R20) (A) (T23-T20) (A) TAB3 (B) (T37-T34) (A) (T33-T30) T3AB (R37-R34) (B) (T37-T34) (B) (R33-R30) (A) (T33-T30) (A) (B) (T47-T44) (A) (T43-T40) IAP3 Input/Output operation OP3A IAP4* OP4A* IAP5* OP5A* CLD RD IAP1 OP1A IAP2 (A) (P1) (P1) (A) (A2-A0) (P22-P20) (A3) 0 (A) (P3) (P3) (A) (A) (P4) (P4) (A) (A) (P5) (P5) (A) (D) 1 (D(Y)) 0 (Y) = 0 to 7 (D(Y)) 1 (Y) = 0 to 7 SZD (D(Y)) = 0 ? (Y) = 0 to 7 (R17-R14) (B) (T17-T14) (B) (R13-R10) (A) (T13-T10) (A) (B) (T27-T24) (A) (T23-T20) GroupMnemonic ing TAW4 TW4A TAW6 TW6A TAB1 Function (A) (W4) (W4) (A) (A) (W6) (W6) (A) (B) (T17-T14) (A) (T13-T10) Timer operation SNZT2 GroupMnemonic ing SNZT1 Function (T1F) = 1 ? After skipping (T1F) 0 (T2F) = 1 ? After skipping (T2F) 0 SNZT3 (T3F) = 1 ? After skipping (T3F) 0 SNZT4 (T4F) = 1 ? After skipping (T4F) 0 (A) (P0) (P0) (A)
SNZI1
TAB2
IAP0 OP0A
TAV1
*: The 4513 Group does not have these instructions.
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LIST OF INSTRUCTION FUNCTION
LIST OF INSTRUCTION FUNCTION (continued)
Grouping Mnemonic TK0A Input/Output operation TAK0 TPU0A TAPU0 TFR0A* TABSI Function (K0) (A) (A) (K0) (PU0) (A) (A) (PU0) TALA (FR0) (A) (A) (SI3-SI0) (B) (SI7-SI4) (SI3-SI0) (A) (SI7-SI4) (B) (A) (J1) (J1) (A) SNZAD SST (SIOF) 0 Serial I/O starting (SIOF) = 1 ? After skipping (SIOF) 0 TAQ2 TQ2A NOP POF EPOF SNZP Other operation WRST TAMR TMRA TAQ3 TQ3A (ADF) = 1 ? After skipping (ADF) 0 (A) (Q2) (Q2) (A) (PC) (PC) + 1 RAM back-up POF instruction valid (P) = 1 ? (WDF1) 0, (WEF) 1 (A) (MR) (MR) (A) (A) (Q3) (Q33, Q32) (A3, A2) (Q31) (CMP1 comparison result) (Q30) (CMP0 comparison result) A-D conversion operation TADAB Grouping Mnemonic TABAD Function (A) (AD5-AD2) (B) (AD9-AD6) However, in the comparator mode, (A) (AD3-AD0) (B) (AD7-AD4) (A) (AD1, AD0, 0, 0) (AD3-AD0) (A) (AD7-AD4) (B) (A) (Q1) (Q1) (A) (ADF) 0 A-D conversion starting
TAQ1 TQ1A ADST
TSIAB Serial I/O control operation
TAJ1 TJ1A
SNZSI
*: The 4513 Group does not have these instructions.
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INSTRUCTION CODE TABLE
INSTRUCTION CODE TABLE (for 4513 Group)
D9-D4 000000 000001000010 000011 000100 000101 000110 000111 001000 001001001010 001011 001100 001101 001110 001111 D3-D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Hex.
010000 011000 010111 011111
00 NOP - POF
01 BLA CLD -
02
03
04 - - - - RT
05 TASP TAD TAX TAZ TAV1
06 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15
07 LA 0 LA 1 LA 2 LA 3 LA 4 LA 5 LA 6 LA 7 LA 8 LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 15
08
09
0A
0B
0C
0D
0E
0F BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL***
10-17 18-1F BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM B B B B B B B B B B B B B B B B
SZB BMLA 0 SZB 1 SZB 2 SZB 3 SZD SEAn SEAM - - - - - - - - - SNZ0
TABP TABP TABP TABP BML BML*** BL 0 16*** 32** 48* TABP TABP TABP TABP BML BML*** BL 1 17*** 33** 49* TABP TABP TABP TABP BML BML*** BL 2 18*** 34** 50* TABP TABP TABP TABP BML BML*** BL 3 19*** 35** 51* TABP TABP TABP TABP BML BML*** BL 4 20*** 36** 52* TABP TABP TABP TABP BML BML*** BL 5 21*** 37** 53* TABP TABP TABP TABP BML BML*** BL 6 22*** 38** 54* TABP TABP TABP TABP BML BML*** BL 7 23*** 39** 55* TABP TABP TABP TABP BML BML*** BL 8 24*** 40** 56* TABP TABP TABP TABP BML BML*** BL 9 25*** 41** 57* TABP TABP TABP TABP BML BML*** BL 10 26*** 42** 58* TABP TABP TABP TABP BML BML*** BL 11 27*** 43** 59* TABP TABP TABP TABP BML BML*** BL 12 28*** 44** 60* TABP TABP TABP TABP BML BML*** BL 13 29*** 45** 61* TABP TABP TABP TABP BML BML*** BL 14 30*** 46** 62* TABP TABP TABP TABP BML BML*** BL 15 31*** 47** 63*
SNZP INY DI EI RC SC - - RD SD - DEY AND OR
RTS TAV2 RTI - LZ 0 LZ 1 LZ 2 LZ 3 RB 0 RB 1 RB 2 RB 3 - - - - - EPOF SB 0 SB 1 SB 2 SB 3
TDA SNZ1
AM TEAB TABE SNZI0 AMC TYA - TBA - - CMA RAR TAB TAY - - - - SNZI1 - - TV2A
SZC TV1A
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the low-order 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011 * * * * *, **, and *** cannot be used in the M34513M2-XXXSP/FP. * and ** cannot be used in the M34513M4-XXXSP/FP. * and ** cannot be used in the M34513E4FP. * cannot be used in the M34513M6-XXXFP.
BL BML BLA BMLA SEA SZD
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INSTRUCTION CODE TABLE
INSTRUCTION CODE TABLE (continued) (for 4513 Group)
D9-D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001101010 101011 101100 101101 101110 101111 D3-D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Hex.
110000 111111
20 - - TJ1A - TQ1A TQ2A
21
22
23
24 - -
25
26
27
28
29 - - - - - - - - - - - - - - SST ADST
2A WRST - - - - - - - - - - - - - - -
2B
2C
2D
2E
2F
30-3F
TW3A OP0A T1AB TW4A OP1A T2AB - -
TAW6 IAP0 TAB1 SNZT1 - IAP1 TAB2 SNZT2
TMA TAM XAM XAMI XAMD LXY 0 0 0 0 0 TMA TAM XAM XAMI XAMD LXY 1 1 1 1 1 TMA TAM XAM XAMI XAMD LXY 2 2 2 2 2 TMA TAM XAM XAMI XAMD LXY 3 3 3 3 3 TMA TAM XAM XAMI XAMD LXY 4 4 4 4 4 TMA TAM XAM XAMI XAMD LXY 5 5 5 5 5 TMA TAM XAM XAMI XAMD LXY 6 6 6 6 6 TMA TAM XAM XAMI XAMD LXY 7 7 7 7 7 TMA TAM XAM XAMI XAMD LXY 8 8 8 8 8 TMA TAM XAM XAMI XAMD LXY 9 9 9 9 9 TMA TAM XAM XAMI XAMD LXY 10 10 10 10 10 TMA TAM XAM XAMI XAMD LXY 11 11 11 11 11 TMA TAM XAM XAMI XAMD LXY 12 12 12 12 12 TMA TAM XAM XAMI XAMD LXY 13 13 13 13 13 TMA TAM XAM XAMI XAMD LXY 14 14 14 14 14 TMA TAM XAM XAMI XAMD LXY 15 15 15 15 15
T3AB TAJ1 TAMR IAP2 TAB3 SNZT3 - TAI1 IAP3 TAB4 SNZT4 - - - - - - - - - - - - - - - - - - - SNZAD
TW6A OP3A T4AB - - - - - - - - - - - TPU0A - - - - - - TSIAB
TAQ1 TAI2 TAQ2 -
TQ3A TMRA - - - - - - - TW1A TW2A TI1A TI2A - - TK0A - - - -
TAQ3 TAK0 - - TAPU0 - - - - - - - -
TABSI SNZSI TABAD - - - - - - - - - - - - -
TADAB TALA - -
TR3AB TAW1 - - - TR1AB TAW2 TAW3 TAW4 -
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the loworder 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011
BL BML BLA BMLA SEA SZD
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INSTRUCTION CODE TABLE
INSTRUCTION CODE TABLE (for 4514 Group)
D9-D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001001010 001011 001100 001101 001110 001111 D3-D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Hex.
010000 011000 010111 011111
00 NOP - POF
01 BLA CLD -
02
03
04 - - - - RT
05 TASP TAD TAX TAZ TAV1
06 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15
07 LA 0 LA 1 LA 2 LA 3 LA 4 LA 5 LA 6 LA 7 LA 8 LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 15
08
09
0A
0B
0C
0D BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML
0E BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL
0F BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL
10-17 18-1F BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM B B B B B B B B B B B B B B B B
SZB BMLA 0 SZB 1 SZB 2 SZB 3 SZD SEAn SEAM - - - - - - - - - SNZ0
TABP TABP TABP TABP BML 48* 0 16 32 TABP TABP TABP TABP BML 49* 1 17 33 TABP TABP TABP TABP BML 50* 2 18 34 TABP TABP TABP TABP BML 51* 3 19 35 TABP TABP TABP TABP BML 52* 4 20 36 TABP TABP TABP TABP BML 53* 5 21 37 TABP TABP TABP TABP BML 54* 6 22 38 TABP TABP TABP TABP BML 55* 7 23 39 TABP TABP TABP TABP BML 56* 8 24 40 TABP TABP TABP TABP 57* BML 9 25 41 TABP TABP TABP TABP BML 58* 10 26 42 TABP TABP TABP TABP 59* BML 11 27 43 TABP TABP TABP TABP BML 60* 12 28 44 TABP TABP TABP TABP 61* BML 13 29 45 TABP TABP TABP TABP 62* BML 14 30 46 TABP TABP TABP TABP 63* BML 15 31 47
SNZP INY DI EI RC SC - - AM AMC TYA - TBA - RD SD - DEY AND OR
RTS TAV2 RTI - LZ 0 LZ 1 LZ 2 LZ 3 RB 0 RB 1 RB 2 RB 3 - - - - - EPOF SB 0 SB 1 SB 2 SB 3
TDA SNZ1
TEAB TABE SNZI0 - CMA RAR TAB TAY - - - - SNZI1 - - TV2A
SZC TV1A
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the low-order 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011 * * cannot be used in the M34514M6-XXXFP.
BL BML BLA BMLA SEA SZD
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INSTRUCTION CODE TABLE
INSTRUCTION CODE TABLE (continued) (for 4514 Group)
D9-D4 100000 100001100010 100011 100100 100101 100110 100111 101000 101001101010 101011 101100 101101 101110 101111 D3-D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Hex.
110000 111111 30-3F
20 - - TJ1A - TQ1A TQ2A
21
22
23
24 - -
25
26
27
28
29 - - - - - - - - - - - - - - SST ADST
2A WRST - - - - - - - - - - - - - - -
2B
2C
2D
2E
2F
TW3A OP0A T1AB TW4A OP1A T2AB - -
TAW6 IAP0 TAB1 SNZT1 - IAP1 TAB2 SNZT2
TMA TAM XAM XAMI XAMD LXY 0 0 0 0 0 TMA TAM XAM XAMI XAMD LXY 1 1 1 1 1 TMA TAM XAM XAMI XAMD LXY 2 2 2 2 2 TMA TAM XAM XAMI XAMD LXY 3 3 3 3 3 TMA TAM XAM XAMI XAMD LXY 4 4 4 4 4 TMA TAM XAM XAMI XAMD LXY 5 5 5 5 5 TMA TAM XAM XAMI XAMD LXY 6 6 6 6 6 TMA TAM XAM XAMI XAMD LXY 7 7 7 7 7 TMA TAM XAM XAMI XAMD LXY 8 8 8 8 8 TMA TAM XAM XAMI XAMD LXY 9 9 9 9 9 TMA TAM XAM XAMI XAMD LXY 10 10 10 10 10 TMA TAM XAM XAMI XAMD LXY 11 11 11 11 11 TMA TAM XAM XAMI XAMD LXY 12 12 12 12 12 TMA TAM XAM XAMI XAMD LXY 13 13 13 13 13 TMA TAM XAM XAMI XAMD LXY 14 14 14 14 14 TMA TAM XAM XAMI XAMD LXY 15 15 15 15 15
T3AB TAJ1 TAMR IAP2 TAB3 SNZT3 - TAI1 IAP3 TAB4 SNZT4 - - - - - - - SNZAD
TW6A OP3A T4AB - - OP4A OP5A - - - - - -
TAQ1 TAI2 IAP4 TAQ2 - IAP5 - - - - - - - - - -
TQ3A TMRA - - - - - - - TW1A TW2A TI1A
TAQ3 TAK0 - - TAPU0 - - - - - - - -
TI2A TFR0ATSIAB - - TK0A - - - - - - - - TPU0A - -
TABSI SNZSI TABAD - - - - - - - - - - - - -
TADAB TALA - -
TR3AB TAW1 - - - TR1AB TAW2 TAW3 TAW4 -
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the loworder 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011
BL BML BLA BMLA SEA SZD
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MACHINE INSTRUCTIONS
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAB TBA TAY TYA 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 1 1 0 0
01E 00E 01F 00C 01A 02A 029 051 053 052 050 3xy
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
(A) (B) (B) (A) (A) (Y) (Y) (A) (E7-E4) (B) (E3-E0) (A) (B) (E7-E4) (A) (E3-E0) (DR2-DR0) (A2-A0) (A2-A0) (DR2-DR0) (A3) 0 (A1, A0) (Z1, Z0) (A3, A2) 0 (A) (X) (A2-A0) (SP2-SP0) (A3) 0 (X) x, x = 0 to 15 (Y) y, y = 0 to 15 (Z) z, z = 0 to 3 (Y) (Y) + 1 (Y) (Y) - 1
Register to register transfer
TEAB TABE TDA TAD TAZ TAX TASP LXY x, y
x3 x2 x1 x0 y3 y2 y1 y0
RAM addresses
LZ z INY DEY
0 0 0
0 0 0
0 0 0
1 0 0
0 0 0
0 1 1
1 0 0
0 0 1
z1 z0 1 1 1 1
048 +z 013 017
1 1 1
1 1 1
TAM j
1
0
1
1
0
0
j
j
j
j
2 Cj
1
1
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1 (M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15
XAM j RAM to register transfer
1
0
1
1
0
1
j
j
j
j
2 Dj
1
1
XAMD j
1
0
1
1
1
1
j
j
j
j
2Fj
1
1
XAMI j
1
0
1
1
1
0
j
j
j
j
2Ej
1
1
TMA j
1
0
1
0
1
1
j
j
j
j
2Bj
1
1
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HARDWARE
MACHINE INSTRUCTIONS
Skip condition
Carry flag CY
Datailed description
- - - - - - - - - - - Continuous description - (Y) = 0 (Y) = 15
- - - - - - - - - - - -
Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of registers A and B to register E. Transfers the contents of register E to registers A and B. Transfers the contents of register A to register D. Transfers the contents of register D to register A. Transfers the contents of register Z to register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
- - -
-
-
-
-
(Y) = 15
-
(Y) = 0
-
-
-
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HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LA n 0 0 0 1 1 1 n n n n
07n
1
1
(A) n n = 0 to 15 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (PC) (SK(SP)) (SP) (SP) - 1 (Note) (A) (A) + (M(DP)) (A) (A) + (M(DP)) +(CY) (CY) Carry (A) (A) + n n = 0 to 15 (A) (A) AND (M(DP)) (A) (A) OR (M(DP)) (CY) 1 (CY) 0 (CY) = 0 ? (A) (A) CY A3A2A1A0 (Mj(DP)) 1 j = 0 to 3 (Mj(DP)) 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15
TABP p
0
0
1
0
p5 p4 p3 p2 p1 p0
08p +p
1
3
AM Arithmetic operation AMC An
0 0 0
0 0 0
0 0 0
0 0 1
0 0 1
0 0 0
1 1 n
0 0 n
1 1 n
0 1 n
00A 00B 06n
1 1 1
1 1 1
AND OR SC RC SZC CMA RAR SB j
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 1 0 0 0 1
0 0 0 0 1 0 0 0 0 1 1 1 1
1 1 0 0 0 1 1 1 0 0 0 0 1
1 1 0 0 1 1 1 1 1 0 0 0 n
0 0 1 1 1 1 1 1 1 0 1 1 n
0 0 1 1 1 0 0 j j j 1 0 n
0 1 1 0 1 0 1 j j j 0 1 n
018 019 007 006 02F 01C 01D 05C +j 04C +j 02j 026 025 07n
1 1 1 1 1 1 1 1 1 1 1 2
1 1 1 1 1 1 1 1 1 1 1 2
Bit operation Comparison operation
RB j SZB j SEAM SEA n
Note : p is 0 to 15 for M34513M2, p is 0 to 31 for M34513M4/E4, p is 0 to 47 for M34513M6 and M34514M6, and p is 0 to 63 for M34513M8/E8 and M34514M8/E8.
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HARDWARE
MACHINE INSTRUCTIONS
Skip condition
Carry flag CY
Datailed description
Continuous description -
-
Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, 1 stage of stack register is used.
-
- - Overflow = 0
-
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. - Adds the value n in the immediate field to register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is "0." Stores the one's complement for register A's contents in register A.
- - - - (CY) = 0 - - - - (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n
- - 1 0 - -
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. - - - - - Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is "0." Skips the next instruction when the contents of register A is equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
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HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ba BL p, a 0 0 1 BLA p 0 1 BM a 0 1 0 0 0 0 1 1 1 a6 a5 a4 a3 a2 a1 a0 1 1 p4 p3 p2 p1 p0
18a +a 0Ep +p 2pa +a 010 2pp 1aa
1 2
1 2
(PCL) a6-a0 (PCH) p (PCL) a6-a0 (Note)
Branch operation
p5 a6 a5 a4 a3 a2 a1 a0 0 0 0 1 0 0 0 0 0
2
2
p5 p4 0 0
p3 p2 p1 p0
(PCH) p (PCL) (DR2-DR0, A3-A0) (Note) (SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) a6-a0 (Note) (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0,A3-A0) (Note) (PC) (SK(SP)) (SP) (SP) - 1 (PC) (SK(SP)) (SP) (SP) - 1 (PC) (SK(SP)) (SP) (SP) - 1 (INTE) 0 (INTE) 1 (EXF0) = 1 ? After skipping (EXF0) 0 (EXF1) = 1 ? After skipping (EXF1) 0
a6 a5 a4 a3 a2 a1 a0
1
1
Subroutine operation
BML p, a
0 1
0 0 0 0
1
1
0
p4 p3 p2 p1 p0
0Cp +p 2pa +a 030 2pp
2
2
p5 a6 a5 a4 a3 a2 a1 a0 0 0 1 1 0 0 0 0 0
BMLA p
0 1
2
2
p5 p4 0
p3 p2 p1 p0
RTI Return operation
0
0
0
1
0
0
0
1
1
0
046
1
1
RT RTS DI
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
1 1 0 0 0
0 0 0 0 1
0 0 0 0 1
0 0 0 0 1
1 1 1 1 0
0 0 0 0 0
0 1 0 1 0
044 045 004 005 038
1 1 1 1 1
2 2 1 1 1
Interrupt operation
EI SNZ0
SNZ1
0
0
0
0
1
1
1
0
0
1
039
1
1
Note : p is 0 to 15 for M34513M2, p is 0 to 31 for M34513M4/E4, p is 0 to 47 for M34513M6 and M34514M6, and p is 0 to 63 for M34513M8/E8 and M34514M8/E8.
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HARDWARE
MACHINE INSTRUCTIONS
Skip condition
Carry flag CY
Datailed description
- -
- -
Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p.
-
-
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
-
-
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
-
-
Call the subroutine : Calls the subroutine at address a in page p.
-
-
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
-
-
Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine. Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. Clears (0) to the interrupt enable flag INTE, and disables the interrupt. Sets (1) to the interrupt enable flag INTE, and enables the interrupt. Skips the next instruction when the contents of EXF0 flag is "1." After skipping, clears (0) to the EXF0 flag. Skips the next instruction when the contents of EXF1 flag is "1." After skipping, clears (0) to the EXF1 flag.
- Skip at uncondition - - (EXF0) = 1
- - - - -
(EXF1) = 1
-
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HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SNZI0 0 0 0 0 1 1 1 0 1 0
03A
1
1
I12 = 1 : (INT0) = "H" ? I12 = 0 : (INT0) = "L" ?
SNZI1
0
0
0
0
1
1
1
0
1
1
03B
1
1
I22 = 1 : (INT1) = "H" ? I22 = 0 : (INT1) = "L" ?
Interrupt operation
TAV1 TV1A TAV2 TV2A TAI1 TI1A TAI2 TI2A TAW1 TW1A TAW2
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 1 1
0 1 0 1 0 0 0 1 1 1 1 1 1 0 1 0 0 0
1 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 0 0
0 1 0 1 1 1 0 0 1 1 0 1 0 0 1 0 0 1
0 1 1 0 1 1 0 0 1 0 0 1 1 0 0 1 0 1
054 03F 055 03E 253 217 254 218 24B 20E 24C 20F 24D 210 24E 211 250 213
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(A) (V1) (V1) (A) (A) (V2) (V2) (A) (A) (I1) (I1) (A) (A) (I2) (I2) (A) (A) (W1) (W1) (A) (A) (W2) (W2) (A) (A) (W3) (W3) (A) (A) (W4) (W4) (A) (A) (W6) (W6) (A)
Timer operation
TW2A TAW3 TW3A TAW4 TW4A TAW6 TW6A
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4513/4514 Group User's Manual
HARDWARE
MACHINE INSTRUCTIONS
Skip condition
Carry flag CY
Datailed description
(INT0) = "H" However, I12 = 1 (INT0) = "L" However, I12 = 0 (INT1) = "H" However, I22 = 1 (INT1) = "L" However, I22 = 0 - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - -
When bit 2 (I12) of register I1 is "1" : Skips the next instruction when the level of INT0 pin is "H." When bit 2 (I12) of register I1 is "0" : Skips the next instruction when the level of INT0 pin is "L." When bit 2 (I22) of register I2 is "1" : Skips the next instruction when the level of INT1 pin is "H." When bit 2 (I22) of register I2 is "0" : Skips the next instruction when the level of INT1 pin is "L." Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register V2 to register A. Transfers the contents of register A to interrupt control register V2. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1. Transfers the contents of interrupt control register I2 to register A. Transfers the contents of register A to interrupt control register I2. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W3 to register A. Transfers the contents of register A to timer control register W3. Transfers the contents of timer control register W4 to register A. Transfers the contents of register A to timer control register W4. Transfers the contents of timer control register W6 to register A. Transfers the contents of register A to timer control register W6.
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HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAB1 T1AB 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0
270 230
1 1
1 1
(B) (T17-T14) (A) (T13-T10) (R17-R14) (B) (T17-T14) (B) (R13-R10) (A) (T13-T10) (A) (B) (T27-T24) (A) (T23-T20) (R27-R24) (B) (T27-T24) (B) (R23-R20) (A) (T23-T20) (A) (B) (T37-T34) (A) (T33-T30) (R37-R34) (B) (T37-T34) (B) (R33-R30) (A) (T33-T30) (A) (B) (T47-T44) (A) (T43-T40) (R47-R44) (B) (T47-T44) (B) (R43-R40) (A) (T43-T40) (A) (R17-R14) (B) (R13-R10) (A) (R37-R34) (B) (R33-R30) (A) (T1F) = 1 ? After skipping (T1F) 0 (T2F) = 1 ? After skipping (T2F) 0 (T3F) = 1 ? After skipping (T3F) 0 (T4F) = 1 ? After skipping (T4F) 0
TAB2 T2AB
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
0 0
1 1
271 231
1 1
1 1
TAB3 T3AB
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
1 1
0 0
272 232
1 1
1 1
Timer operation
TAB4 T4AB
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
1 1
1 1
273 233
1 1
1 1
TR1AB TR3AB SNZT1
1 1 1
0 0 0
0 0 1
0 0 0
1 1 0
1 1 0
1 1 0
1 0 0
1 1 0
1 1 0
23F 23B 280
1 1 1
1 1 1
SNZT2
1
0
1
0
0
0
0
0
0
1
281
1
1
SNZT3
1
0
1
0
0
0
0
0
1
0
282
1
1
SNZT4
1
0
1
0
0
0
0
0
1
1
283
1
1
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4513/4514 Group User's Manual
HARDWARE
MACHINE INSTRUCTIONS
Skip condition
Carry flag CY
Datailed description
- -
- -
Transfers the contents of timer 1 to registers A and B. Transfers the contents of registers A and B to timer 1 and timer 1 reload register.
- -
- -
Transfers the contents of timer 2 to registers A and B. Transfers the contents of registers A and B to timer 2 and timer 2 reload register.
- -
- -
Transfers the contents of timer 3 to registers A and B. Transfers the contents of registers A and B to timer 3 and timer 3 reload register.
- -
- -
Transfers the contents of timer 4 to registers A and B. Transfers the contents of registers A and B to timer 4 and timer 4 reload register.
- - (T1F) = 1
- - -
Transfers the contents of registers A and B to timer 1 reload register. Transfers the contents of registers A and B to timer 3 reload register. Skips the next instruction when the contents of T1F flag is "1." After skipping, clears (0) to T1F flag. Skips the next instruction when the contents of T2F flag is "1." After skipping, clears (0) to T2F flag. Skips the next instruction when the contents of T3F flag is "1." After skipping, clears (0) to T3F flag. Skips the next instruction when the contents of T4F flag is "1." After skipping, clears (0) to T4F flag.
(T2F) =1
-
(T3F) = 1
-
(T4F) = 1
-
4513/4514 Group User's Manual
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HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IAP0 OP0A IAP1 OP1A IAP2 IAP3 OP3A IAP4* OP4A* 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 TK0A TAK0 TPU0A TAPU0 TFR0A* 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0
260 220 261 221 262 263 223 264 224 265 225 011 014 015 024 02B 21B 256 22D 257 228
1 1 1 1 1 1 1 1 1 1 1 1 1 1 2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 2
(A) (P0) (P0) (A) (A) (P1) (P1) (A) (A2-A0) (P22-P20) (A3) 0 (A) (P3) (P3) (A) (A) (P4) (P4) (A) (A) (P5) (P5) (A) (D) 1 (D(Y)) 0 (Y) = 0 to 7 (D(Y)) 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 0 to 7
Input/Output operation
IAP5* OP5A* CLD RD SD SZD
1 1 1 1 1
1 1 1 1 1
(K0) (A) (A) (K0) (PU0) (A) (A) (PU0) (FR0) (A)
*: The 4513 Group does not have these instructions.
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4513/4514 Group User's Manual
HARDWARE
MACHINE INSTRUCTIONS
Skip condition
Carry flag CY
Datailed description
- - - - - - - - - - - - - - (D(Y)) = 0 (Y) = 0 to 7
- - - - - - - - - - - - - - -
Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to register A. Transfers the input of port P3 to register A. Outputs the contents of register A to port P3. Transfers the input of port P4 to register A. Outputs the contents of register A to port P4. Transfers the input of port P5 to register A. Outputs the contents of register A to port P5. Sets (1) to port D. Clears (0) to a bit of port D specified by register Y. Sets (1) to a bit of port D specified by register Y. Skips the next instruction when a bit of port D specified by register Y is "0."
- - - - -
- - - - -
Transfers the contents of register A to key-on wakeup control register K0. Transfers the contents of key-on wakeup control register K0 to register A. Transfers the contents of register A to pull-up control register PU0. Transfers the contents of pull-up control register PU0 to register A. Transfers the contents of register A to direction register FR0.
4513/4514 Group User's Manual
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HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TABSI 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0
278 238 242 202 29E 288
1 1 1 1 1 1
1 1 1 1 1 1
(A) (SI3-SI0) (B) (SI7-SI4) (SI3-SI0) (A) (SI7-SI4) (B) (A) (J1) (J1) (A) (SIOF) 0 Serial I/O starting (SIOF) = 1 ? After skipping (SIOF) 0 (A) (AD5-AD2) (B) (AD9-AD6) However, in the comparator mode, (A) (AD3-AD0) (B) (AD7-AD4) (A) (AD1, AD0, 0, 0) (AD3-AD0) (A) (AD7-AD4) (B) (A) (Q1) (Q1) (A) (ADF) 0 A-D conversion starting (ADF) = 1 ? After skipping (ADF) 0 (A) (Q2) (Q2) (A) (PC) (PC) + 1 RAM back-up POF instruction valid (P) = 1 ? (WDF1) 0 (WEF) 1 (A) (MR) (MR) (A) (A) (Q3) (Q33, Q32) (A3, A2) (Q31) (CMP1 comparison result) (Q30) (CMP0 comparison result)
Serial I/O control operation
TSIAB TAJ1 TJ1A SST SNZSI
TABAD
1
0
0
1
1
1
1
0
0
1
279
1
1
TALA A-D conversion operation TADAB TAQ1 TQ1A ADST SNZAD
1 1 1 1 1 1
0 0 0 0 0 0
0 0 0 0 1 1
1 0 1 0 0 0
0 1 0 0 0 0
0 1 0 0 1 0
1 1 0 0 1 0
0 0 1 1 1 1
0 0 0 0 1 1
1 1 0 0 1 1
249 239 244 204 29F 287
1 1 1 1 1 1
1 1 1 1 1 1
TAQ2 TQ2A NOP POF EPOF Other operation SNZP WRST TAMR TMRA TAQ3 TQ3A
1 1 0 0 0 0 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 0 0 0 0
1 0 0 0 1 0 0 1 0 1 0
0 0 0 0 0 0 1 0 0 0 0
0 0 0 0 1 0 0 1 1 0 0
0 0 0 0 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0 1 1 1
0 0 0 1 1 1 0 1 1 1 1
1 1 0 0 1 1 0 0 0 0 0
245 205 000 002 05B 003 2A0 252 216 246 206
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1
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HARDWARE
MACHINE INSTRUCTIONS
Skip condition
Carry flag CY
Datailed description
- - - - - (SIOF) = 1
- - - - - -
Transfers the contents of serial I/O register SI to registers A and B. Transfers the contents of registers A and B to serial I/O register SI. Transfers the contents of serial I/O mode register J1 to register A. Transfers the contents of register A to serial I/O mode register J1. Clears (0) to SIOF flag and starts serial I/O. Skips the next instruction when the contents of SIOF flag is "1." After skipping, clears (0) to SIOF flag. Transfers the high-order 8 bits of the contents of register AD to registers A and B.
-
-
- - - - - (ADF) = 1
- - - - - -
Transfers the low-order 2 bits of the contents of register AD to the high-order 2 bits of the contents of register A. Simultaneously, the low-order 2 bits of the contents of the register A is "0." Transfers the contents of registers A and B to the comparator register at the comparator mode. Transfers the contents of the A-D control register Q1 to register A. Transfers the contents of register A to the A-D control register Q1. Clears the ADF flag, and the A-D conversion at the A-D conversion mode or the comparator operation at the comparator mode is started. Skips the next instruction when the contents of ADF flag is "1". After skipping, clears (0) the contents of ADF flag. Transfers the contents of the A-D control register Q2 to register A. Transfers the contents of register A to the A-D control register Q2. No operation Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction. Makes the immediate POF instruction valid by executing the EPOF instruction. Skips the next instruction when P flag is "1". After skipping, P flag remains unchanged. Operates the watchdog timer and initializes the watchdog timer flag WDF1. Transfers the contents of the clock control register MR to register A. Transfers the contents of register A to the clock control register MR. Transfers the contents of the voltage comparator control register Q3 to register A. Transfers the contents of the high-order 2 bits of register A to the high-order 2 bits of voltage comparator control register Q3, and the comparison result of the voltage comparator is transferred to the low-order 2 bits of the register Q3.
- - - - - (P) = 1 - - - - -
- - - - - - - - - - -
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HARDWARE
CONTROL REGISTERS
CONTROL REGISTERS
Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit Interrupt control register V2 V23 V22 V21 V20 Serial I/O interrupt enable bit A-D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit Interrupt control register I1 I13 Not used 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) at reset : 00002 at RAM back-up : 00002 R/W
Interrupt disabled (SNZSI instruction is valid) Interrupt enabled (SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) at reset : 00002 at RAM back-up : state retained R/W
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT0 pin is recognized with the SNZI0 instruction)/"L" level Rising waveform ("H" level of INT0 pin is recognized with the SNZI0 instruction)/"H" level One-sided edge detected Both edges detected Disabled Enabled at reset : 00002 at RAM back-up : state retained R/W
I12
Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2)
I11 I10
INT0 pin edge detection circuit control bit INT0 pin timer 1 control enable bit Interrupt control register I2
I23
Not used
0 1 0 1 0 1 0 1
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT1 pin is recognized with the SNZI1 instruction)/"L" level Rising waveform ("H" level of INT1 pin is recognized with the SNZI1 instruction)/"H" level One-sided edge detected Both edges detected Disabled Enabled
I22
Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3)
I21 I20
INT1 pin edge detection circuit control bit INT1 pin timer 3 control enable bit
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction. 3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
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CONTROL REGISTERS
Timer control register W1 W13 W12 W11 W10 Prescaler control bit Prescaler dividing ratio selection bit Timer 1 control bit Timer 1 count start synchronous circuit control bit Timer control register W2 W23 W22 W21 Timer 2 count source selection bits W20 Timer 2 control bit Not used 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : 00002
R/W
Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected at reset : 00002 at RAM back-up : state retained R/W
0 1 0 1 W21 W20 0 0 0 1 1 0 1 1
Stop (state retained) Operating This bit has no function, but read/write is enabled. Count source Timer 1 underflow signal Prescaler output CNTR0 input 16 bit timer (WDT) underflow signal at RAM back-up : state retained R/W
Timer control register W3 W33 W32 W31 Timer 3 count source selection bits W30 Timer 3 control bit Timer 3 count start synchronous circuit control bit
at reset : 00002 0 1 0 1 W31 W30 0 0 0 1 1 0 1 1
Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected Count source Timer 2 underflow signal Prescaler output Not available Not available at RAM back-up : state retained R/W
Timer control register W4 W43 W42 W41 Timer 4 count source selection bits W40 Timer 4 control bit Not used
at reset : 00002 0 1 0 1 W41 W40 0 0 0 1 1 0 1 1
Stop (state retained) Operating This bit has no function, but read/write is enabled. Count source Timer 3 underflow signal Prescaler output CNTR1 input Not available at RAM back-up : state retained R/W
Timer control register W6 W63 W62 W61 W60 CNTR1 output control bit D7/CNTR1 function selection bit CNTR0 output control bit D6/CNTR0 output control bit 0 1 0 1 0 1 0 1
at reset : 00002
Timer 3 underflow signal output divided by 2 CNTR1 output control by timer 4 underflow signal divided by 2 D7(I/O)/CNTR1 input CNTR1 (I/O)/D7(input) Timer 1 underflow signal output divided by 2 CNTR0 output control by timer 2 underflow signal divided by 2 D6(I/O)/CNTR0 input CNTR0 (I/O)/D6(input)
Note: "R" represents read enabled, and "W" represents write enabled.
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CONTROL REGISTERS
Serial I/O mode register J1 J13 J12 J11 J10 Not used Serial I/O internal clock dividing ratio selection bit Serial I/O port selection bit Serial I/O synchronous clock selection bit A-D control register Q1 Q13 Note used 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled. Instruction clock signal divided by 8 Instruction clock signal divided by 4 Input ports P20, P21, P22 selected Serial I/O ports SCK, SOUT, SIN/input ports P20, P21, P22 selected External clock Internal clock (instruction clock divided by 4 or 8) at reset : 00002 at RAM back-up : state retained R/W
Q12
Q11
Analog input pin selection bits (Note 2)
Q10
0 1 Q12Q11 Q10 000 001 010 011 100 101 110 111
This bit has no function, but read/write is enabled. Selected pins AIN0 AIN1 AIN2 AIN3 AIN4 (Not available for the 4513 Group) AIN5 (Not available for the 4513 Group) AIN6 (Not available for the 4513 Group) AIN7 (Not available for the 4513 Group) at RAM back-up : state retained R/W
A-D control register Q2 Q23 Q22 Q21 Q20 A-D operation mode selection bit P43/AIN7 and P42/AIN6 pin function selection bit (Not used for the 4513 Group) P41/AIN5 pin function selection bit (Not used for the 4513 Group) P40/AIN4 pin function selection bit (Not used for the 4513 Group) Comparator control register Q3 (Note 3) Q33 Q32 Q31 Q30 Voltage comparator (CMP1) control bit Voltage comparator (CMP0) control bit CMP1 comparison result store bit CMP0 comparison reslut store bit Clock control register MR MR3 MR2 MR1 MR0 System clock selection bit Not used Not used Not used 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
at reset : 00002
A-D conversion mode Comparator mode P43, P42 (read/write enabled for the 4513 Group) AIN7, AIN6/P43, P42 (read/write enabled for the 4513 Group) P41 (read/write enabled for the 4513 Group) AIN5/P41 (read/write enabled for the 4513 Group) P40 (read/write enabled for the 4513 Group) AIN4/P40 (read/write enabled for the 4513 Group) at reset : 00002 Voltage Voltage Voltage Voltage at RAM back-up : state retained R/W
comparator (CMP1) invalid comparator (CMP1) valid comparator (CMP0) invalid comparator (CMP0) valid
CMP1- > CMP1+ CMP1- < CMP1+ CMP0- > CMP0+ CMP0- < CMP0+ at reset : 10002 at RAM back-up : 10002 R/W
f(XIN) (high-speed mode) f(XIN)/2 (middle-speed mode) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled.
Notes 1: "R" represents read enabled, "W" represents write enabled. 2: Select AIN4-AIN7 with register Q1 after setting register Q2. 3: Bits 0 and 1 of register Q3 can be only read.
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CONTROL REGISTERS
Key-on wakeup control register K0 K03 K02 K01 K00 Pins P12 and P13 key-on wakeup control bit Pins P10 and P11 key-on wakeup control bit Pins P02 and P03 key-on wakeup control bit Pins P00 and P01 key-on wakeup control bit Pull-up control register PU0 PU03 PU02 PU01 PU00 Pins P12 and P13 pull-up transistor control bit Pins P10 and P11 pull-up transistor control bit Pins P02 and P03 pull-up transistor control bit Pins P00 and P01 pull-up transistor control bit Direction register FR0 (Note 2) FR03 FR02 FR01 FR00 Port P53 input/output control bit Port P52 input/output control bit Port P51 input/output control bit Port P50 input/output control bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W
Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at reset : 00002 Port P53 input Port P53 output Port P52 Port P52 Port P51 Port P51 input output input output at RAM back-up : state retained W at RAM back-up : state retained R/W
Port P50 input Port P50 output
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: The 4513 Group does not have the direction register FR0.
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HARDWARE
BUILT-IN PROM VERSION
BUILT-IN PROM VERSION
In addition to the mask ROM versions, the 4513/4514 Group has programmable ROM version software compatible with mask ROM. The built-in PROM of One Time PROM version can be written to and not be erased. The built-in PROM versions have functions similar to those of the mask ROM versions, but they have PROM mode that enables writing to built-in PROM. Table 25 shows the product of built-in PROM version. Figure 49 and 50 show the pin configurations of built-in PROM versions. Table 25 Product of built-in PROM version Product M34513E4SP/FP M34513E8FP M34514E8FP PROM size (! 10 bits) 4096 words 8192 words 8192 words RAM size (! 4 bits) 256 words 384 words 384 words Package SP: 32P4B FP: 32P6B-A 32P6B-A 42P2R-A ROM type One Time PROM version [shipped in blank]
D0 D1 D2 D3 D4 D5 D6/CNTR0 D7/CNTR1 P20/SCK P21/SOUT P22/SIN RESET CNVSS XOUT XIN VSS
1 2 3 4 5
32 31 30 29 28
P13 P12 P11 P10 P03 P02 P01 P00 AIN3/CMP1+ AIN2/CMP1AIN1/CMP0+ AIN0/CMP0P31/INT1 P30/INT0 VDCE VDD
P13 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6/CNTR0 8 D7/CNTR1 9 P50 10 P51 11 P52 12 P53 13 P20/SCK P21/SOUT
14 15
42 P12 41 P11 40 P10 39 P03 38 P02 37 P01 36 P00 35 P43/AIN7 34 P42/AIN6 33 P41/AIN5 32 P40/AIN4 31 AIN3/CMP1+ 30 AIN2/CMP129 AIN1/CMP0+ 28 AIN0/CMP027 P33 26 P32 25 P31/INT1 24 P30/INT0 23 VDCE 22 VDD
M34513E4SP
6 7 8 9 10 11 12 13 14 15 16
27 26 25 24 23 22 21 20 19 18 17
M34514E8FP
P22/SIN 16 RESET 17 CNVSS 18 XOUT
19
Outline 32P4B
XIN 20
29 P13 26 P10 28 P12 25 P03 27 P11 31 D1 30 D0 32 D2
VSS 21
D3 1 D4 2 D5 3 D6/CNTR0 4 D7/CNTR1 5 P20/SCK 6 P21/SOUT 7 P22/SIN 8
P30/INT0 16
11
24 P02 23 P01 22 P00
Outline 42P2R-A
M34513ExFP
21 20 19 18
AIN3/CMP1+ AIN2/CMP1AIN1/CMP0+ AIN0/CMP0-
Fig. 50 Pin configuration of built-in PROM version of 4514 Group
17 P31/INT1
VDD 14
VSS 13
XIN 12
CNVSS 10
RESET 9
Outline 32P6B-A
Fig. 49 Pin configuration of built-in PROM version of 4513 Group
XOUT
VDCE 15
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HARDWARE
BUILT-IN PROM VERSIONS
(1) PROM mode
The built-in PROM version has a PROM mode in addition to a normal operation mode. The PROM mode is used to write to and read from the built-in PROM. In the PROM mode, the programming adapter can be used with a general-purpose PROM programmer to write to or read from the built-in PROM as if it were M5M27C256K. Programming adapters are listed in Table 26.Contact addresses at the end of this sheet for the appropriate PROM programmer. * Writing and reading of built-in PROM Programming voltage is 12.5 V. Write the program in the PROM of the built-in PROM version as shown in Figure 51.
Table 26 Programming adapters Microcomputer M34513E4SP M34513E4FP, M34513E8FP M34514E8FP Programming adapter PCA7442SP PCA7442FP PCA7441
Address 000016 1FFF16
1
1
1
D4 D3
D2
D1
D0
Low-order 5 bits
(2) Notes on handling
A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. For the One Time PROM version shipped in blank, Mitsubishi Electric corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 52 before using is recommended (Products shipped in blank: PROM contents is not written in factory when shipped).
400016 5FFF16
1
1
1
D4 D3
D2
D1
D0
High-order 5 bits
7FFF16 Set "FF16" to the shaded area.
Fig. 51 PROM memory map
Writing with PROM programmer
Screening (Leave at 150 C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device Note: Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 C exceeding 100 hours.
Fig. 52 Flow of writing and test of the product shipped in blank
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BUILT-IN PROM VERSION
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CHAPTER 2 APPLICATION
2.1 I/O pins 2.2 Interrupts 2.3 Timers 2.4 Serial I/O 2.5 A-D converter 2.6 Voltage comparator 2.7 Reset 2.8 Voltage drop detection circuit 2.9 RAM back-up 2.10 Oscillation circuit
APPLICATION
2.1 I/O pins
2.1 I/O pins
The 4513/4514 Group has the twenty-eight I/O pins (eighteen I/O pins for 4513 Group), three input pins. (Ports P20-P22, P30, P31, D6 and D7 are also used as serial I/O pins SCK, SOUT, SIN, and INT0, INT1, CNTR0 and CNTR1 pins, respectively). This section describes each port I/O function, related registers, application example using each port function and notes. 2.1.1 I/O ports (1) Port P0 Port P0 is a 4-bit I/O port. Port P0 has the key-on wakeup function which turns ON/OFF with register K0 and pull-up transistor which turns ON/OFF with register PU0. s Input/output of port P0 q Data input to port P0 Set the output latch of specified port P0i (i=0 to 3) to "1" with the OP0A instruction. If the output latch is set to "0," "L" level is input. The state of port P0 is transferred to register A when the IAP0 instruction is executed. q Data output from port P0 The contents of register A is output to port P0 with the OP0A instruction. The output structure is an N-channel open-drain. (2) Port P1 Port P1 is a 4-bit I/O port. Port P1 has the key-on wakeup function which turns ON/OFF with register K0 and pull-up transistor which turns ON/OFF with register PU0. s Input/output of port P1 q Data input to port P1 Set the output latch of specified port P1i (i=0 to 3) to "1" with the OP1A instruction. If the output latch is set to "0," "L" level is input. The state of port P1 is transferred to register A when the IAP1 instruction is executed. q Data output from port P1 The contents of register A is output to port P1 with the OP1A instruction. The output structure is an N-channel open-drain. (3) Port P2 Port P2 is a 3-bit input port. s Input of port P2 q Data input to port P2 The state of port P2 is transferred to register A when the IAP2 instruction is executed. However, port P2 is 3 bits and A3 is fixed to "0."
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APPLICATION
2.1 I/O pins
(4) Port P3 Port P3 is a 4-bit I/O port for the 4514 Group, and a 2-bit I/O port for the 4513 Group. s Input/output of port P3 q Data input to port P3 Set the output latch of specified port P3i (i=0 to 3) to "1" with the OP3A instruction. If the output latch is set to "0," "L" level is input. The state of port P3 is transferred to register A when the IAP3 instruction is executed. However, A2 and A3 are undefined in the 4513 Group. q Data output from port P3 The contents of register A is output to port P3 with the OP3A instruction. The output structure is an N-channel open-drain. (5) Port P4 (The 4513 Group does not have this port.) Port P4 is a 4-bit I/O port. s Input/output of port P4 Ports P40-P43 are also used as AIN4-AIN7. Therefore, when P40/AIN4-P43/AIN7 are used as port P4, set corresponding bits of A-D control register Q2 to "0". q Data input to port P4 Set the output latch of specified port P4i (i=0 to 3) to "1" with the OP4A instruction. If the output latch is set to "0," "L" level is input. The state of port P4 is transferred to register A when the IAP4 instruction is executed. q Data output from port P4 The contents of register A is output to port P4 with the OP4A instruction. The output structure is an N-channel open-drain. (6) Port P5 (The 4513 Group does not have this port.) Port P5 is a 4-bit I/O port. s Input/output of port P5 Port P5 has direction register FR0 to input/output by the bit. q Data input to port P5 Set the bit of register FR0i(i=0 to 3) corresponding to specified port P5i (i=0 to 3) to "0." When the register FR0 is set to "1," the value of output latch is input. The state of port P5 is transferred to register A when the IAP5 instruction is executed. q Data output from port P5 Set the bit of register FR0i(i=0 to 3) corresponding to specified port P5i (i=0 to 3) to "1." When the register FR0 is set to "0," specified port P5i is in the high-impedance state. The contents of register A is output to port P5 with the OP5A instruction. The output structure is CMOS.
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APPLICATION
2.1 I/O pins
(7) Port D D0-D7 are eight independent I/O ports. s Input/output of port D Each pin of port D has an independent 1-bit wide I/O function. For I/O of ports D0-D7, select one of port D with the register Y of the data pointer first. q Data input to port D Set the output latch of specified port Di (i = 0 to 7) to "1" with the SD instruction. When the output latch is set to "0," "L" level is input. When the SZD instruction is executed, if the port specified by register Y is "0," the next instruction is skipped. If it is "1," the next instruction is executed. q Data output from port D Set the output level to the output latch with the SD and RD instructions. The state of pin enters the high-impedance state when the SD instruction is executed. The states of all port D enter the high-impedance state when the CLD instruction is executed. The state of pin becomes "L" level when the RD instruction is executed. The output structure is an N-channel open-drain. Notes 1: When the SD and RD instructions are used, do not set "10002" or more to register Y. 2: Port D6 is also used as CNTR0, and port D7 is also used as CNTR1. Accordingly, when using ports D6 and D7 functions, set bit 0 (W60) and bit 2 (W62) of timer control register W6 to "0." 2.1.2 Related registers (1) Pull-up control register PU0 Register PU0 controls the ON/OFF of the ports P00-P03 and P10-P13 pull-up transistor. Set the contents of this register through register A with the TPU0A instruction. The contents of register PU0 is transferred to register A with the TAPU0 instruction. Table 2.1.1 shows the pull-up control register PU0.
Table 2.1.1 Pull-up control register PU0 Pull-up control register PU0 PU03 PU02 PU01 PU00 Ports P12, P13 pull-up transistor control bit Ports P10, P11 pull-up transistor control bit Ports P02, P03 pull-up transistor control bit at reset : 00002 0 1 0 1 0 1 at RAM back-up : state retained R/W
Pull-up transistor OFF Pull-up Pull-up Pull-up Pull-up Pull-up transistor transistor transistor transistor transistor ON OFF ON OFF ON
Ports P00, P01 Pull-up transistor OFF 0 pull-up transistor control bit Pull-up transistor ON 1 Note: "R" represents read enabled, and "W" represents write enabled.
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APPLICATION
2.1 I/O pins
(2) Key-on wakeup control register K0 Register K0 controls the ON/OFF of the key-on wakeup function of ports P00-P03 and P10-P13. Set the contents of this register through register A with the TK0A instruction. The contents of register K0 is transferred to register A with the TAK0 instruction. Table 2.1.2 shows the key-on wakeup control register K0.
Table 2.1.2 Key-on wakeup control register K0 Key-on wakeup control register K0 K03 K02 K01 Ports P12, P13 key-on wakeup control bit Ports P10, P11 key-on wakeup control bit Ports P02, P03 at reset : 00002 0 1 0 1 0 Key-on Key-on Key-on Key-on Key-on at RAM back-up : state retained not used used not used used not used R/W
wakeup wakeup wakeup wakeup wakeup
key-on wakeup control bit Ports P00, P01 K00 key-on wakeup control bit Note: "R" represents read enabled, and "W"
Key-on wakeup used 1 Key-on wakeup not used 0 Key-on wakeup used 1 represents write enabled.
(3) A-D control register Q2 Bits 0 to 2 of register Q2 controls the pin function selection bits. Set the contents of this register through register A with the TQ2A instruction. The contents of register Q2 is transferred to register A with the TAQ2 instruction. Table 2.1.3 shows the A-D control register Q2. Table 2.1.3 A-D control register Q2 A-D control register Q2 Q23 Q22 Q21 Q20 A-D operation mode control bit P43/AIN7, P42/AIN6 pin function selection bit (Note 3) P41/AIN5 pin function selection bit (Note 3) at reset : 00002 0 1 0 1 0 1 0 at RAM back-up : state retained R/W
A-D conversion mode Comparator mode P43, P42 (I/O) (Note 4) AIN7, AIN6/P43, P42 (Output) (Note 4) P41 (I/O) (Note 4) AIN5/P41 (Output) (Note 4) P40 (I/O) (Note 4)
P40/AIN4 pin function selection bit (Note 3) AIN4/P40 (Output) (Note 4) 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: Select AIN4-AIN7 with register Q1 after setting register Q2. 3: For the 4513 Group, these bits are not used. 4: For the 4513 Group, only read/write of these bits is enabled. 5: When setting ports, Q23 is not used.
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APPLICATION
2.1 I/O pins
(4) Direction register FR0 (The 4513 Group does not have this register.) Register FR0 is used to switch to input/output of P50-P53. Set the contents of this register through register A with the TFR0A instruction. Table 2.1.4 shows the direction register FR0.
Table 2.1.4 Direction register FR0 Direction register FR0 (Note 2) FR03 FR02 Port P53 input/output control bit Port P52 input/output control bit at reset : 00002 0 1 0 Port Port Port Port P53 P53 P52 P52 P51 P51 P50 P50 FR0. input output input output input output input output at RAM back-up : state retained W
1 0 Port FR01 Port P51 input/output control bit 1 Port 0 Port FR00 Port P50 input/output control bit 1 Port Notes 1: "W" represents write enabled. 2: The 4513 Group does not have register (5)
Timer control register W6 D6/CNTR0 function selection bit is assigned to bit 0, D7/CNTR1 function selection bit is assigned to bit 2. Set the contents of this register through register A with the TW6A instruction. The contents of register W6 is transferred to register A with the TAW6 instruction. Table 2.1.5 shows the timer control register W6.
Table 2.1.5 Timer control register W6 Timer control register W6 W63 W62 W61 W60 CNTR1 output control bit at reset : 00002 0 at RAM back-up : state retained R/W
1 0 D7/CNTR1 function selection bit 1 0 CNTR0 output control bit 1 D6/CNTR0 function selection bit
Timer 3 underflow signal output divided by 2 CNTR1 output control by timer 4 underflow signal divided by 2 D7(I/O)/CNTR1 input CNTR1 I/O/D7 (input) Timer 1 underflow signal output divided by 2 CNTR0 output control by timer 2 underflow signal divided by 2 D6 (I/O)/CNTR0 input
0 1 CNTR0 I/O/D6 (input) Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When setting ports, W63 and W61 are not used.
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APPLICATION
2.1 I/O pins
2.1.3 Port application examples (1) Key input by key scan Key matrix can be set up by connecting keys externally because port D output structure is an Nchannel open-drain and port P0 has the pull-up resistor. Outline: The connecting required external part is just keys. Specifications: Port D is used to output "L" level and port P0 is used to input 16 keys. Multiple key inputs are not detected. Figure 2.1.1 shows the key input and Figure 2.1.2 shows the key input timing.
M34513/M34514
D0
SW4
SW3
SW2
SW1
SW8
SW7
SW6
SW5
D1
SW12 SW11 SW10 SW9
D2
SW16 SW15 SW14 SW13
D3
P00 P01 P02 P03
Fig. 2.1.1 Key input by key scan
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APPLICATION
2.1 I/O pins
Switching key input selection port (D 0 D 1) Stabilizing wait time for input Reading port (key input)
Key input period D0 D1 D2 D3 "H" "L" "H" "L" "H" "L" "H" "L" IAP0 Input to SW1-SW4 IAP0 Input to SW5-SW8 IAP0 Input to SW9-SW12 IAP0 Input to SW13-SW16 IAP0
Input to SW1-SW4
Note: "H" output of port D becomes high-impedance state.
Fig. 2.1.2 Key scan input timing
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APPLICATION
2.1 I/O pins
2.1.4 Notes on use (1) Note when an I/O port except port P5 is used as an input port Set the output latch to "1" and input the port value before input. If the output latch is set to "0," "L" level can be input. Noise and latch-up prevention Connect an approximate 0.1 F bypass capacitor directly to the VSS line and the VDD line with the thickest possible wire at the shortest distance, and equalize its wiring in width and length. The CNVSS pin is also used as the VPP pin (programming voltage = 12.5 V) at the built-in PROM version. Connect the CNVSS/VPP pin to VSS through an approximate 5 k resistor which is connected to the CNVSS/VPP pin at the shortest distance. Note on multifunction The input of D6, D7, P20-P22, CMP0-, CMP0+, CMP1-, CMP1+ and the input/output of P30, P31, P40-P43 can be used even when CNTR0, CNTR1, SCK, SOUT, SIN, AIN0-AIN3, INT0, INT1, and AIN4- AIN7 are selected. Connection of unused pins Table 2.1.6 shows the connections of unused pins. SD, RD instructions When the SD and RD instructions are used, do not set "10002" or more to register Y. Analog input pins When both analog input AIN4-AIN7 and I/O port P4 function are used, note the following; * Notes when selecting analog input pins Even when register Q2 is used to set the pins for analog input, P40/AIN4-P43/AIN7 continue to function as P40-P43 I/O. Accordingly, when any of them are used as I/O port P4 and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to "1." Also, for the port input, the port input function of the pin functions as analog input is undefined. Notes on port P3 In the 4513 Group, when the IAP3 instruction is executed, the contents of high-order 2 bits of register A are undefined.
(2)
(3)
(4)
(5)
(6)
(7)
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2.1 I/O pins
Table 2.1.6 connections of unused pins Connection Pin Open (when using an external clock). XOUT VDCE D0-D5 D6/CNTR0 D7/CNTR1 P20/SCK P21/SOUT P22/SIN P30/INT0 P31/INT1 P32, P33 P40/AIN4-P43/AIN7 P50-P53 (Note 1) AIN0/CMP0AIN1/CMP0+ AIN2/CMP1AIN3/CMP1+ P00-P03 P10-P13 Connect to VSS. Connect to VSS, or set the output latch to "0" and open.
Connect to VSS.
Connect to VSS, or set the output latch to "0" and open.
Connect to VSS, or set the output latch to "0" and open. When the input mode is selected by software, pull-up to VDD through a resistor or pull-down to VSS. When selecting the output mode, open. Connect to VSS.
Open or connect to VSS (Note 2). Open or connect to VSS (Note 2).
Notes 1: After system is released from reset, port P5 is in an input mode (direction register FR0 = 00002) 2: When the P00-P03 and P10-P13 are connected to VSS, turn off their pull-up transistors (register PU0i="0") and also invalidate the key-on wakeup functions (register K0i="0") by software. When these pins are connected to VSS while the key-on wakeup functions are left valid, the system fails to return from RAM back-up state. When these pins are open, turn on their pull-up transistors (register PU0i="1") by software, or set the output latch to "0." Be sure to select the key-on wakeup functions and the pull-up functions with every two pins. If only one of the two pins for the key-on wakeup function is used, turn on their pull-up transistors by software and also disconnect the other pin. (i = 0, 1, 2, or 3.) (Note in order to set the output latch to "0" and make pins open) * After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to "0" by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur. * To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away (caused by noise). (Note in order to connect unused pins to VSS or VDD) * To avoid noise, connect the unused pins to VSS or VDD at the shortest distance using a thick wire.
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2.2 Interrupts
2.2 Interrupts
The 4513/4514 Group has eight interrupt sources : external (INT0, INT1), timer 1, timer 2, timer 3, timer 4, A-D, and serial I/O. This section describes individual types of interrupts, related registers, application examples using interrupts and notes. 2.2.1 Interrupt functions (1) External 0 interrupt (INT0) The interrupt request occurs by the change of input level of INT0 pin. The interrupt valid waveform can be selected by the bits 1 and 2 of the interrupt control register I1. s External 0 interrupt INT0 processing q When the interrupt is used The interrupt occurrence is enabled when the bit 0 of the interrupt control register V1 and the interrupt enable flag INTE are set to "1." When the external 0 interrupt occurs, the interrupt processing is executed from address 0 in page 1. q When the interrupt is not used The interrupt is disabled and the SNZ0 instruction is valid when the bit 0 of register V1 is set to "0." (2) External 1 interrupt (INT1) The interrupt request occurs by the change of input level of INT1 pin. The interrupt valid waveform can be selected by the bits 1 and 2 of the interrupt control register I2. s External 1 interrupt INT1 processing q When the interrupt is used The interrupt occurrence is enabled when the bit 1 of the interrupt control register V1 and the interrupt enable flag INTE are set to "1." When the external 1 interrupt occurs, the interrupt processing is executed from address 2 in page 1. q When the interrupt is not used The interrupt is disabled and the SNZ1 instruction is valid when the bit 1 of register V1 is set to "0." (3) Timer 1 interrupt The interrupt request occurs by the timer 1 underflow. s Timer 1 interrupt processing q When the interrupt is used The interrupt occurrence is enabled when the bit 2 of the interrupt control register V1 and the interrupt enable flag INTE are set to "1." When the timer 1 interrupt occurs, the interrupt processing is executed from address 4 in page 1. q When the interrupt is not used The interrupt is disabled and the SNZT1 instruction is valid when the bit 2 of register V1 is set to "0."
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2.2 Interrupts
(4) Timer 2 interrupt The interrupt request occurs by the timer 2 underflow. s Timer 2 interrupt processing q When the interrupt is used The interrupt occurrence is enabled when the bit 3 of the interrupt control register V1 and the interrupt enable flag INTE are set to "1." When the timer 2 interrupt occurs, the interrupt processing is executed from address 6 in page 1. q When the interrupt is not used The interrupt is disabled and the SNZT2 instruction is valid when the bit 3 of register V1 is set to "0." (5) Timer 3 interrupt The interrupt request occurs by the timer 3 underflow. s Timer 3 interrupt processing q When the interrupt is used The interrupt occurrence is enabled when the bit 0 of the interrupt control register V2 and the interrupt enable flag INTE are set to "1." When the timer 3 interrupt occurs, the interrupt processing is executed from address 8 in page 1. q When the interrupt is not used The interrupt is disabled and the SNZT3 instruction is valid when the bit 0 of register V2 is set to "0." (6) Timer 4 interrupt The interrupt request occurs by the timer 4 underflow. s Timer 4 interrupt processing q When the interrupt is used The interrupt occurrence is enabled when the bit 1 of the interrupt control register V2 and the interrupt enable flag INTE are set to "1." When the timer 4 interrupt occurs, the interrupt processing is executed from address A in page 1. q When the interrupt is not used The interrupt is disabled and the SNZT4 instruction is valid when the bit 1 of register V2 is set to "0."
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2.2 Interrupts
(7) A-D interrupt The interrupt request occurs by the end of the A-D conversion. s A-D interrupt processing q When the interrupt is used The interrupt occurrence is enabled when the bit 2 of the interrupt control register V2 and the interrupt enable flag INTE are set to "1." When the A-D interrupt occurs, the interrupt processing is executed from address C in page 1. q When the interrupt is not used The interrupt is disabled and the SNZAD instruction is valid when the bit 2 of register V2 is set to "0." (8) Serial I/O interrupt The interrupt request occurs by the end of the serial I/O transmit/receive. s Serial I/O interrupt processing q When the interrupt is used The interrupt occurrence is enabled when the bit 3 of the interrupt control register V2 and the interrupt enable flag INTE are set to "1." When the serial I/O interrupt occurs, the interrupt processing is executed from address E in page 1. q When the interrupt is not used The interrupt is disabled and the SNZSI instruction is valid when the bit 3 of register V2 is set to "0." 2.2.2 Related registers (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to "1" with the EI instruction and disabled when INTE flag is cleared to "0" with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to "0," so that other interrupts are disabled until the EI instruction is executed. Note: The interrupt enabled with the EI instruction is performed after the EI instruction and one more instruction.
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2.2 Interrupts
(2) Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. In addition, the TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 2.2.1 shows the interrupt control register V1.
Table 2.2.1 Interrupt control register V1 Interrupt control register V1 V13 V12 V11 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit at reset : 00002 0 1 0 1 0 Interrupt Interrupt Interrupt Interrupt Interrupt at RAM back-up : 00002 disabled (SNZT2 instruction is valid) enabled (SNZT2 instruction is invalid) disabled (SNZT1 instruction is valid) enabled (SNZT1 instruction is invalid) disabled (SNZ1 instruction is valid) R/W
Interrupt enabled (SNZ1 instruction is invalid) 1 Interrupt disabled (SNZ0 instruction is valid) 0 V10 External 0 interrupt enable bit Interrupt enabled (SNZ0 instruction is invalid) 1 Note: "R" represents read enabled, and "W" represents write enabled. (3) Interrupt control register V2 Interrupt enable bits of timer 3, timer 4, A-D, and serial I/O are assigned to register V2. Set the contents of this register through register A with the TV2A instruction. In addition, the TAV2 instruction can be used to transfer the contents of register V2 to register A. Table 2.2.2 shows the interrupt control register V2.
Table 2.2.2 Interrupt control register V2 Interrupt control register V2 V23 V22 V21 V20 Serial I/O interrupt enable bit A-D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit at reset : 00002 0 1 0 1 0 1 0 1 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt at RAM back-up : 00002 disabled (SNZSI instruction is valid) enabled (SNZSI instruction is invalid) disabled (SNZAD instruction is valid) enabled (SNZAD instruction is invalid) disabled (SNZT4 instruction is valid) enabled (SNZT4 instruction is invalid) disabled (SNZT3 instruction is valid) enabled (SNZT3 instruction is invalid) R/W
Note: "R" represents read enabled, and "W" represents write enabled. (4) Interrupt request flag The activated condition for each interrupt is examined. Each interrupt request flag is set to "1" when the activated condition is satisfied, even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Each interrupt request flag is cleared to "0" when either; *an interrupt occurs, or *the next instruction is skipped with a skip instruction.
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2.2 Interrupts
(5) Interrupt control register I1 The INT0 pin timer 1 control enable bit is assigned to bit 0, INT0 pin edge detection circuit control bit is assigned to bit 1, and interrupt valid waveform for INT0 pin/return level selection bit is assigned to bit 2. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 2.2.3 shows the interrupt control register I1.
Table 2.2.3 Interrupt control register I1 Interrupt control register I1 I13 Not used Interrupt valid waveform for INT0 pin/return level selection bit (Note 2) at reset : 00002 0 1 0 1 at RAM back-up : state retained R/W
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT0 pin is recognized with the SNZI0 instruction)/"L" level Rising waveform ("H" level of INT0 pin is recognized with the SNZI0 instruction)/"H" level
I12
INT0 pin edge detection circuit One-sided edge detected 0 control bit Both edges detected 1 INT0 pin Disabled 0 I10 timer 1 control enable bit Enabled 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction. I11 (6) Interrupt control register I2 The INT1 pin timer 3 control enable bit is assigned to bit 0, the INT1 pin edge detection circuit control bit is assigned to bit 1 and the interrupt valid waveform for INT1 pin/return level selection bit is assigned to bit 2. Set the contents of this register through register A with the TI2A instruction. In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A. Table 2.2.4 shows the interrupt control register I2.
Table 2.2.4 Interrupt control register I2 Interrupt control register I2 I23 Not used Interrupt valid waveform for INT1 pin/return level selection bit (Note 2) INT1 pin edge detection circuit control bit at reset : 00002 0 1 0 1 at RAM back-up : state retained R/W
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT1 pin is recognized with the SNZI1 instruction)/"L" level Rising waveform ("H" level of INT1 pin is recognized with the SNZI1 instruction)/"H" level One-sided edge detected Both edges detected
I22
0 1 INT1 pin Disabled 0 I20 timer 3 control enable bit Enabled 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction. I21
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2.2 Interrupts
2.2.3 Interrupt application examples (1) External 0 interrupt The INT0 pin is used for external 0 interrupt, of which valid waveforms can be chosen, which can recognize the change of both edges ("H""L" or "L""H"). Outline: An external 0 interrupt can be used by dealing with the change of edge ("H""L" or "L""H") in both directions as a trigger. Specifications: An interrupt occurs by the change of an external signals edge ("H""L" or "L""H"). Figure 2.2.1 shows an operation example of an external 0 interrupt, and Figure 2.2.2 shows a setting example of an external 0 interrupt. (2) External 1 interrupt The INT1 pin is used for external 1 interrupt, of which valid waveforms can be chosen, which can recognize the change of both edges ("H""L" or "L""H"). Outline: An external 1 interrupt can be used by dealing with the change of edge ("H""L" or "L""H") in both directions as a trigger. Specifications: An interrupt occurs by the change of an external signals edge ("H""L" or "L""H"). Figure 2.2.3 shows an operation example of an external 1 interrupt, and Figure 2.2.4 shows a setting example of an external 1 interrupt. (3) Timer 1 interrupt Constant period interrupts by a setting value to timer 1 can be used. Outline: The constant period interrupts by the timer 1 underflow signal can be used. Specifications: Prescaler and timer 1 divide the system clock frequency f(XIN) = 4.0 MHz, and the timer 1 interrupt occurs every 1 ms. Figure 2.2.5 shows a setting example of the timer 1 constant period interrupt. (4) Timer 2 interrupt Constant period interrupts by a setting value to timer 2 can be used. Outline: The constant period interrupts by the timer 2 underflow signal can be used. Specifications: Timer 2 divides the 16-bit fixed dividing frequency timer, and the timer 2 interrupt occurs every about 2 sec. Figure 2.2.6 shows a setting example of the timer 2 constant period interrupt. (5) Timer 3 interrupt Constant period interrupts by a setting value to timer 3 can be used. Outline: The constant period interrupts by the timer 3 underflow signal can be used. Specifications: Prescaler and timer 3 divide the system clock frequency f(XIN) = 4.0 MHz, and the timer 3 interrupt occurs every 1 ms. Figure 2.2.7 shows a setting example of the timer 3 constant period interrupt.
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2.2 Interrupts
(6) Timer 4 interrupt Constant period interrupts by a setting value to timer 4 can be used. Outline: The constant period interrupts by the timer 4 underflow signal can be used. Specifications: Prescaler, timer 3 and timer 4 divide the system clock frequency f(XIN) = 4.0 MHz, and the timer 4 interrupt occurs every 250 ms. Figure 2.2.8 shows a setting example of the timer 4 constant period interrupt.
P30/INT0
"H" "L"
P30/INT0
"H" "L"
An interrupt occurs after the valid waveform "falling" is detected. An interrupt occurs after the valid waveform "rising" is detected.
Fig. 2.2.1 INT0 interrupt operation example
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2.2 Interrupts
Disable Interrupts
INT0 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3
Interrupt control register V1
All interrupts disabled (DI instruction) INT0 interrupt occurrence disabled ! ! ! 0 (TV1A instruction)
b0
Set Port
Port used for INT0 interrupt is set to input port.
b3 b0
Port P30 output latch
! ! ! 1 Set to input (OP3A instruction)
Set Valid Waveform
Valid waveform of INT pin is selected. Both edges detection selected b3 b0 Interrupt control register I1 ! ! 1 ! Both edges detection selected (TI1A instruction)
Clear Interrupt Request
External interrupt activated condition is cleared. INT0 interrupt request flag EXF0 "0" INT0 interrupt activated condition cleared (SNZ0 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag EXF0, insert the NOP instruction after the SNZ0 instruction.
Enable Interrupts
The INT0 interrupt which is temporarily disabled is enabled. b3 b0 INT0 interrupt occurrence enabled Interrupt control register V1 ! ! ! 1 (TV1A instruction) All interrupts enabled (EI instruction) Interrupt enable flag INTE "1"
INT0 interrupt execution started
"!": it can be "0" or "1." Fig. 2.2.2 INT0 interrupt setting example Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of system clock. 2-18
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P31/INT1
"H" "L"
P31/INT1
"H" "L"
An interrupt occurs after the valid waveform "falling" is detected. An interrupt occurs after the valid waveform "rising" is detected.
Fig. 2.2.3 INT1 interrupt operation example
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2.2 Interrupts
Disable Interrupts
INT1 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3
Interrupt control register V1
All interrupts disabled (DI instruction) INT1 interrupt occurrence disabled ! ! 0 ! (TV1A instruction)
b0
Set Port
Port used for INT1 interrupt is set to input port.
b3 b0
Port P31 output latch
! ! 1 ! Set to input (OP3A instruction)
Set Valid Waveform
Valid waveform of INT pin is selected. Both edges detection selected b3 b0 Interrupt control register I2 ! ! 1 ! Both edges detection selected (TI2A instruction)
Clear Interrupt Request
External interrupt activated condition is cleared. INT1 interrupt request flag EXF1 "0" INT1 interrupt activated condition cleared (SNZ1 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag EXF1, insert the NOP instruction after the SNZ1 instruction.
Enable Interrupts
The INT1 interrupt which is temporarily disabled is enabled. b3 b0 INT1 interrupt occurrence enabled Interrupt control register V1 ! ! 1 ! (TV1A instruction) All interrupts enabled (EI instruction) Interrupt enable flag INTE "1"
"!": it can be "0" or "1."
INT1 interrupt execution started
Fig. 2.2.4 INT1 interrupt setting example Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of system clock. 2-20
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2.2 Interrupts
Disable Interrupts
Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3
Interrupt control register V1
All interrupts disabled (DI instruction) Timer 1 interrupt occurrence disabled !0 !! (TV1A instruction)
b0
Stop Timer Operation
Timer 1 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected.
b3 b0
Timer 1 stop (TW1A instruction) Prescaler divided by 16 selected
Timer control register W1
0 1 0 ! Prescaler stop
Set Timer Value
Timer 1 count time is set. (The formula is shown gA below.) Timer 1 reload register R1 "5216" Timer count value 82 set (T1AB instruction)
Clear Interrupt Request
Timer 1 interrupt activated condition is cleared. Timer 1 interrupt request flag T1F "0" g0 h Timer 1 interrupt activated condition cleared (SNZT1 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
Start Timer Operation
Timer 1 and prescaler temporarily stopped are restarted. Timer control register W1 1 1 1 ! Timer 1 operation start (TW1A instruction) Prescaler operation stop
b3 b0
Enable Interrupts
The Timer 1 interrupt which is temporarily disabled is enabled. b3 b0 Timer 1 interrupt occurrence enabled Interrupt control register V1 ! 1 ! ! (TV1A instruction) Interrupt enable flag INTE "1" All interrupts enabled (EI instruction)
Constant period interrupt execution start
gA The prescaler dividing ratio and timer 1 count value to make the interrupt occur every 1 ms are set as follows.
1 ms (4.0 MHz) ! 3
-1
! 16
! (82+1)
System clock Instruction Prescaler Timer 1 clock dividing count ratio value
"!": it can be "0" or "1."
Fig. 2.2.5 Timer 1 constant period interrupt setting example
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2.2 Interrupts
Disable Interrupts
Timer 2 interrupt is temporarily disabled. All interrupts disabled (DI instruction) Interrupt control register V1 0 ! ! ! Timer 2 interrupt occurrence disabled (TV1A instruction)
b3 b0
Interrupt enable flag INTE "0"
Stop Timer Operation
Timer is temporarily stopped. Timer 2 count source is selected.
b3 b0
Timer control register W2 0 ! 1 1
Timer 2 stop (TW2A instruction) 16-bit timer (WDT) underflow signal selected for count source
Set Timer Value
Timer 2 count time is set. (The formula is shown gA below.) Timer 2 reload register R2 "2716" Timer count value 39 set (T2AB instruction)
Clear Interrupt Request
Timer 2 interrupt activated condition is cleared. Timer 2 interrupt request flag T2F "0" Timer 2 interrupt activated condition cleared (SNZT2 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T2F, insert the NOP instruction after the SNZT2 instruction.
Start Timer 2 Operation
Timer 2 temporarily stopped is restarted.
b3 b0
Timer control register W2 1 ! 1 1 Timer 2 operation start (TW2A instruction)
Enable Interrupts
The timer 2 interrupt which is temporarily disabled is enabled. b3 b0 Timer 2 interrupt occurrence enabled Interrupt control register V1 1 ! ! ! (TV1A instruction) All interrupts enabled (EI instruction) Interrupt enable flag INTE "1"
Constant period interrupt execution start
gA The timer 2 count value to make the interrupt occur every about 2 s is set as follows.
2 s (4.0 MHz) -1 ! 3 ! 216 ! System clock Instruction 16-bit clock fixed dividing frequency (39+1) Timer 2 count value
"!": it can be "0" or "1."
Fig. 2.2.6 Timer 2 constant period interrupt setting example 2-22
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2.2 Interrupts
Disable Interrupts
Timer 3 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3
Interrupt control register V2
All interrupts disabled (DI instruction) Timer 3 interrupt occurrence disabled !!! 0 (TV2A instruction)
b0
Stop Timer 3 Operation
Timer 3 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected.
b3 b0
Timer control register W1 Timer control register W3
0 1 !!
b3 b0
Prescaler stop (TW1A instruction) Prescaler divided by 16 selected Timer 3 stop (TW3A instruction)
0! 0 1 Prescaler selected for count source
Set Timer Value
Timer 3 count time is set. (The formula is shown gA below.) Timer 3 reload register R3 "5216" Timer count value 82 set (T3AB instruction)
Clear Interrupt Request
Timer 3 interrupt activated condition is cleared. Timer 3 interrupt request flag T3F "0"
gh 0
Timer 3 interrupt activated condition cleared (SNZT3 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T3F, insert the NOP instruction after the SNZT3 instruction.
Start Timer 3 Operation
Timer 3 and prescaler temporarily stopped are restarted.
b3 b0
Timer control register W3 1 ! 0 1 Timer 3 operation start (TW3A instruction)
b3 b0
Timer control register W1 1 1 ! ! Prescaler operation start (TW1A instruction)
Enable Interrupts
The timer 3 interrupt which is temporarily disabled is enabled. b3 b0 Timer 3 interrupt occurrence enabled Interrupt control register V2 ! ! ! 1 (TV2A instruction) All interrupts enabled (EI instruction) Interrupt enable flag INTE "1"
Constant period interrupt execution start
gA The prescaler dividing ratio and time 3 count value to make the interrupt occur every 1 ms are set as follows.
1 ms (4.0 MHz) ! 3
-1
! 16
! (82+1)
System clock Instruction Prescaler Timer 3 clock dividing count ratio value
"!": it can be "0" or "1."
Fig. 2.2.7 Timer 3 constant period interrupt setting example
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Disable Interrupts
Timer 4 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3
Interrupt control register V2
All interrupts disabled (DI instruction) Timer 4 interrupt occurrence disabled ! ! 0 ! (TV2A instruction)
b0
Stop Timer Operation
Timer 4, timer 3 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected.
b3 b0
Timer control register W1 Timer control register W3 Timer control register W4
01!!
b3 b0
Prescaler stop (TW1A instruction) Prescaler divided by 16 selected Timer 3 stop (TW3A instruction) Prescaler selected for count source Timer 3 underflow signal selected for count source
0! 0 1
b3 b0
0 ! 0 0 Timer 4 stop (TW4A instruction)
Set Timer Value
Timer 3 and timer 4 count times are set. (The formula is shown gA below.) Timer 3 reload register R3 Timer 4 reload register R4 "5216" "F916" Timer count value 82 set (T3AB instruction) Timer count value 249 set (T4AB instruction)
Clear Interrupt Request
Timer 4 interrupt activated condition is cleared. Timer 4 interrupt request flag T4F "0" Timer 4 interrupt activated condition cleared (SNZT4 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T4F, insert the NOP instruction after the SNZT4 instruction.
Start Timer 4 Operation
Timer 4, timer 3 and prescaler temporarily stopped are restarted.
b3 b0
Timer control register W4 1 ! 0 0 Timer 4 operation start (TW4A instruction)
b3 b0
Timer control register W3 1 ! 0 1
b3 b0
Timer 3 operation start (TW3A instruction)
Timer control register W1 1 1 ! ! Prescaler operation start (TW1A instruction)
Enable Interrupts
The timer 4 interrupt which is temporarily disabled is enabled. b3 b0 Timer 4 interrupt occurrence enabled Interrupt control register V2 ! ! 1 ! (TV2A instruction) Interrupt enable flag INTE "1" All interrupts enabled (EI instruction)
Constant period interrupt execution start
gA The prescaler dividing ratio, time 3 count value and timer 4 count value to make the interrupt occur every 250 ms are set as follows.
250 ms (4.0 MHz) ! 3! 16 ! (82+1) ! (249+1) System clock Instruction Prescaler Timer 3 Timer 4 clock dividing count count ratio value value
-1
"!": it can be "0" or "1."
Fig. 2.2.8 Timer 4 constant period interrupt setting example 2-24
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2.2 Interrupts
2.2.4 Notes on use (1) Setting of INT0 interrupt valid waveform Depending on the input state of P30/INT0 pin, the external interrupt request flag (EXF0) may be set to "1" when the interrupt valid waveform is changed. Accordingly, set a value to the bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction. Setting of INT1 interrupt valid waveform Depending on the input state of P31/INT1 pin, the external interrupt request flag (EXF1) may be set to "1" when the interrupt valid waveform is changed. Accordingly, set a value to the bit 2 of register I2, and execute the SNZ1 instruction to clear the EXF1 flag to "0" after executing at least one instruction. Multiple interrupts Multiple interrupts cannot be used in the 4513/4514 Group. Notes on interrupt processing When the interrupt occurs, at the same time, the interrupt enable flag INTE is cleared to "0" (interrupt disable state). In order to enable the interrupt at the same time when system returns from the interrupt, write EI and RTI instructions continuously. P30/INT0 pin The P30/INT0 pin need not be selected the external interrupt input INT function or the normal output port P30 function. However, the EXF0 flag is set to "1" when a valid waveform is input to INT0 pin even if it is used as an I/O port P30. P31/INT1 pin The P31/INT1 pin need not be selected the external interrupt input INT function or the normal output port P31 function. However, the EXF1 flag is set to "1" when a valid waveform is input to INT1 pin even if it is used as an I/O port P31. EPOF instruction Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.
(2)
(3)
(4)
(5)
(6)
(7)
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2.3 Timers
2.3 Timers
The 4513/4514 Group has four 8-bit timers (each has a reload register) and a 16-bit fixed dividing frequency timer which has the watchdog timer function. This section describes individual types of timers, related registers, application examples using timers and notes. 2.3.1 Timer functions (1) Timer 1 s Timer operation (Timer 1 has the timer 1 count start trigger function from P30/INT0 pin input) (2) Timer 2 s Timer operation (3) Timer 3 s Timer operation (Timer 3 has the timer 3 count start trigger function from P31/INT1 pin input) (4) Timer 4 s Timer operation (5) 16-bit timer s Timer 2 count source (16-bit fixed dividing frequency) s Watchdog function Watchdog timer provides a method to reset the system when a program runs incorrectly. When the count value of timer WDT reaches "BFFF16" or "3FFF16," the WDF1 flag is set to "1." If the WRST instruction is never executed while timer WDT counts 32767, WDF2 flag is set to "1" to reset the microcomputer.
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2.3.2 Related registers (1) Interrupt control register V1 The timer 1 interrupt enable bit is assigned to bit 2, and the timer 2 interrupt enable bit is assigned to bit 3. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 2.3.1 shows the interrupt control register V1.
Table 2.3.1 Interrupt control register V1 Interrupt control register V1 V13 V12 V11 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit at reset : 00002 0 1 0 1 Interrupt Interrupt Interrupt Interrupt at RAM back-up : 00002 disabled (SNZT2 instruction is valid) enabled (SNZT2 instruction is invalid) disabled (SNZT1 instruction is valid) enabled (SNZT1 instruction is invalid) R/W
Interrupt disabled (SNZ1 instruction is valid) 0 Interrupt enabled (SNZ1 instruction is invalid) 1 Interrupt disabled (SNZ0 instruction is valid) 0 V10 External 0 interrupt enable bit Interrupt enabled (SNZ0 instruction is invalid) 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When timer is used, V11 and V10 are not used. (2) Interrupt control register V2 The timer 3 interrupt enable bit is assigned to bit 0, and the timer 4 interrupt enable bit is assigned to bit 1. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A. Table 2.3.2 shows the interrupt control register V2.
Table 2.3.2 Interrupt control register V2 Interrupt control register V2 V23 V22 Serial I/O interrupt enable bit A-D interrupt enable bit at reset : 00002 0 1 0 at RAM back-up : 00002 R/W
Interrupt disabled (SNZSI instruction is valid) Interrupt enabled (SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid) 1 Interrupt disabled (SNZT4 instruction is valid) 0 V21 Timer 4 interrupt enable bit Interrupt enabled (SNZT4 instruction is invalid) 1 Interrupt disabled (SNZT3 instruction is valid) 0 V20 Timer 3 interrupt enable bit Interrupt enabled (SNZT3 instruction is invalid) 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When timer is used, V22 and V23 are not used.
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(3) Timer control register W1 The timer 1 count start synchronous circuit control bit is assigned to bit 0, the timer 1 control bit is assigned to bit 1, the prescaler dividing ratio selection bit is assigned to bit 2, and the prescaler control bit is assigned to bit 3. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. Table 2.3.3 shows the timer control register W1. Table 2.3.3 Timer control register W1 Timer control register W1 W13 W12 W11 W10 Prescaler control bit Prescaler dividing ratio selection bit Timer 1 control bit Timer 1 count synchronous circuit control bit at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : 00002 R/W
Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected
Note: "R" represents read enabled, and "W" represents write enabled. (4) Timer control register W2 The timer 2 count source selection bits are assigned to bits 0 and 1, and the timer 2 control bit is assigned to bit 3. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. Table 2.3.4 shows the timer control register W2.
Table 2.3.4 Timer control register W2 Timer control register W2 W23 Timer 2 control bit at reset : 00002 0 at RAM back-up : state retained R/W
Stop (state retained)
Operating 1 0 This bit has no function, but read/write is enabled. W22 Not used 1 W21 W20 Count source W21 0 0 Timer 1 underflow signal Timer 2 count source selection 0 1 Prescaler output bits 1 0 CNTR0 input W20 1 1 16-bit timer (WDT) underflow signal Note: "R" represents read enabled, and "W" represents write enabled.
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(5) Timer control register W3 The timer 3 count source selection bits are assigned to bits 0 and 1, the timer 3 count start synchronous circuit control bit is assigned to bit 2 and the timer 3 control bit is assigned to bit 3. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A. Table 2.3.5 shows the timer control register W3. Table 2.3.5 Timer control register W3 Timer control register W3 W33 W32 Timer 3 control bit Timer 3 count start synchronous circuit control bit at reset : 00002 0 1 at RAM back-up : state retained R/W
Stop (state retained) Operating
Count start synchronous circuit not selected 0 Count start synchronous circuit selected 1 W31 W30 Count source W31 0 0 Timer 2 underflow signal Timer 3 count source selection 0 1 Prescaler output bits 1 0 Not available W30 1 1 Not available Note: "R" represents read enabled, and "W" represents write enabled. (6) Timer control register W4 The timer 4 count source selection bits are assigned to bits 0 and 1, and the timer 4 control bit is assigned to bit 3. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A. Table 2.3.6 shows the timer control register W4.
Table 2.3.6 Timer control register W4 Timer control register W4 W43 W42 Timer 4 control bit Not used at reset : 00002 0 1 0 at RAM back-up : state retained R/W
Stop (state retained) Operating This bit has no function, but read/write is enabled. Count source Timer 3 underflow signal Prescaler output CNTR1 input Not available
W41
W40
1 W41 W40 0 0 Timer 4 count source selection 0 1 bits 1 0 1 1
Note: "R" represents read enabled, and "W" represents write enabled.
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2.3 Timers
2.3.3 Timer application examples (1) Timer operation: measurement of constant period The constant period by the setting timer count value can be measured. Outline: The constant period by the timer 1 underflow signal can be measured. Specifications: Timer 1 and prescaler divides the system clock frequency f(XIN) = 4.0 MHz, and the timer 1 interrupt request occurs every 3 ms. Figure 2.3.3 shows the setting example of the constant period measurement. (2) CNTR0 output operation: piezoelectric buzzer output Outline: Square wave output from timer 1 can be used for piezoelectric buzzer output. Specifications: 4 kHz square wave is output from the CNTR0 pin at system clock frequency f(XIN) = 4.0 MHz. Also, timer 1 interrupt occurs simultaneously. Figure 2.3.1 shows the peripheral circuit example, and Figure 2.3.4 shows the setting example of CNTR0 output.
In order to reduce the current dissipation, output is high-impedance state during buzzer output stop.
4513/4514
125 s125 s Set dividing ratio for timer 1 underflow cycle to 125 s.
CNTR0
Fig. 2.3.1 Peripheral circuit example (3) CNTR0 input operation: event count Outline: Count operation can be performed by using the signal (rising waveform) input from CNTR0 pin as the event. Specifications: The low-frequency pulse from external as the timer 2 count source is input to CNTR0 pin, and the timer 2 interrupt request occurs every 100 counts. Figure 2.3.5 shows the setting example of CNTR0 input.
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(4) CNTR1 output control: square wave output control Outline: The output/stop of square wave from timer 3 every timer 4 underflow can be controlled. Specifications: 4 kHz square wave is output from timer 3 at system clock frequency f(XIN) = 4.0 MHz. Also, timer 4 controls ON/OFF of square wave every constant period. Figure 2.3.6 shows the setting example of CNTR1 output. (5) Timer operation: timer start by external input Outline: The constant period can be measured by external input. Specifications: Timer 1 operates by INT0 input as a trigger and an interrupt occurs after 1 ms. Figure 2.3.7 and Figure 2.3.8 show the setting example of timer start. (6) Watchdog timer Watchdog timer provides a method to reset the system when a program run-away occurs. In the 4513/4514 Group, bit 15 of 16-bit timer is counted twice for the watchdog timer. Accordingly, when the watchdog timer function is set to be valid, execute the WRST instruction at a certain period which consists of timer 16-bit timers' 32767 counts or less (execute WRST instruction at a cycle of 32766 machine cycles or less). Outline: Execute the WRST instruction in 16-bit timer's 32767 counts at the normal operation. If a program runs incorrectly, the WRST instruction is not executed and system reset occurs. Specifications: System clock frequency f(XIN) = 4.0 MHz is used, and program run-away is detected by executing the WRST instruction in 24 ms. Figure 2.3.2 shows the watchdog timer function, and Figure 2.3.9 shows the example of watchdog timer.
FFFF16 Value of timer WDT 0000 16 WEF flag
BFFF16 3FFF16
WDF1 flag WDF2 flag RESET pin output WRST instruction execution Fig. 2.3.2 Watchdog timer function WRST instruction execution
System reset
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2.3 Timers
Disable Interrupts
Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3
Interrupt control register V1
All interrupts disabled (DI instruction) Timer 1 interrupt occurrence disabled ! 0 ! ! (TV1A instruction)
b0
Stop Timer Operation
Timer 1 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected.
b3 b0
Timer control register W1
0 1 0 ! Prescaler stop
Timer 1 stop (TW1A instruction) Prescaler divided by 16 selected
Set Timer Value
Timer 1 count time is set. (The formula is shown gA below.) Timer 1 reload register R1 "F916" Timer count value 249 set (T1AB instruction)
Clear Interrupt Request
Timer 1 interrupt activated condition is cleared. Timer 1 interrupt request flag T1F "0" g0 h Timer 1 interrupt activated condition cleared (SNZT1 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
Start Timer 1 Operation
Timer 1 and prescaler temporarily stopped are restarted.
b3 b0
Timer control register W1 1 1 1 ! Timer 1 operation start (TW1A instruction) Prescaler operation start
Enable Interrupts
The timer 1 interrupt which is temporarily disabled is enabled. b3 b0 Timer 1 interrupt occurrence enabled Interrupt control register V1 ! 1 ! ! (TV1A instruction) Interrupt enable flag INTE "1" All interrupts enabled (EI instruction)
Constant period interrupt execution start
gA The prescaler dividing ratio and timer 1 count value to make the interrupt occur every 4 ms are set as follows.
4 ms (4.0 MHz) ! 3 ! 16 ! System clock Instruction Prescaler clock dividing ratio
-1
(249+1) Timer 1 count value
"!": it can be "0" or "1."
Fig. 2.3.3 Constant period measurement setting example
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Disable Interrupts
Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3 b0
All interrupts disabled (DI instruction) Timer 1 interrupt occurrence disabled (TV1A instruction)
Interrupt control register V1
! 0!!
Stop Timer Operation
Timer 1 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected.
b3 b0
Timer control register W1
0 0 0 ! Prescaler stop
Timer 1 stop (TW1A instruction) Prescaler divided by 4 selected
Set Timer Value, Select CNTR0 Output
CNTR0 output is selected. Timer 1 count time is set.
b3 b0
Timer control register W6 ! ! 0 1 CNTR0 output selected (TW6A instruction) Timer 1 reload register R1 "2916" Timer count value 41 set (T1AB instruction)
Clear Interrupt Request
Timer 1 interrupt activated condition is cleared. Timer 1 interrupt request flag T1F "0"g0 h Timer 1 interrupt activated condition cleared (SNZT1 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
Start Timer 1 Operation
Timer 1 and prescaler temporarily stopped are restarted.
b3 b0
Timer control register W1 1 0 1 ! Timer 1 operation start (TW1A instruction) Prescaler operation start
Enable Interrupts
The timer 1 interrupt which is temporarily disabled is enabled. b3 b0 Timer 1 interrupt occurrence enabled Interrupt control register V1 ! 1 ! ! (TV1A instruction) All interrupts enabled (EI instruction) Interrupt enable flag INTE "1"
Stop CNTR0 Output
D6/CNTR0 pin is set to CNTR0 input pin, and it is set to the high-impedance state.
b3 b0
Timer control register W6 Output latch of port D6 is set to "1." "!": it can be "0" or "1."
! ! 0 0 CNTR0 input pin set (TW6A instruction)
(SD instruction)
Fig. 2.3.4 CNTR0 output setting example
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2.3 Timers Disable Interrupts
Timer 2 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3 b0
All interrupts disabled (DI instruction) (TV1A instruction)
Interrupt control register V1
0 ! ! ! Timer 2 interrupt occurrence disabled
Stop Timer Operation
Timer 1 operation is temporarily stopped. Timer 2 count source is selected.
b3 b0
Timer control register W2
0! 1 0
Timer 2 stop (TW2A instruction) CNTR0 input selected for count source
Set Timer Value
Timer 2 count time is set. Timer 2 reload register R2 "6316" Timer count value 99 set (T2AB instruction)
Clear Interrupt Request
Timer 2 interrupt activated condition is cleared. Timer 2 interrupt request flag T2F "0"g0 h Timer 2 interrupt activated condition cleared (SNZT2 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T2F, insert the NOP instruction after the SNZT2 instruction.
Start Timer 2 Operation
Timer 2 temporarily stopped is restarted.
b3 b0
Timer control register W2 1 ! 1 0 Timer 2 operation start (TW2A instruction)
Enable Interrupts
The timer 2 interrupt which is temporarily disabled is enabled. b3 b0 Timer 2 interrupt occurrence enabled Interrupt control register V1 1 ! ! ! (TV1A instruction) Interrupt enable flag INTE "1" All interrupts enabled (EI instruction)
"!": it can be "0" or "1." Fig. 2.3.5 CNTR1 input setting example However, specify the pulse width input to CNTR0 pin/CNTR1 pin. Refer to section "2.3.4 Notes on use" for the timer external input period condition. 2-34
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Disable Interrupts
Timer 3 and timer 4 interrupt are temporarily disabled. Interrupt enable flag INTE "0"
b3
Interrupt control register V2
All interrupts disabled (DI instruction) Timer 3 and timer 4 interrupt occurrence disabled ! ! 0 0 (TV2A instruction)
b0
Stop Timer Operation
Timer is temporarily stopped. Dividing ratio of prescaler is selected. Timer 3 count source is selected. Timer 4 count source is selected.
b3 b0 Timer 3 stop (TW3A instruction) Timer control register W3 0 ! 0 1 Prescaler selected for count source b3 b0
Timer control register W4
0!0 0 Timer 3 underflow selected for count source
b3 b0
Timer 4 stop (TW4A instruction)
Instruction clock divided by 4 selected Timer control register W1 1 0 ! ! (TW1A instruction)
Set Timer Value, Select CNTR1 Output
CNTR1 output is selected. Timer 3 and timer 4 count time are set.b3 b0 Timer control register W6 1 1 ! ! CNTR1 output selected (TW6A instruction) Timer 3 reload register R3 "2916" Timer 3 reload register R4 "FF16" Timer count value 41 set (T3AB instruction) Timer count value 255 set (T4AB instruction)
Start Timer Operation
Timer 3 and timer 4 temporarily stopped are restarted.
b3 b0
Timer control register W3 1 ! 0 1 Timer 3 operation start (TW3A instruction)
b3 b0
Timer control register W4 1 ! 0 0
Timer 4 operation start (TW4A instruction)
Enable Interrupts
Interrupt enable flag INTE
"1"
All interrupts enabled (EI instruction)
"!": it can be "0" or "1." Fig. 2.3.6 CNTR0 output control setting example
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2.3 Timers
Disable Interrupts
Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3 b0
All interrupts disabled (DI instruction) (TV1A instruction) INT0 interrupt occurrence disabled
Interrupt control register V1
! 0 ! 0 Timer 1 interrupt occurrence disabled
Stop Timer Operation
Timer 1 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected.
b3 b0
Timer control register W1
Timer 1 stop (TW1A instruction) 000! Prescaler stop Prescaler divided by 4 selected
Set Timer Value
Timer 1 count time is set. Timer 1 reload register R1 "5216" Timer count value 82 set (T1AB instruction)
Set Port
P30/INT0 pin is set to INT0 input.
b3 b0
Port P30 output latch ! ! ! 1
INT0 input set (OP3A instruction)
Set Valid Waveform
Valid waveform of INT0 pin is selected. Timer 1 control is enabled.
b3 b0
Interrupt control register I1 ! 1 0 1
Rising edge detected (TI1A instruction)
Clear Interrupt Request
Timer 1 interrupt activated condition is cleared. INT0 interrupt activated condition is cleared.0 h g Timer 1 interrupt request flag T1F "0" INT0 interrupt request flag EXF0 "0" Timer 1 interrupt activated condition cleared (SNZT1 instruction) INT0 interrupt activated condition cleared (SNZ0 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flags T1F and EXF0, insert the NOP instruction after the SNZT1 and SNZ0 instructions.
Enable Interrupts
The timer 1 interrupt which is temporarily disabled is enabled. b3 b0 Timer 1 interrupt occurrence enabled Interrupt control register V1 ! 1 ! ! (TV1A instruction) Interrupt enable flag INTE "1" All interrupts enabled (EI instruction)
Timer start by external input
"!": it can be "0" or "1."
Fig. 2.3.7 Timer start by external input setting example (1) 2-36
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2.3 Timers
Processing in interrupt service routine
Stop Timer
Timer 1 control disabled Interrupt control register I1
b3
b0
!10 0
(TI1A instruction)
Reset Timer
Timer 1 reload register R1 "5216" Timer 1 control enabled "!": it can be "0" or "1." Interrupt control register I1
(TI1A instruction) Timer count value 82 set (T1AB instruction)
b3 b0
!101
Fig. 2.3.8 Timer start by external input setting example (2)
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Activate Watchdog Timer
Watchdog timer is activated. Watchdog timer enable flag WEF "1" Watchdog timer enable flag WEF set (WRST instruction)
Main routine (every 20 ms) Reset Flag WDF
Watchdog timer flag WDF1 is reset.
g0 h
"0"
Watchdog timer flag WDF1 cleared (WRST instruction)
Main routine execution
Repeat
Do not clear watchdog timer WDF flag in interrupt service routine. Interrupt may be executed even if program run-away occurs.
When going to RAM back-up mode
* * * * * *
WRST EPOF POF
; WDF flag cleared ; POF instruction enabled
Oscillation stop (RAM back-up mode)
In the RAM back-up mode, WEF, WDF1 and WDF2 flags are initialized. However, when WDF2 flag is set to "1", at the same time, system enters RAM back-up mode, microcomputer may be reset. When watchdog timer and RAM back-up mode are used, execute the WRST instruction before system enters the RAM back-up mode to initialize WDF flag.
"!": it can be "0" or "1." Fig. 2.3.9 Watchdog timer setting example
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2.3.4 Notes on use (1) Prescaler Stop the prescaler operation to change its frequency dividing ratio. Count source Stop timer 1, 2, 3, or 4 counting to change its count source. Reading the count values Stop timer 1, 2, 3, or 4 counting and then execute the TAB1, TAB2, TAB3, or TAB4 instruction to read its data. Writing to reload registers R1, R3 When writing data to reload registers R1, R3 while timer 1 and 3 are operating, avoid a timing when timers 1 and 3 underflow.
(2)
(3)
(4)
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2.4 Serial I/O
2.4 Serial I/O
The 4513/4514 Group has a clock-synchronous serial I/O which can be used to transmit and receive 8-bit data. This section describes serial I/O functions, related registers, application examples using serial I/O and notes. 2.4.1 Carrier functions Serial I/O consists of the serial I/O register SI, serial I/O mode register J1, serial I/O transmit/receive completion flag SIOF and serial I/O counter. A clock-synchronous serial I/O uses the shift clock generated by the clock control circuit as a synchronous clock. Accordingly, the data transmit and receive operations are synchronized with this shift clock. In transmit operation, data is transmitted bit by bit from the SOUT pin synchronously with the falling edges of the shift clock. In receive operation, data is received bit by bit from the SIN pin synchronously with the rising edges of the shift clock. Note: 4513/4514 Group only supports LSB-first transmission and reception. s Shift clock When using the internal clock of 4513/4514 Group as a synchronous clock, eight shift clock pulses are output from the SCK pin when a transfer operation is started. Also, when using some external clock as a synchronous clock, the clock that is input from the SCK pin is used as the shift clock. Data transfer rate (baudrate) When using the internal clock, the data transfer rate can be determined by selecting the instruction clock divided by 4 or 8. When using an external clock, the clock frequency input to the SCK pin determines the data transfer rate.
s
Figure 2.4.1 shows the serial I/O block diagram.
Division circuit (divided by 2) XIN MR3
1 0
Internal clock generation circuit (divided by 3)
Instruction clock
J12 1/4 1/8
1 0
Serial I/O mode register J1 J13 J12 J11 J10
P20/SCK
SCK
Synchronous circuit
Serial I/O counter (3)
SIOF
Serial I/O interrupt
P21/SOUT
SOUT
P22/SIN
SIN
MSB
Serial I/O register SI (8) TSIAB
LSB TABSI
J11
J10
Register B (4)
Register A (4)
Note: The output structure of SCK and SOUT pins is N-channel open-drain.
Fig. 2.4.1 Serial I/O block diagram 2-40
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2.4 Serial I/O
2.4.2 Related registers (1) Serial I/O register SI Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and B with the TSIAB instruction. Serial I/O mode register J1 Serial I/O synchronous clock selection bit is assigned to bit 0, serial I/O port selection bit is assigned to bit 1 and serial I/O internal clock dividing ratio selection bit is assigned to bit 2. Set the contents of this register through register A with the TJ1A instruction. The TAJ1 instruction can be used to transfer the contents of register J1 to register A. Table 2.4.1 shows the serial I/O mode register J1. Table 2.4.1 Serial I/O mode register J1 Serial I/O mode register J1 J13 J12 J11 J10 Not used Serial I/O internal clock dividing ratio selection bit Serial I/O port selection bit at reset : 00002 0 1 0 1 0 1 0 at RAM back-up : state retained R/W
(2)
This bit has no function, but read/write is enabled. Instruction clock signal divided by 8 Instruction clock signal divided by 4 Input ports P20, P21, P22 selected Serial I/O ports SCK, SOUT, SIN/input ports P20, P21, P22 selected
External clock Serial I/O synchronous clock Internal clock (instruction clock divided by 4 or 8) selection bit 1 Note: "R" represents read enabled, and "W" represents write enabled. (3) Serial I/O transmission/reception completion flag (SIOF) Serial I/O transmission/reception completion flag (SIOF) is set to "1" when serial data transmission or reception completes. The state of SIOF flag can be examined with the skip instruction (SNZSI).
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2.4 Serial I/O
2.4.3 Operation description Figure 2.4.2 shows the serial I/O connection example, Figure 2.4.3 shows the serial I/O register state, and Figure 2.4.4 shows the serial I/O transfer timing.
Master (internal clock selected)
4513/4514 D5 SCK SOUT SIN
Slave (external clock selected)
4513/4514
Control signal
D5 SCK SIN SOUT
Note: The control signal is used to inform the master by the pin level that the slave is in a ready state to receive. The 4513/4514 Group does not have a control pin exclusively used for serial I/O. Accordingly, if a control signal is required, use the normal input/output ports. Fig. 2.4.2 Serial I/O connection example
Slave (S7-S0: Transfer data) SIN pin Serial I/O register (SI) M7 M6 M5 M4 M3 M2 M1 M0 SOUT pin SOUT pin SIN pin Serial I/O register (SI) S7 S6 S5 S4 S3 S2 S1 S0
Master (M7-M0: Transfer data)
M7 M6 M5 M4 M3 M2 M1 M0
Transfer data setting Transfer starts
S7 S6 S5 S4 S3 S2 S1 S0
M7 M6 M5 M4 M3 M2 M1
Falling of clock
S7 S6 S5 S4 S3 S2 S1
S0 M7 M6 M5 M4 M3 M2 M1
Rising of clock
M0 S7 S6 S5 S4 S3 S2 S1
S0 M7 M6 M5 M4 M3 M2
Falling of clock
M0 S7 S6 S5 S4 S3 S2
S7 S6 S5 S4 S3 S2 S1 S0
Transfer completes
M7 M6 M5 M4 M3 M2 M1 M0
Fig. 2.4.3 Serial I/O register state when transmitting/receiving
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2.4 Serial I/O
Master
SOUT SIN SST instruction
M7' S7'
M0 S0
M1 S1
M2 S2
M3 S3
M4 S4
M5 S5
M6 S6
M7 S7
SCK
Slave
SST instruction
Control signal SOUT SIN
S7' M7'
S0 M0
S1 M1
S2 M2
S3 M3
S4 M4
S5 M5
S6 M6
S7 M7
M0-M7: the contents of master serial I/O register S0-S7: the contents of slave serial I/O register Rising of SCK: serial input Falling of SCK: serial output M0'-M7': previous MSB contents of master and slave
Fig. 2.4.4 Serial I/O transfer timing
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2.4 Serial I/O
The full duplex communication of master and slave is described using the connection example shown in Figure 2.4.2. (1) Transmit/receive operation of master The transmit data is written into the serial I/O register SI with the TSIAB instruction. When the TSIAB instruction is executed, the contents of register A are transferred to the low-order 4 bits of register SI and the contents of register B are transferred to the high-order 4 bits of register SI. Whether the microcomputer on the receiving side is ready to receive or not is checked. In the connection example in Figure 2.4.2, check that the input level of control signal is "L" level. Serial transfer is started with the SST instruction. When the SST instruction is executed, the serial I/O transmit/receive completion flag (SIOF) is cleared to "0." The transmit data is output from the SOUT pin synchronously with the falling edges of the shift clock. The transmit data is output bit by bit beginning with the LSB bit of register SI. Each time one bit is output, the contents of register SI is shifted one bit position toward the LSB. Also, the receive data is input from the SIN pin synchronously with the rising edges of the shift clock. The receive data is input bit by bit to the MSB bit of register SI. A serial I/O interrupt request occurs when the transfer of transmit data and receive data is completed, and the SIOF flag is set to "1." The receive data is taken in within the serial I/O interrupt service routine; or the data is taken in after examining the completion of the transmit/receive operation with the SNZSI instruction without using an interrupt. Also, the SIOF flag is cleared to "0" when an interrupt occurs or the SNZSI instruction is executed. Notes 1: Repeat steps through to transmit or receive multiple data in succession. 2: For the program on the master side, make sure that transmission is not started before the control signal is released back "H" after a transmit operation is started first.
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2.4 Serial I/O
(2) Transmit/receive operation of slave The transmit data is written into the serial I/O register SI with the TSIAB instruction. When the TSIAB instruction is executed, the contents of register A are transferred to the low-order bits of register SI and the contents of register B are transferred to the high-order bits of register SI. At this time, the SCK pin must be at the "H" level. Serial transfer is started with the SST instruction. However, in Figure 2.4.2 where an external clock is selected, transfer is not started until the clock is input. When the SST instruction is executed, the serial I/O transmit/receive completion flag (SIOF) is cleared to "0." The microcomputer on the transmitting side is informed that the receiving side is ready to receive. In the connection example in Figure 2.4.2, this notification is done by pulling the control signal "L" level. The transmit data is output from the SOUT pin synchronously with the falling edges of the shift clock. The transmit data is output bit by bit beginning with the LSB bit of register SI. Each time one bit is output, the contents of register SI are shifted to one bit position toward the LSB. Also, the receive data is input from the SIN pin synchronously with the rising edges of the shift clock. The receive data is input bit by bit to the MSB bit of register SI. A serial I/O interrupt request occurs when the transmit/receive of data is completed, and the SIOF flag is set to "1." The receive data is taken in within the serial I/O interrupt service routine; or the data is taken in after examining the completion of the transmit/receive operation with the SNZSI instruction without using an interrupt. Also, the SIOF flag is cleared to "0" when an interrupt occurs or the SNZSI instruction is executed. Make sure that the control signal pin level is "H" after the receive operation is completed. Note: Repeat steps through to transmit or receive multiple data in succession. 2.4.4 Serial I/O application example (1) Serial I/O Outline: The 4513/4514 Group can communicate with peripheral ICs. Specifications: Figure 2.4.2 Serial I/O connection example. Figure 2.4.5 shows the master serial I/O setting example, and Figure 2.4.6 shows the slave serial I/O setting example.
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2.4 Serial I/O
Disable Interrupts
Serial I/O interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3 b0
All interrupts disabled (DI instruction) Serial I/O interrupt occurrence disabled (TV2A instruction)
Interrupt control register V2
0!!!
Set Serial I/O
b3 b0 Internal clock selected (TJ1A instruction) Serial I/O mode register J1 ! 1 1 1 Serial I/O port selected Dividing ratio = 4 selected
Clear Interrupt Request
Serial I/O interrupt activated condition is cleared. Serial I/O transmit/receive "0"g0 h completion flag SIOF Serial I/O interrupt activated condition cleared (SNZSI instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the SIOF flag, insert the NOP instruction after the SNZSI instruction. When interrupt is not used
When interrupt is used
Set Interrupt
Interrupts except serial I/O is enabled (EI instruction)
Set Interrupt
Serial I/O interrupt temporarily disabled is enabled. b3 b0 Serial I/O interrupt occurrence Interrupt control register V2 1 ! ! ! enabled (TV2A instruction) Interrupt enable flag INTE "1" All interrupts enabled (EI instruction)
Start Condition of Serial I/O operation
Slave side is enabled to receive is checked. Pin level of control signal = "L"
Start Serial I/O Operation
Serial transfer is started (SST instruction) after checking slave side is enabled to receive.
g0 h
Check Serial I/O Interrupt Request
SIOF flag is checked (SNZSI instruction).
Serial I/O Interrupt Occur
Execute Receive Data
Data received by serial transfer is executed. Register SI register A, register B (TABSI instruction) When serial communication is executed, to are repeated. "!": it can be "0" or "1."
Fig. 2.4.5 Master serial I/O setting example
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2.4 Serial I/O
Disable Interrupts
Serial I/O interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3
Interrupt control register V2
All interrupts disabled (DI instruction) Serial I/O interrupt occurrence disabled 0!!! (TV2A instruction)
b0
Set Serial I/O
Exernal clock selected (TJ1A instruction) Serial I/O mode register J1 ! ! 1 0 Serial I/O port selected
b3 b0
Clear Interrupt Request
Serial I/O interrupt activated condition is cleared. Serial I/O transmit/receive "0"g0 h completion flag SIOF Serial I/O interrupt activated condition cleared (SNZSI instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the SIOF flag, insert the NOP instruction after the SNZSI instruction. When interrupt is not used
When interrupt is used
Set Interrupt
Interrupts except serial I/O is enabled (EI instruction)
Set Interrupt
Serial I/O interrupt temporarily disabled is enabled. b3 b0 Serial I/O interrupt occurrence Interrupt control register V2 1 ! ! ! enabled (TV2A instruction) Interrupt enable flag INTE "1" All interrupts enabled (EI instruction)
Set When Transmit/Receive Operation Start Enabled
Serial transfer start state (SST instruction) System enters to control signal transmission enabled state ("L" level) However, SCK pin initial level = "H" level
Start Serial I/O Operation
Serial transfer starts by clock of master side
Check Serial I/O Interrupt Request
SIOF flag is checked (SNZSI instruction).
Serial I/O Interrupt Occur
Receive Data Processing
System enters to control signal transmission disabled state ("H" level) Data processing received by serial transfer is executed. Register SI register A, register B (TABSI instruction)
When serial communication is executed, to are repeated. "!": it can be "0" or "1."
Fig. 2.4.6 Slave serial I/O example
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2.4 Serial I/O
2.4.5 Notes on use (1) Note when an external clock is used as a synchronous clock: * An external clock is selected as the synchronous clock, the clock is not controlled internally. * Serial transfer is continued as long as an external clock is input. If an external clock is input 9 times or more and serial transfer is continued, the receive data is transferred directly as transmit data, so that be sure to control the clock externally. Note also that the SIOF flag is set when a clock is counted 8 times. * Make sure that the initial input level on the external clock pin is always "H" level. * Table 2.4.2 shows the recommended operating conditions when using serial I/O with an external clock. Figure 2.4.7 shows an input waveform of external clock. Table 2.4.2 Recommended operating conditions (serial I/O) Parameter Condition VDD = 4.0 V to 5.5 V Middle-speed mode VDD = 2.5 V to 5.5 V Serial I/O external clock period (Note 1) High-speed mode VDD = 2.0 V to 5.5 V (Note 2) VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V Limits Unit Min. Typ. Max. 1.5 3.0 4.0 750 1.5 2.0 ns s s
VDD = 2.0 V to 5.5 V (Note 2) Notes 1: Limits shown in Table 2.4.2 represent the pulse widths of "H" and "L." 2: It is effective only for mask version.
External clock input waveform
"L" pulse width "H" pulse width
Note: Set "H" and "L" pulse width for external waveform according to using supply voltage and recommended operating conditions.
Fig. 2.4.7 Input waveform of external clock
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2.5 A-D converter
2.5 A-D converter
The 4513/4514 Group has an A-D converter with the 10-bit successive comparison method: 4 channels for the 4513 Group, 8 channels for the 4514 Group. This A-D converter can also be used as a comparator to compare analog voltages input from the analog input pin with preset values. This section describes the related registers, application examples using the A-D converter and notes. Figure 2.5.1 shows the A-D converter block diagram.
Register B (4)
Register A (4) 4 TAQ2 TQ2A
Q23 Q22 Q21 Q20
4 4
IAP4 (P40--P43)
TAQ1 TQ1A 2
Q13 Q12 Q11 Q10
4
8 TABAD
8 TADAB
TALA Instruction clock 1/6
OP4A (P40--P43) 3
Q23
0
8-channel multi-plexed analog switch
(Note 3) AIN0/CMP0AIN1/CMP0+ AIN2/CMP1AIN3/CMP1+ P40/AIN4 P41/AIN5 P42/AIN6 P43/AIN7
A-D control circuit
1
ADF (1)
A-D interrupt
1
Comparator
0
Successive comparison register (AD) (10) 10 10
1
Q23 8
0 1 0
Q23
1
DAC operation signal
Q23
8 DA converter (Note 1) VSS Comparator register (8) (Note 2) VDD 8 8
Notes 1: This switch is turned ON only when A-D converter is operating and generates the comparison voltage. 2: Writing/reading data to the comparator register is possible only in the comparator mode (Q23=1). The value of the comparator register is retained even when the mode is switched to the A-D conversion mode (Q23=0) because it is separated from the successive comparison register (AD). Also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits. 3: The 4513 Group does not have ports P40/AIN4-P43/AIN7 and the IAP4 and OP4A instructions.
Fig. 2.5.1 A-D converter structure
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2.5 A-D converter
2.5.1 Related registers (1) A-D control register Q1 Analog input pin selection bits are assigned to register Q1. Set the contents of this register through register A with the TQ1A instruction. The TAQ1 instruction can be used to transfer the contents of register Q1 to register A. Table 2.5.1 shows the A-D control register Q1.
Table 2.5.1 A-D control register Q1 A-D control register Q1 Q13 Not used at reset : 00002 0 1 at power down : state retained R/W
This bit has no function, but read/write is enabled.
Q12
Q11
Q10 Notes
Q12 Q11 Q10 Selected pin 0 0 0 AIN0 0 0 1 AIN1 0 1 0 AIN2 Analog input pin selection bits 0 1 1 AIN3 (Note 2) 1 0 0 AIN4 (Not available for 4513 Group) 1 0 1 AIN5 (Not available for 4513 Group) 1 1 0 AIN6 (Not available for 4513 Group) 1 1 1 AIN7 (Not available for 4513 Group) 1: "R" represents read enabled, and "W" represents write enabled. 2: Select AIN4-AIN7 with register Q1 after setting register Q2. A-D control register Q2 Analog input pin selection bits and A-D operation mode control bit are assigned to register Q2. Set the contents of this register through register A with the TQ2A instruction. The TAQ2 instruction can be used to transfer the contents of register Q2 to register A. Table 2.5.2 shows the A-D control register Q2.
(2)
Table 2.5.2 A-D control register Q2 A-D control register Q2 Q23 Q22 Q21 A-D operation mode control bit P43/AIN7, P42/AIN6 pin function selection bit (Note 3) at reset : 00002 0 1 0 1 at power down : state retained R/W
A-D conversion mode Comparator mode P43, P42 (I/O) (Note 4) AIN7, AIN6/P43, P42 (Output) (Note 4)
P41/AIN5 pin function selection bit P41 (I/O) (Note 4) 0 (Note 3) AIN5/P41 (Output) (Note 4) 1 P40/AIN4 pin function selection bit P40 (I/O) (Note 4) 0 Q20 (Note 3) AIN4/P40 (Output) (Note 4) 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: Select AIN4-AIN7 with register Q1 after setting register Q2. 3: In the 4513 Group, these bits are not used. 4: In the 4513 Group, only read/write of these bits is enabled.
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2.5 A-D converter
2.5.2 A-D converter application examples (1) A-D conversion mode Outline: Analog input signal from a sensor can be converted into digital values. Specifications: Analog voltage values from a sensor is converted into digital values by using a 10bit successive comparison method. Use the AIN0 pin for this analog input. Figure 2.5.2 shows the A-D conversion mode setting example.
Disable Interrupts
A-D interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3
Interrupt control register V2
All interrupts disabled (DI instruction) A-D interrupt occurrence disabled !0 !! (TV2A instruction)
b0
Set A-D Converter
A-D conversion mode is selected to A-D operation mode. Analog input pin AIN0 is selected.
b3 b0
A-D control register Q2 0 ! ! ! A-D conversion mode selected (TQ2A instruction)
b3 b0
A-D control register Q1 ! 0 0 0 AIN0 selected (TQ1A instruction)
Clear Interrupt Request
A-D interrupt activated condition is cleared. A-D conversion completion flag ADF "0" A-D conversion interrupt activated condition cleared (SNZAD instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the flag ADF, insert the NOP instruction after the SNZAD instruction. When interrupt is not used
When interrupt is used
Set Interrupt
Interrupts except A-D conversion is enabled (EI instruction)
Set Interrupt
A-D conversion interrupt temporarily disabled is enabled. Interrupt control register V2 ! 1 ! ! A-D interrupt occurrence enabled (TV2A instruction) Interrupt enable flag INTE "1" All interrupts enabled (EI instruction)
b3 b0
Start A-D Conversion
A-D conversion operation is started (ADST instruction).
When interrupt is not used
When interrupt is used
Check A-D Interrupt Request
A-D conversion completion flag is checked (SNZAD instruciton)
A-D Conversion Interrupt Occur
Execute A-D Conversion
High-order 8 bits of register AD register A and register B (TABAD instruction) Low-order 2 bits of register AD high-order 2 bits of register A (TALA instruction) "0" is set to low-order 2 bits of register A When A-D conversion is executed by the same channel, to is repeated. When A-D conversion is executed by the another channel, to is repeated.
"!": it can be "0" or "1."
Fig. 2.5.2 A-D conversion mode setting example
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2.5 A-D converter
2.5.3 Notes on use (1) Note when the A-D conversion starts again When the A-D conversion starts again with the ADST instruction during A-D conversion, the previous input data is invalidated and the A-D conversion starts again. A-D control register Q2 Select AIN4-AIN7 with register Q1 after setting register Q2. A-D converter-1 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A-D accuracy may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 F to 1 F) to analog input pins. Figure 2.5.3 shows the analog input external circuit example-1. When the overvoltage applied to the A-D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 2.5.4. In addition, test the application products sufficiently.
(2)
(3)
Sensor
AINi (Note) Sensor
About 1 k
AINi (Note) Note: i = 0 to 7
Note: Apply the voltage within the specifications to an analog input pin. (i = 0 to 7)
Fig. 2.5.4 Analog input external circuit example-2
Fig. 2.5.3 Analog input external circuit example-1 (4) Notes for the use of A-D conversion 2 When the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode with bit 3 of register Q2 in a program, be careful about the following notes. * Clear bit 2 of register V2 to "0" to change the operating mode of the A-D converter from the comparator mode to the A-D conversion mode with bit 3 of register Q2 (refer to Figure 2.5.5). * The A-D conversion completion flag (ADF) may be set when the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode. Accordingly, set a value to register Q2, and execute the SNZAD instruction to clear the ADF flag. Do not change the operating mode (both A-D conversion mode and comparator mode) of A-D converter with bit 3 of register Q2 during operating the A-D converter. * * * Clear bit 2 of register V2 to "0"....... Change of the operating mode of the A-D converter from the comparator mode to the A-D conversion mode Clear the ADF flag to "0" with the SNZAD instruction Execute the NOP instruction for the case when a skip is performed with the SNZAD instruction * * * Fig. 2.5.5 A-D converter operating mode program example 2-52
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2.5 A-D converter
(5) A-D converter is used at the comparator mode The analog input voltage is higher than the comparison voltage as a result of comparison, the contents of ADF flag retains "0," not set to "1." In this case, the A-D interrupt does not occur even when the usage of the A-D interrupt is enabled. Accordingly, consider the time until the comparator operation is completed, and examine the state of ADF flag by software. The comparator operation is completed after 8 machine cycles. Analog input pins Even when P40/AIN4-P43/AIN7 are set to pins for analog input, they continue to function as P40-P43 I/O. Accordingly, when any of them are used as I/O port P4 and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to "1." Also, the port input function of the pin functions as an analog input is undefined. TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the highorder 2 bits of register A, and simultaneously, the low-order 2 bits of register A is "0." Recommended operating conditions when using A-D converter The recommended operating conditions of supply voltage and system clock frequency when using AD converter are different from those when not using A-D converter. Table 2.5.3 shows the recommended operating conditions when using A-D converter.
(6)
(7)
(8)
Table 2.5.3 Recommended operating conditions (when using A-D converter) Parameter VDD System clock frequency VDD (at ceramic resonance) VDD VDD System clock frequency VDD (at external clock input) VDD Condition = 4.5 V to 5.5 V (high-speed mode) = 4.0 V to 5.5 V (high-speed mode) = = = = 2.7 4.5 4.0 2.7 V V V V to to to to 5.5 5.5 5.5 5.5 V V V V Limits Min. Typ. 0.4 0.4 0.4 Max. 4.2 2.0 4.2 3.0 1.0 3.0 Unit
(middle-speed mode) 0.4 (high-speed mode) Duty 0.4 (high-speed mode) 40 % to 60 % 0.4 (middle-speed mode)
MHz
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2.6 Voltage comparator
2.6 Voltage comparator
The 4513/4514 Group has two voltage comparators; CMP0-, CMP0+, CMP1-, CMP1+. This section describes the voltage comparator function, related registers, and notes. 2.6.1 Voltage comparator function (1) CMP0 s Voltage comparison The voltage of CMP0- is compared with that of CMP0+, and the result is stored into bit 0 of the voltage comparator control register Q3. CMP1 s Voltage comparison The voltage of CMP1- is compared with that of CMP1+, and the result is stored into bit 1 of the voltage comparator control register Q3.
(2)
2.6.2 Related registers (1) Voltage comparator control register Q3 The voltage comparator (CMP1) control bit is assigned to bit 3, the voltage comparator (CMP0) control bit is assigned to bit 2, the CMP1 comparison result store bit is assigned to bit 1 and the CMP0 comparison result store bit is assigned to bit 0. Set the contents of this register through register A with the TQ3A instruction. The TAQ3 instruction can be used to transfer the contents of register Q3 to register A. Table 2.6.1 shows the voltage comparator control register Q3.
Table 2.6.1 Voltage comparator control register Q3 Voltage comparator control register Q3 at reset : 00002 at RAM back-up : state retained (Note 2) Voltage comparator (CMP1) invalid 0 Voltage comparator (CMP1) Q33 Voltage comparator (CMP1) valid 1 control bit Voltage comparator (CMP0) invalid 0 Voltage comparator (CMP0) Q32 Voltage comparator (CMP0) valid control bit 1 CMP1- > CMP1+ 0 Q31 CMP1 comparison result store bit CMP1- < CMP1+ 1 CMP0- > CMP0+ 0 Q30 CMP0 comparison reslut store bit CMP0- < CMP0+ 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: Bits 0 and 1 of register Q3 can be only read.
R/W
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2.6 Voltage comparator
2.6.3 Notes on use q Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode. Accordingly, be careful about such state because it causes the increase of the operation current in the RAM back-up mode. In order to reduce the operation current in the RAM back-up mode, invalidate (bits 2 and 3 of register Q3 = "0") the voltage comparator function by software before the POF instruction is executed. Also, while the voltage comparator function is valid, current is always consumed by voltage comparator. On the system required for the low-power dissipation, invalidate the voltage comparator when it is unused by software. Register Q3 Bits 0 and 1 of register Q3 can be only read. Note that they cannot be written. Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time (max. 20 s) is passed from the voltage comparator function become valid.
q
q
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2.7 Reset
2.7 Reset
System reset is performed by applying "L" level to the RESET pin for 1 machine cycle or more when the following conditions are satisfied: q the value of supply voltage is the minimum value or more of the recommended operating conditions q oscillation is stabilized. Then when "H" level is applied to RESET pin, the software starts from address 0 in page 0 after elapsing of the internal oscillation stabilizing time (f(XIN) is counted for 16892 to 16895 machine cycles). Figure 2.7.2 shows the oscillation stabilizing time. 2.7.1 Reset circuit The 4513/4514 Group has the power-on reset circuit and voltage drop detection circuit. (1) Power-on reset Reset can be performed automatically at power on (power-on reset) by connecting resistors, a diode, and a capacitor to RESET pin. Connect a capacitor between the RESET pin and VSS at the shortest distance.
VDD
VDD RESET pin voltage
Internal reset signal
RESET pin
(Note)
Reset state
Voltage drop detection circuit
Watchdog timer output
WEF
Internal reset signal
Reset released Note: Power-on This symbol represents a parasitic diode. Applied potential to RESET pin must be VDD or less.
Fig. 2.7.1 Power-on reset circuit example Reset input
=
1 machine cycle or more
f(XIN) is counted 16892 to 16895 times.
0.85VDD RESET 0.3VDD
Software starts (address 0 in page 0)
(Note)
Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Fig. 2.7.2 Oscillation stabilizing time after system is released from reset 2-56
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2.7 Reset
2.7.2 Internal state at reset Figure 2.7.3 shows the internal state at reset. The contents of timers, registers, flags and RAM other than shown in Figure 2.7.3 are undefined, so that set them to initial values.
* Program counter (PC) ............................................................................................ 000000 Address 0 in page 0 is set to program counter. * Interrupt enable flag (INTE) ................................................................................... (Interrupt disabled) 0 * Power down flag (P) ............................................................................................... 0 * External 0 interrupt request flag (EXF0) ................................................................ 0 * External 1 interrupt request flag (EXF1) ................................................................ 0 * Interrupt control register V1 ................................................................................... 0000 * Interrupt control register V2 ................................................................................... 0000 * Interrupt control register I1 .................................................................................... 0000 * Interrupt control register I2 .................................................................................... 0000 * Timer 1 interrupt request flag (T1F) ...................................................................... 0 * Timer 2 interrupt request flag (T2F) ...................................................................... 0 * Timer 3 interrupt request flag (T3F) ...................................................................... 0 * Timer 4 interrupt request flag (T4F) ...................................................................... 0 * Watchdog timer flags (WDF1, WDF2) ................................................................... 0 * Watchdog timer enable flag (WEF) ....................................................................... 0 * Timer control register W1 ...................................................................................... 0000 * Timer control register W2 ...................................................................................... 0000 * Timer control register W3 ...................................................................................... 0000 * Timer control register W4 ...................................................................................... 0000 * Timer control register W6 ...................................................................................... 0000 * Clock control register MR ...................................................................................... 1000 * Serial I/O transmit/receive completion flag ............................................................ 0 * Serial I/O mode register J1 .................................................................................... 0000 * Serial I/O register SI .............................................................................................. !!!!!!!! * A-D conversion completion flag ADF .................................................................... 0 * A-D control register Q1 .......................................................................................... 0000 * A-D control register Q2 .......................................................................................... 0000 * Voltage comparator control register Q3 ................................................................ 0000 * Successive comparison register AD ...................................................................... !!!!!!!!!! * Comparator register ............................................................................................... !!!!!!!! * Key-on wakeup control register K0 ....................................................................... 0000 * Pull-up control register PU0 ................................................................................... 0000 * Direction register FR0 ............................................................................................ 0000 * Carry flag (CY) ....................................................................................................... 0 * Register A .............................................................................................................. 0000 * Register B .............................................................................................................. 0000 * Register D .............................................................................................................. !!! !!!!!!!! * Register E .............................................................................................................. * Register X .............................................................................................................. 0000 * Register Y .............................................................................................................. 0000 * Register Z ............................................................................................................... !! * Stack pointer (SP) .................................................................................................. 111 (Port P5 input mode) (Prescaler, timer 1 stopped) (Timer 2 stopped) (Timer 3 stopped) (Timer 4 stopped) (Interrupt disabled) (Interrupt disabled) 0 0 0 0 0 0 0 0
(External clock selected, serial I/O port not selected))
"!" represents undefined.
Fig. 2.7.3 Internal state at reset
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2.8 Voltage drop detection circuit
2.8 Voltage drop detection circuit
The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. Figure 2.8.1 shows the voltage drop detection reset circuit, and Figure 2.8.2 shows the operation waveform example of the voltage drop detection circuit.
RESET pin
Internal reset signal Voltage drop detection circuit Watchdog timer output WEF Note: The output structure of RESET pin is N-channel open-drain.
Fig. 2.8.1 Voltage drop detection reset circuit
VDD VRST (detection voltage)
Voltage drop detection circuit output The microcomputer starts operation after f(XIN) is counted 16892 to 16895 times. RESET pin Notes 1: Pull-up RESET pin externally. 2: Refer to the voltage drop detection circuit in the electrical characteristics for the rating value of VRST (detection voltage). Fig. 2.8.2 Voltage drop detection circuit operation waveform Note: Refer to section "3.1 Electrical characteristics" for the reset voltage of the voltage drop detection circuit.
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2.9 RAM back-up
2.9 RAM back-up
2.9.1 RAM back-up mode The system enters RAM back-up mode when the POF instruction is executed after the EPOF instruction is executed. Table 2.9.1 shows the function and state retained at RAM back-up mode. Also, Table 2.9.2 shows the return source from this state. (1) RAM back-up mode As oscillation stops with RAM, the state of reset circuit retained, current dissipation can be reduced without losing the contents of RAM. back-up mode RAM back-up O Pull-up control register PU0 O Key-on wakeup control register K0 O Direction register FR0 ! External 0 interrupt request flag (EXF0) Function
Table 2.9.1 Functions and states retained at RAM RAM back-up Function Program counter (PC), registers A, B, ! carry flag (CY), stack pointer (SP) (Note 2) O Contents of RAM O Port level
! Timer control register W1 External 1 interrupt request flag (EXF1) ! O Timer control registers W2 to W4. W6 Timer 1 interrupt request flag (T1F) ! ! Clock control register MR Timer 2 interrupt request flag (T2F) (Note 3) ! Interrupt control registers V1, V2 Timer 3 interrupt request flag (T3F) (Note 3) O Interrupt control registers I1, I2 Timer 4 interrupt request flag (T4F) (Note 3) Timer 1 function ! Watchdog timer flags (WDF1, WDF2) ! (Note 4) Timer 2 function (Note 3) Watchdog timer enable flag (WEF) ! (Note 4) Timer 3 function (Note 3) 16-bit timer (WDT) ! (Note 4) Timer 4 function (Note 3) A-D conversion completion flag (ADF) ! A-D function ! Serial I/O transmit/receive completion flag ! A-D control registers Q1, Q2 O (SIOF) Voltage comparator function O (Note 5) Interrupt enable flag (INTE) ! Voltage comparator control register Q3 O Serial I/O function ! Serial I/O mode register J1 O Notes 1: "O" represents that the function can be retained, and "!" represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to "7" at RAM backup. 3: The state of the timer is undefined. 4: Initialize the watchdog timer with the WRST instruction, and then execute the POF instruction. 5: The state is retained when the voltage comparator function is selected with the voltage comparator control register Q3.
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2.9 RAM back-up
Table 2.9.2 Return source and return condition Return source Ports P0, P1 External wakeup signal Return condition Remarks Return by an external falling Set the port using the key-on wakeup function selected edge input ("H""L"). with register K0 to "H" level before going into the RAM back-up state because the port P0 shares the falling edge detection circuit with port P1. Return by an external "H" level or "L" level input. The EXF0 flag is not set. Return by an external "H" level or "L" level input. The EXF1 flag is not set. (2) Select the return level ("L" level or "H" level) with the bit 2 of register I1 according to the external state before going into the RAM back-up state. Select the return level ("L" level or "H" level) with the bit 2 of register I2 according to the external state before going into the RAM back-up state.
Port P30/INT0
Port P31/INT1
Start condition identification When system returns from both RAM back-up mode and reset, software is started from address 0 in page 0. The start condition (warm start or cold start) can be identified by examining the state of the power down flag (P) with the SNZP instruction.
Table 2.9.3 Start condition identification Return condition P flag External wakeup signal input 1 Reset 0
Software start P = "1" ? No Cold start Yes
Warm start
Fig. 2.9.1 Start condition identified example 2.9.2 Related register (1) Key-on wakeup control register K0 Key-on wakeup control register K0 controls key-on wakeup functions of ports P00-P03, P10-P13. Set the contents of this register through register A with the TK0A instruction. The TAK0 instruction can be used to transfer the contents of register K0 to register A. Table 2.9.4 shows the key-on wakeup control register K0. Table 2.9.4 Key-on wakeup control register K0 Key-on wakeup control register K0 K03 K02 K01 Pins P12 and P13 key-on wakeup control bit Pins P10 and P11 key-on wakeup control bit Pins P02 and P03 key-on wakeup control bit at reset : 00002 0 1 0 1 Key-on Key-on Key-on Key-on at RAM back-up : state retained not used used not used used R/W
wakeup wakeup wakeup wakeup
0 Key-on wakeup not used 1 Key-on wakeup used 0 Pins P00 and P01 key-on wakeup Key-on wakeup not used K00 1 control bit Key-on wakeup used Note: "R" represents read enabled, and "W" represents write enabled.
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APPLICATION
2.9 RAM back-up
(2) Pull-up control register PU0 Pull-up control register PU0 controls the pull-up functions of ports P00-P03, P10-P13. Set the contents of this register through register A with the TPU0A instruction. The TAPU0 instruction can be used to transfer the contents of register PU0 to register A. Table 2.9.5 shows the pull-up control register PU0. Table 2.9.5 Pull-up control register PU0 Pull-up control register PU0 PU03 PU02 PU01 PU00 Pins P12 and transistor control Pins P10 and transistor control Pins P02 and transistor control Pins P00 and transistor control P13 bit P11 bit P03 bit P01 bit pull-up pull-up pull-up pull-up at reset : 00002 0 1 0 1 0 1 at RAM back-up : state retained R/W
Pull-up transistor OFF Pull-up Pull-up Pull-up Pull-up Pull-up transistor transistor transistor transistor transistor ON OFF ON OFF ON
Pull-up transistor OFF 0 Pull-up transistor ON 1 Note: "R" represents read enabled, and "W" represents write enabled. (3) Interrupt control register I1 The interrupt valid waveform for INT0 pin/return level selection bit is assigned to bit 2, INT0 pin edge detection circuit control bit is assigned to bit 1, and INT0 pin timer 1 control enable bit is assigned to bit 0. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 2.9.6 shows the interrupt control register I1.
Table 2.9.6 Interrupt control register I1 Interrupt control register I1 I13 Not used Interrupt valid waveform for INT0 pin/return level selection bit (Note 2) at reset : 00002 0 1 0 1 at RAM back-up : state retained R/W
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT0 pin is recognized with the SNZI0 instruction)/"L" level Rising waveform ("H" level of INT0 pin is recognized with the SNZI0 instruction)/"H" level One-sided edge detected
I12
INT0 pin edge detection circuit 0 control bit Both edges detected 1 INT0 pin Disabled 0 I10 timer 1 control enable bit Enabled 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction. I11
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APPLICATION
2.9 RAM back-up
(4) Interrupt control register I2 The interrupt valid waveform for INT1 pin/return level selection bit is assigned to bit 2, the INT1 pin edge detection circuit control bit is assigned to bit 1, and the INT1 pin timer 1 control enable bit is assigned to bit 1. Set the contents of this register through register A with the TI2A instruction. In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A. Table 2.9.7 shows the interrupt control register I2.
Table 2.9.7 Interrupt control register I2 Interrupt control register I2 I23 Not used Interrupt valid waveform for INT1 pin/return level selection bit (Note 2) at reset : 00002 0 1 0 1 at RAM back-up : state retained R/W
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT1 pin is recognized with the SNZI1 instruction)/"L" level
Rising waveform ("H" level of INT1 pin is recognized with the SNZI1 instruction)/"H" level INT1 pin edge detection circuit One-sided edge detected 0 I21 control bit Both edges detected 1 INT1 pin Disabled 0 I20 timer 3 control enable bit Enabled 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction. 2.9.3 Notes on use (1) Key-on wakeup function After setting ports (P1 specified with register PU0 and P0) which key-on wakeup function is valid to "H," execute the POF instruction. "L" level is input to the falling edge detection circuit even if one of ports which key-on wakeup function is valid is in the "L" level state, and the edge is not detected. POF instruction Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the POF instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction. Return from RAM back-up After system returns from RAM back-up, set the undefined registers and flags. Especially, be sure to set data pointer (registers Z, X, Y).
I22
(2)
(3)
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APPLICATION
2.10 Oscillation circuit
2.10 Oscillation circuit
The 4513/4514 Group has an internal oscillation circuit to produce the clock required for microcomputer operation. The clock signal f(XIN) is obtained by connecting a ceramic resonator to XIN pin and XOUT pin. 2.10.1 Oscillation circuit (1) f(XIN) clock generating circuit The clock signal f(XIN) is obtained by connecting a ceramic resonator externally. Connect this external circuit to pins XIN and XOUT at the shortest distance. A feed-back resistor is built-in between XIN pin and XOUT pin. Figure 2.10.1 shows an example of an oscillation circuit connecting a ceramic resonator externally. Keep the maximum value of oscillation frequency within the range listed Table 2.10.1. oscillation frequency and supply voltage (System clock) Oscillation frequency Middle-speed mode 4.2 MHz High-speed mode 4.2 MHz 2.0 MHz 3.0 MHz 1.5 MHz
High-speed mode 2.0 V to 5.5 V (Note) (f(XIN)/2) Middle-speed mode 2.0 V to 5.5 V (Note) (f(XIN)) High-speed mode Note: 2.5 V to 5.5 V for the One Timer PROM version.
Table 2.10.1 Maximum value of Supply voltage 2.5 V to 5.5 V (f(XIN)/2) 4.0 V to 5.5 V (f(XIN)) 2.5 V to 5.5 V (f(XIN))
4513/4514
XIN
CIN
Note: Externally connect a damping resistor Rd depending on the oscillaXOUT tion frequency. (A feedback resistor is built-in.) Rd Use the resonator manufacturer's recommended value because COUT constants such as capacitance depend on the resonator.
Fig. 2.10.1 Oscillation circuit example connecting ceramic resonator externally
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APPLICATION
2.10 Oscillation circuit
2.10.2 Oscillation operation System clock is supplied to CPU and peripheral device as the standard clock for the microcomputer operation. For the 4513/4514 Group, the clock (f(XIN)), (f(XIN)/2) which is supplied from the oscillation circuit is selected with the register MR. Figure 2.10.2 shows the structure of the clock control circuit.
Division circuit (divided by 2) XIN XOUT
MR3
1 0
System clock Internal clock generation circuit (divided by 3) Instruction clock Counter Wait time (Note) control circuit
Oscillation circuit
POF instruction
R S
Q
RESET Key-on wake up control register K00,K01,K02,K03 Ports P00, P01 MultiPorts P02, P03 Falling detected Ports P10, P11 plexer Ports P12, P13 I12
0
Software start signal
P30/INT0
1
"H" level
"L" level
I22
0
P31/INT1
1
"H" level
Note: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation.
Fig. 2.10.2 Structure of clock control circuit 2.10.3 Notes on use (1) Value of a part connected to an oscillator Values of a capacitor and a resistor of the oscillation circuit depend on the connected oscillator and the board. Accordingly, consult the oscillator manufacturer for values of each part connected the oscillator.
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CHAPTER 3 APPENDIX
3.1 Electrical characteristics 3.2 Typical characteristics 3.3 List of precautions 3.4 Notes on noise 3.5 Mask ROM confirmation form 3.6 Mark specification form 3.7 Package outline
APPENDIX
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings Table 3.1.1 Absolute maximum ratings
Symbol VDD VI VI VI VO VO VO Pd Topr Tstg Parameter Supply voltage Input voltage P0, P1, P2, P3, P4, P5, RESET, XIN, VDCE Input voltage D0-D7 Input voltage AIN0-AIN7 Output voltage P0, P1, P3, P4, P5, RESET Output voltage D0-D7 Output voltage XOUT Power dissipation Operating temperature range Storage temperature range Conditions Ratings -0.3 to 7.0 -0.3 to VDD+0.3 -0.3 to 13 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to 13 -0.3 to VDD+0.3 300 300 1100 -20 to 85 -40 to 125 Unit V V V V V V V mW C C
Output transistors in cut-off state
Ta = 25 C
Package: 42P2R Package: 32P6B Package: 32P4B
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APPENDIX
3.1 Electrical characteristics
3.1.2 Recommended operating conditions Table 3.1.2 Recommended operating conditions 1
(Mask ROM version:Ta = -20 C to 85 C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = -20 C to 85 C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Symbol Parameter Conditions Mask ROM version Middle-speed mode Mask ROM version High-speed mode One Time PROM version f(XIN) 4.2 MHz f(XIN) 3.0 MHz f(XIN) 4.2 MHz f(XIN) 2.0 MHz f(XIN) 1.5 MHz Limits Min. 2.5 2.0 4.0 2.5 2.0 2.5 4.0 2.5 1.8 2.0 0 P0, P1, P2, P3, P4, P5, XIN, VDCE D0-D7
RESET
Typ.
Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5
Unit
VDD
Supply voltage
V
VRAM VSS VIH VIH VIH VIH VIL VIL VIL IOH(peak) IOH(avg) IOL(peak) IOL(peak) IOL(peak) IOL(peak) IOL(avg) IOL(avg) IOL(avg) IOL(avg) IOH(avg) IOL(avg)
RAM back-up voltage (at RAM back-up mode) Supply voltage "H" level input voltage "H" level input voltage "H" level input voltage "H" level input voltage "L" level input voltage "L" level input voltage "L" level input voltage "H" level peak output current "H" level average output current "L" level peak output current "L" level peak output current "L" level peak output current "L" level peak output current "L" level average output current "L" level average output current "L" level average output current "L" level average output current "H" level total average current "L" level total average current
f(XIN) 4.2 MHz Middle-speed mode One Time PROM version f(XIN) 4.2 MHz f(XIN) 2.0 MHz High-speed mode Mask ROM version One Time PROM version
V V V V V V V V V mA mA 10 4 40 30 24 12 24 12 5 2 30 15 15 7 12 6 mA mA mA mA mA mA mA mA
CNTR0, CNTR1, SIN, SCK, INT0, INT1 P0, P1, P2, P3, P4, P5, D0-D7, XIN, VDCE
RESET
0.8VDD 0.8VDD 0.85VDD 0.85VDD 0 0 0 -20 -10 -10 -5
VDD 12 VDD VDD 0.2VDD 0.3VDD 0.15VDD
CNTR0, CNTR1, SIN, SCK, INT0, INT1 VDD = 5.0 V P5 VDD = 3.0 V P5 (Note) P3, RESET D6, D7 D0-D5 P0, P1, P4, P5, SCK, SOUT P3, RESET (Note) D6, D7 (Note) D0-D5 (Note) P0, P1, P4, P5, SCK, SOUT (Note) P5 P5, D, RESET, SCK, SOUT P0, P1, P3, P4 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD = 5.0 V = 3.0 V = 5.0 V = 3.0 V = 5.0 V = 3.0 V = 5.0 V = 3.0 V = 5.0 V = 3.0 V = 5.0 V = 3.0 V = 5.0 V = 3.0 V = 5.0 V
VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V -30
80 80
mA
Note: The average output current (IOH, IOL) is the average value during 100 ms.
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APPENDIX
3.1 Electrical characteristics
Table 3.1.3 Recommended operating conditions 2
(Mask ROM version:Ta = -20 C to 85 C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = -20 C to 85 C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Symbol Parameter Mask ROM version Middle-speed mode One Time PROM version Middle-speed mode Mask ROM version High-speed mode One Time PROM version High-speed mode Mask ROM version Middle-speed mode One Time PROM version Middle-speed mode Mask ROM version High-speed mode One Time PROM version High-speed mode Mask ROM version Middle-speed mode One Time PROM version Middle-speed mode Mask ROM version High-speed mode One Time PROM version High-speed mode Mask ROM version Middle-speed mode One Time PROM version Middle-speed mode Mask ROM version High-speed mode One Time PROM version High-speed mode Conditions VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = VDD = VDD = VDD = VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 4.0 V to 5.5 V 2.5 V to 5.5 V 2.0 V to 5.5 V 4.0 V to 5.5 V 1.5 3.0 4.0 1.5 3.0 750 1.5 2.0 750 1.5 1.5 3.0 4.0 1.5 3.0 750 1.5 2.0 750 1.5 Min. Limits Typ. Max. 4.2 3.0 4.2 4.2 2.0 1.5 4.2 2.0 3.0 3.0 3.0 1.0 0.8 3.0 1.0 MHz MHz Unit
f(XIN)
Oscillation frequency (with a ceramic resonator)
f(XIN)
Oscillation frequency (with external clock input)
= 2.5 V to 5.5 V = 4.0 V to 5.5 V = 2.5 V to 5.5 V = 2.0 V to 5.5 V = 4.0 V to 5.5 V = 2.5 V to 5.5 V = 4.0 V to 5.5 V = 2.5 V to 5.5 V = 2.0 V to 5.5 V = 4.0 V to 5.5 V = 2.5 V to 5.5 V = 4.0 V to 5.5 V = 2.5 V to 5.5 V = 2.0 V to 5.5 V = 4.0 V to 5.5 V = 2.5 V to 5.5 V = 4.0 V to 5.5 V = 2.5 V to 5.5 V = 2.0 V to 5.5 V = 4.0 V to 5.5 V
s
tw(SCK)
Serial I/O external clock period ("H" and "L" pulse width)
ns
s
ns s
s
tw(CNTR)
Timer external input period ("H" and "L" pulse width)
ns
s
ns s
VDD = 2.5 V to 5.5 V
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APPENDIX
3.1 Electrical characteristics
3.1.3 Electrical characteristics Table 3.1.4 Electrical characteristics
(Mask ROM version:Ta = -20 C to 85 C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = -20 C to 85 C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Symbol VOH VOL VOL Parameter "H" level output voltage P5 "L" level output voltage P0, P1, P4, P5 "L" level output voltage P3, RESET VDD VDD VDD VDD =5V =3V =5V =3V Test conditions IOH = -10 mA IOH = -5 mA IOL = 12 mA IOL = 6 mA IOL = 5 mA IOL = 2 mA IOL = 30 mA IOL = 10 mA IOL = 15 mA IOL = 5 mA Limits Min. 3 2 Typ. Max. Unit V 2 0.9 2 0.9 2 0.9 2 0.9 2 0.9 1 1 -1 -1 1.8 0.5 0.9 0.2 3.0 0.6 0.9 0.3 0.1 5.5 1.5 2.7 0.6 9.0 1.8 2.7 0.9 1 10 6 125 250 V V V V V
VDD = 5 V VDD = 3 V VDD = 5 V
VOL
"L" level output voltage D6, D7 VDD = 3 V
VOL IIH IIH IIL IIL
"L" level output voltage D0-D5 "H" level input current P0, P1, P2, P3, P4, P5, RESET, VDCE "H" level input current D0-D7 "L" level input current P0, P1, P2, P3, P4, P5, RESET, VDCE "L" level input current D0-D7
VDD = 5 V IOL = 15 mA VDD = 3 V IOL = 3 mA VI = VDD, port P4 selected, port P5: input state VI = 12 V VI = 0 V No pull-up of ports P0 and P1, port P4 selected, port P5: input state VI = 0 V VDD = 5 V Middle-speed mode VDD = 3 V Middle-speed mode VDD = 5 V High-speed mode VDD = 3 V High-speed mode Ta = 25 C VDD = 5 V VDD VDD VDD VDD VDD =3V =5V =3V =5V =3V f(XIN) = 4.0 MHz f(XIN) = 400 kHz f(XIN) = 4.0 MHz f(XIN) = 400 kHz f(XIN) = 4.0 MHz f(XIN) = 400 kHz f(XIN) = 2.0 MHz f(XIN) = 400 kHz
A A A A
at active mode IDD Supply current
mA
at RAM back-up mode
A
RPU VT+ - VT- VT+ - VT-
Pull-up resistor value Hysteresis INT0, INT1, CNTR0, CNTR1, SIN, SCK Hysteresis RESET
VI = 0 V
20 40
50 100 0.3 0.3 1.5 0.6
k V V
VDD = 5 V VDD = 3 V
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APPENDIX
3.1 Electrical characteristics
3.1.4 A-D converter recommended operating conditions Table 3.1.5 A-D converter recommended operating conditions
(Comparator mode included, Ta = -20 C to 85 C, unless otherwise noted) Symbol VDD VIA f(XIN) Parameter Supply voltage Analog input voltage Oscillation frequency Middle-speed mode, VDD 2.7 V High-speed mode, VDD 2.7 V Conditions Min. 2.7 0 0.8 0.4 Limits Typ. Max. 5.5 VDD Unit V V MHz MHz
Table 3.1.6 A-D converter characteristics
(Ta = -20 C to 85 C, unless otherwise noted) Symbol - - - V0T VFST IADD TCONV - - - Parameter Resolution Linearity error Differential non-linearity error Zero transition voltage Full-scale transition voltage A-D operating current A-D conversion time Comparator resolution Comparator error (Note) Comparator comparison time Ta Ta Ta Ta = = = = 25 C, VDD = 2.7 V to 5.5 V -25 C to 85 C, VDD = 3.0 V to 5.5 V 25 C, VDD = 2.7 V to 5.5 V -25 C to 85 C, VDD = 3.0 V to 5.5 V = 5.12 V = 3.072 V = 5.12 V = 3.072 V = 5.0 V 0 0 5105 3060 f(XIN) = 0.4 MHz to 4.0 MHz f(XIN) = 0.4 MHz to 2.0 MHz 5 3 5115 3069 0.7 0.2 Test conditions Min. Limits Typ. Unit Max. 10 2 0.9 20 15 5125 3075 2.0 0.4 93.0 46.5 8 20 15 12 6 bits LSB LSB mV mV mA
VDD VDD VDD VDD VDD
VDD = 3.0 V f(XIN) = 4.0 MHz, Middle-speed mode f(XIN) = 4.0 MHz, High-speed mode Comparator mode VDD = 5.12 V VDD = 3.072 V f(XIN) = 4.0 MHz, Middle-speed mode f(XIN) = 4.0 MHz, High-speed mode
s
bits mV
s
Note: As for the error from the ideal value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison voltage Vref which is generated by the built-in DA converter can be obtained by the following formula.
Logic value of comparison voltage Vref Vref = VDD 256 !n
n = Value of register AD (n = 0 to 255)
3.1.5 Voltage drop detection circuit characteristics Table 3.1.7 Voltage drop detection circuit characteristics
(Ta = -20 C to 85 C, unless otherwise noted) Symbol VRST IRST Parameter Detection voltage Operation current of voltage drop detection circuit Test conditions Min. 2.7 3.3 Limits Typ. 3.5 50 Max. 4.1 3.7 100 Unit V
Ta = 25 C VDD = 5.0 V
A
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APPENDIX
3.1 Electrical characteristics
3.1.6 Voltage comparator characteristics Table 3.1.8 Voltage comparator recommended operating conditions
(Ta = -20 C to 85 C, unless otherwise noted) Symbol VDD VINCMP tCMP Parameter Supply voltage Voltage comparator input voltage Voltage comparator response time Conditions Limits Typ. Unit V V s
VDD = 3.0 V to 5.5 V VDD = 3.0 V to 5.5 V
Min. 3.0 0.3VDD
Max. 5.5 0.7VDD 20
Table 3.1.9 Voltage comparator characteristics
(Ta = -20 C to 85 C, VDD = 3.0 V to 5.5 V, unless otherwise noted) Symbol - ICMP Parameter Comparison decision voltage error Voltage comparator operation current Test conditions CMP0- > CMP0+, CMP0- < CMP0+ CMP1- > CMP1+, CMP1- < CMP1+ VDD = 5.0 V Min. Limits Typ. 20 15 Max. 100 50 Unit mV
A
3.1.7 Basic timing diagram Machine cycle Parameter Clock
Pin name XIN System clock = f(XIN) XIN System clock = f(XIN)/2
Mi
Mi+1
Port D output Port D input Ports P0, P1, P3, P4, P5 output
D0-D7 D0-D7 P00-P03 P10-P13 P30-P33 P40-P43 P50-P53
Ports P0, P1, P2, P3, P00-P03 P10-P13 P4, P5 input P20-P22
P30-P33 P40-P43 P50-P53
Interrupt input
INT0,INT1
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APPENDIX
3.2 Typical characteristics
3.2 Typical characteristics
3.2.1 VDD-IDD characteristics (1) CPU operating, middle-speed mode
2.5 2.4 2.3 2.2 2.1 2 1.9 1.8
Ta = 25 C
Supply current IDD (mA)
1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 4 4.5 5 5.5
f(XIN) = 4 MHz
f(XIN) = 1 MHz
Supply voltage VDD (V) (2) CPU operating, high-speed mode
2.5 2.4 2.3 2.2 2.1 2 1.9 1.8
Ta = 25 C
f(XIN) = 4 MHz
Supply current IDD (mA)
1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 4 4.5 5 5.5
f(XIN) = 1 MHz
Supply voltage VDD (V) 3-8
4513/4514 Group User's Manual
APPENDIX
3.2 Typical characteristics
(3) A-D operating, middle-speed mode
2.5 2.4 2.3 2.2 2.1 2 1.9 1.8
Ta = 25 C
f(XIN) = 4 MHz
Supply current IDD (mA)
1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 4 4.5 5 5.5
f(XIN) = 1 MHz
(4)
Supply voltage VDD (V) A-D operating, high-speed mode Ta = 25 C
2.5 2.4 2.3 2.2 2.1 2 1.9 1.8 1.7
f(XIN) = 4 MHz
Supply current IDD (mA)
1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 4 4.5 5 5.5
f(XIN) = 1 MHz
Supply voltage VDD (V)
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APPENDIX
3.2 Typical characteristics
(5) RAM back-up Ta = 25 C
5
4.5
4
3.5
3
Supply current IDD (nA)
2.5
2
1.5
1
0.5
0 2 2.5 3 3.5 4 4.5 5 5.5
Supply voltage VDD (V)
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APPENDIX
3.2 Typical characteristics
3.2.2 VOL-IOL characteristics (1) Ports P0, P1, P4, P5, SCK, SOUT
100
Ta = 25 C
90
VDD = 6 V
80
VDD = 5 V
70
Output current IOL (mA)
60
VDD = 4 V
50
40
VDD = 3 V
30
20
VDD = 2 V
10
0 0 0.5 1 1.5 2
Output voltage VOL (V) (2) Port P3, RESET pin
100
Ta = 25 C
90
80
Output current IOL (mA)
70
60
50
VDD = 6 V VDD = 5 V VDD = 4 V
40
30
20
VDD = 3 V VDD = 2 V
0 0.5 1 1.5 2
10
0
Output voltage VOL (V)
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APPENDIX
3.2 Typical characteristics
(3) Pins D0-D5
100
Ta = 25 C
90
80
Output current IOL (mA)
70
60
VDD = 6 V
50
VDD = 5 V VDD = 4 V
40
30
VDD = 3 V
20
10
VDD = 2 V
0 0 0.5 1 1.5 2
Output voltage VOL (V) (4) Pins D6/CNTR0, D7/CNTR1
100
Ta = 25 C
90
80
VDD = 6 V Output current IOL (mA)
70
VDD = 5 V VDD = 4 V
60
50
VDD = 3 V
40
30
20
VDD = 2 V
10
0 0 0.5 1 1.5 2
Output voltage VOL (V)
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APPENDIX
3.2 Typical characteristics
3.2.3 VOH-IOH characteristics (Port P5)
0
VDD = 2 V
VDD = 3 V
VDD = 4 V
VDD = 5 V
VDD = 6 V
Ta = 25 C
-10
-20
-30
Output current IOH (mA)
-40
-50
-60
-70
-80
-90
-100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Output voltage VOH (V) 3.2.4 VDD-RPU characteristics (Ports P0, P1)
350
Ta = 25 C
300
Pull-up resistor RPU (k)
250
200
150
100
50
0 2 2.5 3 3.5 4 4.5 5 5.5 6
Supply voltage VDD (V)
4513/4514 Group User's Manual
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APPENDIX
3.2 Typical characteristics
3.2.5 A-D converter typical characteristics
30 1LSB WIDTH +1LSB
1LSB WIDTH [ mV]
ERROR [mV]
0

ERROR
0
-1LSB -30
0
1
1022 1023
Fig. 3.2.1 A-D conversion characteristics data Figure 3.2.1 shows the A-D accuracy measurement data. (1) Non-linearity error ......................... This means a deviation from the ideal characteristics between V0 to V1022 of actual A-D conversion characteristics. In Figure 3.2.1, it is (-)/1LSB. (2) Differencial non-linearity error .... This means a deviation from the ideal characteristics between the input voltages V0 to V1022 necessary to change the output data to "1." In Figure 3.2.1, this is /1LSB. (3) Zero transition error ..................... This means a deviation from the ideal characteristics between the input voltages 0 to VDD when the output data changes from "0" to "1." In Figure 3.2.1, this is the value of . (4) Full-scale transition error ............. This means a deviation from the ideal characteristics between the input voltages 0 to VDD when the output data changes from "1022" to "1023." In Figure 3.2.1, this is the value of . (5) Absolute accuracy ........................ This menas a deviation from the ideal characteristics between 0 to VDD of actual A-D conversion characteristics. In Figure 3.2.1, this is the value of ERROR in each of , , and . For the A-D converter characteristics, refer to the section 3.1 Electrical characteristics.
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APPENDIX
3.2 Typical characteristics
(1) VDD = 3.072 V, f(XIN) = 2 MHz, high-speed mode
Ta = 25 C
4.5
1LSB WIDTH
ERROR / 1LSB WIDTH(mV)
3 1.5 0 -1.5 -3 -4.5 0 16 32 48 64 80 96 112 128 STEP No. 4.5 144 160 176 192 208 224 240 256
ERRO R
ERROR / 1LSB WIDTH(mV)
3 1.5 0 -1.5 -3 -4.5 256
272
288
304
320
336
352
368
384 STEP No.
400
416
432
448
464
480
496
512
4.5
ERROR / 1LSB WIDTH(mV)
3 1.5 0 -1.5 -3 -4.5 512
528
544
560
576
592
608
624
640 STEP No.
656
672
688
704
720
736
752
768
4.5
ERROR / 1LSB WIDTH(mV)
3 1.5 0 -1.5 -3 -4.5 768
784
800
816
832
848
864
880
896 STEP No.
912
928
944
960
976
992
1008
1024
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APPENDIX
3.2 Typical characteristics
(2) VDD = 5.12 V, f(XIN) = 4 MHz, high-speed mode
Ta = 25 C
7.5
1LSB WIDTH
ERROR / 1LSB WIDTH(mV)
5 2.5 0 -2.5 -5 -7.5 0 16 32 48 64 80 96 112 128
ERRO R
144
160
176
192
208
224
240
256
STEP No. 7.5
ERROR / 1LSB WIDTH(mV)
5 2.5 0 -2.5 -5 -7.5 256
272
288
304
320
336
352
368
384 STEP No.
400
416
432
448
464
480
496
512
7.5
ERROR / 1LSB WIDTH(mV)
5 2.5 0 -2.5 -5 -7.5 512
528
544
560
576
592
608
624
640 STEP No.
656
672
688
704
720
736
752
768
7.5
ERROR / 1LSB WIDTH(mV)
5 2.5 0 -2.5 -5 -7.5 768
784
800
816
832
848
864
880
896 STEP No.
912
928
944
960
976
992
1008
1024
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4513/4514 Group User's Manual
APPENDIX
3.2 Typical characteristics
3.2.6 Analog input current characteristics pins AIN0-AIN7 (1) VDD = 3.0 V, f(XIN) = 2 MHz, middle-speed mode
25
Ta = 25 C
20
Analog input current IAIN (nA)
15
10
5
0
-5
-10
-15
-20
-25 0 0.5 1 1.5 2 2.5 3
Analog input voltage VAIN (V) (2) VDD = 3.0 V, f(XIN) = 4 MHz, middle-speed mode
100
Ta = 25 C
80
60
Analog input current IAIN (nA)
40
20
0
-20
-40
-60
-80
-100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Analog input voltage VAIN (V)
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APPENDIX
3.2 Typical characteristics
(3) VDD = 3.0 V, f(XIN) = 2 MHz, high-speed mode Ta = 25 C
50
40
30
Analog input current IAIN (nA)
20
10
0
-10
-20
-30
-40
-50 0 0.5 1 1.5 2 2.5 3
Analog input voltage VAIN (V) (4) VDD = 5.0 V, f(XIN) = 4 MHz, high-speed mode
200
Ta = 25 C
160
120
80
Analog input current IAIN (nA)
40
0
-40
-80
-120
-160
-200 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Analog input voltage VAIN (V) 3-18
4513/4514 Group User's Manual
APPENDIX
3.2 Typical characteristics
3.2.7 VDD-VIH/VIL characteristics (1)
5.5
RESET pin Ta = 25 C VIH (rating value) VIH
5
4.5
4
3.5
3
VIH/VIL (V)
VIL
2.5
2
1.5
VIL (rating value)
1
0.5
0 2 2.5 3 3.5 4 4.5 5 5.5 6
Supply voltage VDD (V)
(2)
5.5
Ports P0, P1, P2, P3, P4, P5, D, XIN pin, VDCE pin Ta = 25 C
5
VIH (rating value)
4.5
4
3.5
VIH/VIL (V)
3
VIH, VIL
2.5
2
1.5
1
VIL (rating value)
0.5
0 2 2.5 3 3.5 4 4.5 5 5.5 6
Supply voltage VDD (V)
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APPENDIX
3.2 Typical characteristics
(3)
5.5
Pins INT0, INT1, CNTR0, CNTR1, SCK, SIN Ta = 25 C VIL (rating value)
5
4.5
4
3.5
VIH/VIL (V)
3
VIH VIL
2.5
2
1.5
1
0.5
VIH (rating value)
2 2.5 3 3.5 4 4.5 5 5.5 6
0
Supply voltage VDD (V)
3.2.8 Detection voltage temperature characteristics of voltage drop detection circuit
4.5 4.4 4.3 4.2 4.1 4
Detection voltage VRST (V)
3.9 3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3 2.9 2.8 2.7 2.6 2.5 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
Storage temperature range Ta (C)
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4513/4514 Group User's Manual
APPENDIX
3.3 List of precautions
3.3 List of precautions
Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; * connect a bypass capacitor (approx. 0.1 F) between pins VDD and VSS at the shortest distance, * equalize its wiring in width and length, and * use relatively thick wire. In the One Time PROM version, CNVSS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 k in series at the shortest distance. Prescaler Stop the prescaler operation to change its frequency dividing ratio. Timer count source Stop timer 1, 2, 3, or 4 counting to change its count source. Reading the count value Stop timer 1, 2, 3, or 4 counting and then execute the TAB1, TAB2, TAB3, or TAB4 instruction to read its data. Writing to reload registers R1 and R3 When writing data to reload registers R1 or R3 while timer 1 or timer 3 is operating, avoid a timing when timer 1 or timer 3 underflows. P30/INT0 pin When the interrupt valid waveform of the P30/INT0 pin is changed with the bit 2 of register I1 in software, be careful about the following notes. * Clear the bit 0 of register V1 to "0" before the interrupt valid waveform of P30/INT0 pin is changed with the bit 2 of register I1 (refer to Figure 44). * Depending on the input state of the P30/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the interrupt valid waveform is changed. Accordingly, clear bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction (refer to Figure 44) P31/INT1 pin When the interrupt valid waveform of P31/INT1 pin is changed with the bit 2 of register I2 in software, be careful about the following notes. * Clear the bit 1 of register V1 to "0" before the interrupt valid waveform of P31/INT1 pin is changed with the bit 2 of register I2 (refer to Figure 45). * Depending on the input state of the P31/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the interrupt valid waveform is changed. Accordingly, clear bit 2 of register I2 and execute the SNZ1 instruction to clear the EXF1 flag after executing at least one instruction (refer to Figure 45).
. . .
LA 8 TV1A LA 8 TI2A NOP SNZ1 NOP ; (!!0!2) ; The SNZ1 instruction is valid ........... ; Change of the interrupt valid waveform ........................................................... ; The SNZ1 instruction is executed
. . .
! : this bit is not related to the setting of INT1.
Fig. 45 External 1 interrupt program example One Time PROM version The operating power voltage of the One Time PROM version is 2.5 V to 5.5 V. Multifunction The input of D6, D7, P20-P22, I/O of P30 and P31, input of CMP0-, CMP0+, CMP1-, CMP1+, and I/O of P40-P43 can be used even when CNTR0, CNTR1, SCK, SOUT, SIN, INT0, INT1, AIN0-AIN3 and AIN4-AIN7 are selected.
. . .
LA 4 TV1A LA 4 TI1A NOP SNZ0 NOP ; (!!!02) ; The SNZ0 instruction is valid ........... ; ; Interrupt valid waveform is changed ........................................................... ; The SNZ0 instruction is executed
. . .
! : this bit is not related to the setting of INT0 pin. Fig. 44 External 0 interrupt program example
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APPENDIX
3.3 List of precautions
A-D converter-1 When the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 in a program, be careful about the following notes. * Clear the bit 2 of register V2 to "0" to change the operating mode of the A-D converter from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 (refer to Figure 46). * The A-D conversion completion flag (ADF) may be set when the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode. Accordingly, set a value to register Q2, and execute the SNZAD instruction to clear the ADF flag. Do not change the operating mode (both A-D conversion mode and comparator mode) of A-D converter with the bit 3 of register Q2 during operating the A-D converter.
Sensor
AIN
Apply the voltage withiin the specifications to an analog input pin.
Fig. 47 Analog input external circuit example-1
. . .
LA 8 TV2A LA 0 TQ2A ; (!0!!2) ; The SNZAD instruction is valid ........ ; (0!!!2) ; Change of the operating mode of the A-D converter from the comparator mode to the A-D conversion mode
About 1k
Sensor
AIN
SNZAD NOP
Fig. 48 Analog input external circuit example-2
12
. . .
!: this bit is not related to the change of the operating mode of the A-D conversion.
Fig. 46 A-D converter operating mode program example
11
A-D converter-2 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A-D accuracy may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 F to 1 F) to analog input pins (Figure 47). When the overvoltage applied to the A-D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 48. In addition, test the application products sufficiently.
POF instruction Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM back-up. Note that system cannot enter the RAM back-up state when executing only the POF instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.
Analog input pins Note the following when using the analog input pins also for I/O port P4 functions: * Even when P40/AIN4-P43/AIN7 are set to pins for analog input, they continue to function as P40-P43 I/O. Accordingly, when any of them are used as I/O port P4 and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to "1." Also, the port input function of the pin functions as an analog input is undefined. * TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is "0."
13 14
Program counter Make sure that the PCH does not specify after the last page of the built-in ROM. Port P3 In the 4513 Group, when the IAP3 instruction is executed, note that the high-order 2 bits of register A is undefined.
15
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APPENDIX
3.3 List of precautions
16
Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode. Accordingly, be careful about such state because it causes the increase of the operation current in the RAM backup mode. In order to reduce the operation current in the RAM back-up mode, invalidate (bits 2 and 3 of register Q3 = "0") the voltage comparator function by software before the POF instruction is executed. Also, while the voltage comparator function is valid, current is always consumed by voltage comparator. On the system required for the low-power dissipation, invalidate the voltage comparator when it is unused by software. Register Q3 Bits 0 and 1 of register Q3 can be only read. Note that they cannot be written. Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time (max. 20 s) is passed from the voltage comparator function become valid.
17
18
4513/4514 Group User's Manual
3-23
APPENDIX
3.4 Notes on noise
3.4 Notes on noise
Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.4.1 Shortest wiring length The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Package Select the smallest possible package to make the total wiring length short. q Reason The wiring length depends on a microcomputer package. Use of a small package, for example QFP and not DIP, makes the total wiring length short to reduce influence of noise.
(2) Wiring for RESET input pin Make the length of wiring which is connected to the RESET input pin as short as possible. Especially, connect a capacitor across the RESET input pin and the VSS pin with the shortest possible wiring. q Reason In order to reset a microcomputer correctly, 1 machine cycle or more of the width of a pulse input into the RESET pin is required. If noise having a shorter pulse width than this is input to the RESET input pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway.
Noise
Reset circuit VSS
N.G.
RESET VSS
DIP SDIP SOP QFP
O.K.
Reset circuit VSS
RESET VSS
Fig. 3.4.2 Wiring for the RESET input pin Fig. 3.4.1 Selection of packages
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APPENDIX
3.4 Notes on noise
(3) Wiring for clock input/output pins * Make the length of wiring which is connected to clock I/O pins as short as possible. * Make the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. * Separate the VSS pattern only for oscillation from other VSS patterns. (4) Wiring to CNVSS pin Connect the CNVSS pin to the VSS pin with the shortest possible wiring. q Reason The operation mode of a microcomputer is influenced by a potential at the CNVSS pin. If a potential difference is caused by the noise between pins CNVSS and VSS, the operation mode may become unstable. This may cause a microcomputer malfunction or a program runaway. Noise
Noise
XIN XOUT VSS
N.G.
XIN XOUT VSS
O.K.
CNVSS VSS
CNVSS VSS
Fig. 3.4.3 Wiring for clock I/O pins q Reason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer.
N.G.
O.K.
Fig. 3.4.4 Wiring for CNVSS pin
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APPENDIX
3.4 Notes on noise
(5) Wiring to VPP pin of One Time PROM version In the built-in PROM version of the 4513/4514 Group, the CNVSS pin is also used as the built-in PROM power supply input pin VPP. q When the VPP pin is also used as the CNVSS pin Connect an approximately 5 k resistor to the VPP pin the shortest possible in series a n d a l s o t o t h e VSS p i n . W h e n n o t connecting the resistor, make the length of wiring between the VPP pin and the VSS pin the shortest possible (refer to Figure 3.4.5) Note: Even when a circuit which included an approximately 5 k resistor is used in the Mask ROM version, the microcomputer operates correctly. q Reason The VPP pin of the One Time PROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current for writing flow into the PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the built-in PROM, which may cause a program runaway.
When the VPP pin is also used as the CNVSS pin Approximately 5k CNVSS/VPP VSS
3.4.2 Connection of bypass capacitor across VSS line and VDD line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VDD line as follows: * Connect a bypass capacitor across the VSS pin and the VDD pin at equal length. * Connect a bypass capacitor across the VSS pin and the VDD pin with the shortest possible wiring. * Use lines with a larger diameter than other signal lines for VSS line and VDD line. * Connect the power source wiring via a bypass capacitor to the VSS pin and the VDD pin.
VDD
VDD
VSS
VSS
N.G.
O.K.
Fig. 3.4.6 Bypass capacitor across the VSS line and the VDD line
In the shortest distance
Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM version
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4513/4514 Group User's Manual
APPENDIX
3.4 Notes on noise
3.4.3 Wiring to analog input pins * Connect an approximately 100 to 1 k resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. * Connect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides, connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog input pin and the VSS pin at equal length. q Reason Signals which is input in an analog input pin (such as an A-D converter/comparator input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. Noise
(Note)
3.4.4 Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. q Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance.
Microcomputer Mutual inductance M
Microcomputer Analog input pin
N.G. O.K.
Large current GND
XIN XOUT VSS
Thermistor
Fig. 3.4.8 Wiring for a large current signal line VSS (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. q Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway.
Note : The resistor is used for dividing resistance with a thermistor.
Fig. 3.4.7 Analog signal line and a resistor and a capacitor
4513/4514 Group User's Manual
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APPENDIX
3.4 Notes on noise
3.4.5 Setup for I/O ports Setup I/O ports using hardware and software as follows: * Connect a resistor of 100 or more to an I/O port in series. * As for an input port, read data several times by a program for checking whether input levels are equal or not. * As for an output port or an I/O port, since the output data may reverse because of noise, rewrite data to its output latch at fixed periods. * Rewrite data to pull-up control registers at fixed periods. 3.4.6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
N.G.
Do not cross
CNTR XIN XOUT VSS
Fig. 3.4.9 Wiring to a signal line where potential levels change frequently (3) Oscillator protection using VSS pattern As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides, separate this VSS pattern from other VSS patterns.
An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example
XIN XOUT VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.10 VSS pattern on the underside of an oscillator
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4513/4514 Group User's Manual
APPENDIX
3.4 Notes on noise
* Assigns a single word of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 (Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. * Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set. * Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. * Decrements the SWDT contents by 1 at each interrupt processing. * Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). * Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less.
Main routine (SWDT) N EI Main processing N (SWDT) =N? N Interrupt processing routine (SWDT) (SWDT)--1 Interrupt processing (SWDT) 0? 0 >0 RTI Return Main routine errors
Interrupt processing routine errors
Fig. 3.4.11 Watchdog timer by software
4513/4514 Group User's Manual
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APPENDIX
3.5 Mask ROM order confirmation form
3.5 Mask ROM order confirmation form
GZZ-SH52-45B <81A0> 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34513M2-XXXSP/FP MITSUBISHI ELECTRIC Please fill in all items marked V . Mask ROM number Date: Receipt ) 000016 2.00K 07FF16 400016 2.00K 47FF16 FFFF16 Issuance signature
Section head S u p e r v i s o r signature signature
Company name
V Customer
Date issued Date:
Responsible Supervisor officer
TEL (
V 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Microcomputer name: M34513M2-XXXSP M34513M2-XXXFP (hexadecimal notation)
Checksum code for entire EPROM area
EPROM Type: 27C256
Low-order 5-bit data
27C512
Low-order 5-bit data
000016 2.00K 07FF16 400016 2.00K 47FF16 7FFF16
High-order 5-bit data
High-order 5-bit data
Set "FF16" in the shaded area. Set "1112" in the area of low-order and high-order 5-bit data.
V 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (32P4B for M34513M2-XXXSP, 32P6B-A for M34513M2-XXXFP) and attach to the Mask ROM Order Confirmation Form. V 3. Comments
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4513/4514 Group User's Manual
APPENDIX
3.5 Mask ROM order confirmation form
GZZ-SH52-44B <81A0> 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34513M4-XXXSP/FP MITSUBISHI ELECTRIC Please fill in all items marked V .
Mask ROM number Date: Receipt ) 000016 4.00K 0FFF16 400016 4.00K 4FFF16 FFFF16 Issuance signature
Section head S u p e r v i s o r signature signature
Company name V Customer Date issued Date: TEL (
Responsible Supervisor officer
V 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name: M34513M4-XXXSP M34513M4-XXXFP (hexadecimal notation)
Checksum code for entire EPROM area
EPROM Type: 27C256
Low-order 5-bit data
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
27C512
Low-order 5-bit data
5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321
000016 4.00K 0FFF16 400016 4.00K 4FFF16 7FFF16
High-order 5-bit data
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
High-order 5-bit data
5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321
Set "FF16" in the shaded area. Set "1112" in the area of low-order and high-order 5-bit data. V 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (32P4B for M34513M4-XXXSP, 32P6B-A for M34513M4-XXXFP) and attach to the Mask ROM Order Confirmation Form. V 3. Comments
4513/4514 Group User's Manual
3-31
APPENDIX
3.5 Mask ROM order confirmation form
GZZ-SH53-01B <85A0> 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34513M6-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked V .
Mask ROM number Date: Receipt ) 000016 6.00K 17FF16 400016 6.00K 57FF16 FFFF16 Issuance signature
Section head S u p e r v i s o r signature signature
Company name V Customer Date issued Date: TEL (
Responsible Supervisor officer
V 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM area
(hexadecimal notation)
EPROM Type: 27C256
Low-order 5-bit data
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
27C512
Low-order 5-bit data
5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321
000016 6.00K 17FF16 400016 6.00K 57FF16 7FFF16
Set "FF16" in the shaded area. Set "1112" in the area of low-order and high-order 5-bit data. V 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (32P6B-A for M34513M6-XXXFP) and attach to the Mask ROM Order Confirmation Form. V 3. Comments
3-32
4513/4514 Group User's Manual
5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
High-order 5-bit data
High-order 5-bit data
APPENDIX
3.5 Mask ROM order confirmation form
GZZ-SH52-99B <85A0> 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34513M8-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked V .
Mask ROM number Date: Receipt ) 000016 8.00K 1FFF16 400016 8.00K 5FFF16 FFFF16 Issuance signature
Section head S u p e r v i s o r signature signature
Company name V Customer Date issued Date: TEL (
Responsible Supervisor officer
V 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM area
(hexadecimal notation)
EPROM Type: 27C256
Low-order 5-bit data
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
27C512
Low-order 5-bit data
5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321
000016 8.00K 1FFF16 400016 8.00K 5FFF16 7FFF16
High-order 5-bit data
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
High-order 5-bit data
5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321
Set "FF16" in the shaded area. Set "1112" in the area of low-order and high-order 5-bit data. V 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (32P6B-A for M34513M8-XXXFP) and attach to the Mask ROM Order Confirmation Form. V 3. Comments
4513/4514 Group User's Manual
3-33
APPENDIX
3.5 Mask ROM order confirmation form
GZZ-SH52-41B <81A0> 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34514M6-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked V .
Mask ROM number Date: Receipt ) 000016 6.00K 17FF16 400016 6.00K 57FF16 FFFF16 Issuance signature
Section head S u p e r v i s o r signature signature
Company name V Customer Date issued Date: TEL (
Responsible Supervisor officer
V 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation)
EPROM Type:
27C256
Low-order 5-bit data
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
27C512
Low-order 5-bit data
5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321
000016 6.00K 17FF16 400016 6.00K 57FF16 7FFF16
High-order 5-bit data
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
High-order 5-bit data
5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321
Set "FF16" in the shaded area. Set "1112" in the area of low-order and high-order 5-bit data. V 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (42P2R-A for M34514M6-XXXFP) and attach to the Mask ROM Order Confirmation Form. V 3. Comments
3-34
4513/4514 Group User's Manual
APPENDIX
3.5 Mask ROM order confirmation form
GZZ-SH52-40B <81A0> 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34514M8-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked V .
Mask ROM number Date: Receipt ) 000016 8.00K 1FFF16 400016 8.00K 5FFF16 FFFF16 Issuance signature
Section head S u p e r v i s o r signature signature
Company name V Customer Date issued Date: TEL (
Responsible Supervisor officer
V 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation)
EPROM Type:
27C256
Low-order 5-bit data
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
27C512
Low-order 5-bit data
5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321
000016 8.00K 1FFF16 400016 8.00K 5FFF16 7FFF16
High-order 5-bit data
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
High-order 5-bit data
5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321
Set "FF16" in the shaded area. Set "1112" in the area of low-order and high-order 5-bit data. V 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (42P2R-A for M34514M8-XXXFP) and attach to the Mask ROM Order Confirmation Form. V 3. Comments
4513/4514 Group User's Manual
3-35
APPENDIX
3.6 Mark specification form
3.6 Mark specification form
32P4B (32-PIN SHRINK DIP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark
32 17
Mitsubishi lot number (6-digit or 7-digit)
Mitsubishi IC catalog name
1
16
B. Customer's Parts Number + Mitsubishi catalog name
32 17
Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name
Mitsubishi lot number (6-digit or 7-digit)
1
16
Note1 : 2: 3: 4:
The mark field should be written right aligned. The fonts and size of characters are standard Mitsubishi type. Customer's Parts Number can be up to 16 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, (c), (periods), and (commas) are usable. If the Mitsubishi logo is not required, check the box on the right. Mitsubishi logo is not required
.
,
C. Special Mark Required
32 17
1
16
Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the upper figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer's trade mark logo must be used in the Special Mark, check the Special logo required box on the right. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. 3 : The standard Mitsubishi font is used for all characters except for a logo.
3-36
4513/4514 Group User's Manual
APPENDIX
3.6 Mark specification form
32P6B (32-PIN LQFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name Please choose one of the marking types below (A, B), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark
24 25 17 16
Mitsubishi IC catalog name Mitsubishi IC catalog name
Mitsubishi lot number (4-digit or 5-digit)
32 1 8
9
B. Customer's Parts Number + Mitsubishi catalog name
24 25 17 16
Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's Parts Number can be up to 7 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, (c),. (periods), (commas) are usable.
,
32 1 8
9
4513/4514 Group User's Manual
3-37
APPENDIX
3.6 Mark specification form
42P2R-A (42-PIN SHRINK SOP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark
42 22
Mitsubishi IC catalog name Mitsubishi IC catalog name Mitsubishi lot number (6-digit or 7-digit)
1 21
B. Customer's Parts Number + Mitsubishi catalog name
42
22
Mitsubishi lot number (6-digit or 7-digit)
1 21
Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's Parts Number can be up to 11 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, (c), (periods), (commas) are usable. 4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required
.
,
C. Special Mark Required
42 22
1
21
Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer's trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required
3-38
4513/4514 Group User's Manual
APPENDIX
3.7 Package outline
3.7 Package outline
32P4B
EIAJ Package Code SDIP32-P-400-1.78 JEDEC Code - Weight(g) 2.2 Lead Material Alloy 42/Cu Alloy
Plastic 32pin 400mil SDIP
32
17
1
16
D Symbol A A1 A2 b b1 b2 c D E e e1 L
e SEATING PLANE
b1
b
b2
Dimension in Millimeters Min Nom Max - - 5.08 0.51 - - - 3.8 - 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 - 1.778 - - 10.16 - 3.0 - - 0 - 15
A
32P6B-A
EIAJ Package Code LQFP32-P-77-0.80 JEDEC Code - Weight(g) Lead Material Alloy 42
L
A1
A2
Plastic 32pin 7!7mm body LQFP
MD
e
32
25
b2
HD D
I2
1 24
Recommended Mount Pad
E HE
Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME
8
17
9
16
A L1 e F
A2
b
A1
y
L Detail F
Dimension in Millimeters Min Nom Max 1.7 - - 0.1 0.2 0 1.4 - - 0.3 0.35 0.45 0.105 0.125 0.175 6.9 7.0 7.1 6.9 7.0 7.1 0.8 - - 8.8 9.0 9.2 8.8 9.0 9.2 0.3 0.5 0.7 1.0 - - 0.1 - - 0 10 - 0.5 - - 1.0 - - - - 7.4 - - 7.4
4513/4514 Group User's Manual
c
ME
e1
E
c
3-39
APPENDIX
3.7 Package outline
42P2R-A
EIAJ Package Code SSOP42-P-450-0.80 JEDEC Code - Weight(g) 0.63 Lead Material Alloy 42/Cu Alloy
Plastic 42pin 450mil SSOP
e
42 22
b2
HE
E
e1
F
Recommended Mount Pad Symbol Dimension in Millimeters Min Nom Max 2.4 - - - - 0.05 - 2.0 - 0.5 0.4 0.35 0.2 0.15 0.13 17.7 17.5 17.3 8.6 8.4 8.2 - 0.8 - 12.23 11.93 11.63 0.7 0.5 0.3 - 1.765 - 0.15 - - 0 - 10 - 0.5 - - 11.43 - - 1.27 -
1
21
A
D
A2
A1
L1
e
y
b
c Detail F
L
A A1 A2 b c D E e HE L L1 y b2 e1 I2
3-40
4513/4514 Group User's Manual
I2
MITSUBISHI SEMICONDUCTORS USER'S MANUAL 4513/4514 Group
Dec. First Edition 1998 Editioned by Committee of editing of Mitsubishi Semiconductor USER'S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.
(c)1998 MITSUBISHI ELECTRIC CORPORATION
REVISION DESCRIPTION LIST
Rev. No. 1.0 First Edition
4513/4514 GROUP USER'S MANUAL
Revision Description Rev. date 981211
(1/1)
User's Manual 4513/4514 Group
(c) 1998 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective Dec. 1998. Specifications subject to change without notice.

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