View HV22007_4884161.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HV220/HV20220/HV20320 Low Charge Injection 8-Channel High Voltage Analog Switches
Features
HVCMOS(R) technology for high performance Very low quiescent power dissipation - 10A Output on-resistance typically 22 ohms Low parasitic capacitances DC to 10MHz analog signal frequency -60dB typical output off isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity On-chip shift register, latch and clear logic circuitry Flexible high voltage supplies
General Description
These devices are low charge injection 8-channel high-voltage analog switch integrated circuits (ICs) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. Input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. To reduce any possible clock feed-through noise, Latch Enable Bar (LE) should be left high until all bits are clocked in. Using HVCMOS technology, these switches combine high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. These ICs are suitable for various combinations of high voltage supplies, e.g., VPP/VNN : +50V/-150V, or +100V/-100V.B
Applications
Medical ultrasound imaging Piezoelectric transducer drivers
Block Diagram
DIN
LATCHES D LE CL
LEVEL SHIFTERS
OUTPUT SWITCHES
SW0
D LE CL CLK D LE CL
SW1
SW2
8-Bit Shift Register
D LE CL
SW3
D LE CL
SW4
D LE CL
SW5
DOUT
D LE CL
SW6
D LE CL
SW7
VDD
LE
CL
V NN V PP
HV220/HV20220/HV20320
Ordering Information
Package Options Device 28-Lead PLCC HV20220PJ HV20220PJ-G HV20320PJ HV20320PJ-G 48-Lead LQFP/TQFP (1.4mm) HV20220FG HV20220FG-G 25-Ball fpBGA HV220GA HV220GA-G -
HV220 HV20220 HV20320
-G indicates the part is RoHS compliant (`Green')
Absolute Maximum Ratings
Parameter VDD logic power supply voltage VPP - VNN supply voltage VPP positive high voltage supply VNN negative high voltage supply Logic input voltages Analog signal range Peak analog signal current/channel Storage temperature Power dissipation: 28-Lead PLCC 48-Lead LQFP/ TQFP(1.4mm) 25-Ball fpBGA Value -0.5V to +15V 220V -0.5V to VNN +200V +0.5V to -200V -0.5V to VDD +0.3V VNN to VPP 3.0A -65OC to +150OC 1.2W 1.0W 1.0W
Product Marking
Top Marking
YY = Year Sealed WW = Week Sealed LLLLLLLLL L = Lot Number Bottom Marking C = Country of Origin* A = Assembler ID* = "Green" Packaging CCCCCCCC
HV20220FG
AAA
YYWW
*May be part of top marking
HV20220 FG
Top Marking
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
YY = Year Sealed WW = Week Sealed L = Lot Number Bottom Marking C = Country of Origin* A = Assembler ID* = "Green" Packaging CCCCCCCCCCC
YYWW
HV20220PJ
LLLLLLLLLL
AAA
*May be part of top marking
HV20220 PJ
Operating Conditions
Symbol Parameter VDD VPP VNN VIH VIL VSIG TA Logic power supply voltage 1,3 positive high voltage supply 1,3 negative high voltage supply High level input voltage Low-level input voltage Analog signal voltage peak-to-peak Operating free air temperature
1,3
Top Marking
Value 4.5V to 13.2V 40V to VNN +200V -40V to -160V VDD -1.5V to VDD 0V to 1.5V VNN +10V to VPP -10V 2 0OC to 70OC
YY = Year Sealed WW = Week Sealed L = Lot Number Bottom Marking C = Country of Origin* A = Assembler ID* = "Green" Packaging CCCCCCCCCCC
YYWW
HV20320PJ
LLLLLLLLLL
AAA
*May be part of top marking
HV20320 PJ
Top Marking
Notes: 1. Power up/down sequence is arbtrary except GND must be powered -up first and powered down last. 2. VSIG must be VNN VSIG VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec.
YYWW HV220GA LLLLLLLLL
YY = Year Sealed WW = Week Sealed L = Lot Number = "Green" Packaging
HV20220 GA
2
HV220/HV20220/HV20320
DC Electrical Characteristics
(Over operating conditions unless otherwise specified )
0OC Sym Parameter Min RONS Small signal switch on-resistance RONS RONL ISOL VOS IPPQ INNQ IPPQ INNQ ISW fSW Small signal switch on-resistance matching Large signal switch on-resistance Switch off leakage per switch DC offset switch off DC offset switch on Quiescent VPP supply current Quiescent VNN supply current Quiescent VPP supply current Quiescent VNN supply current Switch output peak current Output switching frequency IPP Supply current INN Supply curent IDD IDDQ ISOR ISINK CIN Logic supply average current Logic supply Quiescent current Data out source current Data out sink current Logic input capacitance 0.45 0.45 Max 30 25 25 18 23 22 20 5.0 300 500 3.0 6.5 4.0 4.0 6.5 4.0 4.0 4.0 10 10 Min 0.45 0.45 -
+25OC Typ 26 22 22 18 20 16 5.0 15 1.0 100 100 10 -10 10 -10 3.0 0.70 0.70 Max 38 27 27 24 25 25 20 10 300 500 50 -50 50 -50 2.0 50 7.0 5.0 5.0 7.0 5.0 5.0 4.0 10 10
+70OC Units Min 0.40 0.40 Max 48 32 30 27 30 27 20 15 300 500 2.0 8.0 5.5 5.5 8.0 5.5 5.5 4.0 10 10 mA A mA mA pF mA mA % A mV mV A A A A A kHz ISIG = 5mA ISIG = 200mA ISIG = 5mA ISIG = 200mA ISIG = 5mA ISIG = 200mA VPP = +40V VNN = -160V VPP = +100V VNN = -100V VPP = +160V VNN = -40V Conditions
ISIG = 5.0mA, VPP = +100V, VNN = - 100V VSIG = VPP -10V, ISIG = 1.0A VSIG = VPP -10V, VNN +10V RL = 100 RL = 100k All switches off All switches off All switches on, ISW = 5.0mA All switches on, ISW = 5.0mA VSIG duty cycly < 0.1% Duty cycle = 50% VPP = +40V VNN = -160V VPP = +100V VNN = -100V VPP = +160V VNN = -40V VPP = +40V VNN = -160V VPP = +100V VNN = -100V VPP = +160V VNN = -40V fCLK = 5.0MHz, VDD = 5.0V --VOUT = VDD -0.7V VOUT = 0.7V --All output switches are turning On and Off at 50kHz with no load
3
HV220/HV20220/HV20320
AC Electrical Characteristics
(Over recommended operating conditions: VDD = 5.0V, unless otherwise specified)
0OC Sym tSD tWLE tDO tWCL tSU tH fCLK tR, tF tON tOFF dv/dt Parameter Min Set up time before LE rises Time width of LE Clock delay time to data out Time width of CL Set up time data to clock Hold time data from clock Clock frequency Clock rise and fall times Turn on time Turn off time 150 15 35 5.0 50 5.0 5.0 20 Maximun VSIG slew rate -30 -58 -60 300 5.0 25 Output voltage spike QC Charge injection 17 50 5.0 25 20 20 KO KCR IID CSG(OFF) CSG(ON) +VSPK -VSPK +VSPK -VSPK +VSPK -VSPK Off isolation Switch crosstalk Output switch isolation diode current Off capacitance SW to GND On capacitance SW to GND -30 -58 -60 150 150 150 150 15 35 Max Min 150 150
+25OC Typ Max
+70OC Units Min 150 150 150 150 150 Max ns ns ns ns ns ns 5.0 50 5.0 5.0 20 20 20 -30 -58 dB dB 300 5.0 25 17 50 pC mV mA pF pF V/ns MHz ns s s ------------50% Duty cycle, fDATA= fCLK/2 --VSIG = VPP -10V, RLOAD = 10k VSIG = VPP -10V, RLOAD = 10k VPP = +160V, VNN = -40V VPP = +100V, VNN = -100V VPP = +40V, VNN = -160V f = 5.0MHz, 1k/15pF load f = 5.0MHz, 50 load f = 5.0MHz, 50 load 300ns pulse width, 2.0% duty cycle 0V, f = 1.0MHz 0V, f = 1.0MHz VPP = +40V, VNN = -160V, RLOAD = 50 VPP = +100V, VNN = -100V, RLOAD = 50 VPP = +160V, VNN = -40V, RLOAD = 50 VPP = +40V, VNN = -160V, VSIG = 0V VPP = +100V, VNN = -100V, VSIG = 0V VPP = +160V, VNN = -40V, VSIG = 0V Conditions
8.0
20 35 5.0 50 5.0 5.0 20 20 20
-33
-70 300 12 38 820 600 350 17 50 150 150 150 150 150 150 -
-60
4
HV220/HV20220/HV20320
Truth Table
D0 L H L H L H L H L H L H L H L H X X X X X X X X X X X X X X X X D1 D2 D3 D4 D5 D6 D7 LE L L L L L L L L L L L L L L L L H X CLR L L L L L L L L L L L L L L L L L H Hold Previous State All Switches Off SW0 Off On Off On Off On Off On Off On Off On Off On Off On SW1 SW2 SW3 SW4 SW5 SW6 SW7
Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch. 4. DOUT is high when data in the shift register 7 is high. 5. Shift register clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs.
Logic Timing Waveforms
DN+1 DATA IN LE
50% 50% t WLE t SD 50%
D
N
DN-1
50%
CLOCK
50% t SU t t h 50%
DD
DATA OUT
50% t t ON
OFF
VOUT OFF
(TYP)
90%
ON
10%
50%
50%
CLR
t WCL
5
HV220/HV20220/HV20320
Test Circuits
VPP -10V RL 10K
VPP -10V
ISOL
VOUT
VOUT
VNN +10V
100K
RL
VPP VNN
VPP VNN
VDD
GND
5V
VPP VNN
VPP VNN
VDD
GND
5V
VPP
VNN
VPP VNN
VDD
GND
5V
Switch OFF Leakage
DC Offset ON/OFF
TON /TOFF Test Circuit
VIN = 10 VP-P @5MHz
VSIG
VOUT RL
VIN = 10 VP-P @5MHz
IID
VNN
50 NC
50
VPP VNN
VPP VNN
VDD GND
5V
VPP VNN
VPP VNN
VDD
GND
5V
VPP VNN
VPP VNN
VDD GND
5V
KO = 20Log
VOUT VIN
KCR = 20Log
VOUT VIN
OFF Isolation
Isolation Diode Current
Crosstalk
VOUT
VOUT
+VSPK
VOUT
-V SPK
50
1000pF
VSIG
1K RL
VPP VNN
VPP VNN
VDD
GND
5V
VPP VNN
VPP VNN
VDD
GND
5V
Q = 1000pF x VOUT
Charge Injection
Output Voltage Spike
6
HV220/HV20220/HV20320
Typical Performance Curves
IDD vs Clock Frequency VDD = 5.0V, VPP/VNN = 100V, TA = 0C to 70C
3.0 -80.0
Off-Isolation vs. Signal Voltage Frequency
VDD = 5.0V, VPP/VNN = 100V
-75.0 TA = 70C
Off-Isolation (dB)
TA = 0C
IDD Current (mA)
2.0
-70.0
-65.0
1.0
-60.0
-55.0
0.0 10 100 1000 10000
-50.0 1.0 10.0
CLK Frequency (KHz) RON vs. Ambient Temperature TA
VDD = 5.0V, VPP/VNN = 100V 40.0 50.0
Signal Voltage Frequency (MHz) RON vs. VPP/VNN
VDD = 5.0V
ISW = 5mA 30.0
TA = 125C 40.0
RON (ohms) @5mA
TA = 85C 30.0
RON (ohms)
20.0 ISW = 200mA 10.0
TA = 25C 20.0 TA = 0C 10.0
0 -50 -25 0 25 50 75 100 125 150
0 VPP 40V VNN -160V 60V -140V 80V -120V 100V -100V 120V -80V 140V -60V 160V -40V
Ambient Temperature (oC) TDO vs. Ambient Temperature TA
VPP/VNN = 100V 100 VDD = 5.0V 80
IPP/INN vs. Output Switching Frequency
VDD = 5.0V, VPP/VNN = 100V 5 TA = 0oC
IPP/INN Average Current (mA)
TA = 25oC 4 TA = 70oC TA = 125oC 3
TDO (ns)
60 VDD = 13.5V 40
2
20
1
0 -50 -25 0 25 50 75 100 125
0 0 25 50 75 100 125 150
Ambient Temp TA (C)
Output Switching Frequency (KHz)
7
HV220/HV20220/HV20320
Pin Description (HV220GA)
Ball Location A3 B2 B3 B4 B5 B6 C1 C2 C3 C4 C5 C6 C7 D1 D2 D3 D4 D5 D6 E2 E3 E4 E5 E6 F3 Function SW1 SW2 SW1 SW0 SW0 VNN SW3 SW3 SW2 VPP GND DIN VDD SW4 SW4 SW5 SW7 LE CLK SW5 SW6 SW7 DOUT CLR SW6
Pin Description (48-Lead FG)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Function SW5 N/C SW4 N/C SW4 N/C N/C SW3 N/C SW3 N/C SW2 N/C SW2 N/C SW1 N/C SW1 N/C SW0 N/C SW0 N/C VPP Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Function VNN N/C N/C GND VDD N/C N/C N/C DIN CLK LE CLR DOUT N/C SW7 N/C SW7 N/C SW6 N/C SW6 N/C SW5 N/C
Pin Description (HV20220PJ)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Function SW3 SW3 SW2 SW2 SW1 SW1 SW0 SW0 N/C VPP N/C VNN GND VDD Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function N/C DIN CLK LE CL DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4
Pin Description (HV20320PJ)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Function SW3 SW3 SW2 SW2 SW1 SW1 SW0 SW0 VPP VNN N/C GND VDD N/C Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function N/C DIN CLK LE CL DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4
8
HV220/HV20220/HV20320
48-Lead LQFP Package Outline (FG)
7x7mm body, 1.4mm height (min), 0.50mm pitch
D D1
E
E1 Note 1 (Index Area D1/4 x E1/4) L2 48 1 b e L L1 Seating Plane Gauge Plane
Top View
View B A A2 Seating Plane A1
View B
Side View
Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (mm) NOM MAX
Drawings not to scale.
A 1.40 1.60
A1 0.05 0.15
A2 1.35 1.40 1.45
b 0.17 0.22 0.27
D 8.80 9.00 9.20
D1 6.80 7.00 7.20
E 8.80 9.00 9.20
E1 6.80 7.00 7.20
e 0.50 BSC
L 0.45 0.60 0.75
L1 1.00 REF
L2 0.25 BSC
0O 3.5O 7O
JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001.
9
HV220/HV20220/HV20320
HV220GA 25-Ball fpBGA (GA)
Top View
Bottom View
Enlarged Side View
Note: All dimensions are in millimeters
10
HV220/HV20220/HV20320
28-Lead PLCC Package Outline (PJ)
.048/.042 x 45O 4 D D1 1 .056/.042 x 45O 28 26
.150 MAX
Note 1 (Index Area) .075 MAX E1 E
.020 MAX 3 Places
Top View
View B b1 A A1 A2 e Base Plane .020 MIN Seating Plane b
Side View
View B
Note 1: A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (inches) NOM MAX
A .165 .172 .180
A1 .090 .105 .120
A2 .062 .083
b .013 .021
D .485 .490 .495
D1 .450 .453 .456
E .485 .490 .495
E1 .450 .453 .456
e .050 BSC
JEDEC Registration MS-018, Variation AB, Issue A, June, 1993. Drawings not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP - HV220_HV20220_HV20320 C073107
11

▲Up To Search▲

Price & Availability of HV22007

	To Download HV22007 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .