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CAT4016 16-Channel Constant Current LED Driver
Description
The CAT4016 is a 16 channel constant current driver for LED billboard and other general display applications. LED channel currents are programmed together via an external RSET resistor. Low output voltage operation on the LED channels as low as 0.4 V (for 2 to 100 mA LED current) allows for more power efficient designs. A high-speed 4-wire serial interface of up to 25 MHz clock frequency controls each individual channel using a shift register and latch configuration. A serial output data pin (SOUT) allows multiple devices to be cascaded and programmed via one serial interface. The device also includes a blanking control pin (BLANK) that can be used to disable all channels independently of the interface. Thermal shutdown protection is incorporated in the device to disable the LED outputs if the die temperature exceeds a set limit. The device is available in the 24-lead SOIC, TSSOP, QSOP and the compact TQFN 4 x 4 mm packages.
Features
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SOIC-24 W SUFFIX CASE 751BK
TSSOP-24 Y SUFFIX CASE 948AR
QSOP-24 VS, VSR SUFFIX CASE 492AB
TQFN-24 HV6 SUFFIX CASE 510AM
* * * * * * * * *
MARKING DIAGRAMS (Top Views)
SOIC-24 A3B CAT4016WO FYMXXXX CAT4016W = CAT4016W-T1 TSSOP-24 OAB CAT4016YO 3YMXXX CAT4016Y = CAT4016Y-T2 4016VSR 3YYWWB 4016VSR = CAT4016VSR-T2 TQFN-24 LAAD AXXX YMCC LAAD = CAT4016HV6-GT2
16 Constant Current-sink Channels Serial Interface up to 25 MHz Clock Frequency 3 V to 5.5 V Logic Supply LED Current Range from 2 mA to 100 mA LED Current set by External RSET Resistor 300 mV LED Dropout at 30 mA Thermal Shutdown Protection Available in 24-lead SOIC, TSSOP, QSOP, and 4 x 4 mm TQFN Packages These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant Billboard Display Marquee Display Instrument Display General Purpose Display
4016VS 3YYWWB 4016VS = CAT4016VS-T2 LAAA AXXX YMCC LAAA = CAT4016HV6-T2
QSOP-24
Applications
* * * *
A = Assembly Location 3 = Lead Finish - Matte-Tin B = Product Revision (Fixed as "B") O = Leave Blank F = Fab Code Y or YY = Production Year (Last 1 or 2 Digits) M = Production Month (1-9, A, B, C) WW = Production Week (01 - 52) CC = Country Code (Last Two Digits) XXX or XXXX = Last 3 or 4 Digits XXX or XXXX = of Assembly Lot Number
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2010
April, 2010 - Rev. 4
1
Publication Order Number: CAT4016/D
CAT4016
VDD RSET SOUT BLANK LED16 LED15 1 GND SIN CLK LATCH LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 24-Lead TQFN (HV6) 20 mA LED16 SOUT RSET GND 3 kW to next device Rating 6 -0.3 V to VDD+0.3 V 6 150 -55 to +160 -40 to +150 300 LED14 LED13 LED12 LED11 LED10 LED9
PIN CONNECTIONS
GND SIN CLK LATCH LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 1 VDD RSET SOUT BLANK LED16 LED15 LED14 LED13 LED12 LED11 LED10 LED9 1
LED15 LED16 BLANK SOUT RSET VDD GND SIN CLK LATCH LED1 LED2
LED14 LED13 LED12 LED11 LED10 LED9 LED8 LED7 LED6 LED5 LED4 LED3
24-Lead SOIC (W), TSSOP (Y), QSOP (VS)
24-Lead QSOP (VSR) (Top Views)
VIN 3 V to 5.5 V
1 mF VDD LED1 LED2
CONTROLLER
BLANK LATCH SIN CLK CAT4016
Figure 1. Typical Application Circuit
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter VDD Supply Voltage Logic input/output voltage (SIN, SOUT, CLK, BLANK, LATCH) LEDn voltage DC output current on LED1 to LED16 Storage Temperature Range Junction Temperature Range Lead Soldering Temperature (10 sec.) Units V V V mA _C _C _C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 2. RECOMMENDED OPERATING CONDITIONS
Parameter VDD Voltage applied to LED1 to LED16 LED current RSET control range Ambient Temperature Range Range 3.0 to 5.5 0.4 to 5.5 up to 100 -40 to +85 Units V V mA _C
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Table 3. ELECTRICAL OPERATING CHARACTERISTICS
Symbol DC CHARACTERISTICS ILED-ACC LED Current (any channel) VLED = 1 V, RSET = 3 kW VLED = 1 V, RSET = 1.5 kW VLED = 1 V, RSET = 750 W ILED-MAT LED Current Matching (ILED - ILEDAVR) / ILEDAVR VLED = 1 V, RSET = 3 kW VLED = 1 V, RSET = 1.5 kW VLED = 1 V, RSET = 750 W IVDD IVLED IDDOFF IDDON ILKG RLATCH RBLANK VIH VIL VHYS IIL VOH VOL VRSET TSD THYST LED current regulation vs. VDD LED current regulation vs. VLED Supply Current (all outputs off) VDD within 4.5 V and 5.5 V LED current 30 mA VLED within 1 V and 3 V LED current 30 mA RSET = 3 kW RSET = 750 W Supply Current (all outputs on) RSET = 3 kW RSET = 750 W LEDn output Leakage LATCH Pull-down Resistance BLANK Pull-up Resistance Logic high input voltage Logic low input voltage Logic input hysteresis voltage Logic Input leakage current (CLK, SIN) SOUT logic high output voltage SOUT logic low output voltage RSET Regulated Voltage Thermal Shutdown Thermal Hysteresis VI = VDD or GND IOH = -1 mA IOL = 1 mA -5 VCC-0.3 V 0.3 1.17 1.20 160 20 1.23 V C C VLED = 5 V, outputs off -1 100 100 0.7xVDD 0.3xVDD 0.1xVDD 0 5 V mA V 180 180 -6.0 18 36 20 40 80 1.5 1.5 2.0 0.1 0.05 3 8.5 4 10 1 300 300 mA kW kW V 9 mA 8 %/V %/V mA +6.0 % 22 44 mA Name (VDD = 5.0 V, TAMB = 25C, over recommended operating conditions unless specified otherwise.) Conditions Min Typ Max Units
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Table 4. TIMING CHARACTERISTICS
(For 3.0 V VDD 5.5 V, TAMB = 25C, unless specified otherwise.) Symbol CLK fclk tcwh tcwl SIN tssu tsh LATCH tlwh Tlh Tlsu LEDn tld tls tlst tbd tlr tlf LED1 Propagation delay LED Propagation delay stagger LED Propagation delay stagger total BLANK Propagation delay LED rise time (10% to 90%) LED fall time (90% to 10%) LATCH to LED1 off/on LED(n) to LED(n+1) LED1 to LED16 BLANK to LED(n) off/on Pull-up resistor = 50 W to 3.0 V Pull-up resistor = 50 W to 3.0 V 40 17 250 60 40 30 300 200 250 300 40 ns ns ns ns ns ns LATCH Pulse width Hold time LATCH to CLK Setup time LATCH to CLK Channel Stagger Delay 20 4 800 ns ns ns Setup time SIN to CLK Hold time SIN to CLK 4 4 ns ns CLK Clock Frequency CLK Pulse Width High CLK Pulse Width Low 20 20 25 MHz ns ns Name Conditions Min (Note 1) Typ (Note 2) Max (Note 1) Units
SOUT
tor tof tod SOUT rise time (10% to 90%) SOUT fall time (90% to 10%) Propagation delay time SOUT CL = 15 pF CL = 15 pF CLK to SOUT 8 5 5 15 25 ns ns ns
1. All min and max values are guaranteed by design. 2. VDD = 5 V, LED current 30 mA.
VDD
1 mF
VDD LED1 CONTROLLER BLANK LATCH SIN CLK RSET RSET GND CAT4016 LED16 SOUT
Rp
50 W
Rp
50 W V1 Cl 15 pF 3V
Figure 2. Test Circuit for AC Characteristics
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1/fclk CLK tssu SIN tod SOUT tlh LATCH tlwh tlsu tsh tcwl tcwh
Figure 3. Serial Input Timing Diagram
tld LATCH tbd BLANK tls LED1
LED2 tlst = 15 tls LED16
Figure 4. LED Output Timing Diagram
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TYPICAL PERFORMANCE CHARACTERISTICS
(VDD = 5.0 V, LED current 30 mA, all LEDs On, TAMB = 25C unless otherwise specified.) 70 60 SUPPLY CURRENT (mA) LED CURRENT (mA) 50 40 30 20 10 0 0 0.3 0.6 0.9 1.2 1.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 ALL LED's OFF ALL LED's ON
3.0
3.5
4.0 VDD (V)
4.5
5.0
5.5
LED PIN (V)
Figure 5. LED Current vs. LED Pin Voltage
31.5 31.0 LED CURRENT (mA) 30.5 30.0 29.5 29.0 28.5 12 10 8
Figure 6. Supply Current vs. VDD Pin Voltage
SUPPLY CURRENT (mA)
ALL LED's ON 6 4 2 0 ALL LED's OFF
3.0
3.5
4.0 VDD (V)
4.5
5.0
5.5
0
0.5
1.0 RSET CURRENT (mA)
1.5
2.0
Figure 7. LED Current vs. VDD Pin Voltage
1.30 100 80 LED CURRENT (mA) 60 40 20 0
Figure 8. Supply Current vs. RSET Current
1.25 RSET PIN (V)
1.20
1.15
1.10
3.0
3.5
4.0 VDD (V)
4.5
5.0
5.5
0.1
1 RSET (kW)
10
100
Figure 9. RSET Voltage vs. VDD Pin Voltage
Figure 10. LED Current vs. RSET Resistor
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CAT4016
TYPICAL PERFORMANCE CHARACTERISTICS
(VDD = 5.0 V, LED current 30 mA, all LEDs On, TAMB = 25C unless otherwise specified.) 1.30 31.5 31.0 LED CURRENT (mA) 1.25 RSET PIN (V) 30.5 30.0 29.5 29.0 1.10 -50 28.5 -50
1.20
1.15
0
50 TEMPERATURE (C)
100
150
0
50 TEMPERATURE (C)
100
150
Figure 11. RSET Voltage vs. Temperature
30 PULL-DOWN CURRENT (mA) PULL-UP CURRENT (mA) 25 20 15 10 5 0 30 25 20 15 10 5 0
Figure 12. LED Current vs. Temperature
0
1
2
3
4
5
0
1
2
3
4
5
LATCH VOLTAGE (V)
BLANK VOLTAGE (V)
Figure 13. Internal Pull-Down Current (LATCH Pin)
100 80 DUTY CYCLE (%) 60 40 20 0
Figure 14. Internal Pull-Up Current (BLANK Pin)
0
5
10
15
20
25
30
LED CURRENT (mA)
Figure 15. PWM Dimming on BLANK Pin (f = 10 kHz)
Figure 16. BLANK Transient Response
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Table 5. PIN DESCRIPTION
Name GND SIN CLK LATCH LED1-LED16 BLANK SOUT RSET VDD TAB (TQFN package only) Ground Serial data input pin Serial clock input pin Latch serial data to output registers LED channel 1 to 16 cathode terminals Enable / disable all channels Serial data output pin. LED current set pin Positive supply Voltage Connect to GND on the PCB Function
Pin Function GND is the ground reference pin for the device. This pin must be connected to the ground plane on the PCB. SIN is the serial data input. Data is loaded into the internal register on each rising edge of CLK. CLK is the serial clock input. On each rising CLK edge, data is transferred from SIN to the internal 16-bit serial shift register. LATCH is the latch data input. On the rising edge of LATCH, data is loaded from the 16-bit serial shift register into the output register latch. On the falling edge, this data is latched in the output register and isolated from the state of the serial shift register. LED1 - LED16 are the LED current sink channels. These pins are connected to the LED cathodes. The current sinks drive the LEDs with a current equal to 50 times RSET pin current. For the LED sink to operate correctly, the voltage on the LED pin must be above 0.4 V.
BLANK is the LED channel enable and disable input pin. When low, LEDs are enabled according to the output latch register content. When high, all LEDs are off, while preserving the data in the output latch register. SOUT is the serial data output of the 16-bit serial shift register. This pin is used to cascade several devices on the serial bus. The SOUT pin is then connected to the SIN input of the next device on the serial bus to cascade. RSET is the LED current setting pin. A resistor is connected between this pin and ground. Each LED channel current is set to 50 times the current pulled out of the pin. The RSET pin voltage is regulated to 1.2 V. VDD is the positive supply pin voltage for the entire device. A small 1 mF ceramic is recommended close to pin.
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CAT4016
Block Diagram
LED1 LED2 LED3 VIN VDD + CURRENT SINKS LED16 + Current Setting 1.2 V Ref GND LATCH L1 L2 L3 LATCHES L16 RSET
BLANK
SIN CLK
S1
S2
S3
SHIFT REGISTER
S16
SOUT
Figure 17. CAT4016 Functional Block Diagram
Basic Operation The CAT4016 uses 16 tightly matched current sinks to accurately regulate the LED current in each channel. The external resistor, RSET, is used to set the LED channel current to 50 times the current in RSET.
LED current + 50 1.2 R SET
Pull-up and pull-down resistors are internally provided to set the state of the BLANK and LATCH pins to the off-state when not externally driven.
Serial Interface
Tight current regulation for all channels is possible over a wide range of input and LED voltages due to independent current sensing circuitry on each channel. The LED channels have a maximum dropout of 0.4 V for most current and supply voltage conditions. This helps improve the heat dissipation and efficiency of the LED driver. Upon power-up, an under-voltage lockout circuit clears all latches and shift registers and sets all outputs to off. Once the under-voltage lockout threshold has been reached the device can be programmed. The driver delays the activation of each consecutive LED output channel by 17 ns (typical). Relative to LED1, LED2 is delayed by 17 ns, LED3 by 34 ns and LED16 by 250 ns typical. The delay is introduced when LATCH is activated. The delay minimizes the inrush current on the LED supply by staggering the turn on and off current spikes over a period of time and therefore allowing usage of smaller bypass capacitors.
A high-speed serial 4-wire interface is provided to program the state of each LED on or off. The interface contains a 16-bit serial to parallel shift register (S1-S16) and a 16-bit latch (L1-L16). Programming the serial to parallel register is accomplished via SIN and CLK input pins. On each rising edge of the CLK signal, the data from SIN is moved through the shift register serially. Data is also moved out of SOUT which can be connected to a next device if programming more than one device on the same interface. On the rising edge of LATCH, the data contents of the serial to parallel shift register is reflected in the latches. On the falling edge of LATCH, the state of the serial to parallel register at that particular time is saved in the latches and does not change irrespective of the contents of the serial to parallel register. BLANK is used to disable all LEDs (turn off) simultaneously while maintaining the same data in the latch register. When low, the LED outputs reflect the data in the latches. When high, all outputs are high impedance (zero current).
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PACKAGE DIMENSIONS
SOIC-24, 300 mils CASE 751BK-01 ISSUE O
SYMBOL
A A1 A2 b E1 E c D E E1 e h b PIN#1 IDENTIFICATION TOP VIEW e L 0.25 0.40
MIN
2.35 0.10 2.05 0.31 0.20 15.20 10.11 7.34
NOM
MAX
2.65 0.30 2.55 0.51 0.33 15.40 10.51 7.60
1.27 BSC 0.75 1.27
1
0 5
8 15
D
h
h
q1
A
A2
q q1 END VIEW
A1 SIDE VIEW
L
c
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013.
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PACKAGE DIMENSIONS
TSSOP24, 4.4x7.8 CASE 948AR-01 ISSUE A
b
SYMBOL
A A1 A2 b c E1 E D E E1 e L L1
MIN
0.05 0.80 0.19 0.09 7.70 6.25 4.30 0.50
NOM
MAX
1.20 0.15 1.05 0.30 0.20
7.80 6.40 4.40 0.65 BSC 0.60 1.00 REF
7.90 6.55 4.50 0.70
0
8
e TOP VIEW
D c A2 A 1 L SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. END VIEW L1
A1
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PACKAGE DIMENSIONS
QSOP-24, 150 mils CASE 492AB-01 ISSUE O
D SYMBOL A A1 b c D E1 E E E1 e h L L2 0.28 0.41 0.254 BSC MIN 1.37 0.10 0.20 0.19 8.56 5.82 3.81 0.635 BSC 0.48 0.86 NOM MAX 1.73 0.25 0.30 0.25 8.74 6.19 3.98
1 2
e TOP VIEW q2 h b
0 7 BSC
8
A
q1 L END VIEW
A1 SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-137.
c
L2
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PACKAGE DIMENSIONS
TQFN24, 4x4 AR CASE 510AM-01 ISSUE O
D A DETAIL A
E
E2
PIN#1 ID PIN#1 INDEX AREA TOP VIEW D2 BOTTOM VIEW
A1 SIDE VIEW
SYMBOL A A1 A3 b D D2 E E2 e L
MIN 0.70 0.00 0.20 2.40 2.40 0.30
NOM 0.75 - 0.20 REF 0.25 4.00 BSC - 4.00 BSC - 0.50 BSC -
MAX 0.80 0.05 L 0.30 2.90 2.90 0.50 DETAIL A b e
A
Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-220. (3) Minimum space between leads and flag cannot be smaller than 0.15 mm.
FRONT VIEW
A3
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CAT4016
Example of Ordering Information (Note 4)
Prefix CAT Device # 4016 Suffix HV6 -G T2
Company ID (Optional)
Product Number 4016
Package W: SOIC Y: TSSOP VS: QSOP VSR: QSOP (Note 6) HV6: TQFN
Lead Finish G: NiPdAu Blank: Matte-Tin
Tape & Reel (Note 10) T: Tape & Reel 1: 1,000 / Reel (Note 7) 2: 2,000 / Reel
Table 6. ORDERING INFORMATION
Part Number CAT4016W-T1 CAT4016Y-T2 CAT4016VS-T2 CAT4016VSR-T2 CAT4016HV6-T2 CAT4016HV6-GT2 Package SOIC24 (Note 8) TSSOP24 (Note 8) QSOP24 (Note 8) QSOP24 (Note 8) TQFN24 (Note 8) TQFN24 (Note 9) Quantity per Reel 1,000 2,000 2,000 2,000 2,000 2,000 Package Marking CAT4016W CAT4016Y 4016VS 4016VSR LAAA LAAD
3. All packages are RoHS-compliant (Lead-free, Halogen-free). 4. The device used in the above example is a CAT4016HV6-GT2 (TQFN, NiPdAu, Tape & Reel, 2,000/Reel). 5. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 6. Different pin outs, see page 2. 7. SOIC package availability in 1,000/Reel. All other packages are 2,000/Reel. 8. Matte-Tin Plated Finish (RoHS-compliant). 9. NiPdAu Plated Finish (RoHS-compliant). 10. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CAT4016/D

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