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XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
JUNE 2009 REV. 1.0.1
GENERAL DESCRIPTION
The XRT86VX38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and Long-haul/Shorthual LIU integrated solution featuring R3 technology (Relayless, Reconfigurable, Redundancy) and BITS Timing element. The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86VX38 provides protection from power failures and hot swapping. The XRT86VX38 contains an integrated DS1/E1/J1 framer and LIU which provide DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications. Each framer has its own framing synchronizer and transmit-receive slip buffers. The slip buffers can be independently enabled or disabled as required and can be configured to frame to the common DS1/E1/J1 signal formats. Each Framer block contains its own Transmit and Receive T1/E1/J1 Framing function. There are 3 Transmit HDLC controllers per channel which encapsulate contents of the Transmit HDLC buffers into LAPD Message frames. There are 3 Receive HDLC controllers per channel which extract the
payload content of Receive LAPD Message frames from the incoming T1/E1/J1 data stream and write the contents into the Receive HDLC buffers. Each framer also contains a Transmit and Overhead Data Input port, which permits Data Link Terminal Equipment direct access to the outbound T1/E1/J1 frames. Likewise, a Receive Overhead output data port permits Data Link Terminal Equipment direct access to the Data Link bits of the inbound T1/E1/J1 frames. The XRT86VX38 fully meets all of the latest T1/E1/J1 specifications: ANSI T1/E1.107-1988, ANSI T1/ E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/ E1.408-1990, AT&T TR 62411 (12-90) TR54016, and ITU G-703, G.704, G706 and G.733, AT&T Pub. 43801, and ETS 300 011, 300 233, JT G.703, JT G.704, JT G706, I.431. Extensive test and diagnostic functions include Loop-backs, Boundary scan, Pseudo Random bit sequence (PRBS) test pattern generation, Performance Monitor, Bit Error Rate (BER) meter, forced error insertion, and LAPD unchannelized data payload processing according to ITU-T standard Q.921. Applications and Features (next page)
FIGURE 1. XRT86VX38 8-CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO
External Data Link Controller
Local PCM Highway
XRT86VX38
1 of 8-channels Tx Serial Data In
Tx Overhead In
Rx Overhead Out
1:2 Turns Ratio TTIP
2-Frame Slip Buffer Elastic Store
Tx Framer
Tx LIU Interface
TRING
Tx Serial Clock
LLB Rx Serial Data Out 2-Frame Slip Buffer Elastic Store Rx Framer
LB
RTIP 1:1 Turns Ratio
ST-BUS
Rx LIU Interface
RRING
Rx Serial Clock
PRBS Generator & Analyser
Performance Monitor
HDLC/LAPD Controllers
LIU & Loopback Control
RxLOS
8kHz sync OSC Signaling & Alarms JTAG DMA Interface
Line Side
Microprocessor Interface
Back Plane 1.544-16.384 Mbit/s
3
System (Terminal) Side
TxON Memory
INT
D[7:0]
A[14:0]
P Select
WR 4 ALE_AS RD RDY_DTACK
Intel/Motorola P Configuration , Control & Status Monitor
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION APPLICATIONS
REV. 1.0.1
High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems SONET/SDH terminal or Add/Drop multiplexers (ADMs) T1/E1/J1 add/drop multiplexers (MUX) Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1 BITS Timing Digital Access Cross-connect System (DACs) Digital Cross-connect Systems (DCS) Frame Relay Switches and Access Devices (FRADS) ISDN Primary Rate Interfaces (PRA) PBXs and PCM channel bank T3 channelized access concentrators and M13 MUX Wireless base stations ATM equipment with integrated DS1 interfaces Multichannel DS1 Test Equipment T1/E1/J1 Performance Monitoring Voice over packet gateways Routers
FEATURES
Supports Section 13 - Synchronization Interface in ITU G.703 for both Transmit and Receive Paths Supports SSM Synchronous Messaging Generation (BOC for T1, National Bits for E1) on the Transmit Path Supports SSM Synchronous Messaging Extraction (BOC for T1, National Bits for E1) on the Receive Path Supports BITS timing generation on the Transmit Outputs Supports BITS timing extraction from NRZ data on the Analog Receive Path DS-0 Monitoring on both Transmit and Receive Time Slots Supports SSM Synchronization Messaging per ANSI T1.101-1999 and ITU G.704 Supports a Customized Section 13 - Synchronization Interface in G.703 at 1.544MHz Independent, full duplex DS1 Tx and Rx Framer/LIUs Each channel has full featured Long-haul/Short-haul LIU Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz
asynchronous back plane connections with jitter and wander attenuation
Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 2-channel
multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus
Programmable output clocks for Fractional T1/E1/J1 Supports Channel Associated Signaling (CAS) Supports Common Channel Signalling (CCS) Supports ISDN Primary Rate Interface (ISDN PRI) signaling
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XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
Extracts and inserts robbed bit signaling (RBS) 3 Integrated HDLC controllers for transmit and receive, each controller having two 96-byte buffers (buffer 0 /
buffer 1)
HDLC Controllers Support SS7 Timeslot assignable HDLC V5.1 or V5.2 Interface Automatic Performance Report Generation (PMON Status) can be inserted into the transmit LAPD interface
every 1 second or for a single transmission
Supports SPRM and NPRM Alarm Indication Signal with Customer Installation signature (AIS-CI) Remote Alarm Indication with Customer Installation (RAI-CI) Gapped Clock interface mode for Transmit and Receive. Intel/Motorola and Power PC interfaces for configuration, control and status monitoring Parallel search algorithm for fast frame synchronization Wide choice of T1 framing structures: SF/D4, ESF, SLC(R)96, T1DM and N-Frame (non-signaling) Direct access to D and E channels for fast transmission of data link information Full BERT Controller for generation and detection on system and line side of the chip PRBS, QRSS, and Network Loop Code generation and detection Seven Independent, simultaneous Loop Code Detectors per Channel Programmable Interrupt output pin Supports programmed I/O and DMA modes of Read-Write access The framer block encodes and decodes the T1/E1/J1 Frame serial data Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms Detects OOF, LOF, LOS errors and COFA conditions Loopbacks: Local (LLB) and Line remote (LB) Facilitates Inverse Multiplexing for ATM Performance monitor with one second polling Boundary scan (IEEE 1149.1) JTAG test port Accepts external 8kHz Sync reference 1.8V Inner Core 3.3V CMOS operation with 5V tolerant inputs 256-pin fpBGA and 329-pin fpBGA package with -40C to +85C operation ORDERING INFORMATION
PART NUMBER XRT86VX38IB329 XRT86VX38IB256 PACKAGE 329 Fine Pitch Ball Grid Array 256 Fine Pitch Ball Grid Array OPERATING TEMPERATURE RANGE -40C to +85C -40C to +85C
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XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
329 BALL - FINE PITCH BALL GRID ARRAY (BOTTOM VIEW - SEE PIN LIST FOR DESCRIPTION)
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W
OOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOOOO OOOOOOO OOOOOOO OOOOOOO OOOOOOO OOOOOOO OOOOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO
OOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOO
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XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
256 BALL - FINE PITCH BALL GRID ARRAY (BOTTOM VIEW - SEE PIN LIST FOR DESCRIPTION)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T
OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO
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XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
LIST OF PARAGRAPHS
1.0 PIN LISTS .................................................................................................................................................6 2.0 PIN DESCRIPTIONS ..............................................................................................................................12
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XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
LIST OF FIGURES
Figure 1.: XRT86VX38 8-channel DS1 (T1/E1/J1) Framer/LIU Combo ............................................................................ 1 Figure 2.: ITU G.703 Pulse Template .............................................................................................................................. 43 Figure 3.: ITU G.703 Section 13 Synchronous Interface Pulse Template ....................................................................... 44 Figure 4.: DSX-1 Pulse Template (normalized amplitude) .............................................................................................. 45
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XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
LIST OF TABLES
Table 1:: 329 Ball List by Ball Number ............................................................................................................................... 6 Table 2:: 256 Ball List by Ball Number ............................................................................................................................... 9 Table 3:: Pin Description Structure .................................................................................................................................. 12 Table 4:: E1 Receiver Electrical Characteristics .............................................................................................................. 40 Table 5:: T1 Receiver Electrical Characteristics .............................................................................................................. 41 Table 6:: E1 Transmitter Electrical Characteristics .......................................................................................................... 41 Table 7:: E1 Transmit Return Loss Requirement ............................................................................................................. 42 Table 8:: T1 Transmitter Electrical Characteristics .......................................................................................................... 42 Table 9:: Transmit Pulse Mask Specification ................................................................................................................... 43 Table 10:: E1 Synchronous Interface Transmit Pulse Mask Specification ....................................................................... 44 Table 11:: DSX1 Interface Isolated pulse mask and corner points .................................................................................. 45 Table 12:: AC Electrical Characteristics ........................................................................................................................... 46
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XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 1: 329 BALL LIST BY BALL NUMBER
PIN B13 PIN NAME RXLOS1 TXMSYNC1 TXSIG1 RXSERCLK2 RXSER2 TXSIG2 RXSER3 RTIP0 RVDD0 GNDPLL VDDPLL18 VSS AGND aTEST MCLKIN TRST TCK RxSCLK0 RXSER1 RXSYNC1 RXCASYNC1 RXSYNC2 RXSIG2 TXSERCLK2 TXMSYNC2 RXCRCSYNC3 RRING0 RGND0 TTIP0 TVDD0 GNDPLL AVDD18
1.0 PIN LISTS TABLE 1: 329 BALL LIST BY BALL NUMBER
PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 PIN NAME VDD VDDPLL18 VSS DGND TDI VSS RXSIG0 RXSYNC0 TXSYNC0 TXSIG0 RXSERCLK1 VDD TXSYNC1 TXSER1 VSS RXCASYNC2 RXCRCSYNC2 RxSCLK2 VDD GNDPLL VDDPLL18 VDDPLL18 DVDD18 RXTSEL VDD TMS RXLOS0 VDD TXMSYNC0 TXSERCLK0 RXSIG1
TABLE 1: 329 BALL LIST BY BALL NUMBER
PIN D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 PIN NAME TDO RXSER0 RXSERCLK0 RXCRCSYNC0 TXSER0 RXCRCSYNC1 VDD18 TXSERCLK1 RXLOS2 TXSYNC2 TXSER2 RXSIG3 RXCASYNC3 RTIP1 RVDD1 TRING0 TGND0 ANALOG VDD18 VSS VDD18 VDD18 RXCASYNC0 VDD18 VDD18 VDD18 RxSCLK1 VDD18 VDD RXSYNC3 RXLOS3 TXSYNC3
TABLE 1: 329 BALL LIST BY BALL NUMBER
PIN F1 F2 F3 F4 F5 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 G7 G8 G9 G10 G11 G12 G13 G15 G16 G17 G18 G19 H1 H2 H3 H4 H5 PIN NAME RRING1 VSS TTIP1 TRING1 VDD VDD18 RXSERCLK3 RxSCLK3 TXSERCLK3 TXSER3 RVDD2 RGND1 TGND1 TVDD1 VDD18 VDD18 VSS VDD18 VSS VDD18 VSS VDD18 DATA7 TXMSYNC3 WR / R/W TXSIG3 CS RTIP2 RGND2 TRING2 TTIP2 VSS
B14 B15 B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D1 D2 D3 D4 D5 D6
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XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 1: 329 BALL LIST BY BALL NUMBER
PIN H7 H8 H9 H10 H11 H12 H13 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J7 J8 J9 J10 J11 J12 J13 J15 J16 J17 J18 J19 K1 K2 K3 PIN NAME VSS VSS VSS VSS VSS VSS VSS ADDR12 DATA6 ADDR14 DATA5 ADDR13 RRING2 RVDD3 TGND2 TVDD2 VDD18 VDD18 VSS VSS VSS VSS VSS VDD18 ADDR11 ADDR9 VDD INT DATA4 RTIP3 RGND3 TRING3
REV. 1.0.1
TABLE 1: 329 BALL LIST BY BALL NUMBER
PIN K4 K5 K7 K8 K9 K10 K11 K12 K13 K15 K16 K17 K18 K19 L1 L2 L3 L4 L5 L7 L8 L9 L10 L11 L12 L13 L15 L16 L17 L18 L19 M1 PIN NAME TTIP3 TVDD3 VSS VSS VSS VSS VSS VSS VSS ADDR8 DATA2 ALE / AS ADDR10 PTYPE2 RRING3 RVDD4 TTIP4 TRING4 TGND3 VDD18 VSS VSS VSS VSS VSS VDD18 VDD18 ADDR4 ADDR6 DATA3 ADDR7 RTIP4
TABLE 1: 329 BALL LIST BY BALL NUMBER
PIN M2 M3 M4 M5 M7 M8 M9 M10 M11 M12 M13 M15 M16 M17 M18 M19 N1 N2 N3 N4 N5 N7 N8 N9 N10 N11 N12 N13 N15 N16 N17 N18 PIN NAME RGND4 TGND4 TVDD4 VDD18 VSS VSS VSS VSS VSS VSS VSS ADDR3 RDY / DTACK ADDR1 ADDR2 ADDR5 RRING4 RVDD5 TTIP5 TRING5 TVDD5 VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS DATA0 RD / DS / WE PTYPE1
TABLE 1: 329 BALL LIST BY BALL NUMBER
PIN N19 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 T1 T2 PIN NAME ADDR0 RTIP5 VSS TGND5 RVDD6 TGND6 VDD18 VDD PTYPE0 PCLK DATA1 RRING5 RGND5 TVDD6 TRING6 TTIP6 VSS RXCRCSYNC7 TXMSYNC6 VDD18 VDD18 VDD VDD18 VDD VDD18 VDD REQ1 RXSERCLK4 VDD ACK1 RTIP6 RGND6
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XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 1: 329 BALL LIST BY BALL NUMBER
PIN U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5 W6 W7 W8 W9 PIN NAME TXMSYNC4 RXCASYNC4 RXSIG4 RXLOS4 VDD TGND7 RGND7 RESET E1OSCCLK TXMSYNC7 RXLOS7 RXSER7 TXSYNC6 RXCRCSYNC6 RXLOS6 RXSIG6 TXSER5 RXSER5 RXCASYNC5 TXSIG4 TXSERCLK4 RXSER4 RXCRCSYNC4 VSS RTIP7 RRING7 TXON T1OSCCLK TXSER7 TXSYNC7 TXSERCLK6 TXSER6
TABLE 1: 329 BALL LIST BY BALL NUMBER
PIN T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 PIN NAME TTIP7 TVDD7 8KEXTOSC VDD18 VDD RXSYNC7 RXCASYNC7 RXSYNC6 TXSERCLK5 RXSERCLK6 TXMSYNC5 RxSCLK5 RXSERCLK5 TXSYNC4 RXSYNC4 ACK0 REQ0 RRING6 RVDD7 TRING7 VDD TXSERCLK7 TXSIG7 RXSERCLK7 RxSCLK7 RXSIG7 TXSIG6 RxSCLK6 VSS TXSYNC5 RXSYNC5 RXLOS5
TABLE 1: 329 BALL LIST BY BALL NUMBER
PIN W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 PIN NAME RXCASYNC6 VDD RXSER6 TXSIG5 RXSIG5 VDD RXCRCSYNC5 TXSER4 RxSCLK4 VSS
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XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 2: 256 BALL LIST BY BALL NUMBER
PIN B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 PIN NAME RXSER3 RRING0 RGND0 TTIP0 GNDPLL AVDD18 DVDD18 aTEST TDI TXSYNC0 RXCRCSYNC1 RXLOS1 TXSER1 RXSERCLK2 RXCRCSYNC2 TXMSYNC2 RXSYNC3 RTIP1 RVDD1 TRING0 TVDD0 VDDPLL18 DGND TRST TCK TXMSYNC0 TXSERCLK0 RXCASYNC1 RxSCLK1 RXCASYNC2 TXSER2 RXSERCLK3
REV. 1.0.1
TABLE 2: 256 BALL LIST BY BALL NUMBER
PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 PIN NAME GNDPLL GNDPLL VDDPLL18 VDDPLL18 RxTSEL TMS RXLOS0 RXCRCSYNC0 RXCASYNC0 RXSERCLK1 RXSYNC1 TXMSYNC1 RXSYNC2 TXSYNC2 RxSCLK2 VDD RTIP0 RVDD0 VDDPLL18 ANALOG AGND TDO RXSER0 RXSERCLK0 RXSYNC0 RxSCLK0 RXSER1 TXSYNC1 TXSERCLK1 RXSER2 TXSERCLK2
TABLE 2: 256 BALL LIST BY BALL NUMBER
PIN D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 PIN NAME RXLOS3 RRING1 RGND1 TTIP1 TRING1 TGND0 MCLKIN VSS VDD VSS TXSER0 VDD RXCRCSYNC3 RXCASYNC3 TXMSYNC3 TXSYNC3 TXSERCLK3 RTIP2 RVDD2 TGND1 TVDD1 TVDD2 VSS VSS VDD18 VDD18 VDD18 RXLOS2 RxSCLK3 WR / R/W CS TXSER3
TABLE 2: 256 BALL LIST BY BALL NUMBER
PIN F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 PIN NAME ADDR13 RRING2 RGND2 TTIP2 TRING2 TGND2 VDD18 VSS VSS VSS VSS ADDR14 DATA6 DATA7 DATA5 VDD ADDR12 RTIP3 RVDD3 TTIP3 TRING3 TVDD3 VDD18 VSS VSS VSS VSS VDD18 PTYPE2 DATA4 ADDR10 INT
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XRT86VX38
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OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 2: 256 BALL LIST BY BALL NUMBER
PIN K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 PIN NAME ADDR5 RRING4 RGND4 TTIP5 TRING5 TGND5 8KEXTOSC VDD18 VDD18 VDD18 VDD18 ADDR3 DATA1 ADDR0 ADDR1 RD / DS / WE RDY / DTACK RTIP5 RVDD5 TTIP6 TRING6 TVDD6 VDD RxSCLK7 RXCASYNC7 VDD RXSERCLK6 TXSYNC5 PTYPE1 PTYPE0 DATA0 ACK1
TABLE 2: 256 BALL LIST BY BALL NUMBER
PIN H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 PIN NAME ADDR11 RRING3 RGND3 TTIP4 TRING4 TGND3 VDD18 VSS VSS VSS VSS VDD18 DATA3 ADDR9 ADDR8 ADDR7 ALE / AS RTIP4 RVDD4 TGND4 TVDD4 TVDD5 VDD18 VSS VSS VSS VSS VDD18 DATA2 ADDR4 ADDR6 ADDR2
TABLE 2: 256 BALL LIST BY BALL NUMBER
PIN M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 PIN NAME PCLK RRING5 RGND5 TGND6 TVDD7 TGND7 TXMSYNC7 RXCRCSYNC7 TXSYNC6 RXCASYNC6 TXSERCLK5 RXSYNC5 TXSER4 RXSYNC4 VDD ACK0 REQ0 RTIP6 RVDD6 TTIP7 TRING7 TXSER7 TXSERCLK7 RXLOS7 RXSER7 RxSCLK6 TXSER5 RXSER5 RXLOS5 TXMSYNC4 RXSERCLK4 RXSER4
TABLE 2: 256 BALL LIST BY BALL NUMBER
PIN P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 PIN NAME RXLOS4 RRING6 RGND6 RGND7 RESET E1OSCCLK RXSERCLK7 RXSYNC7 TXMSYNC6 RXCRCSYNC6 RXLOS6 TXMSYNC5 RXCASYNC5 RXCRCSYNC5 RXCASYNC4 RXCRCSYNC4 REQ1 RVDD7 RTIP7 RRING7 TXON T1OSCCLK TXSYNC7 TXSERCLK6 TXSER6 RXSYNC6 RXSER6 RxSCLK5 RXSERCLK5 TXSYNC4 TXSERCLK4 RxSCLK4
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XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 2: 256 BALL LIST BY BALL NUMBER
PIN T16 PIN NAME VDD
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XRT86VX38
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OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
2.0 PIN DESCRIPTIONS There are six types of pins defined throughout this pin description and the corresponding symbol is presented in table below. The per-channel pin is indicated by the channel number or the letter 'n' which is appended at the end of the signal name, for example, TxSERn, where "n" indicates channels 0 to 7. All output pins are "tristated" upon hardware RESET.
SYMBOL I O I/O GND PWR NC PIN TYPE Input Output Bidirectional Ground Power No Connect
The structure of the pin description is divided into eleven groups, as presented in the table below TABLE 3: PIN DESCRIPTION STRUCTURE
SECTION Transmit System Side Interface Receive System Side Interface Receive Line Interface Transmit Line Interface Timing Interface JTAG Interface Microprocessor Interface Power Pins (3.3V) Power Pins (1.8V) Ground Pins No Connect Pins PAGE NUMBER page 13 page 18 page 23 page 24 page 25 page 26 page 26 page 35 page 36 page 37 page 38
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XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME TxSER0/ TxPOS0 TxSER1/ TxPOS1 TxSER2/ TxPOS2 TxSER3/ TxPOS3 TxSER4/ TxPOS4 TxSER5/ TxPOS5 TxSER6/ TxPOS6 TxSER7/ TxPOS7 329 PKG 256 PKG BALL# BALL # D11 A14 D17 F19 W17 V13 W9 W6 E10 C12 D14 F15 N12 P10 T8 P5 TYPE I OUTPUT DRIVE(MA) DESCRIPTION Transmit Serial Data Input (TxSERn)/Transmit Positive Digital Input (TxPOSn): The exact function of these pins depends on the mode of operation selected, as described below. DS1/E1 Mode - TxSERn These pins function as the transmit serial data input on the system side interface, which are latched on the rising edge of the TxSERCLKn pin. Any payload data applied to this pin will be inserted into an outbound DS1/E1 frame and output to the line. In DS1 mode, the framing alignment bits, facility data link bits, CRC-6 bits, and signaling information can also be inserted from this input pin if configured appropriately. In E1 mode, all data intended to be transported via Time Slots 1 through 15 and Time slots 17 through 31 must be applied to this input pin. Data intended for Time Slots 0 and 16 can also be applied to this input pin If configured accordingly. DS1 or E1 High-Speed Multiplexed Mode* - TxSERn In this mode, these pins are used as the high-speed multiplexed data input pin on the system side. High-speed multiplexed data of channels 0-3 must be applied to TxSER0 and high-speed multiplexed data of channels 4-7 must be applied to TxSER4 in a byte or bit-interleaved way. The framer latches in the multiplexed data on TxSER0 and TxSER4 using TxMSYNC/TxINCLK and demultiplexes this data into 4 serial streams. The LIU block will then output the data to the line interface using TxSERCLKn. DS1 or E1 Framer Bypass Mode - TxPOSn In this mode, TxSERn is used for the positive digital input pin (TxPOSn) to the LIU. NOTE: 1. *High-speed multiplexed modes include (For T1/E1) 16.384MHz HMVIP, H.100, Bit-multiplexed modes, and (For T1 only) 12.352MHz Bit-multiplexed mode. 2. In DS1 high-speed modes, the DS-0 data is mapped into an E1 frame by ignoring every fourth time slot (don't care). 3. These 8 pins are internally pulled "High" for each channel.
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OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME TxSERCLK0/ TxLINECLK0 TxSERCLK1/ TxLINECLK1 TxSERCLK2/ TxLINECLK2 TxSERCLK3/ TxLINECLK3 TxSERCLK4/ TxLINECLK4 TxSERCLK5/ TxLINECLK5 TxSERCLK6/ TxLINECLK6 TxSERCLK7/ TxLINECLK7 329 PKG 256 PKG BALL# BALL # B11 D14 C17 F18 V17 T11 W8 U5 D10 B13 B15 E16 T14 N10 T7 P6 TYPE I/O OUTPUT DRIVE(MA) 12 DESCRIPTION Transmit Serial Clock (TxSERCLKn)/Transmit Line Clock (TxSERCLKn): The exact function of these pins depends on the mode of operation selected, as described below. In Base-Rate Mode (1.544MHz/2.048MHz) - TxSERCLKn: This clock signal is used by the transmit serial interface to latch the contents on the TxSERn pins into the T1/E1 framer on the rising edge of the TxSERCLKn. These pins can be configured as input or output as described below. When TxSERCLKn is configured as Input: These pins will be inputs if the TxSERCLK is chosen as the timing source for the transmit framer. Users must provide a 1.544MHz clock rate to this input pin for T1 mode of operation, and 2.048MHz clock rate in E1 mode. When TxSERCLKn is configured as Output: These pins will be outputs if either the recovered line clock or the MCLK PLL is chosen as the timing source for the T1/E1 transmit framer. The transmit framer will output a 1.544MHz clock rate in T1 mode of operation, and a 2.048MHz clock rate in E1 mode. DS1/E1 High-Speed Backplane Modes* - TxSERCLKn as INPUT ONLY In this mode, TxSERCLK is an optional clock signal input which is used as the timing source for the transmit line interface, and is only required if TxSERCLK is chosen as the timing source for the transmit framer. If TxSERCLK is chosen as the timing source, system equipment should provide 1.544MHz (For T1 mode) or 2.048MHz (For E1 mode) to the TxSERCLKn pins on each channel. TxSERCLK is not required if either the recovered clock or MCLK PLL is chosen as the timing source of the device. High speed or multiplexed data is latched into the device using the TxMSYNC/TxINCLK high-speed clock signal. DS1 or E1 Framer Bypass Mode - TxLINECLKn In this mode, TxSERCLKn is used as the transmit line clock (TxLINECLK) to the LIU. NOTE: *High-speed backplane modes include (For T1/E1) 2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP, H.100, Bit-multiplexed modes, and (For T1 only) 12.352MHz Bit-multiplexed mode.
NOTE: In DS1 high-speed modes, the DS-0 data is mapped into an E1 frame by ignoring every fourth time slot (don't care). NOTE: These 8 pins are internally pulled "High" for each channel.
14
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME TxSYNC0/ TxNEG0 TxSYNC1/ TxNEG1 TxSYNC2/ TxNEG2 TxSYNC3/ TxNEG3 TxSYNC4/ TxNEG4 TxSYNC5/ TxNEG5 TxSYNC6/ TxNEG6 TxSYNC7/ TxNEG7 329 PKG 256 PKG BALL# BALL # A9 A13 D16 E19 T16 U13 V9 W7 C9 B12 A14 E15 T13 M11 N8 T6 TYPE I/O OUTPUT DRIVE(MA) 12 DESCRIPTION Transmit Single Frame Sync Pulse (TxSYNCn) / Transmit Negative Digital Input (TxNEGn): The exact function of these pins depends on the mode of operation selected, as described below. DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) - TxSYNCn: These TxSYNCn pins are used to indicate the single frame boundary within an outbound T1/E1 frame. In both DS1 or E1 mode, the single frame boundary repeats every 125 microseconds (8kHz). In DS1/E1 base rate, TxSYNCn can be configured as either input or output as described below. When TxSYNCn is configured as an Input: Users must provide a signal which must pulse "High" for one period of TxSERCLK during the first bit of an outbound DS1/ E1 frame. It is imperative that the TxSYNC input signal be synchronized with the TxSERCLK input signal. When TxSYNCn is configured as an Output: The transmit T1/E1 framer will output a signal which pulses "High" for one period of TxSERCLK during the first bit of an outbound DS1/E1 frame. DS1/E1 High-Speed Backplane Modes* - TxSYNCn as INPUT ONLY: In this mode, TxSYNCn must be an input regardless of the clock source that is chosen to be the timing source for the transmit framer. In 2.048MVIP/4.096/8.192MHz high-speed modes, TxSYNCn pins must be pulsed 'High' for one period of TxSERCLK during the first bit of the outbound T1/E1 frame. In HMVIP mode, TxSYNC0 and TxSYNC4 must be pulsed 'High' for 4 clock cycles of the TxMSYNC/TxINCLK signal in the position of the first two and the last two bits of a multiplexed frame. In H.100 mode, TxSYNC0 and TxSYNC4 must be pulsed 'High' for 2 clock cycles of the TxMSYNC/TxINCLK signal in the position of the first and the last bit of a multiplexed frame. DS1 or E1 Framer Bypass Mode - TxNEGn In this mode, TxSYNCn is used as the negative digital input pin (TxNEG) to the LIU. NOTE: *High-speed backplane modes include (For T1/E1) 2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP, H.100, Bit-multiplexed modes, and (For T1 only) 12.352MHz Bit-multiplexed mode.
REV. 1.0.1
NOTE: In DS1 high-speed modes, the DS-0 data is mapped into an E1 frame by ignoring every fourth time slot (don't care). NOTE: These 8 pins are internally pulled "Low" for each channel.
15
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME TxMSYNC0/ TxINCLK0 TxMSYNC1/ TxINCLK1 TxMSYNC2/ TxINCLK2 TxMSYNC3/ TxINCLK3 TxMSYNC4/ TxINCLK4 TxMSYNC5/ TxINCLK5 TxMSYNC6/ TxINCLK6 TxMSYNC7/ TxINCLK7 329 PKG 256 PKG BALL# BALL # B10 B14 C18 G16 U16 T13 R8 V6 D9 A12 C15 E14 P13 R11 R8 N6 TYPE I/O OUTPUT DRIVE(MA) 12 DESCRIPTION Multiframe Sync Pulse (TxMSYNCn) / Transmit Input Clock (TxINCLKn) The exact function of these pins depends on the mode of operation selected, as described below. DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) - TxMSYNCn In this mode, these pins are used to indicate the multi-frame boundary within an outbound DS1/E1 frame. In DS1 ESF mode, TxMSYNCn repeats every 3ms. In DS1 SF mode, TxMSYNCn repeats every 1.5ms. In E1 mode, TxMSYNCn repeats every 2ms. If TxMSYNCn is configured as an input, TxMSYNCn must pulse "High" for one period of TxSERCLK during the first bit of an outbound DS1/E1 multi-frame. It is imperative that the TxMSYNC input signal be synchronized with the TxSERCLK input signal. If TxMSYNCn is configured as an output, the transmit section of the T1/E1 framer will output and pulse TxMSYNC "High" for one period of TxSERCLK during the first bit of an outbound DS1/E1 frame. DS1/E1 High-Speed Backplane Modes* - (TxINCLKn as INPUT ONLY) In this mode, this pin must be used as the high-speed input clock pin (TxINCLKn) for the backplane interface to latch in high-speed or multiplexed data on the TxSERn pin. The frequency of TxINCLK is presented in the table below. OPERATION MODE 2.048MVIP non-multiplexed 4.096MHz non-multiplexed 8.192MHz non-multiplexed 12.352MHz Bit-multiplexed (DS1 ONLY) 16.384MHz Bit-multiplexed 16.384 HMVIP Byte-multiplexed 16.384 H.100 Byte-multiplexed NOTES: 1. *High-speed backplane modes include (For T1/E1) 2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP, H.100, Bit-multiplexed modes, and (For T1 only) 12.352MHz Bit-multiplexed mode. 2. In DS1 high-speed modes, the DS-0 data is mapped into an E1 frame by ignoring every fourth time slot (don't care). 3. These 8 pins are internally pulled "Low" for each channel. FREQUENCY OF TXINCLK(MHZ) 2.048 4.096 8.192 12.352
16.384 16.384 16.384
16
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME TxSIG0 TxSIG1 TxSIG2 TxSIG3 TxSIG4 TxSIG5 TxSIG6 TxSIG7 329 PKG 256 PKG BALL# BALL # A10 B15 B18 G18 V16 W13 U10 U6 TYPE I/O OUTPUT DRIVE(MA) 8 DESCRIPTION Transmit Time Slot Octet Identifier Output 0 (TxCHNn_0) / Transmit Serial Signaling Input (TxSIGn): The exact function of these pins depends on whether or not the transmit framer enables the transmit fractional/signaling interface, as described below: If transmit fractional/signaling interface is disabled - No function If transmit fractional/signaling interface is enabled TxSIGn: These pins can be used to input robbed-bit signaling data to be inserted within an outbound DS1 frame or to input Channel Associated Signaling (CAS) data within an outbound E1 frame, as described below. T1 Mode: Signaling data (A,B,C,D) of each channel must be provided on bit 4,5,6,7 of each time slot on the TxSIG pin if 16code signaling is used. If 4-code signaling is selected, signaling data (A,B) of each channel must be provided on bit 4, 5 of each time slot on the TxSIG pin. If 2-code signaling is selected, signaling data (A) of each channel must be provided on bit 4 of each time slot on the TxSIG pin. E1 Mode: Signaling data in E1 mode can be provided on the TxSIGn pins on a time-slot-basis as in T1 mode, or it can be provided on time slot 16 only via the TxSIGn input pins. In the latter case, signaling data (A,B,C,D) of channel 1 and channel 17 must be inserted on the TxSIGn pin during time slot 16 of frame 1, signaling data (A,B,C,D) of channel 2 and channel 18 must be inserted on the TxSIGn pin during time slot 16 of frame 2...etc. The CAS multiframe Alignments bits (0000 bits) and the extra bits/alarm bit (xyxx) must be inserted on the TxSIGn pin during time slot 16 of frame 0. NOTE: Transmit fractional interface can be enabled by programming to bit 4 - TxFr1544/TxFr2048 bit from register 0xn120 to `1'. These 8 pins are internally pulled "Low" for each channel.
REV. 1.0.1
NOTE:
17
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME RxSYNC0/ RxNEG0 RxSYNC1/ RxNEG1 RxSYNC2/ RxNEG2 RxSYNC3/ RxNEG3 RxSYNC4/ RxNEG4 RxSYNC5/ RxNEG5 RxSYNC6/ RxNEG6 RxSYNC7/ RxNEG7 329 PKG BALL# A8 C13 C15 E17 T17 U14 T10 T8 256 PKG BALL # B9 A11 A13 C16 N13 N11 T9 R7 TYPE I/O OUTPUT DRIVE (MA) 12 DESCRIPTION Receive Single Frame Sync Pulse (RxSYNCn): The exact function of these pins depends on the mode of operation selected, as described below. DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) RxSYNCn: These RxSYNCn pins are used to indicate the single frame boundary within an inbound T1/E1 frame. In both DS1 or E1 mode, the single frame boundary repeats every 125 microseconds (8kHz). In DS1/E1 base rate, RxSYNCn can be configured as either input or output depending on the slip buffer configuration as described below. When RxSYNCn is configured as an Input: Users must provide a signal which must pulse "High" for one period of RxSERCLK and repeats every 125S. The receive serial Interface will output the first bit of an inbound DS1/E1 frame during the provided RxSYNC pulse. NOTE: It is imperative that the RxSYNC input signal be synchronized with the RxSERCLK input signal. When RxSYNCn is configured as an Output: The receive T1/E1 framer will output a signal which pulses "High" for one period of RxSERCLK during the first bit of an inbound DS1/E1 frame. DS1/E1 High-Speed Backplane Modes* - RxSYNCn as INPUT ONLY: In this mode, RxSYNCn must be an input regardless of the slip buffer configuration. In 2.048MVIP/4.096/ 8.192MHz high-speed modes, RxSYNCn pins must be pulsed 'High' for one period of RxSERCLK during the first bit of the inbound T1/E1 frame. In HMVIP mode, RxSYNCn must be pulsed 'High' for 4 clock cycles of the RxSERCLK signal in the position of the first two and the last two bits of a multiplexed frame. In H.100 mode, RxSYNCn must be pulsed 'High' for 2 clock cycles of the RxSERCLK signal in the position of the first and the last bit of a multiplexed frame. DS1 or E1 Framer Bypass Mode - RxNEGn In this mode, RxSYNCn is used as the Receive negative digital output pin (RxNEG) from the LIU. NOTE: *High-speed backplane modes include (For T1/ E1) 2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP, H.100, Bit-multiplexed modes, and (For T1 only) 12.352MHz Bitmultiplexed mode. NOTE: In DS1 high-speed modes, the DS-0 data is mapped into an E1 frame by ignoring every fourth time slot (don't care).
NOTE: These 8 pins are internally pulled "Low" for each channel.
18
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME RxCRCSYNC0 RxCRCSYNC1 RxCRCSYNC2 RxCRCSYNC3 RxCRCSYNC4 RxCRCSYNC5 RxCRCSYNC6 RxCRCSYNC7 RxCASYNC0 RxCASYNC1 RxCASYNC2 RxCASYNC3 RxCASYNC4 RxCASYNC5 RxCASYNC6 RxCASYNC7 329 PKG BALL# D10 D12 A17 C19 V19 W16 V10 R7 E10 C14 A16 D19 U17 V15 W10 T9 256 PKG BALL # A8 C10 C14 E12 R15 R13 R9 N7 A9 D11 D13 E13 R14 R12 N9 M8 TYPE O OUTPUT DRIVE (MA) 12 DESCRIPTION Receive Multiframe Sync Pulse (RxCRCSYNCn): The RxCRCSYNCn pins are used to indicate the receive multi-frame boundary. These pins pulse "High" for one period of RxSERCLK when the first bit of an inbound DS1/E1 Multi-frame is being output on the RxCRCSYNCn pin.
REV. 1.0.1
* In DS1 ESF mode, RxCRCSYNCn repeats every 3ms * In DS1 SF mode, RxCRCSYNCn repeats every 1.5ms * In E1 mode, RxCRCSYNCn repeats every 2ms.
O 12 Receive CAS Multiframe Sync Pulse (RxCASYNCn): - E1 Mode Only The RxCASYNCn pins are used to indicate the E1 CAS Multif-frame boundary. These pins pulse "High" for one period of RxSERCLK when the first bit of an E1 CAS Multi-frame is being output on the RxCASYNCn pin.
19
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME RxSERCLK0/ RxLINECLK0 RxSERCLK1/ RxLINECLK1 RxSERCLK2/ RxLINECLK2 RxSERCLK3/ RxLINECLK3 RxSERCLK4/ RxLINECLK4 RxSERCLK5/ RxLINECLK5 RxSERCLK6/ RxLINECLK6 RxSERCLK7/ RxLINECLK7 329 PKG BALL# D9 A11 B16 F16 R17 T15 T12 U7 256 PKG BALL # B8 A10 C13 D15 P14 T12 M10 R6 TYPE I/O OUTPUT DRIVE (MA) 12 DESCRIPTION Receive Serial Clock Signal (RxSERCLKn) / Receive Line Clock (RxLINECLKn): The exact function of these pins depends on the mode of operation selected, as described below. In Base-Rate Mode (1.544MHz/2.048MHz) - RxSERCLKn: These pins are used as the receive serial clock on the system side interface which can be configured as either input or output. The receive serial interface outputs data on RxSERn on the rising edge of RxSERCLKn. When RxSERCLKn is configured as Input: These pins will be inputs if the slip buffer on the Receive path is enabled. System side equipment must provide a 1.544MHz clock rate to this input pin for T1 mode of operation, and 2.048MHz clock rate in E1 mode. When RxSERCLKn is configured as Output: These pins will be outputs if slip buffer is bypassed. The receive framer will output a 1.544MHz clock rate in T1 mode of operation, and a 2.048MHz clock rate in E1 mode. DS1/E1 High-Speed Backplane Modes* - (RxSERCLK as INPUT ONLY) In this mode, this pin must be used as the high-speed input clock for the backplane interface to output highspeed or multiplexed data on the RxSERn pin. The frequency of RxSERCLK is presented in the table below. OPERATION MODE 2.048MVIP non-multiplexed 4.096MHz non-multiplexed 8.192MHz non-multiplexed 12.352MHz Bit-multiplexed (DS1 ONLY) 16.384MHz Bit-multiplexed 16.384 HMVIP Byte-multiplexed 16.384 H.100 Byte-multiplexed NOTES: 1. *High-speed backplane modes include (For T1/ E1) 2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP, H.100, Bit-multiplexed modes, and (For T1 only) 12.352MHz Bitmultiplexed mode. 2. For DS1 high-speed modes, the DS-0 data is mapped into an E1 frame by ignoring every fourth time slot (don't care). FREQUENCY OF RXSERCLK(MHZ) 2.048 4.096 8.192 12.352
16.384 16.384 16.384
20
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME RxSERCLK0/ RxLINECLK0 RxSERCLK1/ RxLINECLK1 RxSERCLK2/ RxLINECLK2 RxSERCLK3/ RxLINECLK3 RxSERCLK4/ RxLINECLK4 RxSERCLK5/ RxLINECLK5 RxSERCLK6/ RxLINECLK6 RxSERCLK7/ RxLINECLK7 RxSER0/ RxPOS0 RxSER1/ RxPOS1 RxSER2/ RxPOS2 RxSER3/ RxPOS3 RxSER4/ RxPOS4 RxSER5/ RxPOS5 RxSER6/ RxPOS6 RxSER7/ RxPOS7 329 PKG BALL# D9 A11 B16 F16 R17 T15 T12 U7 256 PKG BALL # B8 A10 C13 D15 P14 T12 M10 R6 NOTE: These 8 pins are internally pulled "High" for each channel. TYPE I/O OUTPUT DRIVE (MA) 12 DESCRIPTION (Continued) DS1 or E1 Framer Bypass Mode - RxLINECLKn In this mode, RxSERCLKn is used as the Receive Line Clock output pin (RxLineClk) from the LIU.
REV. 1.0.1
D8 C12 B17 B19 V18 V14 W12 V8
B7 B11 B14 B16 P15 P11 T10 P8
O
12
Receive Serial Data Output (RxSERn): The exact function of these pins depends on the mode of operation selected, as described below. DS1/E1 Mode - RxSERn These pins function as the receive serial data output on the system side interface, which are updated on the rising edge of the RxSERCLKn pin. All the framing alignment bits, facility data link bits, CRC bits, and signaling information will also be extracted to this output pin. DS1 or E1 High-Speed Multiplexed Mode* - RxSERn In this mode, these pins are used as the high-speed multiplexed data output pin on the system side. High-speed multiplexed data of channels 0-3 will output on RxSER0 and high-speed multiplexed data of channels 4-7 will output on RxSER4 in a byte or bit-interleaved way. The framer outputs the multiplexed data on RxSER0 and RxSER4 using the high-speed input clock (RxSERCLKn). DS1 or E1 Framer Bypass Mode In this mode, RxSERn is used as the positive digital output pin (RxPOSn) from the LIU. NOTE: *High-speed multiplexed modes include (For T1/ E1) 16.384MHz HMVIP, H.100, Bit-multiplexed modes, and (For T1 only) 12.352MHz Bitmultiplexed mode. NOTE: In DS1 high-speed modes, the DS-0 data is mapped into an E1 frame by ignoring every fourth time slot (don't care).
21
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME RxSig0 RxSig1 RxSig2 RxSig3 RxSig4 RxSig5 RxSig6 RxSig7 329 PKG BALL# A7 B12 C16 D18 U18 W14 V12 U9 256 PKG BALL # TYPE O OUTPUT DRIVE (MA) 8 DESCRIPTION Receive Serial Signaling Output (RxSIGn): The exact function of these pins depends on whether or not the receive framer enables the receive fractional/signaling interface, as described below: If receive fractional/signaling interface is disabled : -No function If receive fractional/signaling interface is enabled RxSIGn: These pins can be used to output robbed-bit signaling data within an inbound DS1 frame or to output Channel Associated Signaling (CAS) data within an inbound E1 frame, as described below. T1 Mode: Signaling data (A,B,C,D) of each channel will be output on bit 4,5,6,7 of each time slot on the RxSIG pin if 16-code signaling is used. If 4-code signaling is selected, signaling data (A,B) of each channel will be output on bit 4, 5 of each time slot on the RxSIG pin. If 2code signaling is selected, signaling data (A) of each channel will be output on bit 4 of each time slot on the RxSIG pin. E1 Mode: Signaling data in E1 mode will be output on the RxSIGn pins on a time-slot-basis as in T1 mode, or it can be output on time slot 16 only via the RxSIGn output pins. In the latter case, signaling data (A,B,C,D) of channel 1 and channel 17 will be output on the RxSIGn pin during time slot 16 of frame 1, signaling data (A,B,C,D) of channel 2 and channel 18 will be output on the RxSIGn pin during time slot 16 of frame 2...etc. The CAS multiframe Alignments bits (0000 bits) and the extra bits/alarm bit (xyxx) will be output on the RxSIGn pin during time slot 16 of frame 0. NOTE: Receive Fractional/signaling interface can be enabled by programming to bit 4 - RxFr1544/ RxFr2048 bit from register 0xn122 to `1'.
RxSCLK0 RxSCLK1 RxSCLK2 RxSCLK3 RxSCLK4 RxSCLK5 RxSCLK6 RxSCLK7
C11 E14 A18 F17 W18 T14 U11 U8
B10 D12 A15 F12 T15 T11 P9 M7
O
8
Receive Recovered Line Clock Output (RxSCLKn): The exact function of these pins depends on whether or not the receive framer enables the receive fractional/signaling interface, as described below: If receive fractional/signaling interface is disabled -No function If receive fractional/signaling interface is enabled Receive Recovered Line Clock Output (RxSCLKn): These pins output the recovered T1/E1 line clock (1.544MHz in T1 mode and 2.048MHz in E1 mode) for each channel. NOTE: Receive Fractional/Signaling interface can be enabled by programming to bit 4 - RxFr1544/ RxFr2048 bit from register 0xn122 to `1'.
22
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION RECEIVE LINE INTERFACE
SIGNAL NAME RTIP0 RTIP1 RTIP2 RTIP3 RTIP4 RTIP5 RTIP6 RTIP7 329 PKG BALL# C1 E1 H1 K1 M1 P1 T1 W2 256 PKG BALL # B1 D1 F1 H1 K1 M1 P1 T2 TYPE I OUTPUT DRIVE (MA) DESCRIPTION Receive Positive Analog Input (RTIPn): RTIP is the positive differential input from the line interface. This input pin, along with the RRING input pin, functions as the "Receive DS1/E1 Line Signal" input for the XRT86VX38 device. The user is expected to connect this signal and the RRING input signal to a 1:1 transformer for proper operation. The center tap of the receive transformer should have a bypass capacitor of 0.1F to ground (Chip Side) to improve long haul application receive capabilities. Receive Negative Analog Input (RRINGn): RRING is the negative differential input from the line interface. This input pin, along with the RTIP input pin, functions as the "Receive DS1/E1 Line Signal" input for the XRT86VX38 device. The user is expected to connect this signal and the RTIP input signal to a 1:1 transformer for proper operation. The center tap of the receive transformer should have a bypass capacitor of 0.1F to ground (Chip Side) to improve long haul application receive capabilities. Receive Loss of Signal Output Indicator (RLOSn): The XRT86VX38 device will assert this output pin (i.e., toggle it "high") anytime (and for the duration that) the Receive DS1/E1 Framer or LIU block declares the LOS defect condition. Conversely, the XRT86VX38 will "TRI-State" this pin anytime (and for the duration that) the Receive DS1/E1 Framer or LIU block is NOT declaring the LOS defect condition. NOTE: Since the XRT86VX38 tri-states this output pin (anytime the channel is not declaring the LOS defect condition), the user MUST connect a "pulldown" resistor (ranging from 1K to 10K) to each RxLOS output pin, to pull this output pin to the logic "LOW" condition, whenever the Channel is NOT declaring the LOS defect condition. This output pin will toggle "High" (declare LOS) if the Receive Framer or the Receive LIU block associated with Channel N determines that an RLOS condition occurs. In other words, this pin is OR-ed with the LIU RLOS and the Framer RLOS bit. If either the LIU RLOS or the Framer RLOS bit associated with channel N pulses high, the corresponding RLOS pin of that particular channel will be set to "High".
REV. 1.0.1
RRING0 RRING1 RRING2 RRING3 RRING4 RRING5 RRING6 RRING7
D1 F1 J1 L1 N1 R1 U1 W3
C1 E1 G1 J1 L1 N1 R1 T3
I
-
RxLOS0 RxLOS1 RxLOS2 RxLOS3 RxLOS4 RxLOS5 RxLOS6 RxLOS7
B8 B13 D15 E18 U19 U15 V11 V7
A7 C11 F11 D16 P16 P12 R10 P7
O
4
23
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RECEIVE LINE INTERFACE
SIGNAL NAME RxTSEL 329 PKG BALL# B5 256 PKG BALL # A5 TYPE I OUTPUT DRIVE (MA) DESCRIPTION Receive Termination Control (RxTSEL): Upon power up, the receivers are in "High" impedance. Switching to internal termination can be selected through the microprocessor interface by programming the appropriate channel register. However, to switch control to the hardware pin, RxTCNTL must be programmed to "1" in the appropriate global register (0x0FE2). Once control has been granted to the hardware pin, it must be pulled "High" to switch to internal termination. NOTE: Internally pulled "Low" with a 50kresistor.
RxTSEL (pin) 0 1
Rx Termination External Internal
Note: RxTCNTL (bit) must be set to "1"
TRANSMIT LINE INTERFACE
SIGNAL NAME TTIP0 TTIP1 TTIP2 TTIP3 TTIP4 TTIP5 TTIP6 TTIP7 329 PKG BALL# D3 F3 H4 K4 L3 N3 R5 T3 256 PKG BALL # C3 E3 G3 H3 J3 L3 M3 P3 TYPE O DESCRIPTION Transmit Positive Analog Output (TTIPn): TTIP is the positive differential output to the line interface. This output pin, along with the corresponding TRING output pin, function as the Transmit DS1/E1 output signal drivers for the XRT86VX38 device. The user is expected to connect this signal and the corresponding TRING output signal to a 1:2 step up transformer for proper operation. This output pin will be tri-stated whenever the user sets the "TxON" input pin or register bit (0xnF02, bit 3) to "0". NOTE: This pin should have a series line capacitor of 0.68F for DC blocking purposes. TRING0 TRING1 TRING2 TRING3 TRING4 TRING5 TRING6 TRING7 E3 F4 H3 K3 L4 N4 R4 U3 D3 E4 G4 H4 J4 L4 M4 P4 O Transmit Negative Analog Output (TRINGn): TRING is the negative differential output to the line interface. This output pin, along with the corresponding TTIP output pin, function as the Transmit DS1/E1 output signal drivers for the XRT86VX38 device. The user is expected to connect this signal and the corresponding TRING output signal to a 1:2 step up transformer for proper operation. NOTE: This output pin will be tri-stated whenever the user sets the "TxON" input pin or register bit (0xnF02, bit 3) to "0".
24
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TRANSMIT LINE INTERFACE
SIGNAL NAME TxON 329 PKG BALL# W4 256 PKG BALL # T4 TYPE I DESCRIPTION Transmitter On This input pin permits the user to either enable or disable the Transmit Output Driver within the Transmit DS1/E1 LIU Block. If the TxON pin is pulled "Low", all 8 Channels are tri-stated. When this pin is pulled `High', turning on or off the transmitters will be determined by the appropriate channel registers (address 0x0Fn2, bit 3) LOW = Disables the Transmit Output Driver within the Transmit DS1/ E1 LIU Block. In this setting, the TTIP and TRING output pins of all 8 channels will be tri-stated. HIGH = Enables the Transmit Output Driver within the Transmit DS1/ E1 LIU Block. In this setting, the corresponding TTIP and TRING output pins will be enabled or disabled by programming the appropriate channel register. (address 0x0Fn2, bit 3) NOTE: Whenever the transmitters are turned off, the TTIP and TRING output pins will be tri-stated.
REV. 1.0.1
TIMING INTERFACE
SIGNAL NAME MCLKIN 329 PKG BALL# C8 256 PKG BALL # E6 TYPE I OUTPUT DRIVE (MA) DESCRIPTION Master Clock Input: This pin is used to provide the timing reference for the internal master clock of the device. The frequency of this clock is programmable from 8kHz to 16.384MHz in register 0x0FE9. Framer E1 Output Clock Reference This output pin is defaulted to 2.048MHz, but can be programmed to 65.536MHz in register 0x011E. Framer T1 Output Clock Reference This output pin is defaulted to 1.544MHz, but can be programmed to output 49.408MHz in register 0x011E. External Oscillator Select For normal operation, this pin should not be used, or pulled "Low". This pin is internally pulled "Low" with a 50k resistor. Factory Test Mode Pin NOTE: For Internal Use Only
E1OSCCLK
V5
R5
O
8
T1OSCCLK
W5
T5
O
8
8KEXTOSC
T5
L6
I
-
ANALOG
E5
B4
O
25
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
JTAG INTERFACE The XRT86VX38 device's JTAG features comply with the IEEE 1149.1 standard. Please refer to the industry specification for additional information on boundary scan operations.
SIGNAL NAME TCK 329 PKG BALL# C10 256 PKG BALL # D8 TYPE I OUTPUT DRIVE (MA) DESCRIPTION Test clock: Boundary Scan Test clock input: The TCLK signal is the clock for the TAP controller, and it generates the boundary scan data register clocking. The data on TMS and TDI is loaded on the positive edge of TCK. Data is observed at TDO on the falling edge of TCK. Test Mode Select: Boundary Scan Test Mode Select input. The TMS signal controls the transitions of the TAP controller in conjunction with the rising edge of the test clock (TCK). NOTE: TDI A5 C8 I For normal operation this pin must be pulled 'High'.
TMS
B7
A6
I
-
Test Data In: Boundary Scan Test data input The TDI signal is the serial test data input. NOTE: This pin is internally pulled 'high'.
TDO
D7
B6
O
8
Test Data Out: Boundary Scan Test data output The TDO signal is the serial test data output. Test Reset Input: The TRST signal (Active Low) asynchronously resets the TAP controller to the Test-Logic-Reset state. NOTE: This pin is internally pulled 'high'
TRST
C9
D7
I
-
aTEST
C7
C7
I
-
Factory Test Mode Pin NOTE: This pin is internally pulled 'low', and should be pulled 'low' for normal operation.
MICROPROCESSOR INTERFACE
SIGNAL NAME DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 329 PKG BALL# N16 P19 K16 L18 J19 H18 H16 G15 256 PKG BALL # M14 L12 K12 J12 H13 G14 G12 G13 TYPE I/O OUTPUT DRIVE (MA) 8 DESCRIPTION Bidirectional Microprocessor Data Bus These pins are used to drive and receive data over the bidirectional data bus, whenever the Microprocessor performs READ or WRITE operations with the Microprocessor Interface of the XRT86VX38 device. When DMA interface is enabled, these 8-bit bidirectional data bus is also used by the T1/E1 Framer or the external DMA Controller for storing and retrieving information.
26
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION MICROPROCESSOR INTERFACE
SIGNAL NAME REQ0 329 PKG BALL# T19 256 PKG BALL # N16 TYPE O OUTPUT DRIVE (MA) 8 DESCRIPTION DMA Cycle Request Output--DMA Controller 0 (Write): These output pins are used to indicate that DMA transfers (Write) are requested by the T1/E1 Framer. On the transmit side (i.e., To transmit data from external DMA controller to HDLC buffers within the XRT86VX38), DMA transfers are only requested when the transmit buffer status bits indicate that there is space for a complete message or cell. The DMA Write cycle starts by T1/E1 Framer asserting the DMA Request (REQ0) `low', then the external DMA controller should drive the DMA Acknowledge (ACK0) `low' to indicate that it is ready to start the transfer. The external DMA controller should place new data on the Microprocessor data bus each time the Write Signal is Strobed low if the WR is configured as a Write Strobe. If WR is configured as a direction signal, then the external DMA controller would place new data on the Microprocessor data bus each time the Read Signal (RD) is Strobed low. The Framer asserts this output pin (toggles it "Low") when at least one of the Transmit HDLC buffers are empty and can receive one more HDLC message. The Framer negates this output pin (toggles it "High") when the HDLC buffer can no longer receive another HDLC message. DMA Cycle Request Output--DMA Controller 1 (Read): These output pins are used to indicate that DMA transfers (Read) are requested by the T1/E1 Framer. On the receive side (i.e., To transmit data from HDLC buffers within the XRT86VX38 to external DMA Controller), DMA transfers are only requested when the receive buffer contains a complete message or cell. The DMA Read cycle starts by T1/E1 Framer asserting the DMA Request (REQ1) `low', then the external DMA controller should drive the DMA Acknowledge (ACK1) `low' to indicate that it is ready to receive the data. The T1/E1 Framer should place new data on the Microprocessor data bus each time the Read Signal is Strobed low if the RD is configured as a Read Strobe. If RD is configured as a direction signal, then the T1/E1 Framer would place new data on the Microprocessor data bus each time the Write Signal (WR) is Strobed low. The Framer asserts this output pin (toggles it "Low") when one of the Receive HDLC buffer contains a complete HDLC message that needs to be read by the C/P. The Framer negates this output pin (toggles it "High") when the Receive HDLC buffers are depleted.
REV. 1.0.1
REQ1
R16
R16
O
8
27
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
SIGNAL NAME INT 329 PKG BALL# J18 256 PKG BALL # H15 TYPE O OUTPUT DRIVE (MA) 8 DESCRIPTION Interrupt Request Output: This active-low output signal will be asserted when the XRT86VX38 device is requesting interrupt service from the Microprocessor. This output pin should typically be connected to the "Interrupt Request" input of the Microprocessor. The Framer will assert this active "Low" output (toggles it "Low"), to the local P, anytime it requires interrupt service. Microprocessor Clock Input: This clock input signal is only used if the Microprocessor Interface has been configured to operate in the Synchronous Modes (e.g., Power PC 403 Mode). If the Microprocessor Interface is configured to operate in this mode, then it will use this clock signal to do the following. 1. To sample the CS, WR/R/W, A[14:0], D[7:0], RD/DS and DBEN input pins, and 2. To update the state of the D[7:0] and the RDY/ DTACK output signals. NOTES: 1. 2. The Microprocessor Interface can work with PCLK frequencies ranging up to 33MHz. This pin is inactive if the user has configured the Microprocessor Interface to operate in either the Intel-Asynchronous or the MotorolaAsynchronous Modes. In this case, the user should tie this pin to GND.
PCLK
P18
M16
I
-
When DMA interface is enabled, the PCLK input pin is also used by the T1/E1 Framer to latch in or latch out receive or output data respectively. PTYPE0 PTYPE1 PTYPE2 P17 N18 K19 M13 M12 H12 I Microprocessor Type Input: These input pins permit the user to specify which type of Microprocessor/Microcontroller to be interfaced to the XRT86VX38 device. The following table presents the three different microprocessor types that the XRT86VX38 supports.
PType2 PType1 PType0 0 1 1
MICROPROCESSOR TYPE 68HC11, 8051, 80C188 MOTOROLA 68K IBM POWER PC 403
0 0 1
0 0 0
NOTE: These pins are internally pulled "Low" with a 50k resistor.
28
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION MICROPROCESSOR INTERFACE
SIGNAL NAME RDY/DTACK 329 PKG BALL# M16 256 PKG BALL # L16 TYPE O OUTPUT DRIVE (MA) 12 DESCRIPTION Ready/Data Transfer Acknowledge Output: The exact behavior of this pin depends upon the type of Microprocessor/Microcontroller the XRT86VX38 has been configured to operate in, as defined by the PTYPE[2:0] pins. Intel Asynchronous Mode - RDY - Ready Output Tis output pin will function as the "active-low" READY output. During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic low level, ONLY when the Microprocessor Interface is ready to complete or terminate the current READ or WRITE cycle. Once the Microprocessor has determined that this input pin has toggled to the logic "low" level, then it is now safe for it to move on and execute the next READ or WRITE cycle. If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this output pin at a logic "high" level, then the Microprocessor is expected to extend this READ or WRITE cycle, until it detects this output pin being toggled to the logic low level. Motorola Asynchronous Mode - DTACK - Data Transfer Acknowledge Output Tis output pin will function as the "active-low" DTACK output. During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic low level, ONLY when the Microprocessor Interface is ready to complete or terminate the current READ or WRITE cycle. Once the Microprocessor has determined that this input pin has toggled to the logic "low" level, then it is now safe for it to move on and execute the next READ or WRITE cycle. If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this output pin at a logic "high" level, then the Microprocessor is expected to extend this READ or WRITE cycle, until it detects this output pin being toggled to the logic low level.
REV. 1.0.1
29
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
SIGNAL NAME RDY/DTACK 329 PKG BALL# M16 256 PKG BALL # L16 TYPE O OUTPUT DRIVE (MA) 12 DESCRIPTION (Con't) Power PC 403 Mode - RDY Ready Output: This output pin will function as the "active-high" READY output. During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic high level, ONLY when the Microprocessor Interface is ready to complete or terminate the current READ or WRITE cycle. Once the Microprocessor has sampled this signal being at the logic "high" level upon the rising edge of PCLK, then it is now safe for it to move on and execute the next READ or WRITE cycle. If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this output pin at a logic "low" level, then the Microprocessor is expected to extend this READ or WRITE cycle, until it samples this output pin being at the logic low level. NOTE: The Microprocessor Interface will update the state of this output pin upon the rising edge of PCLK. ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 N19 M17 M18 M15 L16 M19 L17 L19 K15 J16 K18 J15 H15 H19 H17 L13 L14 K15 L11 K13 K16 K14 J15 J14 J13 H14 H16 G16 F16 G11 I Microprocessor Interface Address Bus Input These pins permit the Microprocessor to identify on-chip registers and Buffer/Memory locations within the XRT86VX38 device whenever it performs READ and WRITE operations with the XRT86VX38 device. NOTE: These pins are internally pulled "Low" with a 50k resistor, except ADDR[8:14].
30
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION MICROPROCESSOR INTERFACE
SIGNAL NAME ALE / AS 329 PKG BALL# K17 256 PKG BALL # J16 TYPE I OUTPUT DRIVE (MA) DESCRIPTION Address Latch Enable Input Address Strobe The exact behavior of this pin depends upon the type of Microprocessor/Microcontroller the XRT86VX38 has been configured to operate in, as defined by the PTYPE[2:0] pins. Intel-Asynchronous Mode - ALE This active-high input pin is used to latch the address (present at the Microprocessor Interface Address Bus pins (A[14:0]) into the XRT86VX38 Microprocessor Interface block and to indicate the start of a READ or WRITE cycle. Pulling this input pin "high" enables the input bus drivers for the Address Bus input pins (A[14:0]). The contents of the Address Bus will be latched into the XRT86VX38 Microprocessor Interface circuitry, upon the falling edge of this input signal. Motorola-Asynchronous (68K) Mode - AS This active-low input pin is used to latch the data residing on the Address Bus, A[14:0] into the Microprocessor Interface circuitry of the XRT86VX38 device. Pulling this input pin "low" enables the input bus drivers for the Address Bus input pins. The contents of the Address Bus will be latched into the Microprocessor Interface circuitry, upon the rising edge of this signal. Power PC 403 Mode - No Function -Tie to GND: This input pin has no role nor function and should be tied to GND. Microprocessor Interface--Chip Select Input: The user must assert this active low signal in order to select the Microprocessor Interface for READ and WRITE operations between the Microprocessor and the XRT86VX38 on-chip registers and buffer/memory locations.
REV. 1.0.1
CS
G19
F14
I
-
31
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
SIGNAL NAME RD/DS/WE 329 PKG BALL# N17 256 PKG BALL # L15 TYPE I OUTPUT DRIVE (MA) DESCRIPTION Microprocessor Interface--Read Strobe Input: The exact behavior of this pin depends upon the type of Microprocessor/Microcontroller the Framer has been configured to operate in, as defined by the PTYPE[2:0] pins. Intel-Asynchronous Mode - RD - READ Strobe Input: This input pin will function as the RD (Active Low Read Strobe) input signal from the Microprocessor. Once this active-low signal is asserted, then the XRT86VX38 device will place the contents of the addressed register (or buffer location) on the Microprocessor Interface Bi-directional data bus (D[7:0]). When this signal is negated, then the Data Bus will be tristated. Motorola-Asynchronous (68K) Mode - DS - Data Strobe: This input pin will function as the DS (Data Strobe) input signal. Power PC 403 Mode - WE - Write Enable Input: This input pin will function as the WE (Write Enable) input pin. Anytime the Microprocessor Interface samples this activelow input signal (along with CS and WR/R/W) also being asserted (at a logic low level) upon the rising edge of PCLK, then the Microprocessor Interface will (upon the very same rising edge of PCLK) latch the contents on the Bi-Directional Data Bus (D[7:0]) into the "target" on-chip register or buffer location within the XRT86VX38 device. Microprocessor Interface--Write Strobe Input The exact behavior of this pin depends upon the type of Microprocessor/Microcontroller the XRT86VX38 has been configured to operate in, as defined by the PTYPE[2:0] pins. Intel-Asynchronous Mode - WR - Write Strobe Input: This input pin functions as the WR (Active Low WRITE Strobe) input signal from the Microprocessor. Once this active-low signal is asserted, then the input buffers (associated with the Bi-Directional Data Bus pin, D[7:0]) will be enabled. The Microprocessor Interface will latch the contents on the Bi-Directional Data Bus (into the "target" register or address location, within the XRT86VX38) upon the rising edge of this input pin. Motorola-Asynchronous Mode - R/W - Read/Write Operation Identification Input Pin: This pin is functionally equivalent to the "R/W" input pin. In the Motorola Mode, a "READ" operation occurs if this pin is held at a logic "1", coincident to a falling edge of the RD/DS (Data Strobe) input pin. Similarly a WRITE operation occurs if this pin is at a logic "0", coincident to a falling edge of the RD/DS (Data Strobe) input pin.
WR / R/W
G17
F13
I
-
32
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION MICROPROCESSOR INTERFACE
SIGNAL NAME WR / R/W 329 PKG BALL# G17 256 PKG BALL # F13 TYPE I OUTPUT DRIVE (MA) DESCRIPTION (Con't) Power PC 403 Mode - R/W - Read/Write Operation Identification Input: This input pin will function as the "Read/Write Operation Identification Input" pin. Anytime the Microprocessor Interface samples this input signal at a logic "High" (while also sampling the CS input pin "Low") upon the rising edge of PCLK, then the Microprocessor Interface will (upon the very same rising edge of PCLK) latch the contents of the Address Bus (A[14:0]) into the Microprocessor Interface circuitry, in preparation for this forthcoming READ operation. At some point (later in this READ operation) the Microprocessor will also assert the DBEN/OE input pin, and the Microprocessor Interface will then place the contents of the "target" register (or address location within the XRT86VX38 device) upon the Bi-Directional Data Bus pins (D[7:0]), where it can be read by the Microprocessor. Anytime the Microprocessor Interface samples this input signal at a logic "Low" (while also sampling the CS input pin a logic "Low") upon the rising edge of PCLK, then the Microprocessor Interface will (upon the very same rising edge of PCLK) latch the contents of the Address Bus (A[14:0]) into the Microprocessor Interface circuitry, in preparation for the forthcoming WRITE operation. At some point (later in this WRITE operation) the Microprocessor will also assert the RD/DS/WE input pin, and the Microprocessor Interface will then latch the contents of the Bi-Directional Data Bus (D[7:0]) into the contents of the "target" register or buffer location (within the XRT86VX38).
REV. 1.0.1
33
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
SIGNAL NAME ACK0 329 PKG BALL# T18 256 PKG BALL # N15 TYPE I OUTPUT DRIVE (MA) DESCRIPTION DMA Cycle Acknowledge Input--DMA Controller 0 (Write): The external DMA Controller will assert this input pin "Low" when the following two conditions are met: 1. After the DMA Controller, within the Framer has asserted (toggled "Low"), the Req_0 output signal. 2. When the external DMA Controller is ready to transfer data from external memory to the selected Transmit HDLC buffer. At this point, the DMA transfer between the external memory and the selected Transmit HDLC buffer may begin. After completion of the DMA cycle, the external DMA Controller will negate this input pin after the DMA Controller within the Framer has negated the Req_0 output pin. The external DMA Controller must do this in order to acknowledge the end of the DMA cycle. DMA Cycle Acknowledge Input--DMA Controller 1 (Read): The external DMA Controller asserts this input pin "Low" when the following two conditions are met: 1. After the DMA Controller, within the Framer has asserted (toggled "Low"), the Req_1 output signal. 2. When the external DMA Controller is ready to transfer data from the selected Receive HDLC buffer to external memory. At this point, the DMA transfer between the selected Receive HDLC buffer and the external memory may begin. After completion of the DMA cycle, the external DMA Controller will negate this input pin after the DMA Controller within the Framer has negated the Req_1 output pin. The external DMA Controller will do this in order to acknowledge the end of the DMA cycle. NOTE: RESET V4 R4 I This pin is internally pulled "High" with a 50k resistor.
ACK1
R19
M15
Hardware Reset Input Reset is an active low input. If this pin is pulled "Low" for more than 10S, the device will be reset. When this occurs, all output will be `tri-stated', and all internal registers will be reset to their default values.
34
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION POWER SUPPLY PINS (3.3V)
SIGNAL NAME VDD 329 PKG BALL# A1 A12 A19 B6 B9 E16 F5 J17 P16 R11 R13 R15 R18 T7 U4 V1 W11 W15 C2 E2 G1 J2 L2 N2 P4 U2 D4 G4 J4 K5 M4 N5 R3 T4 256 PKG BALL # A16 E8 E11 G15 M6 M9 N14 T16 TYPE PWR DESCRIPTION Framer Block Power Supply (I/O)
REV. 1.0.1
RVDD
B2 D2 F2 H2 K2 M2 P2 T1 D4 F4 F5 H5 K4 K5 M5 N4
PWR
Receiver Analog Power Supply for LIU Section
TVDD
PWR
Transmitter Analog Power Supply for LIU Section
35
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
POWER SUPPLY PINS (1.8V)
SIGNAL NAME VDD18 329 PKG BALL# D13 E6 E8 E9 E11 E12 E13 E15 F15 G5 G7 G9 G11 G13 J5 J7 J13 L7 L13 L15 M5 N7 N9 N11 N13 P15 R9 R10 R12 R14 T6 B4 D6 A2 B2 B3 C4 256 PKG BALL # F8 F9 F10 G6 H6 H11 J6 J11 K6 K11 L7 L8 L9 L10 TYPE PWR DESCRIPTION Framer Block Power Supply
DVDD18 AVDD18 VDDPLL18
C6 C5 A3 A4 B3 D5
PWR PWR PWR
Digital Power Supply for LIU Section Analog Power Supply for LIU Section Analog Power Supply for PLL
36
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION GROUND PINS
SIGNAL NAME VSS 329 PKG BALL# A3, A6 A15, C5 E7, F2 G8, G10 G12, H5 H7, H8 H9, H10 H11, H12 H13, J8 J9, J10 J11, J12 K7, K8 K9, K10 K11, K12 K13, L8 L9, L10 L11, L12 M7, M8 M9, M10 M11, M12 M13, N8 N10, N12 N15, P2 R6, U12 W1, W19 256 PKG BALL # E7 E9 F6 F7 G7 G8 G9 G10 H7 H8 H9 H10 J7 J8 J9 J10 K7 K8 K9 K10 TYPE GND Framer Block Ground DESCRIPTION
REV. 1.0.1
DGND AGND RGND
A4 C6 D2 G2 H2 K2 M2 R2 T2 V3 E4 G3 J3 L5 M3 P3 P5 V2
D6 B5 C2 E2 G2 J2 L2 N2 R2 R3 E5 F3 G5 J5 K3 L5 N3 N5
GND GND GND
Digital Ground for LIU Section Analog Ground for LIU Section Receiver Analog Ground for LIU Section
TGND
GND
Transmitter Analog Ground for LIU Section
37
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
GROUND PINS
SIGNAL NAME GNDPLL 329 PKG BALL# B1 C3 D5 256 PKG BALL # A1 A2 C4 TYPE GND Analog Ground for PLL DESCRIPTION
NO CONNECT PINS
SIGNAL NAME NC 329 PKG BALL# F6 F7 F8 F9 F10 F11 F12 F13 F14 G6 G14 H6 H14 J6 J14 K6 K14 L6 L14 M6 M14 N6 N14 P6 P7 P8 P9 P10 P11 P12 P13 P14 256 PKG BALL # TYPE NC No Connection DESCRIPTION
38
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
ELECTRICAL CHARACTERISTICS
Absolute Maximums
Power Supply..................................................................... VDDIO .. ................................................ -0.5V to +3.465V VDDCORE...............................................-0.5V to +1.890V Storage Temperature ...............................-65C to 150C Operating Temperature Range.................-40C to 85C Supply Voltage ...................... GND-0.5V to +VDD + 0.5V
Power Rating fpBGA Package.................. 2.4
Input Logic Signal Voltage (Any Pin) .........-0.5V to + 5.5V ESD Protection (HBM)...........................................>2000V Input Current (Any Pin) ...................................... + 100mA
DC ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25C, VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5% unless otherwise specified SYMBOL ILL VIL VIH VOL VOH IOC IIH IIL PARAMETER Data Bus Tri-State Bus Leakage Current Input Low voltage Input High Voltage Output Low Voltage Output High Voltage Open Drain Output Leakage Current Input High Voltage Current Input Low Voltage Current -10 -10 10 10 2.0 0.0 2.4 MIN. -10 TYP. MAX. +10 0.8 VDD 0.4 VDD UNITS A V V V V A A A VIH = VDD VIL = GND IOL = -1.6mA IOH = 40A CONDITIONS
XRT86VX38 POWER CONSUMPTION
Test Conditions: TA = 25C, VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, Internal termination, unless otherwise specified MODE T1 IMPEDANCE 100 MIN. TYP. 2.02 1.54 1.95 1.57 1.77 1.44 MAX. UNITS W CONDITIONS All ones Pattern PRBS Pattern All ones Pattern PRBS Pattern All ones Pattern PRBS Pattern
E1
75
W
E1
120
W
39
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 4: E1 RECEIVER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA= -40 to 85C, unless otherwise specified PARAMETER Receiver loss of signal: Number of consecutive zeros before RLOS is set Input signal level at RLOS RLOS De-asserted Receiver Sensitivity (Short Haul with cable loss) Receiver Sensitivity (Long Haul with cable loss) Input Impedance Input Jitter Tolerance: 1 Hz 10kHz-100kHz Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude Jitter Attenuator Corner Frequency (-3dB curve) (JABW=0) (JABW=1) Return Loss: 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz 15 12.5 11 MIN. TYP. MAX. UNIT TEST CONDITIONS Cable attenuation @1024kHz
32 20 dB % ones dB With nominal pulse amplitude of 3.0V for 120 and 2.37V for 75 application. With nominal pulse amplitude of 3.0V for 120 and 2.37V for 75 application. ITU-G.775, ETSI 300 233
0
43
dB
15
k
37 0.3
UIpp UIpp
ITU G.823
-
20 0.5
kHz dB
ITU G.736
-
10 1.5
-
Hz Hz
ITU G.736
12 8 8
-
-
dB dB dB
ITU-G.703
40
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 5: T1 RECEIVER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40 to 85C, unless otherwise specified PARAMETER Receiver loss of signal: Number of consecutive zeros before RLOS is set Input signal level at RLOS RLOS Clear Receiver Sensitivity (Short Haul with cable loss) Receiver Sensitivity (Long Haul with cable loss) Normal Extended Input Impedance Jitter Tolerance: 1Hz 10kHz - 100kHz Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude Jitter Attenuator Corner Frequency (-3dB curve) Return Loss: 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz 15 12.5 12 175 MIN. TYP. MAX. UNIT TEST CONDITIONS
REV. 1.0.1
20 -
-
dB % ones dB
Cable attenuation @772kHz ITU-G.775, ETSI 300 233 With nominal pulse amplitude of 3.0V for 100 termination
0 0 15 36 45 dB dB k With nominal pulse amplitude of 3.0V for 100 termination
138 0.4
-
-
UIpp
AT&T Pub 62411
-
10
0.1
KHz dB Hz
TR-TSY-000499
6
AT&T Pub 62411
-
14 20 16
-
dB dB dB
TABLE 6: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40 to 85C, unless otherwise specified PARAMETER AMI Output Pulse Amplitude: 75 Application 120 Application Output Pulse Width Output Pulse Width Ratio Output Pulse Amplitude Ratio 2.13 2.70 224 0.95 0.95 2.37 3.00 244 2.60 3.30 264 1.05 1.05 V V ns ITU-G.703 ITU-G.703 MIN. TYP. MAX. UNIT TEST CONDITIONS 1:2 transformer
41
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 6: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40 to 85C, unless otherwise specified PARAMETER Jitter Added by the Transmitter Output Output Return Loss: 51kHz -102kHz 102kHz-2048kHz 2048kHz-3072kHz MIN. TYP. 0.025 MAX. 0.05 UNIT UIpp TEST CONDITIONS Broad Band with jitter free TCLK applied to the input.
15 9 8
-
-
dB dB dB
ETSI 300 166
TABLE 7: E1 TRANSMIT RETURN LOSS REQUIREMENT
FREQUENCY 51-102kHz 102-2048kHz 2048-3072kHz RETURN LOSS ETS 300166 6dB 8dB 8dB
TABLE 8: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40 to 85C, unless otherwise specified PARAMETER AMI Output Pulse Amplitude: Output Pulse Width Output Pulse Width Imbalance Output Pulse Amplitude Imbalance Jitter Added by the Transmitter Output Output Return Loss: 51kHz -102kHz 102kHz-2048kHz 2048kHz-3072kHz MIN. 2.4 338 TYP. 3.0 350 0.025 MAX. 3.60 362 20 +200 0.05 UNIT V ns mV UIpp TEST CONDITIONS 1:2 transformer measured at DSX-1. ANSI T1.102 ANSI T1.102 ANSI T1.102 Broad Band with jitter free TCLK applied to the input.
-
17 12 10
-
dB dB dB
42
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION FIGURE 2. ITU G.703 PULSE TEMPLATE
269 ns (244 + 25)
20%
REV. 1.0.1
10%
V = 100%
10%
20%
194 ns (244 - 50)
Nominal pulse
50%
244 ns
10%
488 ns (244 + 244) Note - V corresponds to the nominal peak value.
TABLE 9: TRANSMIT PULSE MASK SPECIFICATION
Test Load Impedance Nominal Peak Voltage of a Mark Peak voltage of a Space (no Mark) Nominal Pulse width Ratio of Positive and Negative Pulses Imbalance 75 Resistive (Coax) 2.37V 0 + 0.237V 244ns 0.95 to 1.05 120 Resistive (twisted Pair) 3.0V 0 + 0.3V 244ns 0.95 to 1.05
20%
43
10%
0%
10%
10%
219 ns (244 - 25)
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
FIGURE 3. ITU G.703 SECTION 13 SYNCHRONOUS INTERFACE PULSE TEMPLATE
TT 30 30 TT 30 30 TT 30 30 +V
+V1
0
-V1
T 4
T 4 T
T 4
T 4
-V
T1818900-92
Shaded area in which signal should be monotonic
T Average period of synchronizing signal
TABLE 10: E1 SYNCHRONOUS INTERFACE TRANSMIT PULSE MASK SPECIFICATION
Test Load Impedance Maximum Peak Voltage of a Mark Minimum Peak Voltage of a Mark Nominal Pulse width 75 Resistive (Coax) 1.5V 0.75V 244ns 120 Resistive (twisted Pair) 1.9V 1.0V 244ns
44
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION FIGURE 4. DSX-1 PULSE TEMPLATE (NORMALIZED AMPLITUDE)
REV. 1.0.1
TABLE 11: DSX1 INTERFACE ISOLATED PULSE MASK AND CORNER POINTS
MINIMUM CURVE TIME (UI) -0.77 -0.23 -0.23 -0.15 0.0 0.15 0.23 0.23 0.46 0.66 0.93 1.16 NORMALIZED AMPLITUDE -.05V -.05V 0.5V 0.95V 0.95V 0.9V 0.5V -0.45V -0.45V -0.2V -0.05V -0.05V TIME (UI) -0.77 -0.39 -0.27 -0.27 -0.12 0.0 0.27 0.35 0.93 1.16 MAXIMUM CURVE NORMALIZED AMPLITUDE .05V .05V .8V 1.15V 1.15V 1.05V 1.05V -0.07V 0.05V 0.05V
45
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 12: AC ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=25C, UNLESS OTHERWISE SPECIFIED PARAMETER SYMBOL MIN. 40 TYP. 50 MAX. 60 UNITS % ppm
MCLKIN Clock Duty Cycle MCLKIN Clock Tolerance
46
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
86VX38
REV. 1.0.1
ORDERING INFORMATION
PRODUCT NUMBER XRT86VX38IB329 XRT86VX38IB256 PACKAGE 329 Fine Pitch Ball Grid Array 256 Fine Pitch Ball Grid Array OPERATING TEMPERATURE RANGE -40C to +85C -40C to +85C
PACKAGE DIMENSIONS FOR 329 FINE PITCH BALL GRID ARRAY
329 Fine Pitch Ball Grid Array (17.0 mm x 17.0 mm, fpBGA)
Rev. 1.00
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A1 corner
A B C D E F G H J
D
D1
K L M N P R T U V W
D1 D (A1 corner feature is mfger option )
Seating Plane A A1 A2 b e
Note: The control dimension is in millimeter. INCHES MIN MAX 0.056 0.067 0.010 0.014 0.046 0.053 0.663 0.675 0.567 BSC 0.014 0.018 0.031 BSC MILLIMETERS MIN MAX 1.43 1.71 0.26 0.36 1.17 1.35 16.85 17.15 14.40 BSC 0.36 0.46 0.80 BSC
SYMBOL A A1 A2 D D1 b e
47
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
4
PACKAGE DIMENSIONS FOR 256 FINE PITCH BALL GRID ARRAY
256 Fine Pitch Ball Grid Array (17.0 mm x 17.0 mm, fpBGA)
Rev. 1.00
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A1 corner
A B C D E F G H
D
D1
J K L M N P R T
D1 D (A1 corner feature is mfger option)
Seating Plane A A1 A2 b e
Note: The control dimension is in millimeter. INCHES MIN MAX 0.058 0.070 0.013 0.017 0.045 0.053 0.661 0.677 0.591 BSC 0.020 0.024 0.039 BSC MILLIMETERS MIN MAX 1.48 1.78 0.33 0.43 1.15 1.35 16.80 17.20 15.00 BSC 0.50 0.60 1.00 BSC
SYMBOL A A1 A2 D D1 b e
48
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2009 EXAR Corporation Datasheet June 2009. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
49
XRT86VX38
REV. 1.0.1
P4.
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REVISION HISTORY
REVISION # 1.0.0 1.0.1 DATE May. 01, 2009 June 15, 2009 DESCRIPTION Initial release of Hardware Description Update packaging name to fpBGA, add BITS functionality to general description, updated features and applications and updates to eletrical tables
50

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