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| DMAC Media Access Controller ver 2.07 OVERVIEW The DMAC is hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external PHY device enables network functionality in design. It is capable of transmitting and receiving Ethernet frames to and from the network. Half and full duplex modes are supported, as well 10 and 100 Mbit/s speed. The core is able to work with wide range of processors: 8, 16 and 32 bit data bus, with little or big endian byte order format. Design is technology independent and thus can be implemented in variety of process technologies. This core strictly conforms to IEEE 802.3 standard. Supports full and half duplex operation at 10 Mbps or 100 Mbps CRC-32 algorithm calculates the FCS nibble at a time, automatic FCS generation and checking, able to capture frames with CRC errors if required Lite design, small gate count and fast operation Programmable or fixed MAC address Promiscuous mode support Dynamic PHY configuration by MII management interface Receive FIFO able to store many messages at a time Allows operation from a wide range of input bus clock frequencies Fully synthesizable Static synchronous design with positive edge clocking and synchronous reset No internal tri-states Scan test ready KEY FEATURES Conforms to IEEE 802.3-2002 specification 8/16/32-bit CPU slave interface with little or big endianess Simple interface allows easy connection to CPU Narrow address bus with indirect I/O interface to the transmit and receive data dual port memories Supports 10BASE-T and 100BASETX/FX IEEE 802.3 compliant MII PHYs Media Independent Interface (MII) for connection to external 10/100 Mbps PHY transceivers APPLICATIONS Embedded microprocessor boards Networking devices (Network Interface Cards, routers, switches) Communications systems All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance clk rst rdcs wrcs rd wr PINS DESCRIPTION PIN TYPE input input input input input input input input input 1 DESCRIPTION Global clock Global reset Read chip select Write chip select Read data strobe Write data strobe Host read address bus Host write address bus Host byte enable Host output data bus RX DPRAM data output TX DPRAM data output Ethernet receive data Ethernet receive data valid Ethernet receive error Ethernet receive clock Ethernet transmit clock Ethernet carrier sense Ethernet collision detection Management data input DoCD debugger input rdaddr(4:0) wraddr(4:0) be(3:0) 2 datai(31:0) qmr(31:0) qmt(31:0) input input input input input input input input input input input input rxdata(3:0) rxdv rxer rxclk txclk crs col mdi docdbusctrl datao(31:0) irq dmr(31:0) waddrmr(8:0) raddrmr(8:0) enrmr enwmr dmt(31:0) waddrmt(8:0) raddrmt(8:0) enrmt enwmt txer txen txdata(3:0) mdc mdo mdoe clk rst rdcs wrcs 1 Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support SYMBOL rst rdcs wrcs qmt(31:0) rd wr be(3:0)2 datai(31:0)1 rdaddr(4:0) wraddr(4:0) clk qmr(31:0) rxdata(3:0) rxdv rxer rxclk crs col txclk mdi docdbusctrl dmt(31:0) waddrmt(8:0) raddrmt(8:0) enrmt enwmt output Host input data bus output Interrupt signal output RX DPRAM data input output RX DPRAM write address output RX DPRAM read address output RX DPRAM read enable output RX DPRAM write enable output TX DPRAM data input output TX DPRAM write address output TX DPRAM read address output TX DPRAM read enable output TX DPRAM write enable output Ethernet transmit error output Ethernet transmit enable output Ethernet transmit data output Management clock output Management data output output Management data output enable input input input input Global clock Global reset Read chip select Write chip select datao(31:0)1 irq dmr(31:0) waddrmr(8:0) raddrmr(8:0) enrmr enwmr txdata(3:0) txen txer mdc mdo mdoe 1 - data bus can be configured as 8-, 16- or 32- bit depends on processor's bus size 2 - byte enable (be) size is set accordingly to data bus size All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. BLOCK DIAGRAM Figure below shows the DMAC IP Core block diagram. TX RAM pins txclk crs col txen txer txdata(3:0) mdi mdc mdo mdoe rxclk rxdv rxer rxdata(3:0) PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA(R) devices after Place & Route (all key features have been included): Device STRATIX II CYCLONE II STRATIX GX STRATIX CYCLONE APEX II APEX20KC APEX20KE APEX20K Speed grade -3 -6 -5 -5 -6 -7 -7 -1 -1 Logic Cells 967 + 4 kB RAM 1222 + 4 kB RAM 1255 + 4 kB RAM 1255 + 4 kB RAM 1254 + 4 kB RAM 1622 + 4 kB RAM 1622 + 4 kB RAM 1622 + 4 kB RAM 1622 + 4 kB RAM Fmax [MHz] clk / rxclk / txclk 211 / 200 / 175 150 / 156 / 152 152 / 156 / 138 162 / 147 / 137 148 / 133 / 133 145 / 106 / 111 127 / 118 / 117 108 / 99 / 111 86 / 87 / 88 Transmit module TX RAM interface STA Synchronization logic Control & I/O logic Receive module RX FIFO docdbusctrl clk rst rdcs wrcs rd wr be(3:0) rdaddr(4:0) wraddr(4:0) datai(31:0) irq datao(31:0) RX RAM pins Transmit module - Performs transmit management functions, sends frames to Ethernet medium. Receive module - is responsible for receiving frames from the Ethernet. Provides necessary functions for frame decapsulation, CRC checking, address recognizing and error detection. Synchronization logic - There are 3 clock domains in the DMAC core. This module performs synchronization between these. TX RAM / RX FIFO RAM interfaces - Interfaces to external dual port memories used by the DMAC core to store received and transmitted frames. Control and I/O logic - This module provides interface to CPU/BUS. It exchanges data and control logic with transmit and receive modules, thus controls these to perform transmit and receive operations. STA - Station Management entity provides capability to communicate with PHY by simple serial management interface. Core performance in ALTERA(R) devices All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND nfo@dcd.pl e-mail: iinfo@dcd.pl tel. fax : +48 32 282 82 66 : +48 32 282 74 37 Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. |
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