Part Number Hot Search : 
FR151 MAX4582 C1514 F20UP60D 17AS28 CR50HR 421904 4FCT8
Product Description
Full Text Search
 

To Download EN39SL160H Datasheet File
  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
　
 

  Datasheet File OCR Text:
 EN39SL160H/L
EN39SL160H/L
16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory With 4Kbytes Uniform Sector, CMOS 1.8 Volt-only
FEATURES
* Single power supply operation - Full voltage range:1.65-1.95 volt for read and write operations. - Ideal for battery-powered applications. * High performance - Access times as fast as 70 ns * Low power consumption (typical values at 5 MHz) - 5 mA typical active read current - 15 mA typical program/erase current - 0.2 A typical standby current * Uniform Sector Architecture: - 512 sectors of 4-Kbyte / 2-Kword - 32 blocks of 64-Kbyte / 32-Kword - Any sector or block can be erased individually * WP#/ACC Input pin: - Write protect (WP#) function allows protection the first or last blocks, regardless of block protect status - Acceleration (ACC) function acceleration program timing. * Block protection: - Hardware locking of blocks to prevent program or erase operations within individual blocks - Additionally, temporary Block Unprotect allows code changes in previously locked blocks. * High performance program/erase speed Byte/Word program time: 5s/7s typical Sector erase time: 90ms typical Block erase time: 400ms typical Chip erase time: 7 s typical
* JEDEC Standard Embedded Erase and Program Algorithms * JEDEC standard DATA# polling and toggle bits feature * Single Sector, Block and Chip Erase * Block Unprotect Mode * Erase Suspend / Resume modes: Read or program another Sector/Block during Erase Suspend Mode * Low Vcc write inhibit < 1.2V * Minimum 100K endurance cycle * Package Options 48-pin TSOP (Type 1) 48-ball 6mm x 8mm TFBGA 48-ball 4mm x 6mm WFBGA
* Industrial temperature Range
GENERAL DESCRIPTION
The EN39SL160H/L is a 16-Megabit, electrically erasable, read/write non-volatile flash memory, organized as 2,097,152 bytes or 1,048,576 words. Any byte can be programmed typically in 5s.The EN39SL160H/L features 1.8V voltage read and write operation, with access time as fast as 70ns to eliminate the need for WAIT statements in high-performance microprocessor systems. The EN39SL160H/L has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#) controls, which eliminate bus contention issues. This device is designed to allow either single Sector/Block or full chip erase operation, where each block can be individually protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each sector or block.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
1
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
CONNECTION DIAGRAMS
A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# Vss DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# A0
Standard TSOP
TFBGA Top View, Balls Facing Down
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
2
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
WFBGA Top View, Balls Facing Down
A6 A2 A5 A1 A4 A0 A3 CE# A2 VSS B6 A4 B5 A3 B4 A5 B3 DQ8 B2 OE# B1 DQ0 C6 A6 C5 A7 C4 A18 C3 DQ10 C2 DQ9 C1 DQ1 D2 A19 D1 DQ2 E1 DQ3 F1 VDD G1 DQ12 H2 NC H1 DQ13 D6 A17 D5 WP WP#/ACC #/A E6 NC F6 NC G6 WE# H6 Reset# H5 NC I6 A9 I5 A10 I4 A8 I3 DQ4 I2 DQ5 I1 DQ14 J6 A11 J5 A13 J4 A12 J3 DQ11 J2 DQ6 J1 DQ15 K5 A14 K4 A15 K3 A16 K2 DQ7 K1 VSS
Notes:
1. 2. RY/BY#, Byte# are not available for WFBGA / TFBGA package. It is organized as 1M x 16 (16Mbit)
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
3
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Table 1. PIN DESCRIPTION
Pin Name A0-A19 DQ0-DQ14 DQ15 / A-1 CE# OE# RESET# RY/BY# WE# WP#/ACC Vcc Vss NC BYTE# Addresses 15 Data Inputs/Outputs DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) Chip Enable Output Enable Hardware Reset Pin Ready/Busy Output Write Enable Hardware write protect/acceleration pin Supply Voltage (1.65-1.95V) Ground Not Connected to anything Byte/Word Mode
WP#/ACC Reset# CE# OE# WE# Byte# RY/BY#
Figure 1. LOGIC DIAGRAM
EN39SL160H/L
Function
A0 - A19
DQ0 - DQ15 (A-1)
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
4
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Table 2. Uniform Sector / Block Architecture (Block 24 ~ 31)
Address Range Block Sector (X16) 511 510 509 508 507 506 505 504 503 502 501 500 499 498 497 496 495 30 480 479 29
....
(X8)
Sector Size (Kwords / A19 A18 A17 A16 A15 A14 A13 A12 A11 Kbytes) 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4
....
31
0FF800h-0FFFFFh 1FF000h-1FFFFFh 0FF000h-0FF7FFh 1FE000h-1FEFFFh 0FE800h-0FEFFFh 1FD000h-1FDFFFh 0FE000h-0FE7FFh 1FC000h-1FCFFFh 0FD800h-0FDFFFh 1FB000h-1FBFFFh 0FD000h-0FD7FFh 1FA000h-1FAFFFh 0FC800h-0FCFFFh 1F9000h-1F9FFFh 0FC000h-0FC7FFh 1F8000h-1F8FFFh 0FB800h-0FBFFFh 1F7000h-1F7FFFh 0FB000h-0FB7FFh 1F6000h-1F6FFFh 0FA800h-0FAFFFh 1F5000h-1F5FFFh 0FA000h-0FA7FFh 1F4000h-1F4FFFh 0F9800h-0F9FFFh 1F3000h-1F3FFFh 0F9000h-0F97FFh 1F2000h-1F2FFFh 0F8800h-0F8FFFh 1F1000h-1F1FFFh 0F8000h-0F87FFh 0F7800h-0F7FFFh
....
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
....
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
....
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
....
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
....
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
....
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1
....
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1
....
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
....
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
....
1F0000h-1F0FFFh 1EF000h-1EFFFFh 1E0000h-1E0FFFh 1DF000h-1DFFFFh
.... ....
0F0000h-0F07FFh 0EF800h-0EFFFFh
....
2/4 2/4
....
1 1
....
1 1
....
1 1
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
0 1
....
464 463 28
....
0E8000h-0E87FFh 0E7800h-0E7FFFh
....
1D0000h-1D0FFFh 1CF000h-1CFFFFh
....
2/4 2/4
....
1 1
....
1 1
....
1 1
....
0 0
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
448 447 27
....
0E0000h-0E07FFh 0DF800h-0DFFFFh
....
1C0000h-1C0FFFh 1BF000h-1BFFFFh
....
2/4 2/4
....
1 1
....
1 1
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
0 1
....
0 1
....
432 431 26
....
0D8000h-0D87FFh 0D7800h-0D7FFFh
....
1B0000h-1B0FFFh 1AF000h-1AFFFFh
....
2/4 2/4
....
1 1
....
1 1
....
0 0
....
1 1
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
416 415 25
....
0D0000h-0D07FFh 0CF800h-0CFFFFh
....
1A0000h-1A0FFFh 19F000h-19FFFFh
....
2/4 2/4
....
1 1
....
1 1
....
0 0
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
0 1
....
400 399 398 397
....
0C8000h-0C87FFh 0C7800h-0C7FFFh 0C7000h-0C77FFh 0C6800h-0C6FFFh
....
190000h-190FFFh 18F000h-18FFFFh 18E000h-18EFFFh 18D000h-18DFFFh
....
2/4 2/4 2/4 2/4
....
1 1 1 1
....
1 1 1 1
....
0 0 0 0
....
0 0 0 0
....
1 0 0 0
....
0 1 1 1
....
0 1 1 1
....
0 1 1 0
....
0 1 0 1
....
24
386 385 384
0C1000h-0C17FFh 0C0800h-0C0FFFh 0C0000h-0C07FFh
182000h-182FFFh 181000h-181FFFh 180000h-180FFFh
2/4 2/4 2/4
1 1 1
1 1 1
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
1 0 0
0 1 0
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
5
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Table 2. Uniform Sector / Block Architecture (Block 16 ~ 23)
Address Range Block Sector (X16) 383 382 381 23
....
(X8) 17F000h-17FFFFh 17E000h-17EFFFh 17D000h-17DFFFh
....
Sector Size (Kwords / A19 A18 A17 A16 A15 A14 A13 A12 A11 Kbytes) 2/4 2/4 2/4
....
0BF800h-0BFFFFh 0BF000h-0BF7FFh 0BE800h-0BEFFFh
....
1 1 1
....
0 0 0
....
1 1 1
....
1 1 1
....
1 1 1
....
1 1 1
....
1 1 1
....
1 1 0
....
1 0 1
....
370 369 368 367 22
....
0B9000h-0B97FFh 0B8800h-0B8FFFh 0B8000h-0B87FFh 0B7800h-0B7FFFh
....
172000h-172FFFh 171000h-171FFFh 170000h-170FFFh 16F000h-16FFFFh
....
2/4 2/4 2/4 2/4
....
1 1 1 1
....
0 0 0 0
....
1 1 1 1
....
1 1 1 1
....
1 1 1 0
....
0 0 0 1
....
0 0 0 1
....
1 0 0 1
....
0 1 0 1
....
352 351 21
....
0B0000h-0B07FFh 0AF800h-0AFFFFh
....
160000h-160FFFh 15F000h-15FFFFh
....
2/4 2/4
....
1 1
....
0 0
....
1 1
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
0 1
....
336 335 20
....
0A8000h-0A87FFh 0A7800h-0A7FFFh
....
150000h-150FFFh 14F000h-14FFFFh
....
2/4 2/4
....
1 1
....
0 0
....
1 1
....
0 0
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
320 319 19
....
0A0000h-0A07FFh 09F800h-09FFFFh
....
140000h-140FFFh 13F000h-13FFFFh
....
2/4 2/4
....
1 1
....
0 0
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
0 1
....
0 1
....
304 303 18
....
098000h-0987FFh 097800h-097FFFh
....
130000h-130FFFh 12F000h-12FFFFh
....
2/4 2/4
....
1 1
....
0 0
....
0 0
....
1 1
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
288 287 17
....
090000h-0907FFh 08F800h-08FFFFh
....
120000h-120FFFh 11F000h-11FFFFh
....
2/4 2/4
....
1 1
....
0 0
....
0 0
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
0 1
....
272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256
088000h-0887FFh 087800h-087FFFh 087000h-0877FFh 086800h-086FFFh 086000h-0867FFh 085800h-085FFFh 085000h-0857FFh 084800h-084FFFh 084000h-0847FFh 083800h-083FFFh 083000h-0837FFh 082800h-082FFFh 082000h-0827FFh 081800h-081FFFh 081000h-0817FFh 080800h-080FFFh 080000h-0807FFh
110000h-110FFFh 10F000h-10FFFFh 10E000h-10EFFFh 10D000h-10DFFFh 10C000h-10CFFFh 10B000h-10BFFFh 10A000h-10AFFFh 109000h-109FFFh 108000h-108FFFh 107000h-107FFFh 106000h-106FFFh 105000h-105FFFh 104000h-104FFFh 103000h-103FFFh 102000h-102FFFh 101000h-101FFFh 100000h-100FFFh
2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
16
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
6
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Table 2. Uniform Sector / Block Architecture (Block 8 ~ 15)
Block Sector 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 14
....
Address Range (X16) 07F800h-07FFFFh 07F000h-07F7FFh 07E800h-07EFFFh 07E000h-07E7FFh 07D800h-07DFFFh 07D000h-07D7FFh 07C800h-07CFFFh 07C000h-07C7FFh 07B800h-07BFFFh 07B000h-07B7FFh 07A800h-07AFFFh 07A000h-07A7FFh 079800h-079FFFh 079000h-0797FFh 078800h-078FFFh 078000h-0787FFh 077800h-077FFFh
....
(X8) 0FF000h-0FFFFFh 0FE000h-0FEFFFh 0FD000h-0FDFFFh 0FC000h-0FCFFFh 0FB000h-0FBFFFh 0FA000h-0FAFFFh 0F9000h-0F9FFFh 0F8000h-0F8FFFh 0F7000h-0F7FFFh 0F6000h-0F6FFFh 0F5000h-0F5FFFh 0F4000h-0F4FFFh 0F3000h-0F3FFFh 0F2000h-0F2FFFh 0F1000h-0F1FFFh 0F0000h-0F0FFFh 0EF000h-0EFFFFh
....
15
Sector Size (Kwords / A19 A18 A17 A16 A15 A14 A13 A12 A11 Kbytes) 2/4 0 1 1 1 1 1 1 1 1 2/4 0 1 1 1 1 1 1 1 0 2/4 0 1 1 1 1 1 1 0 1 2/4 0 1 1 1 1 1 1 0 0 2/4 0 1 1 1 1 1 0 1 1 2/4 0 1 1 1 1 1 0 1 0 2/4 0 1 1 1 1 1 0 0 1 2/4 0 1 1 1 1 1 0 0 0 2/4 0 1 1 1 1 0 1 1 1 2/4 0 1 1 1 1 0 1 1 0 2/4 0 1 1 1 1 0 1 0 1 2/4 0 1 1 1 1 0 1 0 0 2/4 0 1 1 1 1 0 0 1 1 2/4 0 1 1 1 1 0 0 1 0 2/4 0 1 1 1 1 0 0 0 1 2/4 2/4
....
0 0
....
1 1
....
1 1
....
1 1
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
224 223 13
....
070000h-0707FFh 06F800h-06FFFFh
....
0E0000h-0E0FFFh 0DF000h-0DFFFFh
....
2/4 2/4
....
0 0
....
1 1
....
1 1
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
0 1
....
208 207 12
....
068000h-0687FFh 067800h-067FFFh
....
0D0000h-0D0FFFh 0CF000h-0CFFFFh
....
2/4 2/4
....
0 0
....
1 1
....
1 1
....
0 0
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
192 191 11
....
060000h-0607FFh 05F800h-05FFFFh
....
0C0000h-0C0FFFh 0BF000h-0BFFFFh
....
2/4 2/4
....
0 0
....
1 1
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
0 1
....
0 1
....
176 175 10
....
058000h-0587FFh 057800h-057FFFh
....
0B0000h-0B0FFFh 0AF000h-0AFFFFh
....
2/4 2/4
....
0 0
....
1 1
....
0 0
....
1 1
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
160 159 9
....
050000h-0507FFh 04F800h-04FFFFh
....
0A0000h-0A0FFFh 09F000h-09FFFFh
....
2/4 2/4
....
0 0
....
1 1
....
0 0
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
0 1
....
144 143 142 141 8
....
048000h-0487FFh 047800h-047FFFh 047000h-0477FFh 046800h-046FFFh
....
090000h-090FFFh 08F000h-08FFFFh 08E000h-08EFFFh 08D000h-08DFFFh
....
2/4 2/4 2/4 2/4
....
0 0 0 0
....
1 1 1 1
....
0 0 0 0
....
0 0 0 0
....
1 0 0 0
....
0 1 1 1
....
0 1 1 1
....
0 1 1 0
....
0 1 0 1
....
130 129 128
041000h-0417FFh 040800h-040FFFh 040000h-0407FFh
082000h-082FFFh 081000h-081FFFh 080000h-080FFFh
2/4 2/4 2/4
0 0 0
1 1 1
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
1 0 0
0 1 0
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
7
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Table 2. Uniform Sector / Block Architecture (Block 0 ~ 7)
Block Sector 127 126 125 7
....
Address Range (X16) 03F800h-03FFFFh 03F000h-03F7FFh 03E800h-03EFFFh
....
Sector Size (Kwords / A19 A18 A17 A16 A15 A14 A13 A12 A11 (X8) Kbytes) 07F000h-07FFFFh 2/4 0 0 1 1 1 1 1 1 1 07E000h-07EFFFh 2/4 0 0 1 1 1 1 1 1 0 07D000h-07DFFFh 2/4 0 0 1 1 1 1 1 0 1
.... .... .... .... .... .... .... .... .... ....
114 113 112 111 6
....
039000h-0397FFh 038800h-038FFFh 038000h-0387FFh 037800h-037FFFh
....
072000h-072FFFh 071000h-071FFFh 070000h-070FFFh 06F000h-06FFFFh
....
2/4 2/4 2/4 2/4
....
0 0 0 0
....
0 0 0 0
....
1 1 1 1
....
1 1 1 1
....
1 1 1 0
....
0 0 0 1
....
0 0 0 1
....
1 0 0 1
....
96 95 5
....
030000h-0307FFh 02F800h-02FFFFh
....
060000h-060FFFh 05F000h-05FFFFh
....
2/4 2/4
....
0 0
....
0 0
....
1 1
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
80 79 4
....
028000h-0287FFh 027800h-027FFFh
....
050000h-050FFFh 04F000h-04FFFFh
....
2/4 2/4
....
0 0
....
0 0
....
1 1
....
0 0
....
1 0
....
0 1
....
0 1
....
0 1
....
64 63 3
....
020000h-0207FFh 01F800h-01FFFFh
....
040000h-040FFFh 03F000h-03FFFFh
....
2/4 2/4
....
0 0
....
0 0
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
0 1
....
48 47 2
....
018000h-0187FFh 017800h-017FFFh
....
030000h-030FFFh 02F000h-02FFFFh
....
2/4 2/4
....
0 0
....
0 0
....
0 0
....
1 1
....
1 0
....
0 1
....
0 1
....
0 1
....
32 31 1
....
010000h-0107FFh 00F800h-00FFFFh
....
020000h-020FFFh 01F000h-01FFFFh
....
2/4 2/4
....
0 0
....
0 0
....
0 0
....
1 0
....
0 1
....
0 1
....
0 1
....
0 1
....
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
008000h-0087FFh 007800h-007FFFh 007000h-0077FFh 006800h-006FFFh 006000h-0067FFh 005800h-005FFFh 005000h-0057FFh 004800h-004FFFh 004000h-0047FFh 003800h-003FFFh 003000h-0037FFh 002800h-002FFFh 002000h-0027FFh 001800h-001FFFh 001000h-0017FFh 000800h-000FFFh 000000h-0007FFh
010000h-010FFFh 00F000h-00FFFFh 00E000h-00EFFFh 00D000h-00DFFFh 00C000h-00CFFFh 00B000h-00BFFFh 00A000h-00AFFFh 009000h-009FFFh 008000h-008FFFh 007000h-007FFFh 006000h-006FFFh 005000h-005FFFh 004000h-004FFFh 003000h-003FFFh 002000h-002FFFh 001000h-001FFFh 000000h-000FFFh
2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
0
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
8
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
....
....
....
....
....
....
....
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
EN39SL160H/L
PRODUCT SELECTOR GUIDE
Product Number Speed Option Full Voltage Range: Vcc=1.65 - 1.95 V EN39SL160H/L -70 70 70 30
Max Access Time, ns (tacc) Max CE# Access, ns (tce) Max OE# Access, ns (toe)
BLOCK DIAGRAM
Vcc Vss
RY/BY#
Block Protect Switches
DQ0-DQ15 (A-1)
Erase Voltage Generator State Control Program Voltage Generator Chip Enable Output Enable Logic
STB
Input/Output Buffers
WE# WP#/ACC
Command Register CE# OE#
Data Latch
Y-Decoder Address Latch
STB
Y-Gating
Vcc Detector
Timer
X-Decoder
Cell Matrix
A0-A19
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
9
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Table 3. OPERATING MODES 16M FLASH USER MODE TABLE
Reset # H H Vcc 0.2V H L VID VID VID WP#/ ACC L/H (Note 1) X X X (Note 1) X (Note 1) A0-A19 (Note 1) AIN AIN X X X AIN
Block Address, A6 =L, A1 = H, A0 = L Block Address, A6 =L, A1 = H, A0 = L
Operation Read Write CMOS Standby Output Disable Hardware Reset Temporary Block Unprotect Block Protect (Note 2) Block Unprotect (Note 2)
CE# L L Vcc 0.2V L X X L L
OE# L H X H X X H H
WE# H L X H X X L L
DQ0DQ7 DOUT DIN High-Z High-Z High-Z DIN DIN DIN
DQ8-DQ15 Byte# Byte# = VIH = VIL DOUT High-Z DIN High-Z High-Z High-Z High-Z DIN X X High-Z High-Z High-Z X X X
L=logic low= VIL, H=Logic High= VIH, VID = VHH =10.0 1.0V, X=Don't Care (either L or H, but not floating!), DIN=Data In, DOUT=Data Out, AIN=Address In, Notes: 1. If WP#/ACC = VIL , the first or last blocks are protected. If WP#/ACC = VIH the first or last block protection depends on whether they were last protected or unprotected. If WP#/ACC = VHH, all blocks will be unprotected. 2. Please refer to " Block / Block Group Protection and Unprotection ", Flowchart 7a and Flowchart 7b.
Table 4. DEVICE IDENTIFICTION (Autoselect Codes) 16M FLASH MANUFACTURER/DEVICE ID TABLE
CE # L L L L L L OE # L L L L L L W E# H H H H H H A19 to A12 X X X A11 to A10 X X X
2
Description Manufacturer ID: Eon Device ID
(top boot block)
A9
A8 H L
1
A7 X X X
A6 L L L
A5 to A2 X X X
A1 L L L
A0 L H H
DQ8 to DQ15 X 27h X 27h X X X
DQ7 to DQ0 1Ch 7Fh 4Ah 4Ah 4Bh 4Bh 01h
(Protected)
VID VID VID
Word Byte Word Byte
X X
Device ID
(bottom boot block)
Block Protection Verification
SA
X
VID
X
X
L
X
H
L
00h
(Unprotected)
Note: 1. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh. A further Manufacturing ID must be read with A8=H. 2. A9 = VID is for HV A9 Autoselect mode only. A9 must be Vcc (CMOS logic level) for Command Autoselect Mode.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
10
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L USER MODE DEFINITIONS
Word / Byte Configuration
The signal set on the BYTE# Pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. When the Byte# Pin is set at logic `1', then the device is in word configuration, DQ15DQ0 are active and are controlled by CE# and OE#. On the other hand, if the Byte# Pin is set at logic `0', then the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
Standby Mode
The EN39SL160H/L has a CMOS-compatible standby mode, which reduces the current to < 0.2A (typical). It is placed in CMOS-compatible standby when the CE# pin is at VCC 0.2. RESET# and BYTE# pin must also be at CMOS input levels. If CE# and RESET# are held at VIH, but not within VCC 0.2V, the device will be in the standby modes, but the standby current will be greater. The outputs are in a high-impedance state independent of the OE# input.
Read Mode
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors/blocks, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more additional information. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the "Reset Command" additional details.
Output Disable Mode
When the OE# pin is at a logic high level (VIH), the output from the EN39SL160H/L is disabled. The output pins are placed in a high impedance state.
Auto Select Identification Mode
The autoselect mode provides manufacturer and device identification, and block protection verification, through identifier codes output on DQ15-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID ( 9.0 V to 11.0 V) on address pin A9. Address pins A8, A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying block protection, the block address must appear on the appropriate highest order address bits. Refer to the corresponding block Address Tables. The Command Definitions table shows the remaining address bits that are don't-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15-DQ0. To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See "Command Definitions" for details on using the autoselect mode.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
11
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Write Mode
Write operations, including programming data and erasing sectors/blocks of memory, require the host system to write a command or command sequence to the device. Write cycles are initiated by placing the byte or word address on the device's address inputs while the data to be written is input on DQ[7:0] in Byte Mode (BYTE# = L) or on DQ[15:0] in Word Mode (BYTE# = H). The host system must drive the CE# and WE# pins Low and the OE# pin High for a valid write operation to take place. All addresses are latched on the falling edge of WE# and CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. The system is not required to provide further controls or timings. The device automatically provides internally generated program / erase pulses and verifies the programmed /erased cells' margin. The host system can detect completion of a program or erase operation by observing the RY/BY# pin, or by reading the DQ[7] (Data# Polling) and DQ[6] (Toggle) status bits. The `Command Definitions' section of this document provides details on the specific device commands implemented in the EN39SL160H/L.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at Vss0.3 V, the device draws CMOS standby current (Icc2). If RESET# is held at VIL but not within Vss0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin will immediately go to a "1" but the actual internal operations may be active until tREADY (During Embedded Algorithms: 20us) amount of time has passed. The system thus must wait at least tREADY amount of time after the RESET# is asserted. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed within a time of tREADY (Not during Embedded Algorithms: 500ns). The system can read data tRH after the RESET# pin returns to VIH. Refer to the DC Characteristics tables Icc3 for RESET# parameters and to the figures at page 26 on datasheet for the timing diagram.
Block /Block Group Protection and Unprotection
The hardware block protection feature disables both program and erase operations in any block. The hardware block unprotection feature re-enables both program and erase operations in previously protected blocks. There are two methods to enabling this hardware protection circuitry. The first one requires only that the RESET# pin be at VID and then standard microprocessor timings can be used to enable or disable this feature. See Flowchart 7a and 7b for the algorithm and Figure 12 for the timings. When doing Block Unprotect, all the other blocks should be protected first. The second method is meant for programming equipment. This method requires VID be applied to both OE# and A9 pin and non-standard microprocessor timings are used. This method is described in a separate document called EN39SL160H/L Supplement, which can be obtained by contacting a representative of Eon Silicon Solution, Inc.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
12
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Table 5. Block/Block Group Organization for (Un)Protection (Block Group 4~7)
Block Group Block
31
Sector
511
....
Address range
(X16) 0FF800h-0FFFFFh
....
(X8) 1FF000h-1FFFFFh 1F0000h-1F0FFFh 1EF000h-1EFFFFh 1E0000h-1E0FFFh 1DF000h-1DFFFFh 1D0000h-1D0FFFh 1CF000h-1CFFFFh 1C0000h-1C0FFFh 1BF000h-1BFFFFh 1B0000h-1B0FFFh 1AF000h-1AFFFFh 1A0000h-1A0FFFh 19F000h-19FFFFh 190000h-190FFFh 18F000h-18FFFFh 180000h-180FFFh 17F000h-17FFFFh 170000h-170FFFh 16F000h-16FFFFh 160000h-160FFFh 15F000h-15FFFFh 150000h-150FFFh 14F000h-14FFFFh 140000h-140FFFh 13F000h-13FFFFh 130000h-130FFFh 12F000h-12FFFFh 120000h-120FFFh 11F000h-11FFFFh 110000h-110FFFh 10F000h-10FFFFh 100000h-100FFFh
.... www.eonssi.com .... .... .... .... .... .... .... .... .... .... .... .... .... .... ....
496 495 30 7 29
....
0F8000h-0F87FFh 0F7800h-0F7FFFh 0F0000h-0F07FFh 0EF800h-0EFFFFh 0E8000h-0E87FFh 0E7800h-0E7FFFh 0E0000h-0E07FFh 0DF800h-0DFFFFh 0D8000h-0D87FFh 0D7800h-0D7FFFh 0D0000h-0D07FFh 0CF800h-0CFFFFh 0C8000h-0C87FFh 0C7800h-0C7FFFh 0C0000h-0C07FFh 0BF800h-0BFFFFh 0B8000h-0B87FFh 0B7800h-0B7FFFh 0B0000h-0B07FFh 0AF800h-0AFFFFh 0A8000h-0A87FFh 0A7800h-0A7FFFh 0A0000h-0A07FFh 09F800h-09FFFFh 098000h-0987FFh 097800h-097FFFh 090000h-0907FFh 08F800h-08FFFFh 088000h-0887FFh 087800h-087FFFh 080000h-0807FFh
.... .... .... .... .... .... .... .... .... .... .... .... .... .... ....
480 479 464 463 28 448 447 27 432 431 26
.... .... ....
6 25
416 415 400 399 24 384 383 23 368 367 22
.... .... ....
5 21
352 351 336 335 20 320 319 19 304 303 18
.... .... ....
4 17
288 287 272 271 16 256
.... ....
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
....
....
....
13
(c)2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Table 5. Block/Block Group Organization for (Un)Protection (Block Group 0~3)
Block Group Block
15
Sector
255
....
Address range
(X16) 07F800h-07FFFFh
....
(X8) 0FF000h-0FFFFFh 0F0000h-0F0FFFh 0EF000h-0EFFFFh 0E0000h-0E0FFFh 0DF000h-0DFFFFh 0D0000h-0D0FFFh 0CF000h-0CFFFFh 0C0000h-0C0FFFh 0BF000h-0BFFFFh 0B0000h-0B0FFFh 0AF000h-0AFFFFh 0A0000h-0A0FFFh 09F000h-09FFFFh 090000h-090FFFh 08F000h-08FFFFh 080000h-080FFFh 07F000h-07FFFFh 070000h-070FFFh 06F000h-06FFFFh 060000h-060FFFh 05F000h-05FFFFh 050000h-050FFFh 04F000h-04FFFFh 040000h-040FFFh 03F000h-03FFFFh 030000h-030FFFh 02F000h-02FFFFh 020000h-020FFFh 01F000h-01FFFFh 010000h-010FFFh 00F000h-00FFFFh 000000h-000FFFh
.... www.eonssi.com .... .... .... .... .... .... .... .... .... .... .... .... .... .... ....
240 239 14 3 13
....
078000h-0787FFh 077800h-077FFFh 070000h-0707FFh 06F800h-06FFFFh 068000h-0687FFh 067800h-067FFFh 060000h-0607FFh 05F800h-05FFFFh 058000h-0587FFh 057800h-057FFFh 050000h-0507FFh 04F800h-04FFFFh 048000h-0487FFh 047800h-047FFFh 040000h-0407FFh 03F800h-03FFFFh 038000h-0387FFh 037800h-037FFFh 030000h-0307FFh 02F800h-02FFFFh 028000h-0287FFh 027800h-027FFFh 020000h-0207FFh 01F800h-01FFFFh 018000h-0187FFh 017800h-017FFFh 010000h-0107FFh 00F800h-00FFFFh 008000h-0087FFh 007800h-007FFFh 000000h-0007FFh
.... .... .... .... .... .... .... .... .... .... .... .... .... .... ....
224 223 208 207 12 192 191 11 176 175 10
.... .... ....
2 9
160 159 144 143 8 128 127 7 112 111 6
.... .... ....
1 5
96 95 80 79 4 64 63 3 48 47 2
.... .... ....
0 1
32 31 16 15 0
.... ....
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
....
....
....
0
14
(c)2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Write Protect / Accelerated Program (WP# / ACC)
The WP#/ACC pin provides two functions. The Write Protect (WP#) function provides a hardware method of protecting the first or last 64K-byte Block. The ACC function allows faster manufacturing throughput at the factory, using an external high voltage. When WP#/ACC is Low, the device protects the first or last 64K-byte Block; no matter the blocks are protected or unprotected using the method described in "Block/Block Group Protection & Chip Unprotection", Program and Erase operations in these blocks are ignored. When WP#/ACC is High, the device reverts to the previous protection status of the first or last 64K-byte Block. Program and Erase operations can now modify the data in the first or last 64K-byte Block unless the block is protected using Block Protection. When WP#/ACC is raised to VHH the memory automatically enters the Accelerated Program mode, this mode permit the system to skip the normal command unlock sequences and program byte/word locations directly to reduces the time required for program operation. When WP#/ACC returns to VIH or VIL normal operation resumes. The transitions from VIH or VIL to VHH and from VHH to VIH or VIL must be slower than tVHH, see Figure 14. Note that the WP#/ACC pin must not be left floating or unconnected. In addition, WP#/ACC pin must not be at VHH for operations other than accelerated programming. It could cause the device to be damaged. Never raise this pin to VHH from any mode except Read mode. Otherwise the memory may be left in an indeterminate state. A 0.1F capacitor should be connected between the WP#/ACC pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Accelerated Program mode.
Temporary Block Unprotect
This feature allows temporary unprotection of previously protected block groups to change data while in-system. The Block Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected blocks can be programmed or erased by simply selecting the Block addresses. Once is removed from the RESET# pin, all the previously protected blocks are protected again. See accompanying figure and timing diagrams for more details.
Notes: 1. All protected blocks unprotected. 2. Previously protected blocks protected again.
Start Reset#=VID (note 1) Perform Erase or Program Operations Reset#=VIH Temporary Block Unprotect Completed (note 2)
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tacc + 30ns. The automatic sleep mode is independent of the CE#, WE# and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output is latched and always available to the system. Icc5 in the DC Characteristics table represents the automatic sleep mode current specification.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
15
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
COMMON FLASH INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 5-7. In word mode, the upper address bits (A7-MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode and the system can read CFI data at the addresses given in Tables 6-8. The system must write the reset command to return the device to the autoselect mode.
Table 6. CFI Query Identification String (1)
Adresses (Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Adresses (Byte Mode) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
1. Refer to CFI publication 100 for more details.
Table 7. System Interface String
Addresses (Word Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Addresses (Byte Mode) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0016h 0020h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h Description Vcc Min (write /erase) DQ7-DQ4: volts, DQ3 -DQ0: 100 millivolts Vcc Max (write /erase) DQ7-DQ4: volts, DQ3 -DQ0: 100 millivolts Vpp Min. voltage (00h = no Vpp pin present) Vpp Max. voltage (00h = no Vpp pin present) Typical timeout per single byte/word program 2^N s Typical timeout for Min, size buffer write 2^N s (00h = not supported) Typical timeout per individual sector/block erase 2^N ms Typical timeout for full chip erase 2^N ms (00h = not supported) Max. timeout for byte/word write 2^N times typical Max. timeout for buffer write 2^N times typical Max. timeout per individual sector/block erase 2^N times typical Max timeout for full chip erase 2^N times typical (00h = not supported)
16
(c)2004 Eon Silicon Solution, Inc., www.eonssi.com
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Table 8. Device Geometry Definition
Addresses (Word mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h Addresses (Byte Mode) 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h Data 0015h 0002h 0000h 0000h 0000h 0002h 00FFh 0001h 0010h 0000h 001Fh 0000h 0000h 0001h Description Device Size = 2^N byte Flash Device Interface description; 0002h = x8/x16 asynchronous interface. Max. number of byte in multi-byte write = 2^N (00h = not supported) Number of Erase Sector/Block Regions within device Erase Sector Region 1 Information (y+1 = Number of sectors; z x 256B = sector size) y = 511 + 1 = 512 sectors (01FFh = 511) z = 16 x 256 Bytes = 4 KByte/sector (0010h = 16) Erase Block Region 2 Information (y+1 = Number of blocks; z x 256B = block size) y = 31 + 1 = 32 blocks (001Fh = 31) z = 256 x 256 Bytes = 64 KByte/block (0100h = 256)
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise.
Low VCC Write Inhibit
When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than VLKO.
Write Pulse "Glitch" protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all logical zero (not recommended usage), it will be considered a read.
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE# = VIL, WE# = VIL and OE# = VIH, the device will not accept commands on the rising edge of WE#.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
17
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L COMMAND DEFINITIONS
The operations of EN39SL160H/L are selected by one or more commands written into the command register to perform Read/Reset Memory, Read ID, Read Block Protection, Program, Sector/Block Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 9). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode.
Table 9. EN39SL160H/L Command Definitions
Bus Cycles Command Sequence Read Reset Manufacturer ID Device ID Top Boot Device ID Bottom Boot Block Protect Verify Program Chip Erase Block Erase Sector Erase Erase Suspend Erase Resume CFI Query Word Byte Autoselect Word 4 Byte Word Byte Word Byte Word 4 Byte Word Byte Word Byte Word Byte Word Byte 4 6 6 6 1 1 1 AAA 555 AAA 555 AAA 555 AAA 555 AAA xxx xxx 55 AA AA AA AA AA B0 30 98 4 4 AAA 555 AAA 555 AAA 555 AA 555 2AA 555 2AA 555 2AA 555 2AA 555 55 55 55 55 AA AA
Cycles
1 RA xxx 555
st
2 RD F0 2AA AA 555 2AA 555 2AA 555 2AA
nd
3
rd
4
th
5
th
6
th
Cycle Addr Data
Cycle Addr Data
Cycle Addr Data
Cycle Addr Data
Cycle Addr Data
Cycle Addr Data
1 1
555 55 AAA 55 55 555 AAA 555 AAA 555 55 AAA 555 AAA 555 AAA 555 AAA 555 AAA A0 80 80 80 90 90 90 90
000 100 000 200 X01 X02 X01 X02 (BA) X02 (BA) X04 PA 555 AAA 555 AAA 555 AAA
7F 1C 7F 1C 274A 4A 274B 4B XX00 XX01 00 01 PD AA AA AA 2AA 555 2AA 555 2AA 555 55 55 55 555 AAA BA SA 10 50 30
Address and Data values indicated in hex RA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don't-Care PD = Program Data: data to be programmed at location PA BA = Block Address: address of the Block to be erased or verified. Address bits A19-A15 uniquely select any Block SA = Sector Address: address of the Sector to be erased or verified. Address bits A19-A11 uniquely select any Sector
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
18
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Reading Array Data
The device is automatically set to reading array data after power up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. Following an Erase Suspend command, Erase Suspend mode is entered. The system can read array data using the standard read timings, with the only difference in that if it reads at an address within erase suspended sectors/blocks, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See next section for details on Reset.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don'tcare for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a block is protected. The Command Definitions table shows the address and data requirements. This is an alternative to the method that requires VID on address bit A9 and is intended for PROM programmers. Two unlock cycles followed by the autoselect command initiate the autoselect command sequence. Autoselect mode is then entered and the system may read at addresses shown in Table 4 any number of times, without needing another command sequence. The system must write the reset command to exit the autoselect mode and return to reading array data.
Word / Byte Programming Command
The device may be programmed by byte or by word, depending on the state of the Byte# Pin. Programming the EN39SL160H/L is performed by using a four bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. An internal timer terminates the program operation automatically. Address is latched on the falling edge of CE# or WE#, whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first. Programming status may be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle bit). When the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. Note that data can not be programmed from a 0
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
19
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
to a 1. Only an erase operation can change a data from 0 to 1. When programming time limit is exceeded, DQ5 will produce a logical "1" and a Reset command can return the device to Read mode.
Chip Erase Command
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Chip Erase algorithm are ignored. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See "Write Operation Status" for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to the Chip, Sector/Block Erase Operation Timings for timing waveforms.
Sector/Block Erase Command Sequence
Sector/Block erase is a six bus cycle operation. The sector/block erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector/block to be erased, and the sector/block erase command. The Command Definitions table shows the address and data requirements for the sector/block erase command sequence. Once the sector/block erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to "Write Operation Status" for information on these status bits. Flowchart 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to the Sector/Block Erase Operations Timing diagram for timing waveforms.
Erase Suspend / Resume Command
The Erase Suspend command allows the system to interrupt a sector/block erase operation and then read data from, or program data to, any sector/block not selected for erasure. This command is valid only during the sector/block erase operation. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Addresses are don't-cares when writing the Erase Suspend command. When the Erase Suspend command is written during a sector/block erase operation, the device requires a maximum of 20 s to suspend the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector/block not selected for erasure. (The device "erase suspends" all sector/blocks selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors/blocks produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector/block is actively erasing or is erase-suspended. See "Write Operation Status" for information on these status bits.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
20
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors/blocks. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The Autoselect command is not supported during Erase Suspend Mode. The system must write the Erase Resume command (address bits are don't-care) to exit the erase suspend mode and continue the sector/block erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.
WRITE OPERATION STATUS
DQ7: DATA# Polling
The EN39SL160H/L provides DATA# polling on DQ7 to indicate the status of the embedded operations. The DATA# Polling feature is active during the embedded Programming, Sector/Block Erase, Chip Erase, and Erase Suspend. (See Table 6) When the embedded Programming is in progress, an attempt to read the device will produce the complement of the data last written to DQ7. Upon the completion of the embedded Programming, an attempt to read the device will produce the true data written to DQ7. For the embedded Programming, DATA# polling is valid after the rising edge of the fourth WE# or CE# pulse in the four-cycle sequence. When the embedded Erase is in progress, an attempt to read the device will produce a "0" at the DQ7 output. Upon the completion of the embedded Erase, the device will produce the "1" at the DQ7 output during the read cycles. For Chip Erase, the DATA# polling is valid after the rising edge of the sixth WE# or CE# pulse in the six-cycle sequence. DATA# polling is valid after the last rising edge of the WE# or CE# pulse for chip erase or sector/block erase. DATA# Polling must be performed at any address within a sector/block that is being programmed or erased and not a protected sector/block. Otherwise, DATA# polling may give an inaccurate result if the address used is in a protected block. Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the output enable (OE#) is low. This means that the device is driving status information on DQ7 at one instant of time and valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status of valid data. Even if the device has completed the embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 will be read on the subsequent read attempts. The flowchart for DATA# Polling (DQ7) is shown on Flowchart 5. The DATA# Polling (DQ7) timing diagram is shown in Figure 8.
RY/BY#: Ready/Busy
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or completed. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to Vcc. In the output-low period, signifying Busy, the device is actively erasing or programming. This includes programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
21
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
DQ6: Toggle Bit I
The EN39SL160H/L provides a "Toggle Bit" on DQ6 to indicate to the host system the status of the embedded programming and erase operations. (See Table 6) During an embedded Program or Erase operation, successive attempts to read data from the device at any address (by active OE# or CE#) will result in DQ6 toggling between "zero" and "one". Once the embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During embedded Programming, the Toggle Bit is valid after the rising edge of the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is valid after the rising edge of the sixth WE# pulse for sector/block erase or chip erase. In embedded Programming, if the block being written to is protected, DQ6 will toggles for about 2 s, then stop toggling without the data in the block having changed. In Sector/Block Erase or Chip Erase, if all selected blocks are protected, DQ6 will toggle for about 100 s. The chip will then return to the read mode without changing data in all protected blocks. The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown in Figure 9.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the device has successfully completed its operation and has returned to read mode, the user must check again to see if the DQ6 is toggling after detecting a "1" on DQ5. The DQ5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data.
DQ3: Sector/Block Erase Timer
After writing a sector/block erase command sequence, the output on DQ3 can be used to determine whether or not an erase operation has begun. (The sector/block erase timer does not apply to the chip erase command.) When sector/block erase starts, DQ3 switches from "0" to "1." This device does not support multiple sector/block erase command sequences so it is not very meaningful since it immediately shows as a "1" after the first 30h command. Future devices may support this feature.
DQ2: Erase Toggle Bit II
The "Toggle Bit" on DQ2, when used with DQ6, indicates whether a particular sector/block is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector/block is erasesuspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors/blocks that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector/block is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors/blocks are selected for erasure. Thus, both status bits are required for sector/block and mode information. Refer to the following table to compare outputs for DQ2 and DQ6.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
22
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Flowchart 6 shows the toggle bit algorithm, and the section "DQ2: Toggle Bit" explains the algorithm. See also the "DQ6: Toggle Bit I" subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Flowchart 6).
Write Operation Status
Operation Standar d Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector/Block Reading within Non-Erase Suspended Sector/Block Erase-Suspend Program DQ7 (note2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No Toggle Data Toggle DQ5 (note1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (note2) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0
Erase Suspend Mode
1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See "DQ5:Exceeded Timing Limits" for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
23
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Table 10. Status Register Bits
DQ Name Logic Level `1' 7 Definition Erase Complete or erase Sector/Block in Erase suspend Erase On-Going Program Complete or data of non-erase Sector/Block during Erase Suspend Program On-Going Erase or Program On-going Read during Erase Suspend Erase Complete Program or Erase Error Program or Erase On-going Erase operation start Erase timeout period on-going Chip Erase, Sector/Block Erase or Erase suspend on currently addressed Sector/Block. (When DQ5=1, Erase Error due to currently addressed Sector/Block. Program during Erase Suspend on-going at current address Erase Suspend read on non Erase Suspend Sector/Block
DATA#
POLLING
`0' DQ7 DQ7#
6
TOGGLE BIT TIME OUT BIT ERASE TIME OUT BIT
`-1-0-1-0-1-0-1-' DQ6 `-1-1-1-1-1-1-1-` `1' `0' `1' `0'
5 3
`-1-0-1-0-1-0-1-' 2 TOGGLE BIT DQ2
Notes:
DQ7 DATA# Polling: indicates the P/E C status check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success. DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive reads output complementary data on DQ6 while programming or Erase operation are on-going. DQ5 Time Out Bit: set to "1" if failure in programming or erase DQ3 Sector/Block Erase Command Timeout Bit :Operation has started. Only possible command is Erase suspend (ES). DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector/Block
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
24
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L EMBEDDED ALGORITHMS
Flowchart 1. Embedded Program
START
Write Program Command Sequence (shown below)
Data# Poll Device
Verify Data?
Increment Address
No
Last Address? Yes Programming Done
Flowchart 2. Embedded Program Command Sequence
See the Command Definitions section for more information on WORD mode.
555H / AAH
2AAH / 55H
555H / A0H
PROGRAM ADDRESS / PROGRAM DATA
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
25
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Flowchart 3. Embedded Erase
START
Write Erase Command Sequence
Data Poll from System or Toggle Bit successfully completed
Data =FFh? No Yes Erase Done
Flowchart 4. Embedded Erase Command Sequence
See the Command Definitions section for more information on WORD mode.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
26
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Flowchart 5. DATA# Polling Algorithm
Start
Read Data
DQ7 = Data? No No DQ5 = 1? Yes Read Data (1)
Yes
Notes: (1) This second read is necessary in case the first read was done at the exact instant when the status data was in transition.
DQ7 = Data? No Fail
Yes
Pass
Flowchart 6. Toggle Bit Algorithm
Start
Read Data twice
DQ6 = Toggle? Yes No DQ5 = 1? Yes Read Data twice (2)
No
DQ6 = Toggle?
No
Notes: (2) This second set of reads is necessary in case the first set of reads was done at the exact instant when the status data was in transition.
Yes Fail Pass
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
27
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Flowchart 7a. In-System Block Protect Flowchart
START PLSCNT = 1 RESET# = VID Wait 1 s
No Temporary Sector Unprotect Mode
First Write Cycle = 60h? Yes Set up sector address
Block Protect: Write 60h to sector addr with A6 = 0, A1 = 1, A0 = 0
Wait 150 s
Increment PLSCNT
Verify Block Protect: Write 40h to block address with A6 = 0, A1 = 1, A0 = 0 Wait 0.4 s Read from block address with A6 = 0, A1 = 1, A0=0
Reset PLSCNT = 1
No No
PLSCNT = 25?
Data = 01h? Yes
Yes
Device failed Protect another block? No Remove VID from RESET# Write reset command Yes
Block Protect Algorithm
Block Protect complete
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
28
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Flowchart 7b. In-System Block Unprotect Flowchart
START
PLSCNT = 1 Protect all blocks: The indicated portion of the block protect algorithm must be performed for all unprotected blocks prior to issuing the first block unprotect address (see Diagram 7a.) RESET# = VID Wait 1 S
No First Write Cycle = 60h? Yes No All blocks protected? Yes Set up first block address Block Unprotect: Write 60H to block address with A6 = 1, A1 = 1, A0 = 0
Temporary Block Unprotect Mode
Wait 15 ms
Increment PLSCNT
Verify Block Unprotect: Write 40h to block address with A6 = 1, A1 = 1, A0 =0
Wait 0.4 S
No
Read from block address with A6 = 1, A1 = 1, A0 = 0
PLSCNT = 1000? Yes Device failed
No
Data = 00h? Yes No
Set up next block address
Last block verified? Yes
Block Unprotect Algorithm
Remove VID from RESET#
Write reset command
Block Unprotect complete
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
29
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Table 11. DC Characteristics
(Ta = - 40C to 85C; VCC = 1.65-1.95V)
Symbol ILI ILO ICC1 ICC2 ICC3 ICC4 ICC5 VIL VIH VOL VOH VID IID VLKO
Parameter Input Leakage Current Output Leakage Current Active Read Current (Byte mode) Active Read Current (Word mode) Supply Current (Standby) VCC , Reset Current Supply Current (Program or Erase) Automatic Sleep Mode Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage A9 Voltage (Electronic Signature) A9 Current (Electronic Signature) Supply voltage (Erase and Program lock-out)
Test Conditions 0V VIN Vcc 0V VOUT Vcc CE# = VIL, OE# = VIH, F=5MHz CE# = BYTE# = RESET# = Vcc (Note 1) CE# = BYTE# = RESET# = Vcc (Note 1) Program or Erase in progress VIH = Vcc 0.2 V VIL = Vss 0.2 V
Min
Typ
Max 3 3
Unit A A mA mA A A mA A V V V V
5 5 0.2 0.2 15 0.2 -0.5 0.7 x Vcc
10 10 5.0 5.0 25 5.0 0.3 x VCC Vcc + 0.3 0.1
IOL = 100 A IOH = -100 A, Vcc 0.1 9.0 A9 = VID 1.2 10.0
11.0 50 1.5
V A V
Notes
1. BYTE# pin can also be GND 0.3V. BYTE# and RESET# pin input buffers are always enabled so that they
draw power if not at full CMOS supply voltages.
2. Maximum IBCC specifications are tested with Vcc = Vcc max.
B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
30
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Test Conditions
Test Specifications
Test Conditions Output Load Capacitance, CL Input Rise and Fall times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels -70 30 5 0.0-2.0 1/2 Vcc 1/2 Vcc Unit pF ns V V V
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
31
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
AC CHARACTERISTICS Hardware Reset (Reset#)
(Ta = - 40C to 85C; VCC = 1.65-1.95V)
Paramete r Std tRP1 tRP2 tRH tRB1 tRB2 tREADY1 tREADY2
Description
RESET# Pulse Width (During Embedded Algorithms) RESET# Pulse Width (NOT During Embedded Algorithms) Reset# High Time Before Read RY/BY# Recovery Time ( to CE#, OE# go low) RY/BY# Recovery Time ( to WE# go low) Reset# Pin Low (During Embedded Algorithms) to Read or Write Reset# Pin Low (NOT During Embedded Algorithms) to Read or Write
Test Setup Min Min Min Min Min Max Max
Speed -70 10 500 50 0 50 20 500
Unit us ns ns ns ns us ns
Figure 1. AC Waveforms for RESET# Reset# Timings
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
32
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
AC CHARACTERISTICS Word / Byte Configuration (Byte#)
(Ta = - 40C to 85C; VCC = 1.65-1.95V)
Std Parameter tBCS tCBH tRBH
Description Byte# to CE# switching setup time CE# to Byte# switching hold time RY/BY# to Byte# switching hold time Min Min Min
Speed -70 0 0 0
Unit ns ns ns
Figure 2. AC Waveforms for BYTE#
CE#
OE#
Byte#
tBCS
tCBH
Byte# timings for Read Operations
CE#
WE#
Byte# tBCS RY/BY# Byte #timings for Write Operations
Note: Switching BYTE# pin not allowed during embedded operations
tRBH
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
33
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Table 12. AC CHARACTERISTICS
(Ta = - 40C to 85C; VCC = 1.65-1.95 V)
Read-only Operations Characteristics
Parameter Symbols JEDEC Standard Description Test Setup Min CE# = VIL OE# = VIL OE# = VIL Max Max Max Max Max Min Min Min Speed Options -70 Read Cycle Time Address to Output Delay Chip Enable To Output Delay Output Enable to Output Delay Chip Enable to Output High Z Output Enable to Output High Z Output Hold Time from Addresses, CE# or OE#, whichever occurs first Output Enable Hold Time Read Toggle and Data# Polling 70 70 70 30 20 20 0 0 10 ns ns ns ns ns ns ns ns ns Unit
tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX
tRC tACC tCE tOE tDF tDF tOH tOEH
Notes:
1. High Z is Not 100% tested.
2. For - 70 Vcc =1.65 - 1.95V Output Load : 30pF Input Rise and Fall Times: 5ns Input Rise Levels: 0.0 V to Vcc Timing Measurement Reference Level, Input and Output: 1/2 Vcc Vcc =1.65 - 1.95V Output Load: 100 pF Input Rise and Fall Times: 5 ns Input Pulse Levels: 0.0 V to Vcc Timing Measurement Reference Level, Input and Output: 1/2 Vcc
3. For all others:
Figure 3. AC Waveforms for READ Operations
tBRCB
Addresses CE#
Addresses Stable
tBACC tBOEB tBOEHB tBCEB tBOH
Output Valid HIGH Z
tBDF
OE#
WE#
Outputs RESET#
HIGH Z
RY/BY#
0V
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
34
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Table 13. AC CHARACTERISTICS
(Ta = - 40C to 85C; VCC = 1.65-1.95V)
Write (Erase/Program) Operations
Parameter Symbols JEDEC Standard Speed Options -70 Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Programming Operation (Note 2) Byte Word Sector Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ Typ Min Min Max 70 0 45 30 0 0 0 0 0 35 20 5 7 0.09 0.4 7 50 0 70 Unit ns ns ns ns ns ns ns ns ns ns ns s s s s s s ns ns
Description
tAVAV tAVWL tWLAX tDVWH tWHDX
tWC tAS tAH tDS tDH tOES
tGHWL tELWL tWHEH tWLWH tWHDL tWHWH1
tGHWL tCS tCH tWP tWPH tWHWH1
tWHWH2
tWHWH2 tVCS tRB tBUSY
Erase Operation (Note 2)
Block Chip
Vcc Setup Time (Note 1) Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay
Notes: 1. Not 100% tested. 2. See Erase and Programming Performance for more information.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
35
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Table 14. AC CHARACTERISTICS
(Ta = - 40C to 85C; VCC = 1.65-1.95V)
Write (Erase/Program) Operations
Alternate CE# Controlled Writes Parameter Symbols JEDEC Standard Description Min Min Min Min Min Min Min Min Min Min Min Byte Word Sector Block Chip Typ Typ Typ Typ Typ. Speed Options -70 Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time before Write (OE# High to CE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Programming Operation (Note 2) 70 0 45 30 0 0 0 0 0 35 20 5 7 0.09 0.4 7 Unit ns ns ns ns ns ns ns ns ns ns ns s s s s s
tAVAV tAVEL tELAX tDVEH tEHDX
tWC tAS tAH tDS tDH tOES
tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1
tGHEL tWS tWH tCP tCPH tWHWH1
tWHWH2
tWHWH2
Erase Operation (Note 2)
Notes: 1. Not 100% tested. 2. See Erase and Programming Performance for more information.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
36
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Table 15. ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Block Erase Time Chip Erase Time Word Programming Time Chip Programming Time Erase/Program Endurance Typ 0.09 0.18 4 8 8 100K Limits Max 0.4 2 35 200 11 cycles Minimum 100K cycles Unit sec sec sec s Excludes system level overhead Excludes 00H programming prior to erasure Comments
Table 16. 48-PIN TSOP PIN CAPACITANCE @ 25C, 1.0MHz
( VCC = 1.65-1.95V)
Parameter Symbol CIN COUT CIN2
Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance
Test Setup VIN = 0 VOUT = 0 VIN = 0
Typ 6 8.5 7.5
Max 7.5 12 9
Unit pF pF pF
Table 17. DATA RETENTION
Parameter Description Data Retention Time Test Conditions 150C 125C Min 10 20 Unit Years Years
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
37
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L AC CHARACTERISTICS
Figure 4. AC Waveforms for Chip Erase Operations Timings
Erase Command Sequence (last 2 cycles) Read Status Data (last two cycles)
tWC Addresses CE# tGHWL OE# tWP WE# tCS 0x55 tDS RY/BY# VCC tDH tCH 0x2AA
tAS 0x555
tAH VA VA
tWPH 0x10 tBUSY
tWHWH2 Status DOUT tRB
Data
tVCS
Notes: 1. VA=Valid Address for reading status, Dout=true data at read address. 2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command sequence.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
38
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L AC CHARACTERISTICS
Figure 5. AC Waveforms for Block Erase Operations Timings
Erase Command Sequence (last 2 cycles) Read Status Data (last two cycles)
tWC Addresses CE# tGHWL OE# tWP WE# tCS 0x55 tDS RY/BY# VCC tDH tCH 0x2AA
tAS BA
tAH VA VA
tWPH 0x50 tBUSY
tWHWH2 Status DOUT tRB
Data
tVCS
Notes: 1. BA=Block Address (for block erase), VA=Valid Address for reading status, Dout=true data at read address. 2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command sequence.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
39
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Figure 6. AC Waveforms for Sector Erase Operations Timings
Erase Command Sequence (last 2 cycles) Read Status Data (last two cycles)
tWC Addresses CE# tGHWL OE# tWP WE# tCS 0x55 tDS RY/BY# VCC tDH tCH 0x2AA
tAS SA
tAH VA VA
tWPH 0x30 tBUSY
tWHWH2 Status DOUT tRB
Data
tVCS
Notes: 1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, Dout=true data at read address. 2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command sequence.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
40
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Figure 7. Program Operation Timings
Program Command Sequence (last 2 cycles) Program Command Sequence (last 2 cycles)
tWC Addresses CE# tGHWL OE# WE# tCS Data tDS RY/BY# OxA0 tDH tWP tCH 0x555
tAS PA
tAH PA PA
tWPH PD tBUSY
tWHWH1 Status DOUT tRB
tVCS
VCC
Notes: 1. PA=Program Address, PD=Program Data, DOUT is the true data at the program address. 2. VCC shown in order to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
41
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Figure 8. AC Waveforms for /DATA Polling During Embedded Algorithm Operations
tRC Addresses tCH CE# VA tACC tCE tOE OE# tOEH tDF tOH VA VA
WE#
DQ[7]
Complement
Comple -ment
True
Valid Data
DQ[6:0] tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Notes: 1. VA=Valid Address for reading Data# Polling status data 2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.
Figure 9. AC Waveforms for Toggle Bit During Embedded Algorithm Operations
tRC Addresses tCH CE# VA tACC tCE tOE OE# tOEH tDF VA VA VA
WE#
tOH
Valid Status
Valid Status
DQ6, DQ2 tBUSY RY/BY#
Valid Status (stops toggling)
Valid Data
(first read)
(second read)
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
42
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Figure 10. Alternate CE# Controlled Write Operation Timings
0x555 for Program 0x2AA for Erase PA for Program SA for Sector Erase BA for Block Erase 0x555 for Chip Erase
Addresses tWC WE# tGHEL OE# tWS CE# tDS Data
0xA0 for Program
PD for Program 0x30 for Sector Erase 0x50 for Block Erase 0x10 for Chip Erase
VA tAS tAH
tWH tCP tCPH tWHWH1 / tWHWH2 tBUSY
Status DOUT
tDH
RY/BY tRH Reset#
Notes: PA = address of the memory location to be programmed. PD = data to be programmed at byte address. VA = Valid Address for reading program or erase status Dout = array data read at VA Shown above are the last two cycles of the program or erase command sequence and the last status read cycle Reset# shown to illustrate tRH measurement references. It cannot occur as shown during a valid command sequence.
Figure 11. DQ2 vs. DQ6
Enter Embedded Erase Erase Suspend Enter Erase Suspend Program Enter Suspend Read Enter Suspend Program Erase Resume
WE#
Erase
Erase Suspend Read
Erase
Erase Complete
DQ6
DQ2
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
43
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Figure 12. Block Protect/Unprotect Timing Diagram
VID
RESET#
Vcc 0V 0V
tVIDR
tVIDR
SA, A6,A1,A0 Data 60h
Valid 60h
Valid 40h Verify >0.4S
Valid Status
Block Protect/Unprotect CE# WE# >1S OE#
Block Protect: 150 uS Block Unprotect: 15 mS
Notes: Use standard microprocessor timings for this device for read and write cycles. For Block Protect, use A6=0, A1=1, A0=0. For Block Unprotect, use A6=1, A1=1, A0=0.
Temporary Block Unprotect
Parameter Std tVIDR Description Min Min Speed Option -70 500 4 Unit ns
s
VID Rise and Fall Time RESET# Setup Time for Temporary tRSP Block Unprotect(Note) Notes: tRSP is Not 100% tested.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
44
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Figure 13. Temporary Block Unprotect Timing Diagram
VID
RESET#
0 or 2 V
0 or 2 V tVIDR tVIDR
CE#
WE# tRSP
RY/BY#
Write Protect / Accelerated Program Figure 14. Accelerated Program Timing Diagram
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
45
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
FIGURE 15. 48L TSOP 12mm x 20mm package outline
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
46
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Figure 16. 48L TFBGA 6mm x 8mm package outline
SYMBOL A A1 A2 D E D1 E1 e
DIMENSION IN MM MIN. --0.23 0.84 7.90 5.90 ------NOR --0.29 0.91 8.00 6.00 5.60 4.00 0.80 MAX 1.30 ----8.10 6.10 ------0.45
b 0.35 0.40 Note : 1. Coplanarity: 0.1 mm
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
47
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Figure 17. 48L WFBGA 4mm x 6mm package outline
Note : Controlling dimensions are in millimeters (mm).
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
48
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Plastic Packages Ambient Temperature With Power Applied Output Short Circuit Current1 A9, OE#, Reset# 2 Voltage with Respect to Ground All other pins 3 Value -65 to +150 -65 to +125 -55 to +125 200 -0.5 to +11.5 -0.5 to Vcc+0.5 Unit mA V V
Vcc
-0.5 to + Vcc+0.5
V
Notes: 1. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. 2. Minimum DC input voltage on A9, OE#, RESET# pins is -0.5V. During voltage transitions, A9, OE#, RESET# pins may undershoot Vss to -1.0V for periods of up to 50ns and to -2.0V for periods of up to 20ns. See figure below. Maximum DC input voltage on A9, OE#, and RESET# is 11.5V which may overshoot to 12.5V for periods up to 20ns. 3. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may undershoot Vss to -1.0V for periods of up to 50ns and to -2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5 V. During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure below. 4. Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability.
RECOMMENDED OPERATING RANGES1
Parameter Ambient Operating Temperature Industrial Devices Value -40 to 85 Unit
Operating Supply Voltage Vcc
Full Voltage Range: 1.65 to 1.95
V
1. Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
0
Vcc +2.0V
0
Maximum Negative Overshoot Waveform
Maximum Positive Overshoot Waveform
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
49
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L Purpose
Eon Silicon Solution Inc. (hereinafter called "Eon") is going to provide its products' top marking on ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the compositions of the ICs. Eon is still keeping the promise of quality for all the products with the same as that of Eon delivered before. Please be advised with the change and appreciate your kindly cooperation and fully support Eon's product family.
Eon products' New Top Marking
cFeon Top Marking Example:
cFeon
Part Number: XXXX-XXX Lot Number: XXXXX Date Code: XXXXX
For More Information
Please contact your local sales office for additional information about Eon memory solutions.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
50
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
ORDERING INFORMATION
EN39SL160 H 70 B I P
PACKAGING CONTENT (Blank) = Conventional P = RoHS compliant
TEMPERATURE RANGE I = Industrial (-40C to +85C)
PACKAGE T = 48-pin TSOP B = 48-Ball Thin Fine Pitch Ball Grid Array (TFBGA) 0.8mm pitch, 6mm x 8mm package N = 48-Ball Very-Very-Thin-Profile Fine Pitch Ball Grid Array (WFBGA) 0.5mm pitch, 4mm x 6mm package
SPEED 70 = 70ns
BOOT CODE SECTOR ARCHITECTURE H = Highest address block protected L = Lowest address block protected
BASE PART NUMBER EN = Eon Silicon Solution Inc. 39SL = 1.8V Serial 4KByte Uniform-Sector FLASH 160 = 16 Megabit (2048K x 8 / 1024K x 16)
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
51
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13
EN39SL160H/L
Revisions List Revision No Description
A B Initial Release To modify Table 11, Icc1 active read current (max.) from 6mA to 10mA on page 3
Date
2009/04/03 2009/05/13
C D E
1. Modify TFBGA ball diagram (BYTE# and RY/BY# pins are changed 2009/06/08 to NC status) 2. Removal of WLGA 5mm x 6mm package definition 1. Removal of all of 90ns descriptions 2. modify the max sector erase time to 0.4s Modify the datasheet name from EN39SL160 to EN39SL160H/L 2009/06/15 2009/07/13
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
52
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. E, Issue Date: 2009/07/13


▲Up To Search▲   

 
Price & Availability of EN39SL160H

All Rights Reserved © IC-ON-LINE 2003 - 2022  
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]
 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X