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19-5008; Rev 0; 12/09
TION KIT EVALUA BLE AVAILA
IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET
General Description
The MAX5969A/MAX5969B provide a complete interface for a powered device (PD) to comply with the IEEE(R) 802.3af/at standard in a power-over-Ethernet (PoE) system. The MAX5969A/MAX5969B provide the PD with a detection signature, classification signature, and an integrated isolation power switch with inrush current control. During the inrush period, the MAX5969A/MAX5969B limit the current to less than 180mA before switching to the higher current limit (720mA to 880mA) when the isolation power MOSFET is fully enhanced. The devices feature an input UVLO with wide hysteresis and long deglitch time to compensate for twisted-pair cable resistive drop and to assure glitch-free transition during power-on/-off conditions. The MAX5969A/MAX5969B can withstand up to 100V at the input. The MAX5969A/MAX5969B support a 2-event classification method as specified in the IEEE 802.3at standard and provide a signal to indicate when probed by Type 2 power-sourcing equipment (PSE). The devices detect the presence of a wall adapter power-source connection and allow a smooth switchover from the PoE power source to the wall power adapter. The MAX5969A/MAX5969B also provide a power-good (PG) signal, two-step current limit and foldback, overtemperature protection, and di/dt limit. The MAX5969A/MAX5969B are available in a space-saving, 10-pin, 3mm x 3mm, TDFN power package. These devices are rated over the -40NC to +85NC extended temperature range. S S S S S S S S S S S S
Features
IEEE 802.3af/at Compliant 2-Event Classification Simplified Wall Adapter Interface PoE Classification 0 to 5 100V Input Absolute Maximum Rating Inrush Current Limit of 180mA Maximum Current Limit During Normal Operation Between 720mA and 880mA Current Limit and Foldback Legacy UVLO at 36V (MAX5969A) IEEE 802.3af/at-Compliant, 40V UVLO (MAX5969B) Overtemperature Protection Thermally Enhanced, 3mm x 3mm, 10-Pin TDFN
MAX5969A/MAX5969B
Ordering Information
PART MAX5969AETB+ MAX5969BETB+ TEMP RANGE PINPACKAGE UVLO THRESHOLD (V) 35.4 38.6
-40NC to +85NC 10 TDFN-EP* -40NC to +85NC 10 TDFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
Pin Configuration
TOP VIEW
Applications
IEEE 802.3af/at Powered Devices IP Phones, Wireless Access Nodes, IP Security Cameras WiMAXK Base Station
VDD DET N.C. I.C. VSS
1 2 3 4 5
+
10 9
CLS 2EC PG WAD RTN
MAX5969A MAX5969B
EP*
8 7 6
TDFN (3mm x 3mm)
IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers, Inc. WiMAX is a trademark of WiMAX Forum.
*EP = EXPOSED PAD. CONNECT TO VSS.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET
MAX5969A/MAX5969B
ABSOLUTE MAXIMUM RATINGS
VDD to VSS ..........................................................-0.3V to +100V DET, RTN, WAD, PG, 2EC to VSS ....................... -0.3V to +100V CLS to VSS ..............................................................-0.3V to +6V Maximum Current on CLS (100ms maximum) .................100mA Continuous Power Dissipation (TA = +70NC) (Note 1) 10-Pin TDFN (derate 24.4mW/NC above +70NC) Multilayer Board ........................................................1951mW Package Thermal Resistance (Note 2) BJA .................................................................................4NC/W BJC ................................................................................9NC/W Operating Temperature Range .......................... -40NC to +85NC Maximum Junction Temperature.....................................+150NC Storage Temperature Range............................ -65NC to +150NC Soldering Temperature (reflow) .................................... +260NC
Note 1: Maximum power dissipation is obtained using JEDEC JESD51-5 and JESD51-7 specifications. Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = (VDD - VSS) = 48V, RDET = 24.9k, RCLS = 615. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER DETECTION MODE Input Offset Current Effective Differential Input Resistance CLASSIFICATION MODE Classification Disable Threshold Classification Stability Time Class 0, RCLS = 619I VIN = 12.5V to 20.5V, VDD = RTN = WAD = PG = 2EC Class 1, RCLS = 117I Class 2, RCLS = 66.5I Class 3, RCLS = 43.7I Class 4, RCLS = 30.9I Class 5, RCLS = 21.3I TYPE 2 (802.3at) CLASSIFICATION MODE Mark Event Threshold Hysteresis on Mark Event Threshold Mark Event Current Reset Event Threshold POWER MODE VIN Supply Voltage Range VIN Supply Current IQ Measured at VDD 0.27 60 0.55 V mA IMARK VTHR VIN falling to enter mark event, 5.2V P VIN P 10.1V VIN falling 0.25 2.8 4 VTHM VIN falling 10.1 10.7 0.84 0.85 5.2 11.6 V V mA V 0 9.12 17.2 26.3 36.4 52.7 VTH,CLS VIN rising (Note 6) 22.0 22.8 0.2 3.96 11.88 19.8 29.7 43.6 63.3 mA 23.6 V ms IOFFSET dR VIN = 1.4V to 10.1V (Note 4) VIN = 1.4V up to 10.1V with 1V step, VDD = RTN = WAD = PG = 2EC (Note 5) 23.95 25.00 10 25.5 FA kI SYMBOL CONDITIONS MIN TYP MAX UNITS
Classification Current
ICLASS
2
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IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET
ELECTRICAL CHARACTERISTICS (continued)
(VIN = (VDD - VSS) = 48V, RDET = 24.9k, RCLS = 615. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER VIN Turn-On Voltage VIN Turn-Off Voltage VIN Turn-On/-Off Hysteresis (Note 7) VIN Deglitch Time Inrush to Operating Mode Delay Isolation Power MOSFET On-Resistance RTN Leakage Current CURRENT LIMIT Inrush Current Limit Current Limit During Normal Operation Foldback Threshold LOGIC WAD Detection Threshold WAD Detection Threshold Hysteresis WAD Input Current 2EC Sink Current 2EC Off-Leakage Current PG Sink Current PG Off-Leakage Current THERMAL SHUTDOWN Thermal-Shutdown Threshold Thermal-Shutdown Hysteresis TSD TJ rising TJ falling +140 28 NC NC IWAD-LKG VWAD-REF VWAD rising, VIN = 14V to 48V (referenced to RTN) VWAD falling, VRTN = 0V, VSS unconnected VWAD = 10V (referenced to RTN) V2EC = 3.5V (referenced to RTN), VSS unconnected V2EC = 48V VRTN = 1.5V, VPG = 0.8V, during inrush period VPG = 48V 125 230 1 1.5 8 9 0.725 3.5 2.25 1 375 1 FA mA FA FA FA 10 V IINRUSH ILIM During initial turn-on period, VRTN = 1.5V After inrush completed, VRTN = 1V VRTN (Note 9) 90 720 13 135 800 180 880 16.5 mA mA V SYMBOL VON VOFF VHYST_UVLO tOFF_DLY tDELAY VIN rising CONDITIONS MAX5969A MAX5969B MIN 34.3 37.2 30 4.2 7.3 30 80 TYP 35.4 38.6 MAX 36.6 40 UNITS V V V 120 96 0.5 0.65 0.8 10 FA 112 0.7 1 I Fs ms
MAX5969A/MAX5969B
VIN falling MAX5969A MAX5969B VIN falling from 40V to 20V (Note 8) tDELAY = minimum PG current pulse width after entering into power mode TJ = +25NC IRTN = 600mA TJ = +85NC TJ = +125NC
RON_ISO IRTN_LKG
VRTN = 12.5V to 30V
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IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET
MAX5969A/MAX5969B
ELECTRICAL CHARACTERISTICS (continued)
(VIN = (VDD - VSS) = 48V, RDET = 24.9k, RCLS = 615. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) All devices are 100% production tested at TA = +25NC. Limits over temperature are guaranteed by design. The input offset current is illustrated in Figure 1. Effective differential input resistance is defined as the differential resistance between VDD and VSS. See Figure 1. Classification current is turned off whenever the device is in power mode. UVLO hysteresis is guaranteed by design, not production tested. A 20V glitch on input voltage that takes VDD below VON shorter than or equal to tOFF_DLY does not cause the MAX5969A/ MAX5969B to exit power-on mode. Note 9: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an overload condition across VDD and RTN. Note Note Note Note Note Note 3: 4: 5: 6: 7: 8:
IIN dRi x 1V (VINi + 1 - VINi) = (IINi + 1 - IINi) (IINi + 1 - IINi) VINi dRi
IOFFSET x IINi IINi + 1 IINi
dRi
IOFFSET VINi 1V VINi + 1
VIN
Figure 1. Effective Differential Input Resistance/Offset Current
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IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET
Typical Operating Characteristics
(VIN = (VDD - VSS) = 54V, RDET = 24.9k, RCLS = 615. RTN, WAD, PG, and 2EC unconnected; all voltages are referenced to VSS.)
DETECTION CURRENT vs. INPUT VOLTAGE
MAX5969A toc01
MAX5969A/MAX5969B
SIGNATURE RESISTANCE vs. INPUT VOLTAGE
MAX5969A toc02
INPUT OFFSET CURRENT vs. INPUT VOLTAGE
MAX5969A toc03
0.5 0.4 0.3 0.2 0.1 0 0
25.5 RSIGNATURE (kI)
INPUT OFFSET CURRENT (A)
IIN = IVDD + IDET RDET = 24.9kI RTN = 2EC = PG = WAD = VDD -40C P TA P +85NC
26.0
IIN = IVDD + IDET RDET = 24.9kI RTN = 2EC = PG = WAD = VDD TA = -40NC
4
2
TA = -40NC
TA = +85NC
IIN (mA)
25.0 TA = +25NC 24.5 TA = +85NC
0 TA = +25NC
-2
24.0 2 4 VIN (V) 6 8 10 0 2 4 VIN (V) 6 8 10
-4 0 2 4 VIN (V) 6 8 10
CLASSIFICATION CURRENT vs. INPUT VOLTAGE
MAX5969A toc04
CLASSIFICATION SETTLING TIME
MAX5969A toc05
2EC SINK CURRENT vs. 2EC VOLTAGE
VIN 10V/div TA = -40NC 1.6 1.2 0.8 0.4 0 0 10 20 30 V2EC (V) 40 50 60 VSS UNCONNECTED V2EC REFERENCED TO RTN VWAD = 14V TA = +85NC TA = +25NC
MAX5969A toc06
70 60 50 IIN (mA) 40 30 20 10 0 0 5 10 15 VIN (V) 20 25 CLASS 5
2.0
CLASS 3 CLASS 2 CLASS 1 CLASS 0 30 100s/div RCLS = 30.9I
IIN 0A 200mA/div VCLS 1V/div 0V
I2EC (mA)
CLASS 4
PG SINK CURRENT vs. PG VOLTAGE
MAX5969A toc07
INRUSH CURRENT LIMIT vs. RTN VOLTAGE
MAX5969A toc08
NORMAL OPERATION CURRENT LIMIT vs. RTN VOLTAGE
800 CURRENT LIMIT (mA) 700 600 500 400 300 200
MAX5969A toc09
300 TA = -40NC 250 200 150 100 50 0 10 20 30 VPG (V) 40 50 TA = +85NC TA = +25NC
150 130 110 90 70 50
900
INRUSH CURRENT LIMIT (mA)
IPG (A)
100 0 10 20 30 VRTN (V) 40 50 60 0 10 20 30 VRTN(V) 40 50 60
60
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5
IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET
MAX5969A/MAX5969B
Typical Operating Characteristics (continued)
(VIN = (VDD - VSS) = 54V, RDET = 24.9k, RCLS = 615. RTN, WAD, PG, and 2EC unconnected; all voltages are referenced to VSS.)
INRUSH CONTROL WAVEFORM WITH TYPE 2 CLASSIFICATION
MAX5969A toc10
ENTERING POWER MODE WITH TYPE 2 CLASSIFICATION
V2EC 50V/div VRTN 50V/div 0V IRTN 100mA/div 0A VDD 50V/div
20ms/div
MAX5969A toc11
USING TYPICAL APPLICATION CIRCUIT 2EC PULLED UP TO VDD WITH 10kI
0V
USING TYPICAL APPLICATION CIRCUIT 2EC PULLED UP TO VDD WITH 10kI
VPG 0V 10V/div V2EC 0V 40V/div VRTN 0V 50V/div IRTN 0A 200mA/div VDD 0V 50V/div
0V 200s/div
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IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET
Pin Description
PIN 1 2 3 4 5 NAME VDD DET N.C. I.C. VSS FUNCTION Positive Supply Input. Connect a 68nF (min) bypass capacitor between VDD and VSS. Detection Resistor Input. Connect a signature resistor (RDET = 24.9kI) from DET to VDD. No Connection. Not internally connected. Internally Connected. Leave unconnected. Negative Supply Input. VSS connects to the source of the integrated isolation n-channel power MOSFET. Drain of Isolation MOSFET. RTN connects to the drain of the integrated isolation n-channel power MOSFET. Connect RTN to the downstream DC-DC converter ground as shown in the Typical Application Circuit. Wall Power Adapter Detector Input. Wall adapter detection is enabled the moment VDD - VSS crosses the mark event threshold. Detection occurs when the voltage from WAD to RTN is greater than 9V. When a wall power adapter is present, the isolation n-channel power MOSFET turns off, 2EC current sink turns on. Connect WAD directly to RTN when the wall power adapter or other auxiliary power source is not used. Open-Drain Power-Good Indicator Output. PG sinks 230FA to disable the downstream DC-DC converter while turning on the hot-swap MOSFET switch until the hot-swap switch is fully on. PG current sink is disabled during detection, classification, and in the steady-state power mode. Active-Low 2-Event Classification Detect or Wall Adapter Detect Output. A 1.5mA current sink is enabled at 2EC when a Type 2 PSE or a wall adapter is detected. When powered by a Type 2 PSE, the 2EC current sink is enabled and latched low after the isolation MOSFET is fully on until VIN drops below the UVLO threshold. 2EC also asserts when a wall adapter supply, typically greater than 9V, is applied between WAD and RTN. 2EC is not latched if asserted by WAD. Classification Resistor Input. Connect a resistor (RCLS) from CLS to VSS to set the desired classification current. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classification. Exposed Pad. Do not use EP as an electrical connection to VSS. EP is internally connected to VSS through a resistive path and must be connected to VSS externally. To optimize power dissipation, solder the exposed pad to a large copper power plane.
MAX5969A/MAX5969B
6
RTN
7
WAD
8
PG
9
2EC
10
CLS
--
EP
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7
IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET
MAX5969A/MAX5969B
Simplified Block Diagram
VDD 22.8/22 VDD 5V 5V REGULATOR 1.23V CLR Q CLR Q D SET Q D SET Q EN
VDD CLASSIFICATION 1.23V CLS
2EC PSE 2
VDD 11.6V/4V 5V
1.5mA
PG
46A DET 11.6V/10.8V VON/VOFF VDD VDD THERMAL SHUTDOWN 95ms WAPD WAD 230A
R HSON 4V S
Q
9V 15V ISWITCH ISOLATION SWITCH VON/VOFF = 38.6V/31V FOR MAX5969B VON/VOFF = 35.4V/31V FOR MAX5969A
VSS
RTN
K x ISWITCH S IREF 1/K MUX I0 I1 135mA 760mA
MAX5969A MAX5969B
8
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IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET
Typical Operating Circuit
MAX5969A/MAX5969B
2-EVENT CLASSIFICATION DETECTION GND RJ-45 AND BRIDGE RECTIFIER
VDD
2EC PG
IN+ ENABLE
GND
RDET 24.9kI DET CLS RCLS
68nF
MAX5969A MAX5969B
WAD
DC-DC CONVERTER
SMAJ58A
24V/48V BATTERY VSS
IN-
-54V
RTN
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9
IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET
MAX5969A/MAX5969B
Detailed Description
Depending on the input voltage (VIN = VDD - VSS), the MAX5969A/MAX5969B operate in four different modes: PD detection, PD classification, mark event, and PD power. The devices enter PD detection mode when the input voltage is between 1.4V and 10.1V. The device enters PD classification mode when the input voltage is between 12.6V and 20V. The device enters PD power mode once the input voltage exceeds VON. Detection Mode (1.4V VIN 10.1V) In detection mode, the PSE applies two voltages on VIN in the range of 1.4V to 10.1V (1V step minimum) and then records the current measurements at the two points. The PSE then computes DV/DI to ensure the presence of the 24.9k signature resistor. Connect the signature resistor (RDET) from VDD to DET for proper signature detection. The MAX5969A/MAX5969B pull DET low in detection mode. DET goes high impedance when the input voltage exceeds 12.5V. In detection mode, most of the MAX5969A/MAX5969B internal circuitry is off and the offset current is less than 10A. If the voltage applied to the PD is reversed, install protection diodes at the input terminal to prevent internal damage to the MAX5969A/MAX5969B (see the Typical Application Circuit). Since the PSE uses a slope technique (DV/DI) to calculate the signature resistance, the DC offset due to the protection diodes is subtracted and does not affect the detection process.
Operating Modes
Classification Mode (12.6V VIN 20V) In the classification mode, the PSE classifies the PD based on the power consumption required by the PD. This allows the PSE to efficiently manage power distribution. Class 0 to 5 is defined as shown in Table 1. (The IEEE 802.3af/at standard defines only Class 0 to 4 and Class 5 for any special requirement.) An external resistor (RCLS) connected from CLS to VSS sets the classification current. The PSE determines the class of a PD by applying a voltage at the PD input and measuring the current sourced out of the PSE. When the PSE applies a voltage between 12.6V and 20V, the MAX5969A/MAX5969B exhibit a current characteristic with a value shown in Table 1. The PSE uses the classification current information to classify the power requirement of the PD. The classification current includes the current drawn by RCLS and the supply current of the MAX5969A/MAX5969B so the total current drawn by the PD is within the IEEE 802.3af/at standard figures. The classification current is turned off whenever the device is in power mode. 2-Event Classification and Detection During 2-event classification, a Type 2 PSE probes PD for classification twice. In the first classification event, the PSE presents an input voltage between 12.6V and 20.5V and the MAX5969A/MAX5969B present the programmed load ICLASS. The PSE then drops the probing voltage below the mark event threshold of 10.1V and the MAX5969A/MAX5969B present the mark current (IMARK). This sequence is repeated one more time.
Table 1. Setting Classification Current
CLASS MAXIMUM POWER USED BY PD (W) 0.44 to 12.95 0.44 to 3.94 3.84 to 6.49 6.49 to 12.95 12.95 to 25.5 > 25.5 RCLS (I) 615 117 66.5 43.7 30.9 21.3 VIN* (V) 12.6 to 20 12.6 to 20 12.6 to 20 12.6 to 20 12.6 to 20 12.6 to 20 CLASS CURRENT SEEN AT VIN (mA) MIN 0 9 17 26 36 54 MAX 4 12 20 30 44 64 IEEE 802.3at PSE CLASSIFICATION CURRENT SPECIFICATION (mA) MIN 0 8 16 25 35 -- MAX 5 13 21 31 45 --
0 1 2 3 4 5
*VIN is measured across the MAX5969A/MAX5969B input VDD to VSS.
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IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET
When the MAX5969A/MAX5969B are powered by a Type 2 PSE, the 2-event identification output 2EC asserts low after the internal isolation n-channel MOSFET is fully turned on. 2EC current sink is turned off when VDD goes below the UVLO threshold (VOFF) and turns on when VDD goes above the UVLO threshold (VON), unless VDD goes below VTHR to reset the latched output of the Type 2 PSE detection flag. Alternatively, the 2EC output also serves as a wall adapter detection output when the MAX5969A/MAX5969B are powered by an external wall power adapter. See the Wall Power Adapter Detection and Operation section for more information. Power Mode (Wake Mode) The MAX5969A/MAX5969B enter power mode when VIN rises above the undervoltage lockout threshold (VON). When VIN rises above VON, the MAX5969A/MAX5969B turn on the internal n-channel isolation MOSFET to connect VSS to RTN with inrush current limit internally set to 135mA (typ). The isolation MOSFET is fully turned on when the voltage at RTN is near VSS and the inrush current is reduced below the inrush limit. Once the isolation MOSFET is fully turned on, the MAX5969A/MAX5969B change the current limit to 800mA. The open-drain power-good output (PG) remains low for a minimum of tDELAY until the power MOSFET fully turns on to keep the downstream DC-DC converter disabled during inrush. The MAX5969A/MAX5969B operate up to a 60V supply voltage with a turn-on UVLO threshold (VON) at 35.4V/38.6V and a turn-off UVLO threshold (VOFF) at 31V. When the input voltage is above VON, the MAX5969A/ MAX5969B enter power mode and the internal MOSFET is turned on. When the input voltage goes below VOFF for more than tOFF_DLY, the MOSFET turns off. An open-drain output (PG) is used to allow disabling downstream DC-DC converter until the n-channel isolation MOSFET is fully turned on. PG is pulled low to VSS for a period of tDELAY and until the internal isolation MOSFET is fully turned on. The PG is also pulled low when coming out of thermal shutdown. The MAX5969A/MAX5969B include thermal protection from excessive heating. If the junction temperature exceeds the thermal-shutdown threshold of +140NC, the MAX5969A/MAX5969B turn off the internal power MOSFET and 2EC current sink. When the junction temperature falls below +112NC, the devices enter inrush mode and then return to power mode. Inrush mode ensures the downstream DC-DC converter is turned off as the internal power MOSFET is turned on.
Power-Good Output
MAX5969A/MAX5969B
Thermal-Shutdown Protection
Undervoltage Lockout
For applications where an auxiliary power source such as a wall power adapter is used to power the PD, the MAX5969A/MAX5969B feature wall power adapter detection. Once the input voltage (VDD - VSS) exceeds the mark event threshold, the MAX5969A/MAX5969B enable wall adapter detection. The wall power adapter is connected from WAD to RTN. The MAX5969A/ MAX5969B detect the wall power adapter when the voltage from WAD to RTN is greater than 9V. When a wall power adapter is detected, the internal n-channel isolation MOSFET turns off, 2EC current sink turns on, and classification current is disabled if VIN is in the classification range.
Wall Power Adapter Detection and Operation
______________________________________________________________________________________
11
IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET
MAX5969A/MAX5969B
Applications Information
Operation with 12V Adapter
Layout Procedure Careful PCB layout is critical to achieve high efficiency and low EMI. Follow these layout guidelines for optimum performance: 1) Place the input capacitor, classification resistor, and transient voltage suppressor as close as possible to the MAX5969A/MAX5969B.
2) Use large SMT component pads for power dissipating devices such as the MAX5969A/MAX5969B and the external diodes. 3) Use short and wide traces for high-power paths. 4) Use the MAX5969 Evaluation Kit layout as a reference.
2-EVENT CLASSIFICATION (ASSERTED ON) GND RJ-45 AND BRIDGE RECTIFIER
VDD RDET 24.9kI
2EC PG
IN+ GND ENABLE
68nF
DET CLS
MAX5969A MAX5969B
WAD
DC-DC CONVERTER
SMAJ58A
RCLS VSS
12V BATTERY
IN-
-54V
RTN THIS CIRCUIT ACHIEVES PROPER 2EC LOGIC WHEN BATTERY IS < 12.5V
Figure 2. Typical Configuration When Using a 12V Wall Power Adapter
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IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET
Typical Application Circuit
MAX5969A/MAX5969B
ISOLATED 2-EVENT CLASSIFICATION OUTPUT GND GND
VDD
2EC PG PG
VAC
24.9kI
68nF
DET CLS 43.7I VSS
MAX5969A MAX5969B
WAD
VAC
SMAJ58A
24/48V BATTERY RTN 249I RTN
-54V
GND
33kI
1.37MI
51.5kI
0.1F
4.7F GND ISOLATED +5.3V/2A
PG
RTN ULVO/EN IN 0.1F 0.1F VCC 22F ISOLATED RTN FB 10kI CS
UFLG
VCC NDRV
22.1I
MAX15000
COMP
GND CS 649I
CS
RT 1kI 0.1F
619I 0.75I
8.2nF
18.1kI
330pF
8.06kI
4.99kI VCC 4.99kI RTN
1kI
100pF
33nF 8.06kI 1kI 2.2nF RTN ISOLATED RTN 2.49kI
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13
IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET
MAX5969A/MAX5969B
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE 10 TDFN-EP PACKAGE CODE T1033+1 DOCUMENT NO. 21-0137
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14
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