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PD - 97379
IRFP4768PBF
HEXFET(R) Power MOSFET
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free
D
G S
VDSS RDS(on) typ. max. ID
250V 14.5m 17.5m 93A
D
G
D
S
TO-247AC
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current c Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery e Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
Max.
93 66 370 520 3.4 20 24 -55 to + 175 300 10lbfxin (1.1Nxm) 770 See Fig. 14, 15, 22a, 22b
Units
A W W/C V V/ns C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy d Avalanche Current c Repetitive Avalanche Energy c mJ A mJ
Thermal Resistance
Symbol
RJC RCS RJA
Parameter
Junction-to-Case ij Case-to-Sink, Flat Greased Surface Junction-to-Ambient
Typ.
--- 0.24 ---
Max.
0.29 --- 40
Units
C/W
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1
02/26/09
IRFP4768PBF
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS RG
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance
Min. Typ. Max. Units
250 --- --- 3.0 --- --- --- --- --- --- 0.20 14.5 --- --- --- --- --- 0.71 --- --- 17.5 5.0 20 250 100 -100 ---
Conditions
V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 5mAc m VGS = 10V, ID = 56A f V VDS = VGS, ID = 250A A VDS = 250V, VGS = 0V VDS = 250V, VGS = 0V, TJ = 125C nA VGS = 20V VGS = -20V
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Effective Output Capacitance (Energy Related) h Effective Output Capacitance (Time Related)g
Min. Typ. Max. Units
100 --- --- --- 180 270 --- 52 --- --- 72 --- --- 108 --- --- 36 --- --- 160 --- --- 57 --- --- 110 --- --- 10880 --- --- 700 --- --- 210 --- --- 510 --- --- 830 --- S nC
Conditions
VDS = 50V, ID = 56A ID = 56A VDS =125V VGS = 10V f ID = 56A, VDS =0V, VGS = 10V VDD = 163V ID = 56A RG = 1.0 VGS = 10V f VGS = 0V VDS = 50V = 1.0 MHz, See Fig. 5 VGS = 0V, VDS = 0V to 200V h, See Fig. 11 VGS = 0V, VDS = 0V to 200V g
ns
pF
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) c Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- 93 370 A A
Conditions
MOSFET symbol showing the integral reverse
G S D
--- --- 1.3 V --- 180 --- ns --- 200 --- --- 1480 --- nC TJ = 125C --- 2260 --- --- 16 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode. TJ = 25C, IS = 56A, VGS = 0V f TJ = 25C VR = 200V, TJ = 125C IF = 56A di/dt = 100A/s f TJ = 25C
Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.50mH RG = 25, IAS = 56A, VGS =10V. Part not recommended for use above this value. ISD 56A, di/dt 950A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as R is measured at TJ approximately 90C. RJC value shown is at time zero.
Coss while VDS is rising from 0 to 80% VDSS.
2
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IRFP4768PBF
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 4.8V 4.5V
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 4.8V 4.5V
ID, Drain-to-Source Current (A)
10
BOTTOM
ID, Drain-to-Source Current (A)
100
100
BOTTOM
1
10 4.5V
0.1 4.5V 0.01 0.1 1
60s PULSE WIDTH
Tj = 25C 10 1 100 1000 0.1 1
60s PULSE WIDTH
Tj = 175C 10 100 1000
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
Fig 2. Typical Output Characteristics
3.5
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID, Drain-to-Source Current (A)
3.0 2.5 2.0 1.5 1.0 0.5 0.0
ID = 56A VGS = 10V
100
10
T J = 175C
T J = 25C
1 VDS = 50V 60s PULSE WIDTH 3 4 5 6 7 8
0.1
-60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (C)
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ Ciss = C gs + C gd, C ds SHORTED Crss = C gd Coss = Cds + C gd
Fig 4. Normalized On-Resistance vs. Temperature
14.0 ID= 56A
VGS, Gate-to-Source Voltage (V)
12.0 10.0 8.0 6.0 4.0 2.0 0.0
VDS= 200V VDS= 125V VDS= 50V
C, Capacitance (pF)
10000
Ciss Coss Crss
1000
100 1 10 100 1000 VDS, Drain-to-Source Voltage (V)
0
30
60
90
120 150 180 210 240
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFP4768PBF
1000
1000
OPERATION IN THIS AREA LIMITED BY R DS(on) 100sec
100
T J = 175C T J = 25C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100 1msec 10msec 10 DC Tc = 25C Tj = 175C Single Pulse 1 1 10 100 1000
10
1 VGS = 0V 0.1 0.0 0.5 1.0 1.5 VSD, Source-to-Drain Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
1000
Fig 8. Maximum Safe Operating Area
320 Id = 5mA
ISD, Reverse Drain Current (A)
100
T J = 175C T J = 25C
300
10
280
1 VGS = 0V 0.1 0.0 0.5 1.0 1.5 VSD, Source-to-Drain Voltage (V)
260
240 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( C )
Fig 9. Maximum Drain Current vs. Case Temperature
20.0 18.0 16.0 14.0
Energy (J)
Fig 10. Drain-to-Source Breakdown Voltage
3200
EAS , Single Pulse Avalanche Energy (mJ)
2800 2400 2000 1600 1200 800 400 0
ID 12A 17A BOTTOM 56A TOP
12.0 10.0 8.0 6.0 4.0 2.0 0.0 -50 0 50 100 150 200 250 300
25
50
75
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting T J , Junction Temperature (C)
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4
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IRFP4768PBF
1
Thermal Response ( Z thJC ) C/W
0.1
D = 0.50 0.20 0.10 0.05 0.02 0.01
J J 1 1 R1 R1 2 R2 R2 R3 R3 3 C 3
0.01
Ri (C/W) i (sec) 0.0634 0.000278 0.1109 0.1148 0.005836 0.053606
2
0.001 SINGLE PULSE ( THERMAL RESPONSE ) 1E-005 0.0001
Ci= i/Ri Ci i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.001 0.01 0.1 1
0.0001 1E-006
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100 0.01 10 0.05 0.10
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 0.1 1.0E-06 1.0E-05 1.0E-04 tav (sec) 1.0E-03 1.0E-02 1.0E-01
Fig 14. Typical Avalanche Current vs.Pulsewidth
800 700
EAR , Avalanche Energy (mJ)
600 500 400 300 200 100 0 25 50
TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 56A
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
175
75
100
125
150
Starting T J , Junction Temperature (C)
PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFP4768PBF
6.0
VGS(th) , Gate threshold Voltage (V)
70 60 50
IRRM (A)
5.0 4.0 3.0 2.0 1.0 0.0 -75 -50 -25 0 25 50 75 100 125 150 175 T J , Temperature ( C )
IF = 37A V R = 200V TJ = 25C TJ = 125C
ID = 250A ID = 1.0A
40 30 20 10 0 200 400 600 800 1000 diF /dt (A/s)
ID = 1.0mA
Fig 16. Threshold Voltage vs. Temperature
90 80 70 60 50 40 30 20 10 0 200 400 600 800 1000 diF /dt (A/s) IF = 56A V R = 200V TJ = 25C TJ = 125C
QRR (nC)
Fig. 17 - Typical Recovery Current vs. dif/dt
6000 IF = 37A V R = 200V TJ = 25C TJ = 125C
5000
IRRM (A)
4000
3000
2000
1000 0 200 400 600 800 1000 diF /dt (A/s)
Fig. 18 - Typical Recovery Current vs. dif/dt
8000 7000 6000
QRR (nC)
Fig. 19 - Typical Stored Charge vs. dif/dt
IF = 56A V R = 200V TJ = 25C TJ = 125C
5000 4000 3000 2000 1000 0 200 400 600 800 1000 diF /dt (A/s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFP4768PBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
VDS VGS RG RD
Fig 22b. Unclamped Inductive Waveforms
VDS 90%
D.U.T.
+
- VDD
V10V GS
Pulse Width 1 s Duty Factor 0.1 %
10% VGS
td(on) tr t d(off) tf
Fig 23a. Switching Time Test Circuit
Current Regulator Same Type as D.U.T.
Fig 23b. Switching Time Waveforms
Id Vds Vgs
50K 12V .2F .3F
D.U.T. VGS
3mA
+ V - DS
Vgs(th)
IG
ID
Current Sampling Resistors
Qgs1 Qgs2
Qgd
Qgodr
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Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
7
IRFP4768PBF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
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96U@A8P9@ @6SA A2A! X@@FA"$ GDI@AC
TO-247AC package is not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
8
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 02/09
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