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| PRELIMINARY DATASHEET SERIAL REAL-TIME CLOCK Description The IDT5P90005 is a serial real-time clock (RTC) device that consumes ultra-low power and provides a full binary-coded decimal (BCD) clock/calendar. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. Access to the clock/calendar registers is provided by an I2C interface capable of operating in fast I2C mode. Built-in Power-sense circuitry detects power failures and automatically switches to the backup supply, maintaining time and date operation. IDT5P90005 Features * Packaged in 8-pin SOIC * Counters for seconds, minutes, hours, days, date, months, years, and century * 32 kHz crystal oscillator integrating load capacitance (12.5 pF) providing exceptional oscillator stability and high crystal series resistance operation * Serial interface supports I2C bus (100 or 400 kHz protocol) * * * * * Ultra low battery supply current of 0.8 A (typ at 3 V) 2.0 to 5.5 V clock operating voltage Automatic switch over and deselect circuitry Automatic leap year compensation Operating temperature of -40 to +85C Block Diagram OSCI OSCO 32.768 kHz Oscillator and Divider 1 Hz MUX/ Buffer FT/OUT VCC GND VBAT SCL SDA Power Control Control Logic Clock, Calendar Counter I2 C Interface 1 Byte Control 7 Bytes Buffer IDTTM SERIAL REAL-TIME CLOCK 1 IDT5P90005 REV E 031209 IDT5P90005 SERIAL REAL-TIME CLOCK RTC Pin Assignment OSCI OSCO VBAT VSS 1 2 3 4 8 7 6 5 VCC FT/OUT SCL SDA 8-Pin (150 mil) SOIC Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 Pin Name OSCI OSCO VBAT VSS SDA SCL FT/OUT VCC Pin Type Input Output Power Power I/O Input Output Power Oscillator input. Oscillator output. Battery supply voltage. Connect to ground. Serial data address input/output. Serial clock. Pin Description Frequency test/output driver (open drain). Supply voltage. IDTTM SERIAL REAL-TIME CLOCK 2 IDT5P90005 REV E 031209 IDT5P90005 SERIAL REAL-TIME CLOCK RTC Device Operation The IDT5P90005 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 8 bytes contained in the device can then be accessed sequentially in the following order: 1st byte: seconds register 2nd byte: minutes register 3rd byte: century/hours register 4th byte: day register 5th byte: date register 6th byte: month register 7th byte: years register 8th byte: control register The IDT5P90005 clock continually monitors VCC for an out-of-tolerance condition. Should VCC fall below VSO, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time, to prevent erroneous data from being written to the device from an out-of-tolerance system. When VCC falls below VSO, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. Upon power-up, the device switches from battery to VCC at VSO and recognizes inputs. IDTTM SERIAL REAL-TIME CLOCK 3 IDT5P90005 REV E 031209 IDT5P90005 SERIAL REAL-TIME CLOCK RTC I2C Serial Data Bus The IDT5P90005 supports the I2C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The IDT5P90005 operates as a slave on the I2C bus. Within the bus specifications, a standard mode (100 kHz maximum clock rate) and a fast mode (400 kHz maximum clock rate) are defined. The IDT5P90005 works in both modes. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (see the "Data Transfer on I2C Serial Bus" figure): information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The IDTTM SERIAL REAL-TIME CLOCK 4 IDT5P90005 REV E 031209 IDT5P90005 SERIAL REAL-TIME CLOCK RTC Data Transfer on I2C Serial Bus Depending upon the state of the R/W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. 2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a "not acknowledge" is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit (MSB) first. The IDT5P90005 can operate in the following two modes: 1) Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (see the "Data Write-Slave Receiver Mode" figure). The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit IDT5P90005 address, which is 1101000, followed by the direction bit (R/W), which is 0 for a write. After receiving and decoding the slave address byte the slave outputs an acknowledge on the SDA line. After the IDT5P90005 acknowledges the slave address + write bit, the master transmits a register address to the IDT5P90005. This sets the register pointer on the IDT5P90005, with the IDT5P90005 acknowledging the transfer. The master may then transmit zero or more bytes of data, with the IDT5P90005 acknowledging each byte received. The address pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write. 2) Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the IDT5P90005 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (see the "Data Read-Slave Transmitter Mode" figure). The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit IDT5P90005 address, which is 1101000, followed by the direction bit (R/W), which is 1 for a read. After receiving and decoding the slave address byte the slave outputs an acknowledge on the SDA line. The IDT5P90005 IDTTM SERIAL REAL-TIME CLOCK 5 IDT5P90005 REV E 031209 IDT5P90005 SERIAL REAL-TIME CLOCK RTC then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The address pointer is incremented after each byte is transferred. The IDT5P90005 must receive a "not acknowledge" to end a read. Data Write - Slave Receiver Mode Data Read (from current Pointer location) - Slave Transmitter Mode Data Read (Write Pointer, then Read) - Slave Receive and Transmit IDTTM SERIAL REAL-TIME CLOCK 6 IDT5P90005 REV E 031209 IDT5P90005 SERIAL REAL-TIME CLOCK RTC Bus Timing Requirements Sequence Note: P=STOP and S=START. IDTTM SERIAL REAL-TIME CLOCK 7 IDT5P90005 REV E 031209 IDT5P90005 SERIAL REAL-TIME CLOCK RTC Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT5P90005. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Parameter Supply Voltage, VCC Input or Output Voltages Clock Outputs Storage Temperature Soldering Temperature1 Condition Referenced to GND Referenced to GND Referenced to GND Max 10 seconds Min. -0.3 -0.3 -0.5 -55 Typ. Max. 7 7 VDD+ 0.5 125 260 20 Units V V V C C mA C W Output Current Ambient Operating Temperature Power Dissipation -40 +85 0.25 Note 1: Re flow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds). Caution: Negative undershoots below -0.3 V are not allowed on any pin while in the backup mode. IDTTM SERIAL REAL-TIME CLOCK 8 IDT5P90005 REV E 031209 IDT5P90005 SERIAL REAL-TIME CLOCK RTC DC and AC Parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Operating and AC Measurement Conditions1 Parameter Supply Voltage, VCC Ambient Operating Temperature Load Capacitance Input Rise and Fall times Input Pulse Voltages Input and Output TIming Reference Voltages Rating 2.0 to 5.5 V -40 to +85C 100 pF < 5 ns 0.2 VCC to 0.8 VCC 0.3 VCC to 0.7 VCC Note 1: Output Hi-Z is defined as the point where data is no longer driven. AC Testing Input/Output Waveform Capacitance Parameter1,2 Input Capacitance Output Capacitance (SDA, FT/OUT) Low-pass Filter Input Time Constant (SDA and SCL) Symbol CIN COUT3 tLP Min. Typ. Max. 7 10 Units pF pF ns 250 1000 Note 1: Effective capacitance measured with power supply at 3.3 V; sampled only, not 100% tested. Note 2: At 25C, f = 1 MHz. Note 3: Output deselected. IDTTM SERIAL REAL-TIME CLOCK 9 IDT5P90005 REV E 031209 IDT5P90005 SERIAL REAL-TIME CLOCK RTC DC Characteristics Parameter Input Leakage Current Output Leakage Current Supply Current RTC Supply Current (standby) Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage (open drain) Battery Supply Voltage Battery Supply Current VBAT IBAT TA = 25C, VCC = 0V Oscillator ON, VBAT = 3 V Symbol ILI ILO ICC1 ICC2 VIL VIH VOL Conditions1 0V = VIN = VCC 0V = VOUT = VCC Switch Frequency = 100 kHz SCL, SDA = VCC - 0.3 Min. Typ. Max. 1 1 300 70 Units A A A A V V V V V A -0.3 0.7VCC IOL = 3.0 mA FT/OUT 2.5 0.8 0.3VCC VCC+0.5 0.4 5.5 3.5 1 Note 1: Valid for ambient operating temperature: TA = -40 to 85 C; VCC = 2.0 to 5.5 V (except where noted). Crystal Electrical Characteristics Parameter1 Resonant Frequency Series Resistance Load Capacitance Symbol fO RS CL Min. Typ. 32.768 Max. 60 Units kHz K pF 12.5 Note 1: Load capacitors are integrated within the IDT5P90005. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. IDTTM SERIAL REAL-TIME CLOCK 10 IDT5P90005 REV E 031209 IDT5P90005 SERIAL REAL-TIME CLOCK RTC AC Electrical Characteristics Unless stated otherwise, VCC = 2.0 to 5.5 V, Ambient Temperature -40 to +85C Parameter Symbol STANDARD MODE Min. Max. 100 4.7 4.0 1 300 4 4.7 0 250 4.0 4.7 FAST MODE Min. 1.3 0.6 0.3 300 Units Max. 400 kHz s s s ns s SCL Clock Frequency Clock Low Period Clock High Period SDA and SCL Rise time SDA and SCL Fall Time START Condition Hold Time (after this period the first clock pulse is generated) START Condition Setup Time (only relevant for a repeated start condition) Data Hold Time Data Setup Time STOP Condition Setup Time Time the bus must be free before a new transmission can start fSCL tLOW tHIGH tR tF tHD:STA tSU:STA tHD:DAT1 tSU:DAT tSU:STO tBUF 0.6 1.3 100 0.6 1.3 s ns ns s s Note 1: Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL. Power Down/Up Mode AC Waveforms RTC Power Down/Up AC Characteristics Parameter1,2 SCL and SDA at VIH before Power Down SCL and SDA at VIH after Power Up Symbol tPD trec Min. 0 10 Typ. Max. 2000 Units ns s Note 1: Valid for ambient operating temperature: TA = -40 to 85 C; VCC = 2.0 to 5.5 V (except where noted). Note 2: VCC fall time should not exceed 5 mV/s. IDTTM SERIAL REAL-TIME CLOCK 11 IDT5P90005 REV E 031209 IDT5P90005 SERIAL REAL-TIME CLOCK RTC RTC Power Down/Up Trip Points DC Characteristics Parameter1,2 Backup Switchover Voltage Symbol VSO3 Min. VBAT-0.90 Typ. VBAT-0.50 Max3 VBAT-0.30 Units V Note 1: Valid for ambient operating temperature: TA = -40 to 85 C; VCC = 2.0 to 5.5 V (except where noted). Note 2: All voltages referenced to VSS. Note 3: Switchover and deselect point. Clock Operation The eight byte clock register (see "Register Map" table) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are contained within the first three registers. Bits D6 and D7 of clock register 2 (century/hours register) contain the century enable bit (CEB) and the century bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0', CB will not toggle. Bits D0 through D2 of register 3 contain the day (day of week). Registers 4, 5 and 6 contain the date (day of month), month and years. The final register is the control register (this is described in the clock calibration section). Bit D7 of register 0 contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second. When reading or writing the time and date registers, secondary(user) buffers are used to prevent error when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any start or stop, and when the address pointer rolls over to zero. The countdown chain is reset whenever the seconds register is written. Write transfers occurs on the acknowledge pulse from the device. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within one second. If enabled, the 1Hz square-wave output transitions high 500ms after the seconds data transfer, provided the oscillator is already running. Note: In order to guarantee oscillator start-up after the initial power-up, set the ST bit to a '1,' then reset this bit to a '0.' This sequence enables a "kick start" circuit which aids the oscillator start-up during worst case conditions of voltage and temperature. Register Map1 Address 0 1 2 Data D7 ST R CEB2 CB D6 D5 10 seconds 10 minutes 10 hours D4 D3 D2 Minutes Hours D1 Seconds D0 Function/Range BCD Format Seconds Minutes Century/Hours 00 - 59 00 - 59 0-1/00-23 IDTTM SERIAL REAL-TIME CLOCK 12 IDT5P90005 REV E 031209 IDT5P90005 SERIAL REAL-TIME CLOCK RTC Address 3 4 5 6 7 Data D7 R R R OUT D6 R R R 10 years FT R R R R R D5 R 10 date 10 M D4 R D3 R Date Month Years R R D2 D1 Day D0 Function/Range BCD Format Day Date Month/Century Year Control 01 - 07 01 - 31 01 - 12 00 - 99 Note 1. Keys: FT = frequency test bit ST = stop bit OUT = output level CEB = century enable bit CB = century bit R = Reserved BIT(keep same as default value) Note 2. When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set).When CEB is set to '0', CB will not toggle. Output Driver Pin When the FT bit is not set, the FT/OUT pin becomes an output driver that reflects the contents of D7 of the control register. In other words, when D6 of address 7 is a zero and D7 of address 7 is a zero and then the FT/OUT pin will be driven low. Note: The FT/OUT pin is open drain which requires an external pull-up resistor. Table FT 0 0 1 OUT 0 1 x FT/OUT 0 1 512Hz Initial Power-on Defaults Upon initial application of power to the device, the FT bit will be set to a '0' and the OUT bit will be set to a '1'. All other register bits will initially power on in a random state. IDTTM SERIAL REAL-TIME CLOCK 13 IDT5P90005 REV E 031209 IDT5P90005 SERIAL REAL-TIME CLOCK RTC Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol JA JA JA JC Conditions Still air 1 m/s air flow 3 m/s air flow Min. Typ. 150 140 120 40 Max. Units C/W C/W C/W C/W Marking Diagram 8 5 TBD 1 4 Notes: 1. ###### is the lot number. 2. YYWW is the last two digits of the year and week that the part was assembled. 3. Bottom marking: country of origin if not USA. IDTTM SERIAL REAL-TIME CLOCK 14 IDT5P90005 REV E 031209 IDT5P90005 SERIAL REAL-TIME CLOCK RTC Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 8 Millimeters Symbol Min Max Inches Min Max INDEX AREA E H 12 D A A1 B C D E e H h L 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8 .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8 A A1 h x 45 C -Ce B SEATING PLANE .10 (.004) L C Ordering Information Part / Order Number 5P90005DCGI 5P90005DCGI8 Marking see page 6 Shipping Packaging Tubes Tape and Reel Package 8-pin SOIC 8-pin SOIC Temperature -40 to +85 C -40 to +85 C Parts ordered with a "G" after the two-letter package code are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDTTM SERIAL REAL-TIME CLOCK 15 IDT5P90005 REV E 031209 IDT5P90005 SERIAL REAL-TIME CLOCK RTC Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA |
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