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PD -95104
l l l l l l l
Advanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating 175C Operating Temperature Fast Switching Fully Avalanche Rated Lead-Free
HEXFET(R) Power MOSFET
D
IRF1404SPBF IRF1404LPbF
VDSS = 40V RDS(on) = 0.004
G S
Description
Seventh Generation HEXFET(R) Power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications.
The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRF1404L) is available for lowprofile applications.
ID = 162A
D2Pak IRF1404SPBF
TO-262 IRF1404LPbF
Absolute Maximum Ratings
ID @ TC = 25C ID @ TC = 100C IDM PD @TA = 25C PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
162 115 650 3.8 200 1.3 20 519 95 20 5.0 -55 to +175 -55 to +175 300 (1.6mm from case )
Units
A W W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient (PCB mounted, steady-state)*
Typ.
--- ---
Max.
0.75 40
Units
C/W
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1
03/11/04
IRF1404S/LPbF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
RDS(on) VGS(th) gfs IDSS I GSS Qg Qgs Qgd td(on) tr td(off) tf LS Ciss Coss Crss Coss Coss Coss eff.
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance
Min. 40 --- --- 2.0 106 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
Typ. Max. Units Conditions --- --- V VGS = 0V, ID = 250A 0.036 --- V/C Reference to 25C, ID = 1mA 0.00350.004 VGS = 10V, ID = 95A --- 4.0 V VDS = 10V, ID = 250A --- --- S VDS = 25V, ID = 60A --- 20 VDS = 40V, VGS = 0V A --- 250 VDS = 32V, VGS = 0V, TJ = 150C --- 200 VGS = 20V nA --- -200 VGS = -20V 160 200 ID = 95A 35 --- nC VDS = 32V 42 60 VGS = 10V 17 --- VDD = 20V 140 --- ID = 95A ns 72 --- RG = 2.5 26 --- RD = 0.21 Between lead, nH 7.5 --- and center of die contact 7360 --- VGS = 0V 1680 --- VDS = 25V 240 --- pF = 1.0MHz, See Fig. 5 6630 --- VGS = 0V, VDS = 1.0V, = 1.0MHz 1490 --- VGS = 0V, VDS = 32V, = 1.0MHz 1540 --- VGS = 0V, VDS = 0V to 32V
Source-Drain Ratings and Characteristics
IS
ISM
VSD trr Qrr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol --- --- 162 showing the A G integral reverse --- --- 650 S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 95A, VGS = 0V --- 71 110 ns TJ = 25C, IF = 95A --- 180 270 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11) Starting TJ = 25C, L = 0.12mH RG = 25, IAS = 95A. (See Figure 12)
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 75A
ISD 95A, di/dt 150A/s, VDD V(BR)DSS,
TJ 175C
Use IRF1404 data and test conditions.
Pulse width 300s; duty cycle 2%. * When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
2
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IRF1404S/LPbF
1000
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
1000
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
100
100
4.5V
4.5V
10 0.1
20s PULSE WIDTH TJ = 25 C
1 10 100
10 0.1
20s PULSE WIDTH TJ = 175 C
1 10 100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.5
I D , Drain-to-Source Current (A)
TJ = 25 C TJ = 175 C
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID = 159A
2.0
1.5
100
1.0
0.5
10 4.0
V DS = 25V 20s PULSE WIDTH 5.0 6.0 7.0 8.0 9.0
0.0 -60 -40 -20 0
VGS = 10V
20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature ( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRF1404S/LPbF
12000
10000
VGS , Gate-to-Source Voltage (V)
VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd
20
ID = 95A VDS = 32V VDS = 20V
16
C, Capacitance (pF)
8000
Ciss
12
6000
8
4000
Coss
2000
4
0
Crss
1 10 100
0
FOR TEST CIRCUIT SEE FIGURE 13
0 40 80 120 160 200 240
VDS , Drain-to-Source Voltage (V)
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
10000
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY RDS(on)
100
ID , Drain Current (A)
TJ = 175 C
1000 10us 100us 1ms 10 10ms
100
TJ = 25 C
10
1 0.4
V GS = 0 V
0.8 1.2 1.6 2.0 2.4
1
TC = 25 C TJ = 175 C Single Pulse
1 10 100
VSD ,Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRF1404S/LPbF
200
LIMITED BY PACKAGE
160
VDS VGS RG 10V
Pulse Width 1 s Duty Factor 0.1 %
RD
D.U.T.
+
ID , Drain Current (A)
-V DD
120
80
Fig 10a. Switching Time Test Circuit
40
VDS 90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( C)
Fig 9. Maximum Drain Current Vs. Case Temperature
10% VGS
td(on) tr t d(off) tf
Fig 10b. Switching Time Waveforms
1
Thermal Response(Z thJC )
D = 0.50
0.20 0.1 0.10 0.05 0.02 0.01 PDM t1 SINGLE PULSE (THERMAL RESPONSE) t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x Z thJC + TC 0.001 0.01 0.1 1
0.01 0.00001
0.0001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRF1404S/LPbF
EAS , Single Pulse Avalanche Energy (mJ)
15V
1200
TOP BOTTOM
VDS
L
DRIVER
1000
ID 39A 67A 95A
800
RG
20V
D.U.T
IAS tp
+ V - DD
A
600
0.01
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
400
200
0
25
Starting TJ , Junction Temperature( C)
50
75
100
125
150
175
I AS
Fig 12b. Unclamped Inductive Waveforms
QG
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
10 V
QGS
QGD
V DSav , Avalanche Voltage ( V )
50
VG
48
Charge
46
Fig 13a. Basic Gate Charge Waveform
Current Regulator Same Type as D.U.T.
44
50K 12V .2F .3F
42
D.U.T. VGS
3mA
+ V - DS
40 0 20 40 60 80 100
IAV , Avalanche Current ( A)
IG ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
Fig 12d. Typical Drain-to-Source Voltage Vs. Avalanche Current
6
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IRF1404S/LPbF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-channel HEXFET(R) Power MOSFETs
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IRF1404S/LPbF
Dimensions are shown in millimeters (inches)
D2Pak Package Outline
D2Pak Part Marking Information (Lead-Free)
T H IS IS AN IR F 5 3 0 S W IT H L OT CODE 80 2 4 AS S E M B L E D ON W W 0 2, 20 00 IN T H E AS S E M B L Y L IN E "L " N ote: "P " in as s em bly lin e po s itio n in dicates "L ead-F r ee" IN T E R N AT IO N AL R E C T IF IE R L OGO AS S E M B L Y L O T CO D E P AR T N U M B E R F 5 30 S D AT E C O D E Y E AR 0 = 2 0 0 0 W E E K 02 L IN E L
OR
IN T E R N AT IO N AL R E C T IF IE R L O GO AS S E M B L Y L OT COD E P AR T N U M B E R F 530S D AT E CO D E P = D E S IG N AT E S L E AD -F R E E P R O D U C T (O P T IO N AL ) Y E AR 0 = 2 0 0 0 W E E K 02 A = AS S E M B L Y S IT E CO D E
8
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IRF1404S/LPbF
TO-262 Package Outline
IGBT 1- GATE 2- COLLECTOR 3- EMITTER
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L LOT CODE 1789 AS SEMBLED ON WW 19, 1997 IN T HE ASS EMBLY LINE "C" Note: "P" in as s embly line pos ition indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO ASS EMBLY LOT CODE PART NUMBER
DAT E CODE YEAR 7 = 1997 WEEK 19 LINE C
OR
INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 1997 WEEK 19 A = AS S EMBLY S ITE CODE
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9
IRF1404S/LPbF
D2Pak Tape & Reel Infomation
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153)
1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457) 11.40 (.449)
15.42 (.609) 15.22 (.601)
24.30 (.957) 23.90 (.941)
TRL
10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178)
FEED DIRECTION
13.50 (.532) 12.80 (.504)
27.40 (1.079) 23.90 (.941)
4
330.00 (14.173) MAX.
60.00 (2.362) MIN.
NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039) 24.40 (.961) 3
30.40 (1.197) MAX. 4
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.03/04
10
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Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/

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