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ST
Sitronix
1. INTRODUCTION
drive liquid crystal, it is possible to make a display system with the fewest components.
ST7033
4 x 96 Dot Matrix LCD Controller/Driver
The ST7033 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 96 segment and 4 common driver circuits. This chip is connected directly to a microprocessor, accepts 3-line serial peripheral interface (SPI), display data can stores in an on-chip display data RAM of 4 x 96 bits. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits to
2. FEATURES
Single-chip LCD controller & driver Driver Output Circuits 4 common outputs / 96 segment. Output 96 segment drivers : up to forty-eight 8-segment numeric characters; up to twenty-five 15-segment alphanumeric characters; or any graphics of up to 384 elements On-chip Display Data Ram Capacity: 4X96=384bits Microprocessor Interface Parallel MPU interface: 8-bit parallel 6800-series or 8080-series Serial MPU interface: 4-line and 3-line SPI (serial peripheral interfaces) are available. On-chip Low Power Analog Circuit Built-in Booster (x4 or x5) circuit generates LCD supply voltage (external V0/XV0 voltage supply is also supported). Built-in high-accuracy Regulator. Built-in voltage follower generates LCD bias voltages Built-in Oscillator requires no external components (external clock is also supported) External RESB (reset) pin Logic supply voltage range VDD1-VSS: 1.65V~3.4V VDD2-VSS: 2.5V~3.4V Display supply voltage 4.0V Temperature range: -30 to +80 degree
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3. ST7033 PAD ARRANGEMENT (COG)
Dice Size: Bump Height: Chip Thickness: Bump Pitch: PAD Number 1~23, 120~142, 143~153, 227~238: 24~119: 154~199, 213~226: 200~205, 207~212: 23-24: 119-120: Pitch (um) 37.2 33 59.3 33.3 69.1 60.70 153-154: 199-200 205-206, 206-207 212-213 226-227 PAD Number Pitch (um) 86.97 46.66 38.8 53.44 79.9 5080um X 770um 15um 300um
92
55
112.5
SEG95 COM0
58.5
SEG0
Ver 1.1
NC NC
NC NC
NC NC
NC NC
T12
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4-1. PAD CENTER COORDINATES
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Ver 1.1 NAME NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC SEG[0] SEG[1] SEG[2] SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] X 2450.80 2413.60 2376.40 2339.20 2302.00 2264.80 2227.60 2190.40 2153.20 2116.00 2078.80 2041.60 2004.40 1967.20 1930.00 1892.80 1855.60 1818.40 1781.20 1744.00 1706.80 1669.60 1632.40 1563.30 1530.30 1497.30 1464.30 1431.30 1398.30 1365.30 1332.30 1299.30 1266.30 1233.30 1200.30 1167.30 1134.30 1101.30 1068.30 1035.30 1002.30 969.30 936.30 903.30 870.30 Y 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 3/39 NO. 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 NAME SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] X 837.30 804.30 771.30 738.30 705.30 672.30 639.30 606.30 573.30 540.30 507.30 474.30 441.30 408.30 375.30 342.30 309.30 276.30 243.30 210.30 177.30 144.30 111.30 78.30 45.30 12.30 -20.71 -53.71 -86.71 -119.71 -152.71 -185.71 -218.71 -251.71 -284.71 -317.71 -350.71 -383.71 -416.71 -449.71 -482.71 -515.71 -548.71 -581.71 -614.71 Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 2009/07/17
ST7033
NO. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Ver 1.1 NAME SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] SEG[93] SEG[94] SEG[95] NC COM[0] COM[1] COM[2] COM[3] NC NC NC NC NC NC NC NC NC NC NC NC NC NC X -647.71 -680.71 -713.71 -746.71 -779.71 -812.71 -845.71 -878.71 -911.71 -944.71 -977.71 -1010.71 -1043.71 -1076.71 -1109.71 -1142.71 -1175.71 -1208.71 -1241.71 -1274.71 -1307.71 -1340.71 -1373.71 -1406.71 -1439.71 -1472.71 -1505.71 -1538.71 -1571.71 -1632.40 -1669.60 -1706.80 -1744.00 -1781.20 -1818.40 -1855.60 -1892.80 -1930.00 -1967.20 -2004.40 -2041.60 -2078.80 -2116.00 -2153.20 -2190.40 -2227.60 -2264.80 -2302.00 Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 4/39 NO. 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 NAME NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VM VM VM VGO VGO VGI VGI VGI VGI VGS /RESB /CSB PS0 PS1 TMX TMY BR MODE CP VSS VSS VSS VSS VSS RW_WR E_RD DA A0 D[7] D[6] D[5] D[4] D[3] X -2339.20 -2376.40 -2413.60 -2450.80 -2450.80 -2413.60 -2376.40 -2339.20 -2302.00 -2264.80 -2227.60 -2190.40 -2153.20 -2116.00 -2078.80 -1991.84 -1932.53 -1873.23 -1813.92 -1754.62 -1695.31 -1636.01 -1576.70 -1517.40 -1458.09 -1398.79 -1339.49 -1280.18 -1220.88 -1161.57 -1102.27 -1042.96 -983.66 -924.35 -865.05 -805.74 -746.43 -687.13 -627.83 -568.52 -509.22 -449.91 -390.61 -331.30 -272.00 -212.69 -153.39 -94.08 Y 293.00 293.00 293.00 293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 2009/07/17
ST7033
NO. 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 NAME D[2] D[1] D[0] OSC VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 VRS T[1] T[2] T[3] T[4] T[5] T[6] T[0] T[7] T[8] T[9] T[10] T[11] T[12] V0O V0O V0I V0I V0I V0I V0S XV0O XV0O XV0I XV0I XV0I XV0I XV0S NC NC NC NC NC NC NC X -34.78 24.54 83.84 143.15 202.45 261.75 321.06 380.37 439.67 498.97 558.28 617.59 676.89 723.54 756.84 790.14 823.44 856.74 890.04 928.84 967.64 1000.94 1034.24 1067.54 1100.84 1134.14 1187.58 1246.89 1306.20 1365.50 1424.80 1484.11 1543.42 1605.87 1665.17 1724.48 1783.79 1843.09 1902.39 1961.70 2041.60 2078.80 2116.00 2153.20 2190.40 2227.60 2264.80 Y -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 NO. 234 235 236 237 238 NAME NC NC NC NC NC X 2302.00 2339.20 2376.40 2413.60 2450.80 Y -293.00 -293.00 -293.00 -293.00 -293.00
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5. BLOCK DIAGRAM
SEG0...SEG95
COM0...COM3
VM VG
SEGMENT Drivers
COMMON Drivers
VM VGI VGO VGS XV0I XV0O XV0S V0I V0O V0S
Voltage Follower Display Data Latchs XV0 Generator V0 Generator Power System
XV0
COMMON Output Controller Timing Generator Oscillator OSC
V0
VDD2
Display Data RAM (DDRAM) 4X96
VDD1 VSS
Data Register
Address Counter
Control Registers
Command Decoder Reset Circuit
MPU INTERFACE (Parallel / Serial)
D7 D6 D5 D4 D3 D2 D1 D0 E_RD RW_WR A0 /CSB TMY TMX BR CP MODE DA
/RESB
PS1 PS0
Figure 1. Block Diagram
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6. PINNING DESCRIPTIONS
Pin Name LCD driver outputs I/O
LCD segment driver outputs. The display data and the M signal control the output voltage of segment driver. Display data SEG0 to SEG95 O Frame Segment drover output voltage Normal display VG VSS VSS VG VSS Reverse display VSS VG VG VSS VSS 96
Description
Pin Count
H H + L L + Power save mode LCD column driver outputs.
The internal scanning data and the M signal control the output voltage of common driver. Display data COM0 to COM3 O H H + L L + Power save mode Frame Common drover output voltage Normal display Reverse display 68 XV0 V0 VM VM VSS
MICROPROCESSOR INTERFACE
Microprocessor interface mode selection pins. PS1 PS[1,0] I 1 1 0 0 Chip select input pin. /CSB I Data/instruction I/O is enabled only when /CSB is "L". When chip select is non-active, D7...D0 are high impedance. /RESB I Reset input pin. When /RESB is "L", initialization is executed. It determines whether the data bits are data or a command. A0=" H ": Indicates that D0 to D7 are display data. A0=" L ": Indicates that D0 to D7 are control data. There is no A0 pin in three line , so this pin can fix to " H" Read/Write operation control pin (if using Parallel interface). MPU Type RW_WR I 6800-series RW_WR R/W Interface Mode R/W="H": Read; R/W="L": Write. Signals (Instruction or Data) on 8080-series /WR data bus will be latched at the raising edge of this signal. 1 1 1 PS0 1 0 1 0 Interface Mode 8080-series parallel MPU interface 6800-series parallel MPU interface 4-line SPI MPU interface 3-line SPI MPU interface 2
A0
I
1
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Read/Write operation control pin (if using Parallel interface). MPU Type E_RD Interface Mode Signals (Instruction or Data) on E_RD I 6800-series E data bus will be latched by MPU or this IC (depends on R/W) at the falling edge of this signal. Internal status (or display data) 8080-series /RD will be read out to data bus after the falling edge of this signal. Data Bus. If /CSB signal is not actived, D7...D0 are high impedance. Parallel interface (6800 or 8080): I/O port which is connected to the standard 8-bit MPU data bus. D0...D7 I Serial SPI interface (3 line or 4 line): SCLK: D0; SDA: D1~D3; D4~D7 must connect to VDD1. 8 1
LCD DRIVER SUPPLY
OSC="H": Use the built-in oscillator. OSC="L": Both external clock and built-in oscillator are inhibited. And OSC I the display circuits will not be clocked and kept in a DC state. To avoid this, the chip should always be put into Power-Down Mode before stopping the clock. If using external clock, connect this pin to the external clock. 1
POWER SUPPLY
VSS VDD1 Power Power Ground. Digital circuits supply voltage. The 2 power supply rails, VDD1 and VDD2, could be connected together. Use this power to be the high voltage level for the Option pins. VDD2 Power Power Supply Analog circuits supply voltage. The 2 power supply rails, VDD and VDD2, could be connected together. Negative LCD driver supply voltages. XV0I, XV0O, XV0S XV0I, XV0O & XV0S should be separated in ITO layout. XV0I, XV0O & XV0S should be connected together in FPC layout. This is a multi-level power supply for the liquid crystal. V0 VG VM VSS XV0 V0I, V0O & V0S should be separated in ITO layout. V0I, V0O & V0S should be connected together in FPC layout. VGI, VGO & VGS should be separated in ITO layout. VGI, VGO & VGS should be connected together in FPC layout. VM VRS Power Supply Power LCD driving voltage for commons. Reserved to monitor internal Voltage Regulator reference level, must be left open. Test pin. Must fix to "L" Set Booster stage. CP I VSS=4X; VDD=5X. 1 3 1 6 7 4 4 5
V0I, V0O, V0S; VGI, VGO, VGS
Power Supply
Configuration Pins
MODE I 1
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BR I Test pin. Must fix to "L" 1
Test Pin
T0~T12 TMX --I Test pins. Do not use these pins. Mirror X: SEG bi-direction selection (refer to pad center coordinates). TMX connect to VSS :MX mode1(refer to segment driver direction select) TMX connect to VDD1 :MX mode2(refer to segment driver direction select) Mirror Y: COM bi-direction selection (refer to pad center coordinates). TMY I TMY connect to VSS: MY mode1(refer to common driver direction select) TMY connect to VDD1: MY mode2(refer to common driver direction select) DA I Test pin. Must fix to "L" 1 1 1 13
Recommended I/O PIN ITO Resistance Limitation PIN Name PS[1:0],OSC,CP,BR T0~T12,VRS VDD1, VDD2, VSS V0, VG , VM , XV0 A0,/WR,/RD,/CSB, D0 ...D7 /RESB <5K Floating <100 <500 <1K RESB<10K ITO Resister
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7. FUNCTIONS DESCRIPTION
MICROPROCESSOR INTERFACE Chip Select Input There is /CSB pin for chip selection. The ST7033 can interface with an MPU when /CSB is "L". When /CSB is "H", the internal shift register and the counter are reset.
Parallel / Serial Interface ST7033 has five types of interface with an MPU, which are three serial and two parallel interfaces. This parallel or serial interface is determined by PS [1:0] pin as shown in Table 1.
PS1 H H L L
PS0 H L H L
/CSB A0 State /CSB A0 8080-series parallel MPU interface /CSB A0 6800-series parallel MPU interface /CSB A0 4 Pin-SPI MPU interface /CSB "*" 3 Pin-SPI MPU interface Table 1. Parallel/Serial Interface Mode
Parallel Interface The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS1~PS0 as shown in Table 2. The type of data transfer is determined by signals at A0, /RD (E) and /WR(R/W) as shown in Table 3.
PS1 H H
PS0 H L
/CSB A0 /RD (E) /WR (R/W) DB0 to DB7 MPU bus /CSB A0 /RD /WR DB0 to DB7 8080-series /CSB A0 E R/W DB0 to DB7 6800-series Table 2. Microprocessor Selection for Parallel Interface
Common A0 H H L L
6800-series E R/W H H H L H H H L
8080-series Description /RD /WR L H Display data read out H L Display data write L H Register status read H L Writes to internal register (instruction) Table 3. Parallel Data Transfer
NOTE: By fixing /RD (E) pin at high (VDD1) in 6800-series interface mode, /CSB can be used as enable signal. In this case, interface data is latched at the rising edge of /CSB and the access type is determined by signals on A0, /WR(R/W) just same as 6800-series mode.
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Serial Interface Serial Mode 4-line SPI interface 3-line SPI interface PS1 L L PS0 H L /CSB /CSB /CSB A0 Used Not Used Fix to "H"
Table 4. Microprocessor Selection for Serial Interface PS1= "L", PS0= "H": 4-line SPI interface When the ST7033 is active (/CSB="L"), serial data (D1) and serial clock (D0) inputs are enabled. When /CSB is "High", the internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication is controlled by the register selection pin (A0). The signals transferred on data bus will be display data when A0 is high and will be instruction when A0 is low. The read feature is not supported in this mode. Serial data on SDA (D1) is latched at the rising edge of serial clock on SCLK (D0). After the eighth serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column address pointer will be increased by one automatically after each byte of DDRAM access.
Figure 2. 4-Line SPI Timing
3-line SPI interface When ST7033 is active (/CSB="L"), SDA-out, SDA-in and SCL inputs are enabled. When ST7033 is not active (/CSB="H"), the internal 8-bit shift register and the 3-bit counter are reset. The A0 pin is not available in this mode. Before issuing serial data, an A0 bit is required to indicate the access is data or instruction. The read feature is not supported in this mode except ID code read feature. Serial data on SDA (D1) is latched at the rising edge of serial clock on SCLK (D0). After the eighth serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column address pointer will be increased by one automatically after each byte of DDRAM access.
Figure 3. 3-Line SPI Timing
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DISPLAY DATA RAM (DDRAM) The ST7033 contains a 4x96 bit static RAM that stores the display data. The display data RAM store the dot data for the LCD.It is 4-row by 96-column addressable array. Each pixel can be selected when the column addresses are specified.Data are written to ram directly through D0 to D3 and D4 to D7 are disabled bits. The display data from the microprocessor correspond to the LCD common lines. The microprocessor can write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker.
Line Address Circuit This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line Address repeatedly.At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 96-bit RAM data to the display data latch circuit. Column Address Circuit Column Address Circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM. The display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data write command. This allows the MPU display data to be accessed continuously. ADDRESSING Data is downloaded in bytes into the RAM matrix of ST7033 as indicated in Figure 4. The display RAM has a matrix of 4 by 96 bits. The address pointer addresses the columns. The column address ranges are: 0 to 95 (1011111), .Addresses outside these ranges are not allowed. After the last column address (95) wraps around to 0 .
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Data Structure
Line Address D0 D1 D2 D3 D4 D5 D6 D7 00H 01H 02H 03H Start
COM output COM0 COM1 COM2 COM3 COM3 COM2 COM1 COM0
......
Data
D4~D7 are disabled bits
5FH 5EH 5DH 5CH 5BH 5AH 59H 58H 57H 08H 07H 06H 05H 04H 03H 02H 01H 00H
Normal Reverse direction direction MY=0 MY=1
Column Address
......
Start
Normal direction MX=0 Reverse direction MX=1 SEG88 SEG87 SEG90 SEG89 SEG95 SEG94 SEG93 SEG92 SEG91 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0
......
SEG output
SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95
SEG7 SEG8
SEG5 SEG6
SEG0 SEG1 SEG2 SEG3 SEG4
......
Figure 4. Display Data RAM Map (1/4 Duty)
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LCD layout reference
Layout method LCD SEG LCD COM Display RAM filling order
SEGn+2 SEGn+3
a f g e d DP
SEGn
COM0
SEGn COM0 COM1 c x x x
SEGn+1 SEGn+2 b x x x a x x x
SEGn+3 f x x x
SEGn+4 g x x x
SEGn+5 e x x x
SEGn+6 d x x x
SEGn+7 DP x x x
b
SEGn+1
Method 1
SEGn+4 SEGn+5 SEGn+6
c
SEGn+7
COM2 COM3
SEGn SEGn+1
a f g b
COM0
SEGn COM0 COM1 a b x x
SEGn+1 f g x x
SEGn+2 e c x x
SEGn+3 d DP x x
Method 2
SEGn+2 SEGn+3
e d
c DP
COM1
COM2 COM3
SEGn+1 SEGn+2
a f g e d DP c b
SEGn
COM0
SEGn COM0 COM1 b DP c x
SEGn+1 SEGn+2 a d g x f e x x
Method 3
COM1
COM2
COM2 COM3
SEGn
a f b g e c d DP
COM0
COM2
SEGn COM0 COM1 a c b DP
SEGn+1 f e g d
Method 4
COM1
COM3
COM2 COM3
SEGn+1
Figure 5. Relationships between LCD layout and display RAM filling order and display data Notes 1' x `= data bit unchanged.
Notes 2ST7033 is always operating in 1/4 duty.
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LCD DRIVER CIRCUIT 4-channel common drivers and 96-channel segment drivers configure this driver circuit. This LCD panel driver voltage depends on the combination of display data and frame (positive or negative).
Figure 6. LCD Driver Waveforms
Liquid Crystal Driver Power Circuit The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction.
Figure 7. External Components on V0, XV0 and VG
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8. RESET CIRCUIT
Setting /RESB to "L" or Reset instruction can initialize internal function. When /RESB becomes "L", following procedure is occurred. Power save mode is entered --Oscillator circuit is stopped --The LCD power supply circuit is stopped --Display OFF --Display all point ON --Segment/Common output go to the VSS level Display normal Column address: 0 Common scan direction : MY=0 Segment scan direction : MX=0 Power control [VB VR VF]=0 Booster: CP pad
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9-1. INSTRUCTION TABLE
COMMAND Display data write Display ON/OFF Display normal/reverse Display all points ON/OFF Page address set Column address set Upper 3-bit address Column address set Lower 4-bit address Segment driver direction select A0 1 0 0 0 0 0 0 D7 D7 1 1 1 1 0 0 D6 D6 0 0 0 0 0 0 D5 D5 1 1 1 1 0 0 CODE D4 D4 0 0 0 1 1 0 D3 D3 1 0 0 0 * X3 D2 D2 1 1 1 0 X6 X2 D1 D1 1 1 0 0 X5 X1 D0 D0 0 1 0 1 0 1 0 X4 X0 DESCRIPTION Write data to RAM LCD display 0:OFF,1:ON LCD display 0:normal;1:reverse LCD display 0:normal;1:all points ON Set the DDRAM page address Set the DDRAM column address
0
1
0
1
0
0
0
0
Common driver direction select Power control set Power save mode
0
1
1
0
0
MY
*
*
0 -
0 1 1 1 1 1
0 1 1 1 0 1
1 1 1 1 1 1
0 0 0 1 0 1
1 0 0 0 1 0
VB 0 0 0 1 0
VR 1 1 0 0 0
Reset 0 NOP 0 Enter mode set 0 Duty mode set 0 Finish mode set 0 Notes: "*" = Disabled bit
Sets the correspondence between the DDRAM column MX address and the SEG driver output Sets the correspondence between the DDRAM line * address and the COM driver output Set the on-chip power supply VF circuit operation mode Compound command of Display OFF and Display-all-points-ON 0 Software reset 1 No operation 1 Enter mode set 0 Set 1/4 duty 0 Finish mode set
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9-2. INSTRUCTION DESCRIPTION
Display data Write 8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address . The column address is increased by 1 automatically so that the microprocessor can continuously write data . During auto-increment, the column address wraps to 0 after the last column is written. A0 1 D7 D6 D5 D4 D3 Write data D2 D1 D0 Description Write to the DDRAM
Display ON/OFF This command turns the display ON and OFF. A0 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 1 Description Display OFF Display ON
Display Normal/Reverse This command can reserve the lit and unlit without overwriting the content of the DDRAM. A0 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 0 1 Description LCD ON Voltage LCD OFF Voltage
Display All Points ON/OFF The command makes it possible to force all display points ON regardless of the content of the DDRAM. Even when this is done, the DDRAM contents are maintained. This command takes priority over the Display normal/reverse command. A0 D7 D6 D5 D4 D3 D2 D1 D0 Description 0 Normal Display Mode 0 1 0 1 0 0 1 0 1 Display All Points ON When the Display all points ON command is executed when in the Display OFF mode, Power Save mode is entered. See the "Power Save mode" for detail. Page Address Set This command specifies the start page address of the DDRAM. A0 0 D7 1 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0 Description Ser page address
Column Address Set This command specifies the column address of the DDRAM. The column address is split into two sections (the upper 3-bits and lower 4-bits) when it is set. Each time the DDRAM is accessed, the column address automatically increments by +1, imaging it possible for the MCU to continuously access to the display data. After the last column address (5FH), column address returns to 00H. A0 0 D7 0 D6 0 D5 0 D4 1 0 D3 * X3 D2 X6 X2 D1 X5 X1 D0 X4 X0 Description Upper bit address Lower bit address
Notes:' * `Disabled bit
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X6 0 0 0 0 : 1 1 X5 0 0 0 0 : 0 0 X4 0 0 0 0 : 1 1 X3 0 0 0 0 : 1 1 X2 0 0 0 0 : 1 1 X1 0 0 1 1 : 1 1 X0 0 1 0 1 : 0 1 Column Address 0 1 2 3 : 94 95
Segment Driver Direction Select This command can reverse the correspondence between the DDRAM column address and the segment driver output A0 D7 D6 D5 D4 D3 D2 D1 D0 Description MX=0 SEG95 SEG0 TMX=VSS MX=1 SEG0 SEG95 MX mode 1 0 1 0 1 0 0 0 0 MX MX=0 SEG0 SEG95 TMX=VDD1 MX=1 SEG95 SEG0 MX mode 2 Common Driver Direction Select This command can reverse the correspondence between the DDRAM line address and the common driver output A0 D7 D6 D5 D4 D3 D2 D1 D0 Description TMY=VSS MY=0 COM0 COM67 MY mode 1 MY=1 COM67 COM0 0 1 1 0 0 MY * * * TMY=VDD1 MY=0 COM67 COM0 MY mode 2 MY=1 COM0 COM67 Notes1:' * `Disabled bit
Power control set This command sets the on-chip power supply function ON/OFF. A0 D7 D6 D5 D4 D3 D2 D1 D0 Description Booster: OFF 0 0 0 Voltage Regulator: OFF Voltage Follower: OFF Booster: ON 1 1 1 Voltage Regulator: ON Voltage Follower: ON (D2 : Booster, D1 : Voltage Regulator, D0 : Voltage Follower)
0
0
0
1
0
1
Set 1/4 duty mode (Combinative instructions) These combinative instructions set the driver into 1/4 duty mode. Enter mode set A0 0 D7 1 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1 Description Enter mode set
Duty mode set A0 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 0 D0 0 Description Set 1/4 duty
Finish mode set A0 0 D7 1 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0 Description Finish mode set
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Power Save Mode If the display all points ON command is executed when the display is in display OFF mode, power saver mode is entered. This mode stops every operation of the LCD display system.
Power save (Display OFF & Display all points ON) Command
Power save mode
Effect
Power save OFF (Display all points OFF)
Power save mode canceled Figure 8. Power Save Mode The internal states in power save mode are as follows: -The oscillator circuit is stopped -The LCD driver circuit is stopped -The LCD driver circuit is stopped and segment/common driver output s to VSS level -The display data and operation mode before execution of the Power save are held, and the MCU can access to the DDRAM and internal registers. Reset When this command is issued, the driver is initialized. This command doesn't change DDRAM content. A0 0 NOP Non-operation command A0 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1 Description No operation D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0 Description Software reset
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Command Description Referential instruction setup flow for power on:
Referential instruction setup flow for power down:
Figure 9. Power On and Power Down Sequence
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10. LIMITING VALUES
In accordance with the Absolute Maximum Rating System; see notes 1 and 2. Parameter Power supply voltage Power supply voltage Power supply voltage (VDD2 standard) Power supply voltage (VDD2 standard) Operating temperature Storage temperature VDD1 VDD2 V0, |XV0| VG, VM TOPR TSTR Symbol Conditions -0.3 ~ 3.6 -0.3 ~ 3.6 -0.3 ~ 13.5 0.3 to V0 -30 to +80 -65 to +150 V V V V C C Unit
Figure 10. Notes 1. Stresses above those listed under Limiting Values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 3. Insure that the voltage levels of VG, VM, VSS, and XV0 are always such that V0 VG VM VSS XV0
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11. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices
12. DC CHARACTERISTICS
VSS = 0 V; Ta = -30 to +80; unless otherwise specified. Item Symbol Condition Rating Min. 1.65 Typ. -- Max. 3.4 Units Applicable Pin VSS
Operating Voltage (1)
VDD1
V
Operating Voltage (2) High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input leakage current Output leakage current Liquid Crystal Driver ON
VDD2 (Relative to VSS) VIHC VILC VOHC IOH=1mA VOLC IOL1mA ILI ILO Ta= 25 C V=10% V0 =9.0 V VG = 2.0 V
2.5 0.7 x VDD1 VSS 0.8 x VDD1 VSS -1.0 -3.0 -- --
-- -- -- -- -- -- -- 0.8 0.9
3.4 VDD1
V V
VSS
0.3 x VDD1 V VDD1 V
0.2 x VDD1 V 1.0 3.0 -- K -- A A SEGn COMn
Resistance
RON
Frame frequency
FR
--
70
--
Hz
Internal Power
Supply Step-up output voltage Circuit Voltage regulator Circuit Operating Voltage
V0
(V0 To VSS)
--
4
--
V
V0
XV0
(VG To XV0)
--
-4
--
V
XV0
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Dynamic Consumption Current : During Display, with the Internal Power Supply ON Current consumed by total ICs(bare die) Test pattern Power Down Symbol ISS Condition Ta = 25 C Rating Min. -- Typ. 1.0 Max. 10 Units A Notes
Notes to the DC characteristics 1. The maximum possible V0 oltage that may be generated is dependent on voltage, temperature and (display) load. 2. During power down all static currents are switched off.
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13. TIMING CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0
tAW8 tAS8 /CSB tCYC8 tCCLR,tCCLW WR,RD
tAH8
tCCHR,tCCHW tDS8 D0 to D7 (Write) tDH8
tACC8 D0 to D7 (Read)
tOH8
Figure 11. Parallel 8080 Series Interface Characteristics
(VDD1 = 3.3V , Ta =25C) Rating Item Address hold time Address setup time A0 Address setup time System cycle time Enable L pulse width (WRITE) /WR Enable H pulse width (WRITE) WRITE Data setup time D0 to D7 WRITE Address hold time tDH8 50 -- tCCHW tDS8 50 60 -- -- tAS8 tCYC8 tCCLW 60 350 70 -- -- ns -- Signal Symbol tAH8 tAW8 Condition Min. 10 80 Max. -- -- Units
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(VDD1 = 2.8V , Ta =25 ) C Item Address hold time Address setup time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) WRITE Data setup time WRITE Address hold time D0 to D7 /WR A0 Signal Symbol tAH8 tAW8 tAS8 tCYC8 tCCLW tCCHW tDS8 tDH8 Condition Rating Min. 15 120 80 450 120 100 90 60 Max. -- -- -- -- -- -- -- -- ns Units
(VDD1 = 1.8V , Ta =25 C) Item Address hold time Address setup time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) WRITE Data setup time WRITE Address hold time D0 to D7 /WR A0 Signal Symbol tAH8 tAW8 tAS8 tCYC8 tCCLW tCCHW tDS8 tDH8 Condition Rating Min. 30 150 100 550 170 150 120 70 Max. -- -- -- -- -- -- -- -- ns Units
Notes1:The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,(tr +tf) (tCYC8 - tCCLW - tCCHW) for (tr + tf) (tCYC8 - tCCLR - tCCHR) are specified. Notes2: All timing is specified using 20% and 80% of VDD1 as the reference. Notes3: tCCLW and tCCLR are specified as the overlap between /CSB being "L" and /WR and /RD being at the "L" level.
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System Bus Read/Write Characteristics 1 (For the 6800 Series MPU)
A0 R/W tAW6 /CSB tAH6
tCYC6 tEWHR, tEWHW E tEWLR, tEWLW tDS6 D0 to D7 (Write) tDH6
tACC6 D0 to D7 (Read)
tOH6
Figure 12. Parallel 6800 Series Interface Characteristics
(VDD1 = 3.3V , Ta =25 C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) WRITE Data setup time WRITE Address hold time D0 to D7 E A0 R/W Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tDS6 tDH6 Condition Rating Min. 10 80 240 70 50 60 50 Max. -- -- -- -- -- -- -- ns Units
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(VDD1 = 2.8V , Ta =25C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) WRITE Data setup time WRITE Address hold time D0 to D7 E A0 R/W Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tDS6 tDH6 Condition Rating Min. 15 100 340 120 100 120 60 Max. -- -- -- -- -- -- -- ns Units
(VDD1 = 1.8V , Ta =25 C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) WRITE Data setup time WRITE Address hold time D0 to D7 E A0 R/W Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tDS6 tDH6 Condition Rating Min. 30 150 440 170 150 180 70 Max. -- -- -- -- -- -- -- ns Units
Notes1:The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,(tr +tf) (tCYC6 - tEWLW - tEWHW) for (tr + tf) (tCYC6 - tEWLR - tEWHR) are specified. Notes2:All timing is specified using 20% and 80% of VDD1 as the reference. Notes3:tEWLW and tEWLR are specified as the overlap between /CSB being "L" and E.
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SERIAL INTERFACE (4-Line Interface)
tCSS tCSH
/CSB
tSAS A0 tSCYC tSLW SCLK
tSAH
tSHW tf tSDS SDA tr tSDH
Figure 13. 4- Line Serial Interface Characteristics (VDD1 = 3.3V , Ta =25 ) C Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SDA /CSB SCLK Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 120 60 60 20 90 20 10 20 120 Max. -- -- -- -- -- -- -- -- -- ns Units
(VDD1 = 2.8V , Ta =-25 C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SDA /CSB SCLK Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 200 100 100 30 120 30 20 30 150 Max. -- -- -- -- -- -- -- -- -- ns Units
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(VDD1 = 1.8V , Ta =25 C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SDA /CSB SCLK Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 280 140 140 50 150 50 50 40 180 Max. -- -- -- -- -- -- -- -- -- ns Units
Notes1: The input signal rise and fall time (tr, tf) are specified at 15 ns or less. Notes2: All timing is specified using 20% and 80% of VDD1 as the standard.
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SERIAL INTERFACE (3-Line Interface)
Figure 14. 3- Line Serial Interface Characteristics (VDD1=3.3V ,Ta=25) Item Serial Clock Period(Write) SCL "H" pulse width(Write) SCL "L" pulse width(Write) Data setup time Data hold time CS-SCL time CS-SCL time SCL-CS CS "H" pulse width SDAIN /CSB /CSB /CSB SCLK Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH tSCC tCHW Condition Rating Min. 120 60 60 30 30 30 30 10 30 Max. -- -- -- -- -- -- -- -- -- ns Units
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(VDD1=2.8V ,Ta=25) Item Serial Clock Period(Write) SCL "H" pulse width(Write) SCL "L" pulse width(Write) Data setup time Data hold time CS-SCL time CS-SCL time SCL-CS CS "H" pulse width SDAIN /CSB /CSB /CSB SCLK Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH tSCC tCHW Condition Rating Min. 180 90 90 40 40 40 40 15 35 Max. -- -- -- -- -- -- -- -- -- ns Units
(VDD1=1.8V ,Ta=25) Item Serial Clock Period(Write) SCL "H" pulse width(Write) SCL "L" pulse width(Write) Data setup time Data hold time CS-SCL time CS-SCL time SCL-CS CS "H" pulse width SDAIN /CSB /CSB /CSB SCLK Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH tSCC tCHW Condition Rating Min. 250 100 100 60 60 60 65 20 45 Max. -- -- -- -- -- -- -- -- -- ns Units
Notes1:The input signal rise and fall time (tr, tf) are specified at 15 ns or less. Notes2:All timing is specified using 30% and 70% of VDD1 as the standard.
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14. RESET TIMING
/RESB tRJ tRW
tR Internal status During reset Reset complete
Figure 15. Reset Timing Characteristics (VDD1 = 3.3V , Ta = 25 ) C Item Reset time Reset "L" pulse width Reset rejection (for noise spike) Signal Symbol /RESB tR /RESB tRW /RESB tRJ Condition Rating Min. 20 2 -- Typ. -- -- -- Max. -- -- 1 Units us us us
(VDD1 = 2.8V , Ta =25 ) C Item Reset time Reset "L" pulse width Reset rejection (for noise spike) Signal Symbol /RESB tR /RESB tRW /RESB tRJ Condition Rating Min. 20 2 -- Typ. -- -- -- Max. -- -- 1 Units us us us
(VDD1 =1.8V , Ta = 25 ) C Item Reset time Reset "L" pulse width Reset rejection (for noise spike) Signal Symbol /RESB tR /RESB tRW /RESB tRJ Condition Rating Min. 30 3 -- Typ. -- -- -- Max. -- -- 1 Units us us us
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1
NC
238 .........
NC
..........................................
227
NC
226
222-225 220-221
219
215-218 213-214
23 24
NC SEG0
ST7033
195-198 191-194
15. APPLICATION NOTE
119 120 121 122 123 124
SEG95 NC COM0 COM1 COM2 COM3
190 189 188 187 186 185 184 183 182 181 180 179 178
173-177
.............................................
172 171 170 169 168 167 166 165 164 163
159-162 157-158 154-156
MODE
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BR TMY TMX PS1 PS0 /CSB /RESB VGS VGI VGO VM 153 ................ NC
XV0 V0 VDD2 VDD1 D0 D1 D2 D3 D4 D5 D6 D7 A0 E R/W VSS /CSB /RESB VG
Figure 16. 6800 Parallel Application
.............................................
.............................................
C=1.0uF
212 211 210 209 208 207 206 205 204 203 202 201 200 199
XV0S XV0I XV0O V0S V0I V0O T12 T11 T10 T9 T8 T7 T0 T6 T5 T4 T3 T2 T1 VRS VDD2 VDD1 OSC D0 D1 D2 D3 D4 D5 D6 D7 A0 DA E R/ W Vss CP
ST7033
142
NC
143
NC
IC PAD SIDE
C=1.0uF
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1 .........
NC
238
NC
..........................................
227
NC
226
222-225 220-221
219
215-218 213-214
23 24
NC SEG0
195-198 191-194
119 120 121 122 123 124
SEG95 NC COM0 COM1 COM2 COM3
190 189 188 187 186 185 184 183 182 181 180 179 178
173-177
.............................................
172 171 170 169 168 167 166 165 164 163
159-162 157-158 154-156
MODE
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BR TMY TMX PS1 PS0 /CSB /RESB VGS VGI VGO VM 153 ................ NC
XV0 V0 VDD2 VDD1 D0 D1 D2 D3 D4 D5 D6 D7 A0 /RD /WR VSS /CSB /RESB VG
Figure 17. 8080 Parallel Applicaiton
ST7033
.............................................
.............................................
C=1.0uF
212 211 210 209 208 207 206 205 204 203 202 201 200 199
XV0S XV0I XV0O V0S V0I V0O T12 T11 T10 T9 T8 T7 T0 T6 T5 T4 T3 T2 T1 VRS VDD2 VDD1 OSC D0 D1 D2 D3 D4 D5 D6 D7 A0 DA /RD /WR Vss CP
ST7033
142
NC
143
NC
IC PAD SIDE
C=1.0uF
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.............................................
.............................................
.............................................
..........................................
ST7033
................ .........
IC PAD SIDE
C=1.0uF C=1.0uF
Figure 18. 3-Line Serial Application
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1 .......................................... .........
NC
238
NC
227
NC
23 24
NC SEG0
119 120 121 122 123 124
SEG95 NC COM0 COM1 COM2 COM3
173-177
XV0S 226 XV0I 222-225 XV0O 220-221 219 V0S 215-218 V0I 213-214 V0O 212 T12 211 T11 210 T10 T9 209 T8 208 207 T7 206 T0 205 T6 204 T5 203 T4 202 T3 201 T2 200 T1 199 VRS VDD2 195-198 191-194 VDD1 OSC SCLK SDA_IN SDA_OUT SDA_OUT D4 D5 D6 D7 A0 DA /RD /WR Vss CP
.............................................
172 171 170 169 168 167 166 165 164 163
MODE
153 ................
NC
ST7033
142
NC
143
NC
IC PAD SIDE
159-162 157-158 154-156
BR TMY TMX PS1 PS0 /CSB /RESB VGS VGI VGO VM
C=1.0uF
190 189 188 187 186 185 184 183 182 181 180 179 178
Figure 19. 4-Line Serial Application
ST7033
.............................................
.............................................
C=1.0uF
11 10 9 8 7 6 5 4 3 2 1
XV0 V0 VDD2 VDD1 SCLK SDA A0 VSS /CSB /RESB VG
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ITO Layout Reference
About ITO layout, please refer the following pictures
XV0O XV0S XV0I V0O V0S VDD2
FPC PIN
V0I VDD1
FPC PIN
VGO
VGS
VGI
FPC PIN
FPC PIN
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ST7033 Serial Specification Revision History Version Date Description
1.0 1.1
2008/04/18 First Issue Version 2009/07/15 Modify application note
Ver 1.1
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