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STRUCTURE PRODUCT PART NUMBER PHYSICAL DIMENSION BLOCK DIAGRAM USE FEATURES
Silicon Monolithic Integrated Circuit 256x8 bit Electrically Erasable PROM BU9833GUL-W Fig.-1 Fig.-2 General purpose
256 registers x 8 bits serial architecture Single power supply (1.7V5.5V) Two wire serial interface Self-timed write cycle with automatic erase 8 byte Page Write mode Low power consumption Write ( 5V ) : 1.2mA (Typ.) Read ( 5V ) : 0.2mA (Typ.) Standby ( 5V ) : 0.1A(Typ.) DATA security Write protect feature (WP pin) Inhibit to WRITE at low VCC WLCSP6Pin package ------ VCSP50L1 High reliability fine pattern CMOS technology Endurance : 1,000,000 erase/write cycles Data retention : 40 years Filtered inputs in SCLSDA for noise suppression Initial data FFh in all address ABSOLUTE MAXIMUM RATING (Ta=25) Parameter Supply Voltage Power Dissipation Storage Temperature Operating Temperature Terminal Voltage Symbol VCC Tstg Topr Rating -0.36.5 VCSP50L1 -65125 -4085 -0.3VCC+1.0 *2 220 *1 Unit V mW V
*1 Degradation is done at 2.2mW/ for operation above 25. *2 The max value of Terminal Voltage is not over 6.5V.
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RECOMMENDED OPERATING CONDITION Parameter Supply Voltage Input Voltage Symbol VCC VIN Rating 1.75.5 0VCC Unit V V
DC OPERATING CHARACTERISTICS (Unless otherwise specified Ta=-4085VCC=1.75.5V) Parameter "H" Input Voltage1 "L" Input Voltage1 "H" Input Voltage2 "L" Input Voltage2 "H" Input Voltage3 "L" Input Voltage3 "L" Output Voltage1 "L" Output Voltage2 Input Leakage Current Output Leakage Current Symbol Specification Unit min. VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOL1 VOL2 ILI ILO 0.7VCC -0.3 0.8VCC -0.3 0.9VCC -0.3 -1 -1 typ. max. VCC+1.0 0.3VCC VCC+1.0 0.2VCC VCC+1.0 0.1VCC 0.4 0.2 1 1 V V V V V V V V 2.5VVcc5.5V 2.5VVcc5.5V 1.8VVcc2.5V 1.8VVcc2.5V 1.7VVcc1.8V 1.7VVcc1.8V IOL=3.0mA2.5VVcc5.5V SDA IOL=0.7mA1.7VVcc2.5V SDA test condition
A VIN=0VVCC A VOUT=0VVCC (SDA) VCC=5.5V,fSCL=400Hz,tWR=5ms
ICC1 Operating Current ICC2
2.0
mA
Byte Write Page Write VCC=5.5V,fSCL=400Hz Random Read Current Read Sequential Read VCC=5.5V,SDA,SCL=VCC
0.5
mA
A0,A1,A2=GND,WP=GND This product is not designed for protection against radioactive rays. MEMORY CELL CHARACTERISTICS (Ta=25VCC1.75.5V) Specification Prameter Min. Write/Erase Cycle Data Retention *1 *1 1,000,000 40 Typ. Max. Cycles Years Unit
Standby Current
ISB
2.0
A
*1 Not 100% TESTED
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Product NameBU9833GUL-W
9833
LOT NO.
Fig.-1 PHYSICAL DIMENSION VCSP50L1 Unit : mm BLOCK DIAGRAM
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VCC GND
8bit ADDRESS DECODER
2 Kbit EEPROM ARRAY 8bit SLAVEWORD ADDRESS REGISTER DATA REGISTER
8bit
WP
START
STOP
A2
CONTOROL LOGIC
ACK
SCL
HIGH VOLTAGE GEN.
VCC LEVEL DETECT
SDA
Fig.-2 BLOCK DIAGRAM PIN CONFIGURATION
C B A
C2 C1 B1 B2 A1 A2
INDEX POST
1
2
Fig.-3 BU9833GULbottom view PIN NAME Land No. C2 C1 B2 B1 A2 A1 PIN NAME V A2 WP GND SCL SDA I/O IN IN IN IN/OUT Power Supply Slave Address Set Write Protect Input Ground 0V Serial Clock Input Slave and Word Address, Serial Data Input, Serial Data Output *1 FUNCTIONS
*1 An open drain output requires a pull-up resister.
AC OPERATING CHARACTERISTICS (Unless otherwise specified Ta=-4085VCC=1.75.5V)
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FAST-MODE Parameter Symbol 2.5Vcc5.5V Min. Clock Frequency Data Clock High Period Data Clock Low Period SDA and SCL Rise Time SDA and SCL Fall Time Start Condition Hold Time Start Condition Setup Time Input Data Hold Time Input Data Setup Time Output Data Delay Time Output Data Hold Time Stop Condition Setup Time Bus Free Time Write Cycle Time Noise Spike Width (SDA and SCL) WP Hold Time WP Setup Time WP High Period 1 1 fSCL tHIGH tLOW tR tF tHD:STA tSU:STA tHD:DAT tSU:DAT tPD tDH tSU:STO tBUF tWR tI tHDWP tSUWP tHIGHWP 0.6 1.2 0.6 0.6 0 100 0.1 0.1 0.6 1.2 0 0.1 1.0 Typ. Max. 400 0.3 0.3 0.9 5 0.1
STANDARD-MODE 1.7Vcc5.5V Min. 4.0 4.7 4.0 4.7 0 250 0.2 0.2 4.7 4.7 0 0.1 1.0 Typ. Max. 100 1.0 0.3 3.5 5 0.1 kHz s s s s s s ns ns s s s s ms s ns s s Unit
1ot 100 TESTED
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SYNCHRONOUS DATA TIMING
tR SCL tHD:STA SDA (IN) tBUF SDA (OUT) tPD tDH tSU:DAT tLOW tHD:DAT tF tHIGH
SCL tSU:STA SDA tHD:STA tSU:STO
START BIT
STOP BIT
Fig.-4 SYNCHRONOUS DATA TIMING SDA data is latched into the chip at the rising edge of SCL clock. Output date toggles at the falling edge of SCL clock. WRITE CYCLE TIMING
SCL
SDA
D0 WRITE DATA(n)
ACK
tWR
STOP CONDITION START CONDITION
Fig.-5 WRITE CYCLE TIMING
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WP TIMING
SCL DATA(1) SDA D1 D0 ACK DATA(n) ACK
WP
STOP BIT
tSUWP
Fig-6(a) WP TIMING OF THE WRITE OPERATION
WP
SCL DATA(1) SDA D1 D0 ACK DATA(n) ACK
tHIGH:WP
WP
Fig-6(b) WP TIMING OF THE WRITE CANCEL OPERATION
For the WRITE operation, WP must be "LOW" during the period of time from the rising edge of the clock which takes in D0 of first byte until the end of tWR. ( See Fig-6(a) ) During this period, WRITE operation is canceled by setting WP "HIGH". See Fig-6(b) In the case of setting WP "HIGH" during tWR, WRITE operation is stopped in the middle and the data of accessing address is not guaranteed. Please write correct data again in the case.
DEVICE OPERATION
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START CONDITION (RECOGNITION OF START BIT) All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Fig-4 SYNCHRONOUS DATA TIMING STOP CONDITION (RECOGNITION OF STOP BIT) All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. See Fig-4 SYNCHRONOUS DATA TIMING NOTICE ABOUT WRITE COMMAND In the case that stop condition is not excuted in WRITE mode, transfered data will not be written in a memory. DEVICE ADDRESSING Following a START condition, the master output the slave address to be accessed. The most significant four bits of the slave address are the "device type indentifier," For this device it is fixed as "1010." The next bit (device address) identify the specified device on the bus. The device address is defined by the state of A2 input pin. This IC works only when the device address inputted from SDA pin correspond to the state of A2 input pin. Using this address scheme, up to two devices may be connected to the bus. The last bit of the stream (R/W ... READ/WRITE) determines the operation to be performed. When set to "1", a read operation is selected ; when set to "0", a write operation is selected.
R/W set to "0" WRITE (including word address input of Random Read) R/W set to "1" READ A
WRITE PROTECT (WP) When WP pin set to VCC(H level), write protect is set for 256 words (all address). When WP pin set to GND(L level), enable to write 256 words (all address). Either contorol this pin or connect to GND ( or Vcc). It is inhibited from being left unconnected.
ACKNOWLEDGE
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Acknowledge is a software convention used to indicate successful data transfers. The transmitter device will release the bus after transmitting eight bits. (When inputting the slave address in the write or read operation, transmitter is -COM. When outputting the data in the read operation, it is this device.) During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that the eight bits of data has been received. (When inputting the slave address in the write or read operation, receiver is this device. When outputting the data in the read operation, it is -COM.) The device will respond with an Acknowledge after recognition of a START condition and its slave address (8bit). In the WRITE mode, the device will respond with an Acknowledge, after the receipt o feach subsequent 8-bit word (word address and write data). In the READ mode, the device will transmit eight bit of data, release the SDA line, and monitor the line for an Acknowledge. If an Acknowledge is detected, and no STOP condition is generated by the master, the device will continue to transmit the data. If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition before returning to the standby mode. (See Fig-7 ACKNOWLEDGE RESPONSE FROM RECEIVER)
START CONDITION (START BIT)
SCL
From-COM
1
8
9
SDA
-COM OUTPUT DATA)
SDA
IC OUTPUT DATA
Acknowledge Signal (ACK Signal)
Fig.-7 ACKNOWLEDGE RESPONSE FROM RECEIVER
BYTE WRITE
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S T A R T SDA LINE
SLAVE ADDRESS
W R I T E WA 7 R / W A C K
WORD ADDRESS WA 0 A C K
DATA
S T O P
1 0 1 0 A2 0
0
D7
D0 A C K
WP
Fig.-8 BYTE WRITE CYCLE TIMING By using this command, the data is programed into the indicated word address. When the master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory array. PAGE WRITE
S T A R T SDA LINE W R I T E WA 7 RA /C WK WP
SLAVE ADDRESS
WORD ADDRESS
DATA(n)
DATA(n+7)
S T O P
1 0 1 0 A2 0 0
WA 0 A C K
D7
D0 A C K
D0 A C K
Fig.-9 PAGE WRITE CYCLE TIMING This device is capable of eight byte Page Write operation. When two or more byte data are inputted, the three low order address bits are internally incremented by one after the receipt of each word. The five higher order bits of the address(WA7WA3) remain constant. If the master transmits more than eight words, prior to generating the STOP condition, the address counter will "roll over," and the previous transmitted data will be overwritten.
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CURRENT READ
S T A R T SDA LINE
SLAVE ADRESS
R E A D
DATA
S T O P
1 0 1 0 A2 0 0 R / W A C K
D7
D0 A C K
Fig.-10 CURRENT READ CYCLE TIMING In case that the previous operation is Random or Current Read (which includes Sequential Read respectively), the internal address counter is increased by one from the last accessed address (n). Thus Current Read outputs the data of the next word address (n+1). If the last command is Byte or Page Write, the internal address counter stays at the last address (n). Thus Current Read outputs the data of the word address (n). If an Acknowledge is detected, and no STOP condition is generated by the master (-COM), the device will continue to transmit the data. It can transmit all data (2kbit 256word) If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition befere returning to the standby mode. NOTE) If an Acknowledge is detected with "Low" level, not "High" level, command will become Sequential Read. So the device transmits the next data, Read is not terminated. In the case of terminating Read, input Acknowledge with "High" always, then input stop condition. RANDOM READ
S T A R T SDA LINE W R I T E WA 7 RA /C WK S T A R T WA 0 A C K
SLAVE ADDRESS
WORD ADDRESS
SLAVE ADDRESS
R E A D
DATA(n)
S T O P
1 0 1 0 A2 0 0
1 0 1 0 A2 0 0 RA /C WK
D7
D0 A C K
Fig.-11 RANDOM READ CYCLE TIMING Random Read operation allows the master to access any memory location indicated word address. If an Acknowledge is detected, and no STOP condition is generated by the master (-COM), the device will continue to transmit the data. It can transmit all data (2kbit 256word) If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition befere returning to the standby mode. NOTE) If an Acknowledge is detected with "Low" level, not "High" level, command will become Sequential Read. So the device transmits the next data, Read is not terminated. In the case of terminating Read, input Acknowledge with "High" always, then input stop condition. SEQENTIAL READ
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S T A R T SDA LINE
SLAVE ADDRESS
R E A D
DATA(n)
DATA(n+x)
S T O P D0 A C K
1 0 1 0 A2 0 0 RA /C WK
D7
D0 A C K A C K
D7
Fig.-12 SEQUENTIAL READ CYCLE TIMING Current Read If an Acknowledge is detected, and no STOP condition is generated by the master (-COM), the device will continue to transmit the data. It can transmit all data (2kbit 256word) If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition befere returning to the standby mode. The Sequential Read operation can be performed with both Current Read and Random Read. NOTE) If an Acknowledge is detected with "Low" level, not "High" level, command will become Sequential Read. So the device transmits the next data, Read is not terminated. In the case of terminating Read, input Acknowledge with "High" always, then input stop condition.
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Notice
Notes
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