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VISHAY
TFDU6108
Vishay Semiconductors
Fast Infrared Transceiver Module (4 Mbit/s), IrDA(R) Serial Interface Compatible, 2.7 V to 5.5 V Supply Voltage Range
Description
The TFDU6108 is an infrared transceiver module compliant to the latest IrDA standard for fast infrared data communication, supporting IrDA speeds up to 4.0 Mbit/s (FIR), and carrier based remote control modes up to 2 MHz. Integrated within the transceiver module are a PIN photodiode, an infrared emitter (IRED), and a low-power CMOS control IC to provide a total front-end solution in a single package. These FIR transceivers with an integrated serial interface are compliant with the IrDA "Serial Interface Standard for Transceiver Control". The transceivers are capable of directly interfacing with a wide variety of I/O devices, which perform the modulation/ demodulation function. At a minimum, a VCC bypass capacitor is the only external component required implementing a complete solution. For limiting the transceiver internal power dissipation one additional resistor might be added. The transceiver can be operated with logic I/O voltages as low as 1.5 V.
18102
New Features
* The functionality of the device is similar to the TFDU6102 series. The IrDA compatible serial interface function is replacing the former programming method, guaranteeing a perfect IrDA standardized and compliant programmability. The IRED current is programmable to different levels, no external current limiting resistor is necessary.
Features
* Compliant to the latest IrDA physical layer specification (Up to 4 Mbit/s) TV Remote Control * Compliant to the IrDA "Serial Interface Specification for Transceivers" * For 3.0 V and 5.0 V Applications, fully specified 2.7 V to 5.5 V Operational down to 2.6 V * Compliant to all logic levels between 1.5 V and 5 V * Low Power Consumption (typ. 2.0 mA Supply Current) * Power Shutdown Mode (< 1 A Shutdown Current) * Surface Mount Package Options - Universal (L 9.7 mm x W 4.7 mm x H 4.0 mm) - Side and Top View
Document Number 82537 Rev. 1.6, 25-Jun-04
* Tri-State-Receiver Output, Weak Pull-up when in Shutdown Mode * High Efficiency Emitter * Baby Face (Universal) Package Capable of Surface Mount Soldering to Side and Top View Orientation * Eye safety class 1 (IEC60825-1, ed. 2001), limited LED on-time, LED current is controlled, no single fault to be considered * Built - In EMI Protection including GSM bands. EMI Immunity in GSM Bands > 300 V/m verified No External Shielding Necessary * Few External Components Required * Pin to Pin Compatible to Legacy Vishay Semiconductor SIR and FIR Infrared Transceivers * Split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs, US Patent No. 6,157,476 * Compliant with IrDA EMI and Background Light Specification
Applications
* Notebook Computers, Desktop PCs, Palmtop Computers (Win CE, Palm PC), PDAs * Printers, Fax Machines, Photocopiers, Screen Projectors * Telecommunication Products (Cellular Phones, Pagers) * Internet TV Boxes, Video Conferencing Systems * External Infrared Adapters (Dongles) * Medical and Industrial Data Collection Devices
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TFDU6108
Vishay Semiconductors Parts Table
Part TFDU6108-TR3 TFDU6108-TT3 Description Oriented in carrier tape for side view surface mounting Oriented in carrier tape for top view surface mounting 1000 pcs 1000 pcs
VISHAY
Qty / Reel
Functional Block Diagram
VCC1
Vlogic Driver
Amplifier
Comparator 200
Rxd IRED Anode VCC2
SCLK Txd
AGC Logic
Current controlled driver IRED Cathode
17086
GND
Pin Description
Pin Number 1 Function IRED Anode Description Connect IRED anode directly to VCC2. An unregulated separate power supply can be used at this pin. For VCC2 > 4 V use a serial resistor R1 to reduce the. See derating curve. IRED cathode, internally connected to driver transistor Transmit Data Input, dynamically loaded for noise suppression. Received Data Output, push-pull CMOS driver output capable of driving a standard CMOS or TTL load. No external pull-up or pull-down resistor is required. When disabled it is connected to Vlogic. by a weak pull-up (500 k). Pin is current limited for protection against bus collisions due to programming errors. Serial Clock, dynamically loaded for noise suppression. Supply Voltage Supply voltage for digital part, 1.5 V to 5.5 V, defines logic swing for Txd, SCLK, and Rxd Ground I O HIGH LOW I/O Active
2 3 4
IRED Cathode Txd Rxd
5 6 7 8
SCLK VCC Vlogic GND
I
HIGH
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Document Number 82537 Rev. 1.6, 25-Jun-04
VISHAY
Pinout
TFDU6108 weight 200 mg
TFDU6108
Vishay Semiconductors
"U" Option BabyFace (Universal)
IRED Detector
Definitions:
In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0 MIR 576 kbit/s to 1152 kbit/s FIR 4 Mbit/s
1
17087
2 34 56
78
VFIR 16 Mbit/s MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4. A new version of the standard in any obsoletes the former version.
Absolute Maximum Ratings
Reference point Ground (pin 8) unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Supply voltage range, transceiver Supply voltage range, transmitter Supply voltage range, transceiver logic Input currents Output sinking current Junction temperature Power dissipation Ambient temperature range (operating) Storage temperature range Soldering temperature Average output current Repetitive pulse output current IRED anode voltage Transmitter data input voltage Receiver data output voltage Virtual source size Method: (1 - 1/e) encircled energy < 90 s, ton < 20 % see recommended solder profile (see figure 3) IIRED (DC) IIRED (RP) VIREDA VTxd VRxd d - 0.5 - 0.5 - 0.5 2.5 2.8 Internally limited to class 1 500 see derating curve, figure 4 TJ PD Tamb Tstg - 25 - 40 Test Conditions 0 V < VCC2 < 6 V 0 V < VCC1 < 6 V 0 V < VCC1 < 6 V for all pins, except IRED anode pin Symbol VCC1 VCC2 Vlogic Min - 0.5 - 0.5 - 0.5 Typ. Max +6 +6 +6 10 25 125 350 + 85 + 100 240 130 600 +6 Vlogic + 0.5 Vlogic + 0.5 Unit V V V mA mA C mW C C C mA mA V V V mm mW/sr
Maximum Intensity for Class 1 unidirectional operation, worst Operation of IEC825-1 or case IrDA FIR pulse pattern EN60825-1, edition Jan. 2001*) IrDA specified maximum limit
*) Due to the internal measures the device is a "class1" device. It will not exceed the IrDA intensity limit of 500 mW/sr.
Document Number 82537 Rev. 1.6, 25-Jun-04
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TFDU6108
Vishay Semiconductors
VISHAY
Electrical Characteristics Transceiver
Tamb = 25 C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Supply voltage
1)
Test Conditions
Symbol VCC1 Vlogic
Min 2.7 1.5
Typ.
Max 5.5 5.5
Unit V V mA mA A A
Dynamic supply current
T = - 25 C to 85 C active, no signal Ee = 0 klx T = 25 C T = - 25 C to 85 C idle active, no load Ee = 0 klx T = - 25 C to 85 C Ee = 1 klx2) receive mode, EEo = 100 mW/m2 (9.6 kbit/s to 4.0 Mbit/s), RL = 10 k to Vlogic = 5 V, CL = 15 pF
ICC1
2.0
2.35 2.3
Ilogic Ilogic 160
5 1
Shutdown supply current
inactive, set to shutdown mode T = 25 C, Ee = 0 klx inactive, set to shutdown mode T = 25 C, Ee = 1 klx 2) shutdown mode, T = 85 C, not ambient light sensitive
ISD ISD ISD TA - 25 0.5 Vlogic - 0.5
1 1.5 5 + 85 0.8 0.15 2) Vlogic 0.9 2) Vlogic - 10 + 10 5
A A A C V V V V A pF
Operating temperature range Output voltage low Output voltage high Input voltage low (Txd, SCLK) Input voltage high (Txd, SCLK) Input leakage current (Txd, SCLK) Input capacitance
1) 2) 3)
Cload = 15 pF, Vlogic = 5 V Cload = 15 pF, Vlogic = 5 V CMOS level 3) CMOS level 3)
VOL VOH VIL VIH IL CIN
Receive mode only. In transmit mode, add the averaged programmed current of IRED current as ICC2 Standard Illuminant A
The typical threshold level is between 0.5 x Vlogic/2 (Vlogic = 3 V) and 0.4 x Vlogic (Vlogic = 5.5 V). With that the device will work with less tight levels than the specified min/ max values. However, it is recommended to use the specified min/max values to avoid increased operating/standby supply currents.
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Document Number 82537 Rev. 1.6, 25-Jun-04
VISHAY
TFDU6108
Vishay Semiconductors
V
V (TX1)
7 6 5 4 3 2 1 0 -1
A IVDIODE 0.06
0.05 0.04 0.03 0.02 0.01 0.00 - 0.01
A
IVIC 10-5
1.0 0.5 0.0 - 0.5 - 1.0 - 1.5
A
IDDAD 10-4
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 - 0.5
17088
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8 2.0 ms
Input Load
The waveform "IDDadd" shows the additional operating current of one input buffer (in this case Txd) vs. the logic input voltage V (TXI) for the digital supply
voltage Vdd = 3 V under typical working conditions. The current "IVIC" is the typical input current vs. the input voltage.
Optoelectronic Characteristics Receiver
Tamb = 25 C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Minimum detection threshold irradiance, SIR mode Minimum detection threshold irradiance, MIR mode Minimum detection threshold irradiance, FIR mode Maximum detection threshold irradiance Test Conditions 9.6 kbit/s to 115.2 kbit/s = 850 nm to 900 nm 1.152 Mbit/s = 850 nm to 900 nm 4.0 Mbit/s = 850 nm to 900 nm = 850 nm to 900 nm Symbol Ee Ee Ee Ee 5 Min Typ. 25 65 85 10 90 Max 40 Unit mW/m2 mW/m2 mW/m2 kW/m2
Document Number 82537 Rev. 1.6, 25-Jun-04
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TFDU6108
Vishay Semiconductors
Parameter Logic LOW receiver input irradiance Test Conditions optical ambient noise suppression up to this level for e.g. fluorescent light tolerance equivalent to the IrDA(R) "Background Light and Electromagnetic Field" specification Rise time of output signal Fall time of output signal 10 % to 90 %, @ 2.2 k, 15 pF 90 % to 10 %, @ 2.2 k, 15 pF tr (Rxd) tf (Rxd) tPW tPW tPW 1.3 1.2 110 2 40 40 3 3 260 20 tPW 100 160 20 tL 120 Symbol Ee Min 4 Typ. Max
VISHAY
Unit mW/m2
ns ns s s ns ns ns ns s
Rxd pulse width of output signal, input pulse length 20 s, 50 % SIR mode 9.6 kbit/s input pulse length 1.41 s, 115.2 Mbit/s Rxd pulse width of output signal, input pulse length 217 ns, 50 % MIR mode 1.152 Mbit/s Jitter, leading edge, MIR mode input irradiance = 100 mW/m2, 1.152 Mbit/s
Rxd pulse width of output signal, input pulse length 125 ns, 50 % FIR mode 4.0 Mbit/s Jitter, leading edge, FIR mode Latency input irradiance = 100 mW/m2, 4 Mbit/s
Transmitter
Tamb = 25 C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter IRED operating current internally controlled, programmable using the "serial interface" programming sequence, see Appendix Test Conditions VCC1 = 3.3 V, the maximum current is limited internally. An external resistor can be used to reduce the power dissipation at higher operating voltages, see derating curve. VCC1 = 3.3 V, = 0 , 15 , Txd = High, R1 = 0 programmed to max. power level VCC1 = 3.3 V, = 0 , 15 , Txd = Low, R1 = 0 programmed to shutdown mode Symbol ID Min Typ. 8 15 30 60 110 220 500 0.3 Max Unit mA
600 mW/sr/mA
Max. output radiant intensity
Ie
Output radiant intensity
Ie
0.04
mW/sr
Output radiant intensity, angle of half intensity Peak - emission wavelength Spectral bandwidth Optical rise time, fall time Optical overshoot
p tropt, tfopt 10 880
24 900 40 40 10
nm nm ns %
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Document Number 82537 Rev. 1.6, 25-Jun-04
VISHAY
Recommended Circuit Diagram
Operated with a low impedance power supply the TFDU6108 needs no external components. However, depending on the entire system design and board layout, additional components may be required (see figure 1).
VCC2 R1 VCC1 R2 Rxd IRED Cathode Rxd IRED Anode Txd
TFDU6108
Vishay Semiconductors Recommended Application Circuit Components
Component C1 C2 R1 R2 Recommended Value 4.7 F, 16 V 0.1 F, Ceramic, 16V Recommended for VCC1 4 V Depending on current limit 47 , 0.125 W
I/O and Software
For operating the device from a Controller I/O a driver software must be implemented.
C1 GND Vlogic SCLK Txd
C2
Vcc GND
SCLK Vlogic
Mode Switching
The generic IrDA "Serial Interface programming" needs no special settings for the device. Only the current control table must be taken into account. For the description see the Appendix and the IrDA "Serial Interface specification for transceivers"
17089
Figure 1. Recommended Application Circuit All external components (R, C) are optional
Vishay Semiconductor transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (Txd, SCLK) and the output Rxd should be directly (DC) coupled to the I/O circuit. R1 is used for controlling the maximum current through the IR emitter. This one is necessary when operating over the full range of operating temperature and VCC1 - voltages above 4 V. For increasing the max. output power of the IRED, the value of the resistor should be reduced. It should be dimensioned to keep the IRED anode voltage below 4 V for using the full temperature range. For device and eye protection the pulse duration and current are internally limited. R2, C1 and C2 are optional and dependent on the quality of the supply voltage VCC1 and injected noise. An unstable power supply with dropping voltage during transmission may reduce sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 close to the transceiver power supply pins. An electrolytic capacitor should be used for C1 while a ceramic capacitor is used for C2.
Document Number 82537 Rev. 1.6, 25-Jun-04
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TFDU6108
Vishay Semiconductors Recommended Solder Profile
Solder Profile for Sn/Pb soldering
VISHAY
Lead-Free, Recommended Solder Profile
The TFDU6108 is a lead-free transceiver and qualified for lead-free processing. For lead-free solder paste like Sn(3.0 - 4.0)Ag(0.5 - 0.9)Cu, there are two standard reflow profiles: Ramp-Soak-Spike (RSS) and Ramp-To-Spike (RTS). The Ramp-Soak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. Shown below in figure 3 is Vishay's recommended profile for use with the TFDU6108 transceivers. For more details please refer to Application note: SMD Assembly Instruction.
240 220 200
Temperature (C)
10 s max. @ 230C 2C - 4C/s
180 160 140 120 100 80 60 40 20 0 0 50 100
120 s - 180 s 2C - 4C/s
90 s max
14874
150
200
250
300
350
Time ( s )
Figure 2. Recommended Solder Profile
280 260 240
Temperature/ C
T = 250C for 20 s max T = 217C for 50 s max
Tpeak = 260C max.
220 200 180 160 140 120 100 80 60 40 20 0 0 50 2C...4C/s
20 s max.
90 s...120 s
50 s max. 2C...4C/s
100
150 Time/s
200
250
300
350
19048
Figure 3. Solder Profile, RSS Recommendation
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Document Number 82537 Rev. 1.6, 25-Jun-04
VISHAY
Current Derating Diagram
TFDU6108
Vishay Semiconductors
600
Peak Operating Current ( mA )
500 400 300 200 100 0 -40 -20 0
Current derating as a function of the maximum forward current of IRED. Maximum duty cycle: 25%.
14875
20 40 60 80 100 120 140 Temperature ( C )
Figure 4. Current Derating Diagram
Document Number 82537 Rev. 1.6, 25-Jun-04
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TFDU6108
Vishay Semiconductors Package Dimensions in mm
VISHAY
18473
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Document Number 82537 Rev. 1.6, 25-Jun-04
VISHAY
Appendix A Serial Interface Implementation Basics of the IrDA Definitions
The data lines are multiplexed with the transmitter and receiver signals and separate clocks are used since the transceivers respond to the same address.
TFDU6108
Vishay Semiconductors
When no infrared communication is in progress and the serial bus is idle, the IRTX line is kept low and IRRX is kept high.
17092
Figure 5. Interface to Two Infrared Transceivers
17093
Figure 6. Infrared Dongle with Differential Signaling
Document Number 82537 Rev. 1.6, 25-Jun-04
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TFDU6108
Vishay Semiconductors Functional description
The serial interface is designed to interconnect two or more devices. One of the devices is always in control of the serial interface and is responsible for starting every transaction. This device functions as the bus master and is always the infrared controller. The infrared transceivers act as bus slaves and only respond to transactions initiated by the master. A bus transaction is made up of one or two phases. The first phase is the Command Phase and is present in every transaction. The second phase is the Response Phase and is present only in those transactions in which data must be returned from the slave. If the operation involves a data transfer from the slave, there will be a Response Phase following the Command Phase in which the slave will output the data. The Response Phase, if present, must begin 4 clock cycles after the last bit of the Command Phase, as shown in figures 1 - 7 and 1 - 8, otherwise it is assumed that there will be no response phase and the master can terminate the transaction. The SCLK line is always driven by the master and is used to clock the data being written to or read from the slave. This line is driven by a totem-pole output buffer. The SCLK line is always stopped when the serial interface is idle to minimize power consumption and to avoid any interference with the analog circuitry inside the slave. There are no gaps between the bytes in either the Command or Response Phase. Data is always transferred in Little Endian order (least significant bit first). Input data is sampled on the rising edge of SCLK. IRTX/SWDAT output data from the controller is clocked by SCLK falling edge. IRRX/SRDAT output data from the slave is clocked by SCLK rising edge. Each byte of data in both Command and Response Phases is preceded by one start bit. The data to be written to the slave is carried on the IRTX/SWDAT line. When the control interface is idle, this line carries the infrared data signal used to drive the transmitter LED. When the first low-to-high transition on SCLK is detected at the beginning of the command sequence, the slave will disable the transmitter LED. The infrared controller then outputs the command string on the IRTX/SWDAT line. On the last SCLK cycle of the command sequence the slave re-enables the transmitter LED and normal infrared transmission can resume. No transition on SCLK must occur until the next command sequence otherwise the slave will disable the transmitter LED again. Read data is carried on the IRRX/SRDAT line. The slave disables the internal signal from the receiver photo diode during
VISHAY
the response phase of a read transaction. The addressed slave will output the read data on the IRRX/SRDAT line regardless of the setting of the Receiver Output Enable bit in the Mode Selection register 0. Non addressed slaves will tri-state the IRRX/ SRDAT line. When the transceiver is powered up, the IRTX/SWDAT line should be kept low and SCLK should be cycled at least 30 times by the infrared controller before the first command is issued on the IRTX/ SWDAT line. This guarantees that the transceiver interface circuitry will properly initialize and be ready to receive commands from the controller. In case of a multiple transceiver configuration, only one transceiver should have the receiver output enabled. A series resistor (approx. 200 ohms) should be placed on the receiver output from each transceiver to prevent large currents in case a conflict occurs due to a programming error.
SCLK IRTX/ SWDAT IRRX/ SRDAT TLED_DIS
(INTERNAL SIGNAL)
17175
Figure 7. Initial Reset Timing
SCLK IRTX/ SWDAT IRRX/ SRDAT
(Note 1)
TLED_DIS
(INTERNAL SIGNAL)
RES
(INTERNAL SIGNAL)
17176
Figure 8. Special Command Waveform
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Document Number 82537 Rev. 1.6, 25-Jun-04
VISHAY
TFDU6108
Vishay Semiconductors
17177
17179
Figure 9. Write Data Waveform Note 1: If the APEN bit in control register 0 is set to 1, the internal
Figure 11. Read Data Waveform
signal from the receiver photo diode is discon nected and the IRRX/ SRDAT line is pulsed low for one clock cycle at the end of a write or special command.
17180
Figure 12. Read Data Waveform with Extended Index Note 2: During a read transaction the infrared controller sets the
17178
IRTX/SWDAT line high after sending the address and index byte (or bytes). It will then set it low two clock cycles before the end of the transaction. It is strongly recommended that optical transceivers monitor this line instead of counting clock cycles in order to detect the end of the read trans action. This will always guarantee correct operation in case two or more transceivers from different manufacturers are sharing the serial interface.
Figure 10. Write Data Waveform with Extended Index
Document Number 82537 Rev. 1.6, 25-Jun-04
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TFDU6108
Vishay Semiconductors Switching Characteristics
Maximum capacitive load = 20 pF1) Parameters SCLK Clock Period SCLK Clock High Time SCLK Clock Low Time Output Data Valid (from infrared controller) Output Data Hold (from infrared controller) Output Data Valid (from optical transceiver) Output Data Hold (from optical transceiver) Line Float Delay Input Data Setup Input Data Hold
1)
VISHAY
Test Conditions R.E., SCLK to next R.E., SCLK At 2.0 V for single-ended signals At 0.8 V for single-ended signals After F.E., SCLK After F.E., SCLK After R.E., SCLK After R.E., SCLK After R.E., SCLK Before R.E., SCLK After R.E., SCLK
Symbol tCKp tCKh tCKl tDOtv tDOth tDOrv tDOrh tDOrf tDIs tDIh
Min. 250 60 80
Max. infinity
Unit ns ns ns
40 0 40 40 60 10 5
ns ns ns ns ns ns ns
Capacitive load is different from "Serial interface - specification". For the bus protocol see "RECOMMENDED SERIAL INTERFACE FOR TRANSCEIVER CONTROL, Draft Version 1.0a, March 29, 2000, IrDA". In Appendix B the transceiver related data are given.
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Document Number 82537 Rev. 1.6, 25-Jun-04
VISHAY
Appendix B Application Guideline
In the following some guideline is given for handling the TFDU6108 in an application ambient, especially for testing. It is also a guideline for interfacing with a controller. We recommend to use for first evaluation the Vishay IRM1802 controller. For more information see the special data sheet. Driver software is available on request. Contact irdc@vishay.com.
TFDU6108
Vishay Semiconductors IrDA Serial Interface Basics
The serial interface for transceiver control (SITC) is a master/slave synchronous serial bus which uses the Txd and Rxd as data lines and the SCLK as clock line with a minimum period of 250 ns. The transceiver works always as slave and jump into SITC mode on the first rising edge of the clock line remaining there until the command phase is finished. After power on it is required an initial phase for 30 clock cycles at Txd is continuous low before the transmitter can be programmed. If Txd assume high during the initial phase then must start the initial phase again. The data transfer is organized by one byte preceded by one start bit. The SITC allows the communication between infrared controller and transceiver through write and read transaction. The SITC consists of two store blocks with different functions. The store block called Extended Indexed Registers contain the various supported functionality of the device and can be read only. The other Main Control Registers allow write and read transaction and store the executable configuration of the device. Any configuration is executed after the command phase is completed.
Serial Interface Capability of the Vishay IrDA Transceivers Abstract
A serial interface allows an infrared controller to communicate with one or more infrared transceivers. The basic specification of IrDA(R) specified interface is described in "Serial Interface for Transceiver Control, v 1.0a", IrDA. This part of the document describes the capabilities of the serial interface implemented in the Vishay IrDA transceivers TFDU8108 and TFDU6108. The VFIR (16 Mbit/s) and FIR (4 Mbit/s) programmable versions are using the same interface specification (with specific identification and programming).
Power - up defaults
After power on the transceiver has to stay by definition in the following default mode shown in the table. The default mode of the TFDU6108 is different from the originally defined IrDA Serial Interface default mode. The implemented deviation from the standard was a market request because only in this way a requested quick function test is possible with the TFDU6108 without the need to connect to a programming device. Function Power Mode RX TX_LED APEN Infrared Mode Transmitter Power TFDU6108 active (!) active active enabled SIR defined SIR level
Addressing
The transceiver is addressable with three address bits. There are individual and common addresses with the following values. Description Individual address Common (broadcast) address Mask programmable Address value A [2:0] 001 111
Document Number 82537 Rev. 1.6, 25-Jun-04
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TFDU6108
Vishay Semiconductors Data Acknowledgement
Data acknowledgement generated by the slave is available if the APEN bit is set to 1 in the common control register. In IrDA default state this functionality is disabled. In default state of the TFDU6108 it is enabled (see above). It is strongly recommended that this functionality is enabled to be on the safe side for correct data transmission during SITC mode.
VISHAY
Registers Data Depth
In general the whole data registers consist of a data depth of eight bits. But sometimes it is unnecessary to implement the full depth. In such a case the invisible bits consider like a zero.
Used Index Commands
The table shows the valid index commands, its allowable modes, and the data depth to them. Commands INDEX [3:0] 0h 1h 2h Bh - 3h Ch Dh Mode W/R W/R W/R X X W R Eh Fh X W R Action Common control Infrared mode Txd power level Not used Not used Reset transceiver, Only one byte! Not used Not used Not used Extended indexing Register Name main-ctrl-0 register main-ctrl-1 register main-ctrl-2 register Data Bits [4.2:0] [3:0] [7:4] Default Value TFDU6108 14h 00h 70h
Main-ctrl-0 register values
Value bit 0 Function PM SL - Power Mode Select 0 low power mode (sleep mode) 1 normal operation power mode RX OEN - Receiver Output Enable 0 IRRX/SRDAT line disable (tri-stated) 1 IRRX/SRDAT line enabled TLED EN - Transmitter LED Enable 0 disabled 1 enabled not used APEN
1)
Default active (!)
bit 1
active
bit 2
active
bit 3 bit 4
1)
not used enabled
APEN - Acknowledge Pulse Enable, (optional) This bit is used to enable the acknowledge pulse. When it is set to 1 and RX OEN is 1 (receiver output enabled) the IRRX/SRDAT line will be pulsed low for one clock cycle upon successful completion of every write command or special command with individual (non broadcast) transceiver address. The internal signal from the receiver photo diode is disconnected when this bit is set to 1.
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Document Number 82537 Rev. 1.6, 25-Jun-04
VISHAY
Main-ctrl-1 register values
Value bit 0 bit 1 bit 2 bit 3
(R)
TFDU6108
Vishay Semiconductors
Function SIR (default) MIR FIR Sharp IR Apple Talk(R) (SIR functionality)
If any other value is tried to be written by the controller into the SIF, the transceiver will load 00h into the main_crtl_1 register and will not give an acknowledgement
Main-ctrl-2 register values
bit 7 8xhFxh 7xh1) 6xh 5xh 4xh 3xh 2xh 1xh 0xh
1)
bit 6 x
bit 5 x
bit 4 x
bit 3 x
bit 2 x
bit 1 x
bit 0 x
Mode FIR > 1 m, not for SIR! SIR >1 m FIR > 0.7 m SIR > 0.70 m FIR > 0.45 m SIR > 0.50 m FIR > 0.30 m SIR > 0.35 m FIR > 0.20 m SIR > 0.25 m FIR > 0.15 m SIR > 0.15 m FIR > 0.10 m
Txd-IRED (mA) 550 (switch, ext. R1!) 250 125 60 (45) 30 15 8 0
Remark FIR standard, serial resistor is necessary for VCC2 > 4 V SIR More Ext. FIR LP Extended FIR Low Power FIR Low Power
1
0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0
1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0
x
x
x
x
SIR Low Power e.g. Docking station e.g. Docking station
x
x
x
x
default setting
Used Extended Indexed Registers
The table shows the valid extended indexed commands its allowable modes and the data depth to them. Register Address E_INDEX [7:0] 00h 01h 04h 05h 06h 07h 08h Mode R R R R R R R Action Manufactured ID Device ID Receiver recovery time Power on stabilization Receiver stabilization SCKL max. frequency Common capabilities Supported Infrared modes Supported Infrared modes Data Bits [7:0] [7:0] [6:4, 2:0] [6:4, 2:0] [7:0] [7:0] 0 Fixed Value 0:4h [7:6] 11 24h 30h 03h 0Fh 01h
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Vishay Semiconductors
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TFDU6108
Vishay Semiconductors
Invalid Commands Handling
There are some commands and register addresses, which cannot be decoded by the SITC. The slave ignores such invalid data for the internal logic. Below the different types and the slave reaction to them are shown. Description Invalid command in read mode Invalid command in write mode Valid command in invalid read mode Valid command in invalid write mode Valid command in invalid write mode and invalid data Broadcast (common) address in read mode Master Command Index [3:0] & C = 0 Index [3:0] & C = 1 Index [3:0] & C = 0 Index [3:0] & C = 1 Index [3:0] & C = 1 A [2:0] = 111 & C = 0 Slave Reaction on IRRX/SRDAT no reaction No acknowledgement generating independent of the value of APEN no reaction No acknowledgement generating independent of the value of APEN No acknowledgement generating independent of the value of APEN no reaction
No reaction means that the slave does not start the respond phase.
Reset
There is no external reset pin at Vishay IrDA transceivers. In case of transition error there are two ways to set the SITC in a defined state: The first one is power off. The second one is that the transceiver monitors the IRTX/SWDAT line in any state. If this line is assumed low for 30 clock cycles then the transceiver must be set to the command start state and set all registers to default implemented values.
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TFDU6108
Vishay Semiconductors Appendix C Serial Interface (SIF) Programming Guide
The SIF port of this module allow an IR controller to communicate with it, get module ID and capability information, implement receiver bandwidth mode switching, LED power control, shutdown and some other functions. This interface requires three signals: a clock line (SCLK) that is used for timing, and two unidirectional lines multiplexed with the transmitter (Txd, write) and receiver (Rxd, read) infrared signal lines. The supported programming sequence formats are listed below: one-byte special commands two-byte write commands two-byte read commands three-byte read commands The one-byte special command sequences are reserved for time-critical actions, while the two-byte write command is predominantly used to set basic transceiver characteristics. More information can be found in the IrDA document "Serial Interface for Transceiver Control, v 1.0a" on IrDA.org web site.
SCLK
VISHAY
TX
125 ns < Tclk 18496 s
Tsetup > 10 ns Thold > 10 ns
Protocol Specifications
The serial interface protocol is a command-based communication standard and allows for the communication between controller and transceiver by way of serial programming sequences on the clock (SCLK), transmit (TX), and receive (RX) lines. The SCLK line is used as a clocking signal and the transmit/receive lines are used to write/read data information. The protocol requires all transceivers to implement the write commands, but does not require the read-portion of the protocol to be implemented (though all transceivers must at least follow the various commands, even if they perform no internal action as a result). This serial interface follows but does not support all read/ write commands or extended commands, supporting only the special commands and basic write/read commands. Write commands to the transceiver take place on the SCLK and TX lines and may make use of the RX line for answer back purposes. A command may be directed to a single transceiver on the SCLK, TX and RX bus by specifying a unique three-bit transceiver address, or a command may be directed to all transceivers on the bus by way of a special three-bit broadcast address code. The Vishay VFIR transceiver TFDU8108 will respond to transceiver address 010 and the broadcast address 111 only, and follows but ignores all other transceiver addresses. The transceiver address of Vishay FIR module TFDU6108 is 001. All commands have a common \"header\" or series of leading bits which take the form shown below.
first bit sent to transceiver last bit sent to transceiver
Serial Interface Timing Specifications
In general, serial interface programming sequences are similar to any clocked-data protocol: * there is a range of acceptable clock rates, measured from rising edge to rising edge * there is a minimum data setup time before clock rising edges * there is a minimum data hold time after clock rising edges Recommended programming timing: (4 kHz <) fclk < 8 MHz (4 kHz is a recommended value, according to the Serial Interface Standard quasi-static programming is possible) TCLK > 125 ns (< 250 s, see the remark for quasistatic programming above) Tsetup > 10 ns Thold > 10 ns The timing diagrams below show the setup and hold time for Serial Interface programming sequences:
0
1 1/0 R0 R1 R2 R3 A0 A1 A2
1=Write 0=Read Register Address or Code Transceiver Address
...
Sync Bits
18497
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The bits shown are placed on the TX (DATA) line and clocked into the transceiver using the rising edge of the SCLK signal. Only the data bits are shown as it is assumed that a clock is always present, and that the transceiver samples the data on the rising edge of each clock pulse. Note: as illustrated in the diagram above, the protocol uses "Little Endian" ordering of bits, so that the LSB is sent first, and the MSB is sent last for register addresses, transceiver addresses, and read/write data bytes. The notation that follows presents all addresses and data in LSB-to-MSB order (bits 0, 1, 2, 3, ... 7) unless otherwise stated.
TFDU6108
Vishay Semiconductors
One-byte Special Commands One-byte special commands are used for time-critical transceiver commands, such as full transceiver reset. A total of six special commands are possible, although only one command is available on the TFDU8108 and TFDU6108.
0 1 1 R0 R1 R2 R3 A0 A1 A2 0 0
Sync Bits
18498
Write
Special Command Code
Transceiver Address
Stop Bits
Command RESET (Set all registers to default value)
Module Type TFDU6108 TFDU8108
Programming Sequence (Binary) 011 1011 100 00 011 1011 010 00
Programming Sequence (Hex) 3B 5B
Two-byte Write Commands Two-byte write commands are used for setting the contents of transceiver registers which control transceiver such as shutdown/enable, receiver mode, LED power level, etc. The register space requires four register address bits (R0-3), although three codes are used for controlling transceiver (see above), and the 1111 escape code is for extended commands. The 3-bit transceiver address (A0-3) is for selecting the destination, e.g. 010 to TFDU8108 and 001 to TFDU6108. The second byte is data field (D0-7) for setting the characteristics of the transceiver module, e.g. SIR mode (00) or VFIR (05) when the register address is 0001.
The basic two-byte write command is illustrated below:
0
1
1 R0 R1 R2 R3 A0 A1 A2 1 D0..D7 0
0
Sync Write Bits
18499
Register Address
Transceiver Address
8-Data Bits
Stop Bits
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TFDU6108
Vishay Semiconductors
Some important serial interface sequences are shown below: programming
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TFDU6108
Vishay Semiconductors
Command Common Ctrl (0000) Normal (Enable all) Shutdown Receiver Mode (0001) SIR MIR FIR Apple Talk VFIR Sharp-IR LED Power (0010) 8 mA 15 mA 30 mA 60 mA 125 mA 250 mA 500 mA Value (hex) 0F 00 Value (hex) 00 01 02 03 05 08 Value (hex) 1X 2X 3X 5X 6X 7X FX
TFDU6108 Programming Sequence (Transceiver address: 001) 011 0000 100 1 11110000 00 011 0000 100 1 00000000 00 011 1000 100 1 00000000 00 011 1000 100 1 10000000 00 011 1000 100 1 01000000 00 011 1000 100 1 11000000 00 011 1000 100 1 10100000 00 011 1000 100 1 00010000 00 011 0100 100 1 00001000 00 011 0100 100 1 00000100 00 011 0100 100 1 00001100 00 011 0100 100 1 00001010 00 011 0100 100 1 00000110 00 011 0100 100 1 00001110 00 011 0100 100 1 00001111 00
TFDU8108 Programming Sequence (Transceiver address: 010) 011 0000 010 1 11110000 00 011 0000 010 1 00000000 00 011 1000 010 1 00000000 00 011 1000 010 1 10000000 00 011 1000 010 1 01000000 00 011 1000 010 1 11000000 00 011 1000 010 1 10100000 00 011 1000 010 1 00010000 00 011 0100 010 1 00001000 00 011 0100 010 1 00000100 00 011 0100 010 1 00001100 00 011 0100 010 1 00001010 00 011 0100 010 1 00000110 00 011 0100 010 1 00001110 00 011 0100 010 1 00001111 00
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TFDU6108
Vishay Semiconductors Reel Dimensions
VISHAY
W1
Reel Hub
W2
14017
Tape Width mm 24
A max. mm 330
N mm 60
W1 min. mm 24.4
W2 max. mm 30.4
W3 min. mm 23.9
W3 max. mm 27.4
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Tape Dimensions in mm
TFDU6108
Vishay Semiconductors
18269
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Vishay Semiconductors
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18283
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Document Number 82537 Rev. 1.6, 25-Jun-04
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Ozone Depleting Substances Policy Statement
It is the policy of Vishay Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements.
TFDU6108
Vishay Semiconductors
2. Regularly and continuously improve the performance of our products, processes, distribution and operatingsystems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Vishay Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify Vishay Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423
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