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| DATASHEET 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE ICS1894-40 Description The ICS1894-40 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards, ISO/IEC 8802-3. The ICS1894-40 is intended for MII, Node applications that require the Auto-MDIX feature that automatically corrects crossover errors in plant wiring. The ICS1894-40 incorporates Digital-Signal Processing (DSP) control in its Physical-Medium Dependent (PMD) sub layer. As a result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation in excess of 24 dB at 100MHz. With this IDT-patented technology, the ICS1894-40 can virtually eliminate errors from killer packets. The ICS1894-40 provides a Serial-Management Interface for exchanging command and status information with a Station-Management (STA) entity. The ICS1894-40 Media-Dependent Interface (MDI) can be configured to provide either half- or full-duplex operation at data rates of 10 Mb/s or 100Mb/s. In addition, the ICS1894-40 includes a programmable interupt output function. This function consists of a digital output pin, an interrupt control register, a set of interrupt status register bits and a corresponding set of interrupt enable bits, and a pre-defined set of events which can be assigned as one of the interrupt sources. The purpose of this function is to notify the host of this PHY device when certain event happens via interrupt (the logic level on interrupt output pin going low or going high) instead of polling by the host. The events that could be used to generate interrupts are: receiver error, Jabber, page received, parallel detect fault, link partner acknowledge, link status change, auto-negotiation complete, remote fault, collision, etc Applications: NIC cards, PC motherboards, switches, routers, DSL and cable modems, game machines, printers, network connected appliances, and industrial equipment. Features * Supports category 5 cables with attenuation in excess of 24dB at 100 MHz. * Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sub layers functions of IEEE standard. * 10Base-T and 100Base-TX IEEE 8802.3 compliant * MIIM (MDC/MDIO) management bus for PHY register configuration * RMII interface support with external 50 MHz system clock * Single 3.3V power supply * Highly configurable, supports: - Media Independent Interface (MII) - Auto-Negotiation with Parallel detection - Node applications, managed or unmanaged - 10M or 100M full and half-duplex modes - Loopback mode for Diagnostic Functions Auto-MDI/MDIX crossover correction * * * * * Low-power CMOS (typically 300 mW) Power-Down mode typically 21mW Clock and crystal supported Interrupt pin option Fully integrated, DSP-based PMD includes: - Adaptive equalization and baseline-wander correction - Transmit wave shaping and stream cipher scrambler - MLT-3 encoder and NRZ/NRZI encoder * * * * Single power supply (3.3 V) Built-in 1.8 V regulator for core Available in 40-pin (5mm x 5mm) QFN package, Pb-free Available in Industrial Temp and Lead Free IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 1 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Block Diagram 100Base-T 10/100 MII/RMII MAC Interface Interface MUX PCS * Framer * CRS/COL Detection * Parallel to Serial * 4B/5B PMA * Clock Recovery * Link Monitor * Signal Detection * Error Detection TP_PMD * MLT-3 * Stream Cipher * Adaptive Equalizer * Baseline Wander Correction Integrated Switch 10Base-T MII Extended Register Set Low-Jitter Clock Synthesizer Clock Power TwistedPair Interface to Magnetics Modules and RJ45 Connector MII Management Interface Configuration and Status AutoNegotiation LEDs and PHY Address Pin Assignment P4/LED2 P1/LED1 P0/LED0 REFOUT REFIN AMDIX TP_AP TP_AN VSS VDD TP_BN TP_BP VDD TCSR VSS 1 31 VDDD TXD3 TXD2 TXD1 VSS LED3 TXD0 TXEN SPEED/TXCLK NOD/RXER ANSEL/RXCLK NLG40 Without Ground Connecting to Thermal Pad TXER SPEED RMII/RXDV FDPX/RXD0 11 21 SI/LED4 HWSW/CRS MDC REGPIN/COL AMDIXRXD3 40-pin MLF 40-pin 6mm x 6mm QFN IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 2 RXTR1RXD1 RESET_N P2/INT MDIO P3/RXD2 VDDIO ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Pin Name AMDIX TP_AP TP_AN VSS VDD TP_BN TP_BP VDD TCSR VSS RESET_N P2/INT MDIO MDC VDDIO HWSW/ CRS Regpin/ COL AMDIX/RXD3 P3/RXD2 RXTRI/ RXD1 SI/LED4 FDPX/ RXD0 RMII/RXDV SPEED TXER ANSEL/ RXCLK9 NOD/ RXER Pin Type IN/Ipu AIO AIO Power AIO AIO Power AIO Input IO/Ipd IO Input Power IO/Ipu IO/Ipd IO/Ipu IO/Ipd IO/Ipu IO/Ipd IO/Ipu IO/Ipd Ipd IN IO/Ipu IO/Ipd AMDIX Enable Pin Description Twisted pair port A (for either transmit or receive) positive signal Twisted pair port A (for either transmit or receive) negative signal 3.3V Power Supply Twisted pair port B (for either transmit or receive) negative signal Twisted pair port B (for either transmit or receive) positive signal 3.3V Power Supply Transmit Current bias pin, connected to Vdd and ground via two resistors. Hardware reset for the whole chip (active low) PHY address Bit 2 as input (during power on reset and hardware reset) Interrupt output as output (default active low, can be programmed to active high) Management Data Input/Output Management Data Clock 3.3 V IO Power Supply. Hard pin select enable as input (during power on reset and hardware reset) and MII CRS as output Full register access enable as input (during power on reset and hardware reset) and MII COL output AMDIX enable as input (during power on reset and hardware reset) Receive data Bit 3 for MII PHY address Bit 3 as input (during power on reset and hardware reset) Receive data Bit 2 for MII as output. RX isolate enable (during power on reset and hardware reset) Received data Bit 1 for both RMII and MII MII/SI mode select as input (during power on reset and hardware reset) and LED # 4 as output Full duplex enable (during power on reset and hardware reset) Received data Bit 0 for both RMII and MII RMII/MII select as input (during power on reset and hardware reset) Receive data valid for MII and CRS_DV for RMII as output 10/100M input select. 1 = 100M mode, 0 = 10M mode. TXER Input Auto-negotiation enable(during power on reset and hardware reset) Receive clock MII Node/repeater select (during power on reset and hardware reset) Receive error Ground Connect to ground. Ground Connect to ground. IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 3 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Pin Number 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name SPEED/ TXCLK TXEN TXD0 VDDD LED3 TXD1 TXT2 TXD3 REF_OUT REF_IN P4/LED2 P0/LED0 P1/LED1 Pin Type IO/Ipu Input Input Power IO/Ipd Input Input Input Input IO/Ipu IO IO Pin Description 10M/100M select as input (during power on reset and hardware reset) Transmit clock for MII as output Transmit enable for both RMII and MII Transmit data Bit 0 for both RMII and MII Core Power Supply LED3 output Transmit data Bit 1for both RMII and MII Transmit data Bit 2 for MII Transmit data Bit 3 for MII 25 MHz crystal (or clock) input for MII. 50MHz clock input for RMII PHY address Bit 4 as input (during power on reset and hardware reset) And LED # 2 as output PHY address Bit 0 as input (during power on reset and hardware reset) and LED # 0(function configurable, default is "activity/no activity") as output PHY address Bit 1 as input (during power on reset and hardware reset) and LED # 1 (function configurable, default is "10/100 mode") as output Output 25 MHz crystal output Notes: 1. Ipd = Input with internal pull-down. Ipu = Input with internal pull-up. Opu = Output with internal pull-up. Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise. 2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents valid data to MAC through the MII. RXD[3..0] is invalid when RXDV is de-asserted. 3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of recovered data are sent from the PHY. 4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from the MAC through the MII. TXD[3..0] has no effect when TXEN is de-asserted. 5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of data are received by the PHY from the MAC. IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 4 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Strapping Options Pin Number 1 16 17 18 38 19 12 40 39 21 20 22 Pin Name AMDIX HWSW/CRS REGPIN/COL AMDIX/RXD2 P4/LED2 P3/RXD2 P2/INT P1/LED1 P0/LED0 SI/LED4 RXTRI/RXD1 FDPX/RXD0 Pin Type1 IN/Ipu IO/Ipd IO/Ipd IO/Ipu IO/Ipu IO/Ipd IO/Ipd IO/ IO/ IO/Ipd IO/Ipd IO/Ipu 1 = AMDIX enable 0 = AMDIX disable Pin Function Hardware pin select enable. Active during power-on and hardware reset. Full register access enable. Active during power-on and hardware reset. 1 = AMDIX enable 0 = AMDIX disable The PHY address is set by P[4:0] at power-on reset. P0 and P1 must have external pull-up or pull-down to set address at start up. MII/SI mode select. Active during power-on and hardware reset. 1=RX tri-state for MII/RMII interface 0=RX output enable 1=Full duplex 0=Half duplex Ignored if Auto negotiation is enabled [1x]=RMII mode [01]=SI mode (Serial interface mode) [00]=MII mode 1=100M mode 0=10M mode 1=Enable auto negotiation 0=Disable auto negotiation 0=Node mode 1=repeater mode 1=100M mode 0=10M mode Ignored if Auto negotiation is enabled LED3 output 23 RMII/RXDV IO/Ipd 24 26 27 28 SPEED ANSEL/RXCLK NOD/RXER SPEED/TXCLK IO/Ipu IO/Ipu IO/Ipd IO/Ipu 32 LED3 IO/Ipu 1. Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise. Functional Description The ICS1894-32 is a stream processor. During data transmission, it accepts sequential nibbles from its MAC (Media Access Control) converts them into a serial bit stream, encodes them, and transmits them over the medium through an external isolation transformer. When receiving data, the ICS1894-32 converts and decodes a serial bit stream (acquired from an isolation transformer that interfaces with the medium) into sequential nibbles. It subsequently presents these nibbles to its MAC Interface. The ICS1894-32 implements the OSI model's physical layer, consisting of the following, as defined by the ISO/IEC 8802-3 standard: * Physical Coding sublayer (PCS) IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 5 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER * Physical Medium Attachment sublayer (PMA) * Physical Medium Dependent sublayer (PMD) * Auto-Negotiation sublayer The ICS1894-32 is transparent to the next layer of the OSI model, the link layer. The link layer has two sublayers: the Logical Link Control sublayer and the MAC sublayer. The ICS1894-32 can interface directly to the MAC. The ICS1894-32 transmits framed packets acquired from its MAC Interface and receives encapsulated packets from another PHY, which it translates and presents to its MAC Interface. Note: As per the ISO/IEC standard, the ICS1894-32 does not affect, nor is it affected by, the underlying structure of the MAC frame it is conveying. Management Entity (STA) of the link status. For 100M data transmission, the ICS1894-32 MAC Interface is configured to provide a 100M Media Independent Interface (MII). 10Base-T Operation During 10Base-T data transmission, the ICS1894-32 inserts only the IDL delimiter into the data stream. The ICS1894-32 appends the IDL delimiter to the end of each MAC frame. However, since the 10Base-T preamble already has a Start-of-Frame delimiter (SFD), it is not required that the ICS1894-32 insert an SSD-like delimiter. When receiving data from the medium (such as a twisted-pair cable), the ICS1894-32 uses the preamble to synchronize its receive clock. When the ICS1894-32 receive clock establishes lock, it presents the preamble nibbles to its MAC Interface. The 10M MAC Interface uses the standard MII Interface. In 10M operations, during periods when MAC frames are being neither transmitted nor received, the ICS1894-32 signals and detects Normal Link Pulses. This action allows the integrity of the Link Segment with the remote link partner to be established and then reported to the ICS1894-32's STA. 100Base-TX Operation During 100Base-TX data transmission, the ICS1894-32 accepts packets from a MAC and inserts Start-of-Stream Delimiters (SSDs) and End-of-Stream Delimiters (ESDs) into the data stream. The ICS1894-32 encapsulates each MAC frame, including the preamble, with an SSD and an ESD. As per the ISO/IEC Standard, the ICS1894-32 replaces the first octet of each MAC preamble with an SSD and appends an ESD to the end of each MAC frame. When receiving data from the medium, the ICS1894-32 removes each SSD and replaces it with the pre-defined preamble pattern before presenting the nibbles to its MAC Interface. When the ICS1894-32 encounters an ESD in the received data stream, signifying the end of the frame, it ends the presentation of nibbles to its MAC Interface. Therefore, the local MAC receives an unaltered copy of the transmitted frame sent by the remote MAC. During periods when MAC frames are being neither transmitted nor received, the ICS1894-32 signals and detects the IDLE condition on the Link Segment. In the 100Base-TX mode, the ICS1894-32 transmit channel sends a continuous stream of scrambled ones to signify the IDLE condition. Similarly, the ICS1894-32 receive channel continually monitors its data stream and looks for a pattern of scrambled ones. The results of this signaling and monitoring provide the ICS1894-32 with the means to establish the integrity of the Link Segment between itself and its remote link partner and inform its Station SQE and Jabber Function (10Base-T only) In 10Base-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE Test is required as a test of the 10Base-T transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the 10Base-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250 ms, the 10Base-T transmitter is re-enabled and COL is de-asserted (returns to low). Auto-Negotiation The ICS1894-40 conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3u specification. Autonegotiation is enabled by either hardware pin strapping (pin 20) or software (register 0h bit 12). Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link partners advertise their capabilities to each other, and then compare their own capabilities with those they received from their link partners. The highest speed and duplex IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 6 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER setting that is common to the two link partners is selected as the mode of operation. The following list shows the speed and duplex operation mode from highest to lowest. PHY status and/or configure the PHY settings. Additional details on the MIIM interface can be found in Clause 22.2.4.5 of the IEEE 802.3u Specification. The MIIM interface consists of the following: * * * * Priority 1: 100Base-TX, full-duplex Priority 2: 100Base-TX, half-duplex Priority 3: 10Base-T, full-duplex Priority 4: 10Base-T, half-duplex * A physical connection that incorporates the clock line (MDC) and the data line (MDIO). * A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with one or more ICS1894-40 devices. Each ICS1894-40 device is assigned a PHY address between 1 and 7 by the P[4:0] strapping pins. If auto-negotiation is not supported or the ICS1894-40 link partner is forced to bypass auto-negotiation, the ICS1894-40 sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the ICS1894-40 to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. * An internal addressable set of thirteen 16-bit MDIO registers. Register [0:6] are required, and their functions are defined by the IEEE 802.3u Specification. The additional registers are provided for expanded functionality. The ICS1894-40 supports MIIM in both MII mode and RMII mode. The following table shows the MII Management frame format for the ICS1894-40. MII Management (MIIM) Interface The ICS1894-40 supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the ICS1894-40. An external device with MIIM capability is used to read the MII Management Frame Format Preamble Start of Frame Read Write 32 1's 32 1's 01 01 Read/Write PHY Address OP Code Bits [4:0] 10 01 00AAA 00AAA REG Address Bits [4:0] RRRRR RRRRR TA Z0 10 Data Bits [15:0] DDDDDDDD_DDDDDDDD DDDDDDDD_DDDDDDDD Idle Z Z Interrupt (INT) INT (pin 12) is an optional interrupt signal that is used to inform the external controller that there has been a status update in the ICS1894-40 PHY register. Bits[15:8] of register 1Bh are the interrupt control bits, and are used to enable and disable the conditions for asserting the INT signal. Bits[7:0] of register 1Bh are the interrupt status bits, and are used to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading register 1Bh. Bit 9 of register 1Fh sets the interrupt level to active high or active low. common interface between physical layer and MAC layer devices, and has the following key characteristics: * Supports 10Mbps and 100Mbps data rates. * Uses a 25MHz reference clock, sourced by the PHY. * Provides independent 4-bit wide (nibble) transmit and receive data paths. * Contains two distinct groups of signals: one for transmission and the other for reception. By default, the ICS1894-40 is configured in MII mode after it is power-up or reset with the following: MII Data Interface The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Specification. It provides a * A 25MHz crystal connected to REF_IN, REF_OUT (pins 37, 36), or an external 25MHz clock source (oscillator) connected to REF_IN. IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 7 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER MII Signal Definition The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3u Specification for detailed information. MII Signal Name Direction (with respect to PHY, ICS1894-40 signal) Output Input Input Output Output Output Output Output Output Direction (with respect to MAC) Input Output Output Input Input Input Input, or (not required) Input Input Description TXCLK TXEN TXD[3:0] RXCLK RXDV RXD[3:0] RXER CRS COL Transmit Clock (2.5MHz for 10Mbps; 25MHz for 100Mbps) Transmit Enable Transmit Data [3:0] Receive Clock (2.5MHz for 10Mbps; 25MHz for 100Mbps) Receive Data Valid Receive Data [3:0] Receive Error Carrier Sense Collision Detection Transmit Clock (TXCLK) TXCLK is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0]. TXCLK is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation. * In 10Mbps mode, RXCLK is recovered from the line while carrier is active. RXCLK is derived from the PHY's reference clock when the line is idle, or link is down. * In 100Mbps mode, RXCLK is continuously recovered from the line. If link is down, RXCLK is derived from the PHY's reference clock. RXCLK is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation. Transmit Enable (TXEN) TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated prior to the first TXCLK following the final nibble of a frame. TXEN transitions synchronously with respect to TXCLK. Receive Data Valid (RXDV) RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0]. * In 10Mbps mode, RXDV is asserted with the first nibble of the SFD (Start of Frame Delimiter), "5D", and remains asserted until the end of the frame. Transmit Data [3:0] (TXD[3:0]) TXD[3:0] transitions synchronously with respect to TXCLK. When TXEN is asserted, TXD[3:0] are accepted for transmission by the PHY. TXD[3:0] is "00" to indicate idle when TXEN is de-asserted. Values other than "00" on TXD[3:0] while TXEN is de-asserted are ignored by the PHY. * In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame. RXDV transitions synchronously with respect to RXCLK. Receive Data [3:0] (RXD[3:0]) RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0] transfers a nibble of recovered data from the PHY. Receive Clock (RXCLK) RXCLK provides the timing reference for RXDV, RXD[3:0], and RXER. IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 8 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Receive Error (RXER) RXER is asserted for one or more RXCLK periods to indicate that an error (e.g. a coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame presently being transferred from the PHY. RXER transitions synchronously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC. power-up or reset with the following: * A 50MHz reference clock connected to REF_IN (pin 37). In RMII mode, unused MII signals, TXD[3:2] (pins 35, 34), are tied to ground. Carrier Sense (CRS) CRS is asserted and de-asserted as follows: * In 10Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the reception of an end-of-frame (EOF) marker. * In 100Mbps mode, CRS is asserted when a start-of-stream delimiter, or /J/K symbol pair is detected. CRS is deasserted when an end-of-stream delimiter, or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts CRS if IDLE symbols are received without /T/R. Collision (COL) COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This is used to inform the MAC that a collision has occurred during its transmission to the PHY. COL transitions asynchronously with respect to TXCLK and RXCLK. Reduced MII (RMII) Data Interface The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics: * Supports 10Mbps and 100Mbps data rates. * Uses a single 50MHz reference clock provided by the MAC or the system board. * Provides independent 2-bit wide (di-bit) transmit and receive data paths. * Contains two distinct groups of signals: one for transmission and the other for reception. The ICS1894-40 is configured in RMII mode after it is IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 9 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER RMII Signal Definition The following table describes the RMII signals. Refer to RMII Specification for detailed information. RMII Signal Name Direction (with respect to PHY, ICS1894-40 signal) Input Input Input Output Output Output Direction (with respect to MAC) Input or Output Output Output Input Input Input, or (not required) Description REF_CLK TX_EN TXD[1:0] CRS_DV RXD[1:0 RX_ER Synchronous 50 MHz clock reference for receive, transmit and control interface Transmit Enable Transmit Data [1:0] Carrier Sense/Receive Data Valid Receive Data [1:0] Receive Error Reference Clock (REF_CLK) REF_CLK is sourced by the MAC or system board. It is a continuous 50MHz clock that provides the timing reference for TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and RX_ER. follows the final di-bit. The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous relative to REF_CLK, the data on RXD[1:0] is "00" until proper receive signal decoding takes place. Transmit Enable (TX_EN) TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. It is asserted synchronously with the first nibble of the preamble and remains asserted while all di-bits to be transmitted are presented on the RMII, and is negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN transitions synchronously with respect to REF_CLK. Receive Data [1:0] (RXD[1:0]) RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers two bits of recovered data from the PHY. RXD[1:0] is "00" to indicate idle when CRS_DV is de-asserted. Values other than "00" on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC. Transmit Data [1:0] (TXD[1:0]) TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for transmission by the PHY. TXD[1:0] is "00" to indicate idle when TX_EN is de-asserted. Values other than "00" on TXD[1:0] while TX_EN is de-asserted are ignored by the PHY. Receive Error (RX_ER) RX_ER is asserted for one or more REF_CLK periods to indicate that an error (e.g. a coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame presently being transferred from the PHY. RX_ER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the MAC. Carrier Sense/Receive Data Valid (CRS_DV) CRS_DV is asserted by the PHY when the receive medium is non-idle. It is asserted asynchronously on detection of carrier. This is when squelch is passed in 10Mbps mode, and when 2 non-contiguous zeroes in 10 bits are detected in 100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV. So long as carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered di-bit of the frame through the final recovered di-bit, and it is negated prior to the first REF_CLK that IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 10 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Auto-MDI/MDIX Crossover The ICS1894-40 includes the auto-MDI/MDIX crossover feature. In a typical CAT 5 Ethernet installation the transmit twisted pair signal pins of the RJ45 connector are crossed over in the CAT 5 wiring to the partners receive twisted pair signal pins and receive twisted pair to the partners transmit twisted pair. This is usually accomplished in the wiring plant. Hubs generally wire the RJ45 connector crossed to accomplish the crossover. Two types of CAT 5 cables (straight and crossed) are available to achieve the correct connection. The Auto-MDI/MDIX feature automatically corrects for miss-wired installations by automatically swapping transmit and receive signal pairs at the PHY when no link results. Auto-MDI/MDIX is automatic, but may be disabled for test purposes by writing MDIO register 19 Bits 9:8 in the MDIO register. The Auto-MDI/MDIX function is independent of Auto-Negotiation and preceeds Auto-Negotiation when enabled. Power Management Clock Reference Interface The REF_IN pin provides the ICS1894-40 Clock Reference Interface. The ICS1894-40 requires a single clock reference with a frequency of 25 MHz 50 parts per million. This accuracy is necessary to meet the interface requirements of the ISO/IEEE 8802-3 standard, specifically clauses 22.2.2.1 and 24.2.3.4. The ICS1894-40 supports two clock source configurations: a CMOS oscillator or a CMOS driver. The input to REF_IN is CMOS (10% to 90% VDD), not TTL. Alternately, a 25MHz crystal may be used. IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 11 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Crystal or Oscillator Operation ICS1894CK-40 MII w/ Crystal Input REF_OUT 36 25.000MHz REF_IN 37 33 pF 33 pF ICS1894CK-40 REF_OUT 36 NC CMOS 25.000 MHz 33 Ohm REF_IN 37 MII w/ Oscillator Input 10 pF ICS1894CK-40 REF_OUT 36 NC CMOS 50.000 MHz 33 Ohm REF_IN 37 RMII w/ Oscillator Input 10 pF IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 12 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER If a crystal is used as the clocking source, connect it to both the REF_IN (pin 37) and REF_OUT (pin 36) pins of the ICS1894-40. A pair of bypass capacitors on either side of the crystal are connected to ground. The crystal is used in the parallel resonance or anti-resonance mode. The value of the load caps serve to adjust the final frequency of the crystal oscillation. Typical applications would use 33pF load caps. The exact value will be affected by the board routing capacitance on REF_IN and REF_OUT pins. Smaller load capacitors raise the frequency of oscillation. Specifications Fundamental Frequency (tolerance is sum of freq., temp., stability and aging.) Freq. Tolerance Input Capacitance Once the exact value of load capacitance is established it will be the same for all boards using the same specification crystal. The best way to measure the crystal frequency is to measure the frequency of TXCLK (pin 28) using a frequency counter with a 1 second gate time. Using the buffered output TXCLK prevents the crystal frequency from being affected by the measurement. The crystal specification is shown in the 25MHz Crystal Specification table. 25 MHz Crystal Specification Table Typical Maximum 25.00125 Unit MHz ppm pF Symbol Minimum F0 24.99875 25.00000 F/f Cin 3 50 25 MHz Oscillator Specification table Specifications Output Frequency Freq. Stability (including aging) Duty cycle CMOS level one-half VDD VIH VIL Period Jitter Input Capacitance Tjitter CIN 3 Symbol Minimum F0 Typical Maximum 25.00125 Unit MHz ppm % Volts 0.33 500 Volts pS pF 24.99875 25.00000 35 2.79 F/f Tw/T 50 65 50 MHz Oscillator Specification table Specifications Output Frequency Freq. Stability (including aging) Duty cycle CMOS level one-half VDD VIH VIL Period Jitter Input Capacitance Tjitter CIN 3 Symbol Minimum F0 Typical Maximum 50.0025 Unit MHz ppm % Volts 0.33 500 Volts pS pF 49.9975 50.00000 35 2.79 F/f Tw/T 50 65 Status Interface The ICS1894-40 provides five multi-function configuration pins that report the results of continual link monitoring by providing signals that are intended for driving LEDs. IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 13 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Pins for Monitoring the Data Link table Pin P0AC P1CL P2LI P3TD P4RD LED Driven by the Pin's Output Signal AC (Link Activity) LED CL (Collisions) LED LI (Link Integrity) LED TD (Transmit Data) LED RD (Receive Data) LED the ICS1894-40. LEDs may be placed in series with these resistors to provide a designated status indicator as described in the Pins for Monitoring the Data Link table. Use 1K resistors. Caution: All pins listed in the Pins for Monitoring the Data Link table must not float. 4. As outputs, the asserted state of a multi-function configuration pin is the inverse of the sense sampled during reset. This inversion provides a signal that can illuminate an LED during an asserted state. For example, if a multi-function configuration pin is pulled down to ground through an LED and a current-limiting resistor, then the sampled sense of the input is low. To illuminate this LED for the asserted state, the output is driven high. 5. Adding 10K resistors across the LEDs ensures the PHY address is fully defined during slow VDD power-ramp conditions. 6. PHY address 00 tri-states the MII interface. (Do not select PHY address 00 unless you want the MII tri-stated.) Note: 1. During either a power-on reset or a hardware reset, each multi-function configuration pin is an input that is sampled when the ICS1894-40 exits the reset state. After sampling is complete, these pins are output pins that can drive status LEDs. 2. A software reset does not affect the state of a multi-function configuration pin. During a software reset, all multi-function configuration pins are outputs. 3. Each multi-function configuration pin must be pulled either up or down with a resistor to establish the address of The following figure shows typical biasing and LED connections for the ICS1894-40. ICS1894CK-40 P4/LED2 38 P3/RXD2 19 RXD2 P2//INT 12 INT P1/LED1 40 P0/LED0 39 VDD 10K LED2 10K 10K LED1 10K 1K 1K 1K LED0 10K This circuit decodes to PHY address = 1 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 14 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Register Map Register Address 0 1 2,3 4 5 6 7 8 9 through 15 16 through 31 Control Status PHY Identifier Register Name Basic / Extended Basic Basic Extended Extended Extended Extended Extended Extended Extended Extended Auto-Negotiation Advertisement Auto-Negotiation Link Partner Ability Auto-Negotiation Expansion Auto-Negotiation Next Page Transmit Auto-Negotiation Next Page Link Partner Ability Reserved by IEEE Vendor-Specific (ICS) Registers Register Description Bit Definition When Bit = 0 When Bit = 1 Access SF Default Hex Register 0h - Control 0.15 0.14 0.13 0.12 0.11 0.10 0.9 0.8 0.7 0.6 0.5 0.4 Reset Loopback enable Speed select1 No effect Disable Loopback mode 10 Mbps operation Disable Auto-Negotiation Normal power mode No effect No effect Half-duplex operation No effect Always 0 Always 0 Always 0 ICS1893CF enters Reset mode Enable Loopback mode 100 Mbps operation Enable Auto-Negotiation Low-power mode Isolate ICS1893CF from MII Restart Auto-Negotiation Full-duplex operation Enable collision test N/A N/A N/A R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO SC - - - - - SC - - - - - 0 0 1 1 0 0/1 0 0 0 0 0 0 0 0/4 3 Auto-Negotiation enable Low-power mode Isolate Auto-Negotiation restart Duplex mode1 Collision test IEEE reserved IEEE reserved IEEE reserved IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 15 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 0.3 0.2 0.1 0.0 Definition IEEE reserved IEEE reserved IEEE reserved IEEE reserved When Bit = 0 Always 0 Always 0 Always 0 Always 0 N/A N/A N/A N/A When Bit = 1 Access RO RO RO RO SF - - - - Default 0 0 0 0 Hex 0 Register 1h - Control 1.15 1.14 1.13 1.12 1.11 1.10 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 100Base-T4 100Base-TX full duplex 100Base-TX half duplex 10Base-T full duplex 10Base-T half duplex IEEE reserved IEEE reserved IEEE reserved IEEE reserved MF Preamble suppression Auto-Negotiation complete Remote fault Auto-Negotiation ability Link status Jabber detect Extended capability Always 0. (Not supported.) Mode not supported Mode not supported Mode not supported Mode not supported Always 0 Always 0 Always 0 Always 0 PHY requires MF Preambles Auto-Negotiation is in process, if enabled N/A Mode supported Mode supported Mode supported Mode supported N/A N/A N/A N/A PHY does not require MF Preambles Auto-Negotiation is completed RO CW CW CW CW CW CW CW CW RO RO RO RO RO RO RO - - - - - - - - - - LH LH - LL LH - 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 9 0 8 7 No remote fault detected Remote fault detected N/A Link is invalid/down No jabber condition N/A Always 1: PHY has Auto-Negotiation ability Link is valid/established Jabber condition detected Always 1: PHY has extended capabilities Register 2h, 3h - PHY Identifier 2.15 2.14 2.13 2.12 2.11 2.10 2.9 2.8 OUI bit 3 | c OUI bit 4 | d OUI bit 5 | e OUI bit 6 | f OUI bit 7 | g OUI bit 8 | h OUI bit 9 | I OUI bit 10 | j N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A CW CW CW CW CW CW CW CW - - - - - - - - 0 0 0 0 0 0 0 0 0 0 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 16 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 3.15 3.14 3.13 3.12 3.11 3.10 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0 Definition OUI bit 11 | k OUI bit 12 | l OUI bit 13 | m OUI bit 14 | n OUI bit 15 | o OUI bit 16 | p OUI bit 17 | q OUI bit 18 | r OUI bit 19 | s OUI bit 20 | t OUI bit 21 | u OUI bit 22 | v OUI bit 23 | w OUI bit 24 | x Manufacturer's Model Number bit 5 Manufacturer's Model Number bit 4 Manufacturer's Model Number bit 3 Manufacturer's Model Number bit 2 Manufacturer's Model Number bit 1 Manufacturer's Model Number bit 0 Revision Number bit 3 Revision Number bit 2 Revision Number bit 1 Revision Number bit 0 When Bit = 0 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A When Bit = 1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Access CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW SF - - - - - - - - - - - - - - - - - - - - - - - - Default 0 0 0 1 0 1 0 1 1 1 1 1 0 1 0 0 0 1 0 1 0 0 0 0 Hex 1 5 F 4 5 0 Register 4h - Auto-Negotiation Advertisement 4.15 4.14 4.13 4.12 Next Page IEEE reserved Remote fault IEEE reserved Next page not supported Next page supported Always 0 Locally, no faults detected Always 0 N/A Local fault detected N/A R/W CW R/W CW - - - - 0 0 0 0 0 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 17 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 4.11 4.10 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 Definition IEEE reserved IEEE reserved 100Base-T4 100Base-TX, full duplex When Bit = 0 Always 0 Always 0 Always 0. (Not supported.) Do not advertise ability N/A N/A N/A When Bit = 1 Access CW CW CW R/W R/W R/W R/W CW CW CW CW CW SF - - - - - - - - - - - - Default 0 0 0 1 1 1 1 0 0 0 0 1 Hex 1 Advertise ability Advertise ability Advertise ability Advertise ability N/A N/A N/A N/A IEEE 802.3-specified default 100Base-TX, half duplex Do not advertise ability 10Base-T, full duplex 10Base-T half duplex Selector Field bit S4 Selector Field bit S3 Selector Field bit S2 Selector Field bit S1 Selector Field bit S0 Do not advertise ability Do not advertise ability IEEE 802.3-specified default IEEE 802.3-specified default IEEE 802.3-specified default IEEE 802.3-specified default N/A E 1 Register 5h - Auto-Negotiation Link Partner Ability 5.15 5.14 5.13 5.12 5.11 5.10 5.9 5.8 5.7 5.6 5.5 5.4 Next Page Acknowledge Remote fault IEEE reserved IEEE reserved IEEE reserved 100Base-T4 100Base-TX, full duplex Next Page disabled Always 0 No faults detected Always 0 Always 0 Always 0 Always 0. (Not supported.) Link partner is not capable Next Page enabled N/A Remote fault detected N/A N/A N/A N/A Link partner is capable Link partner is capable Link partner is capable Link partner is capable N/A RO RO RO RO RO RO RO RO RO RO RO RO - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 100Base-TX, half duplex Link partner is not capable 10Base-T, full duplex 10Base-T, half duplex Selector Field bit S4 Link partner is not capable Link partner is not capable IEEE 802.3 defined. Always 0. IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 18 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 5.3 5.2 5.1 5.0 Definition Selector Field bit S3 Selector Field bit S2 Selector Field bit S1 Selector Field bit S0 When Bit = 0 IEEE 802.3 defined. Always 0. IEEE 802.3 defined. Always 0. IEEE 802.3 defined. Always 0. N/A N/A N/A N/A When Bit = 1 Access CW CW CW CW SF - - - - Default 0 0 0 0 Hex 0 IEEE 802.3 defined. Always 1. Register 6h - Auto-Negotiation Expansion 6.15 6.14 6.13 6.12 6.11 6.10 6.9 6.8 6.7 6.6 6.5 6.4 6.3 6.2 6.1 6.0 IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved IEEE reserved Parallel detection fault Link partner Next Page able Next Page able Page received Link partner Auto-Negotiation able Always 0 Always 0 Always 0 Always 0 Always 0 Always 0 Always 0 Always 0 Always 0 Always 0 Always 0 No Fault Link partner is not Next Page able Local device is not Next Page able Next Page not received Link partner is not Auto-Negotiation able N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Multiple technologies detected Link partner is Next Page able Local device is Next Page able Next Page received Link partner is Auto-Negotiation able CW CW CW CW CW CW CW CW CW CW CW RO RO RO RO RO - - - - - - - - - - - LH - - LH - 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 0 0 0 Register 7h - Auto-Negotiation Next Page Transmit 7.15 7.14 7.13 7.12 Next Page IEEE reserved Message Page Acknowledge 2 Last Page Always 0 Unformatted Page Cannot comply with Message Additional Pages follow N/A Message Page Can comply with Message RW RO RW RW - - - - 0 0 1 0 2 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 19 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 7.11 7.10 7.9 7.8 7.7 7.6 7.5 7.4 7.3 7.2 7.1 7.0 Toggle Definition When Bit = 0 Previous Link Code Word was zero Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message When Bit = 1 Previous Link Code Word was one Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Access RO RW RW RW RW RW RW RW RW RW RW RW SF - - - - - - - - - - - - Default 0 0 0 0 0 0 0 0 0 0 0 1 Hex 0 Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field 0 1 Register 8h - Auto-Negotiation Next Page Link Partner Ability 8.15 8.14 8.13 8.12 8.11 8.10 8.9 8.8 Next Page IEEE reserved Message Page Acknowledge 2 Toggle Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Last Page Always 0 Unformatted Page Cannot comply with Message Previous Link Code Word was zero Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Additional Pages follow N/A Message Page Can comply with Message Previous Link Code Word was one Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message RO RO RO RO RO RO RO RO - - - - - - - - 0 0 0 0 0 0 0 0 0 0 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 20 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 8.7 8.6 8.5 8.4 8.3 8.2 8.1 8.0 Definition Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field Message code field /Unformatted code field When Bit = 0 Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message When Bit = 1 Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Bit value depends on the particular message Access RO RO RO RO RO RO RO RO SF - - - - - - - - Default 0 0 0 0 0 0 0 0 Hex 0 0 Register 9 through 15h - Reserved by IEEE Register 16h - Extended Control Register 16.15 16.14 16.13 16.12 16.11 16.10 Command Override Write enable ICS reserved ICS reserved ICS reserved ICS reserved PHY Address Bit 4 Disabled Read unspecified Read unspecified Read unspecified Read unspecified Enabled Read unspecified Read unspecified Read unspecified Read unspecified RW RW/0 RW/0 RW/0 RW/0 RO SC - - - - - 0 0 0 0 0 P4R D P3TD P2LI P1CL P0AC 0 - - - - 16.9 16.8 16.7 16.6 16.5 16.4 PHY Address Bit 3 PHY Address Bit 2 PHY Address Bit 1 PHY Address Bit 0 Stream Cipher Test Mode ICS reserved Normal operation Read unspecified Test mode Read unspecified . RO RO RO RO RW RW/0 - - - - - - IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 21 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 16.3 16.2 16.1 16.0 Definition NRZ/NRZI encoding Transmit invalid codes ICS reserved Stream Cipher disable When Bit = 0 NRZ encoding Disabled Read unspecified Stream Cipher enabled When Bit = 1 NRZI encoding Enabled Read unspecified Stream Cipher disabled Access RW RW RW/0 RW SF - - - - Default 1 0 0 0 Hex 8 Register 17h - Quick Poll Detailed Status Register 17.15 17.14 17.13 17.12 17.11 17.10 17.9 17.8 17.7 17.6 17.5 17.4 17.3 17.2 17.1 17.0 Data rate Duplex Auto-Negotiation Progress Monitor Bit 2 Auto-Negotiation Progress Monitor Bit 1 Auto-Negotiation Progress Monitor Bit 0 100Base-TX signal lost 100BasePLL Lock Error False Carrier detect Invalid symbol detected Halt Symbol detected Premature End detected Auto-Negotiation complete 100Base-TX signal detect Jabber detect Remote fault Link Status 10 Mbps Half duplex 100 Mbps Full duplex RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO - - LM X LM X LM X LH LH LH LH LH LH - - LH LH LL - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - Reference Decode Table Reference Decode Table Reference Decode Table Reference Decode Table Reference Decode Table Reference Decode Table Valid signal PLL locked Normal Carrier or Idle Valid symbols observed Signal lost PLL failed to lock False Carrier Invalid symbol received No Halt Symbol received Halt Symbol received Normal data stream Auto-Negotiation in process Signal present No jabber detected Stream contained two IDLE symbols Auto-Negotiation complete No signal present Jabber detected No remote fault detected Remote fault detected Link is not valid Link is valid Register 18h - 10Base-T Operations Register 18.15 18.14 18.13 18.12 Remote Jabber Detect Polarity reversed Data Bus Mode No Remote Jabber Condition detected Normal polarity Remote Jabber Condition Detected Polarity reversed RO RO R0 R0 LH LH - - 0 0 - - - Bit18.13 is latched pin RXTRI Bit18.12 is latched SI [1x]=RMII mode [01]=SI mode (Serial interface mode) [00]=MII mode IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 22 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 18.11 18.10 18.9 Definition AMDIXEN RXTRI REGEN When Bit = 0 AMDIX disable RX output enable Vender reserved register access enable When Bit = 1 AMDIX enable RX tri-state for MII/RMII interface Vender reserved register (byte25~byte31) access disable Access RW RW RW SF - - - Default - - - Hex - 18.8 18.7 18.6 18.5 18.4 18.3 18.2 18.1 18.0 TM_SWITCH ICS reserved ICS reserved Jabber inhibit ICS reserved Auto polarity inhibit SQE test inhibit Link Loss inhibit Squelch inhibit Switch TMUX2 to TMUX1, test control Read unspecified Read unspecified Normal Jabber behavior Read unspecified Polarity automatically corrected Normal SQE test behavior Normal Link Loss behavior Read unspecified Read unspecified Jabber Check disabled Read unspecified Polarity not automatically corrected SQE test disabled Link Always = Link Pass RW RW/0 RW/0 RW RW/1 RW RW RW RW - - - - - - - - - - - - 0 1 0 0 0 0 0 - Normal squelch behavior No squelch Register 19h - Extended Control Register 19.15 19.14 19.13 19.12 19.11 Node Mode Hardware/Software Mode Remote Fault Register Bank select Node mode Use bit00.13 select speed No faults detected Repeater mode Use real time input pin 24(40NLG) select speed Remote fault detected RW RO RO RW RW - - - - - 0 1 0 0 0 2 4 [01]=Bank1, access register0x00~0x13 and ICS1893CF register 0x14~0x1F [00]=Bank0, access register0x00~0x13, new defined register 0x14~0x19 and ICS1893CF register 0x1A~0x1F [1x]=Bank0, same as [00 Read unspecified See Table 7-22 See Table 7-22 Twisted Pair Signals are not Tri-Stated or No effect Read unspecified Read unspecified Read unspecified Read unspecified See Table 7-22 See Table 7-22 Twisted Pair Signals are Tri-Stated Read unspecified Read unspecified Read unspecified 19.10 19.9 19.8 19.7 ICS reserved AMDIX_EN MDI_MODE Twisted Pair Tri-State Enable, TPTRI ICS reserved ICS reserved ICS reserved RO RW RW RW - - - - 0 1 0 0 0 19.6 19.5 19.4 RW RW RW - - - 0 0 0 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 23 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 19.3 19.2 19.1 19.0 Definition ICS reserved ICS reserved ICS reserved Automatic 100Base-TX Power Down When Bit = 0 Read unspecified Read unspecified Read unspecified Do not automatically power down When Bit = 1 Read unspecified Read unspecified Read unspecified Power down automatically Access RW RW RW RW SF - - - - Default 0 0 0 1 Hex 1 Register 20h - Extended Control Register 20.15 20.14 20.13: 12 Str_enhance Fast_off LED4 Mode Normal digital output strength disable the function 00 = Receive Data 01 = Collision 10 = Full Duplex 11 = OFF (Default LED4) 000 = Link Integrity 001 = activity/no activity 010 = Transmit Data 011 = Receive Data 100 = Collision 101 = 10/100 mode 110 = Full Duplex 111 = OFF (Default LED3) 000 = Link Integrity 001 = activity/no activity 010 = Transmit Data 011 = Receive Data 100 = Collision 101 = 10/100 mode 110 = Full Duplex 111 = OFF (Default LED2) 000 = Link Integrity 001 = activity/no activity 010 = Transmit Data 011 = Receive Data 100 = Collision 101 = 10/100 mode (Default LED1) 110 = Full Duplex 111 = OFF 000 = Link Integrity 001 = activity/no activity (Default LED0) 010 = Transmit Data 011 = Receive Data 100 = Collision 101 = 10/100 mode 110 = Full Duplex 111 = LINK_STA Enhance digital output strength in 1.8V condition Enable fast_off circuit RW RW RW 0 0 3 20.11: 9 LED3 Mode RW 7 20.8:6 LED2 Mode RW 7 20.5:3 LED1 Mode RW 5 20.2:0 LED0 Mode RW 1 Register 21h - Extended Control Register IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 24 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 21.15: 0 Definition RXER_CNT When Bit = 0 When Bit = 1 Access RW SF Default Hex Receive error count for RMII mode 0 Register 22h - Extended Control Register 22.15 22.14 22.13 22.12 Interrupt output enable Interrupt flag read clear enable Interrupt polarity Interrupt flag auto clear enable Interrupt flag re-setup enable Disable interrupt output Interrupt flag clear by read disable Output low when interrupt occur Interrupt flag unchanged when interrupt condition removed Interrupt flag always cleared when write 1 to flag bit Disable Deep power down wake up Interrupt Disable Deep power down Interrupt Disable Auto-Negotiation Complete Interrupt Disable Jabber Interrupt Disable Receive Error Interrup Disable Page Received Interrupt Disable Parallel Detect Fault Interrupt Disable Link Partner Acknowledge Disable Link Down Interrupt Disable Remote Fault Interrupt Enable interrupt output Interrupt flag clear by read enable Output high when interrupt occur Interrupt flag cleared when interrupt condition removed Interrupt flag keep unchanged when interrupt condition exist when write 1 to flag bit. Enable Deep power down wake up Interrupt Enable Deep power down Interrupt Enable Auto-Negotiation Complete Interrupt Enable Jabber Interrupt Enable Receive Error Interrupt Enable Page Received Interrupt Enable Parallel Detect Fault Interrupt Enable Link Partner Acknowledge Interrupt Enable Link Down Interrupt Enable Remote Fault Interrupt 22.11 22.10 22.9 22.8 22.7 22.6 22.5 22.4 22.3 22.2 22.1 22.0 Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Disable Link Up Interrupt Enable Link Up Interrupt Register 23h - Extended Control Register 23.15: 11 23.10 23.9 Reserved Deep power down wake up Interrupt Deep power down Interrupt Reserved Deep power down wake up did not occurred Deep power down did not occurred Deep power down wake up occurred Deep power down occurred RO RO/SC RO/SC 0 0 0 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 25 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 23.8 Definition Auto-Negotiation Interrupt Jabber Interrupt Receive Error Interrupt Page Receive Interrupt Parallel Detect Fault Interrupt Link Partner Acknowledge Interrupt Link Down Interrupt Remote Fault Interrupt Link Up Interrupt When Bit = 0 Auto-Negotiation Complete did not occurred Jabber did not occurred Receive Error did not occurred Page Receive did not occurred Parallel Detect Fault did not occurred Link Partner Acknowledge did not occurred Link Down did not occurred Remote Fault did not occurred Link Up did not occurred When Bit = 1 Auto-Negotiation Complete occurred Jabber occurred Receive Error occurred Page Receive occurred Parallel Detect Fault occurred Link Partner Acknowledge occurred Link Down occurred Remote Fault occurred Link Up occurred Access RO/SC SF Default Hex 0 23.7 23.6 23.5 23.4 23.3 RO/SC RO/SC RO/SC RO/SC RO/SC 0 0 0 0 0 23.2 23.1 23.0 RO/SC RO/SC RO/SC 0 0 0 2 0 0 0 Register 24h - Extended Control Register 24.15: 12 24.11: 9 24.8 24.7 FIFO Half Reserved Deep Power down enable Tpll10_100 DPD Enable RMII FIFO half full bits ((n+3)*2 bit), RMII Reserved Deep power down(DPD) disable Don't power down 10/100 PLL in DPD mode Don't power down RX block in DPD mode Don't power down admix_dac block in DPD mode Deep power down(DPD) enable Controlled auto power down10/100 PLL in DPD mode Controlled auto power down of RX block in DPD mode Control auto power down of admix_dac block in DPD mode Control auto power down of CDR block in DPD mode RW RW RW RW 24.6 RX 100 DPD Enable RW 0 24.5 Admix_TX DPD Enable RW 0 24.4 Cdr100_cdr DPD Enable don't power down in DPD mod Reserved Reserved RW 0 24.3:0 0 Register 25h - Extended Control Register 25.15: 11 25.10 Reserved ADD_BIAS Analog control bits Disable Enable RW RW 0 1 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 26 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Bit 25.9:7 Definition TX10BIAS_SET When Bit = 0 When Bit = 1 Access RW SF Default Hex 4 The normal output current of Bias block for 10BaseT is 540uA. Change the register can modify the current with a step about 5% 000: output 80% current 001: output 85% current 010: output 90% current 011: output 95% current 100: output 100% current 101: output 105% current 110: output 110% current 111: output 115% current The normal output current of Bias block for 100BaseTX is 180uA. Change the register can modify the current with a step about 5% 000: output 80% current 001: output 85% current 010: output 90% current 011: output 95% current 100: output 100% current 101: output 105% current 110: output 110% current 111: output 115% current This register setting the delay time of digital control signal for xmit_dac. Increase the setting value can short the delay time. 00: the longest delay time (same as original design) 01: the long delay time 10: the short delay time 11: the shortest delay time The output current of Bias block for RX block is 108uA. The register can change the current with a step about 16.5% 00: output 83.5% current 01: output 100% current 10: output 116.5% current 11: output 133% current Change this value may modify the RX block performance. 25.6:4 TX100BIAS_SET RW 4 25.3:2 OUTDLY_CTL RW 0 25.1:0 RX_SET RW 1 Register 26-31h - Reserved Note: 1 Ignored if Auto negotiation is enable IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 27 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER DC and AC Operating Conditions Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS1894-40. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Parameter VDD (measured to VSS) Digital Inputs / Outputs Storage Temperature Junction Temperature Soldering Temperature Power Dissipation Rating -0.3 V to 3.6V -0.3 V to VDD +0.3 V -55 C to +150 C 125 C 260 C See section "DC Operating Conditions for Supply Current" Recommended Operating Conditions Parameter Ambient Operating Temperature - Commercial Ambient Operating Temperature - Industrial Power Supply Voltage (measured to VSS) Symbol TA TA VDD Min. 0 -40 Max. Units +70 +85 C C V +3.14 +3.47 Recommended Component Values Parameter Oscillator Frequency TCSR Resistor Value Minimum - - Typical 25 1.8k See figure ICS1893CK-40 TCSR Maximum - - Tolerance 50 ppm 1% Units MHz LED Resistor Value 510 1k 10k - There are two IEEE Std. 802.3 requirements that define the tolerance for the frequency of the oscillator. * Clause 22.2.2.1 requires the MII TX_CLK to have an accuracy of 100 ppm. * Clause 24.2.3.4 is more stringent. It requires the code-bit timer to have an accuracy of 0.005% (that is, 50 ppm). IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 28 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER ICS1893CK-40 TCSR Typical Board Layouts TCSR Bias Resistors ICS1894CK-40 VDD 8 18.2K 1% TCSR 9 VDD 100TCSR 1.82K 1% Note: 1. The bias resistor networks set the 10baseT and 100baseTX output amplitude levels. 2. Amplitude is directly related to current sourced out of the TCSR pin. 3. Resistor values shown above are typical. User should check amplitudes and adjust for transformer effects. 4. The VDD connection to the 18.2K resistor can connect to any VDD. The 18.2K resistor provides negative feedback to compensate for VDD changes. Lowering the 18.2K value will lower the 100baseT amplitude. IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 29 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER DC Operating Characteristics for Supply Current The table below lists the DC operating characteristics for the supply current to the ICS1894-40 under various conditions. Note: All VDD_IO measurements are taken with respect to VSS (which equals 0 V). Parameter Supply Current Supply Current Supply Current Supply Current Supply Current Operating Mode 100Base-TX 10Base-T Auto-Negotiation Power-Down Reset Symbol IDD_IO IDD IDD_IO IDD IDD_IO IDD IDD_IO IDD IDD Min. - - - - - - - - - Typ. - - - - - - - - - Max. 11 125 8 160 8 90 5 5 11 Units mA mA mA mA mA mA mA mA mA These supply current parameters are measured through VDD pins to the ICS1894-40. The supply current parameters include external transformer currents. Measurements taken with 100% data transmission and the minimum inter-packet gap. IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 30 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER DC Operating Characteristics for TTL Inputs and Outputs The table below lists the 3.3V DC operating characteristics of the ICS1894-40 TTL inputs and outputs. Note: All VDD_IO measurements are taken with respect to VSS (which equals 0 V). Parameter TTL Input High Voltage TTL Input Low Voltage TTL Output High Voltage TTL Output Low Voltage TTL Driving CMOS, Output High Voltage TTL Driving CMOS, Output Low Voltage Symbol VIH VIL VOH VOL VOH VOL Conditions VDD_IO = 3.47 V VDD_IO = 3.47 V VDD_IO = 3.14 V VDD_IO = 3.14 V VDD_IO = 3.14 V VDD_IO = 3.14 V - - IOH = -4 mA IOL = +4 mA IOH = -4 mA IOL = +4 mA Min. Max. Units 2.0 - 2.4 - 2.4 - - 0.8 - 0.4 - 0.4 V V V V V V Parameter TTL Input High Voltage TTL Input Low Voltage TTL Output High Voltage TTL Output Low Voltage TTL Driving CMOS, Output High Voltage TTL Driving CMOS, Output Low Voltage Symbol VIH VIL VOH VOL VOH VOL Conditions VDD_IO = 1.8V VDD_IO = 1.8V VDD_IO = 1.8V VDD_IO = 1.8V VDD_IO = 1.8V VDD_IO = 1.8V - - IOH = -4 mA IOL = +4 mA IOH = -4 mA IOL = +4 mA Min. Max. Units - - - - - - V V V V V V IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 31 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER DC Operating Characteristics for REF_IN The table below lists the 3.3V DC characteristics for the REF_IN pin. Note: The REF_IN input switch point is 50% of VDD. Parameter Input High Voltage Input Low Voltage Symbol VIH VIL Test Conditions VDD_IO = 3.47 V VDD_IO = 3.14 V Min. 2.97 - Max. - 0.33 Units V V DC Operating Characteristics for Media Independent Interface The table below lists DC operating characteristics for the Media Independent Interface (MII) for the ICS1894-40. Parameter MII Input Pin Capacitance MII Output Pin Capacitance MII Output Drive Impedance Conditions - - VDD_IO = 3.3V Min. - - - Typ. - - 60 Max. 8 14 - Units pF pF Timing Diagrams Timing for Clock Reference In (REF_IN) Pin The table below lists the significant time periods for signals on the clock reference in (REF_IN) pin. The REF_IN Timing Diagram figure shows the timing diagram for the time periods. Note: The REF_IN switching point is 50% of VDD. Time Period t1 t2 Parameter REF_IN Duty Cycle REF_IN Period Conditions - - Min. 45 - Typ. 50 40 Max. Units 55 - % ns REF_IN Timing Diagram t1 REF_IN t2 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 32 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Timing for Transmit Clock (TXCLK) Pins The table below lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various interfaces. The Transmit Clock Timing Diagram figure shows the timing diagram for the time periods. Time Period t1 t2a t2b Parameter TXCLK Duty Cycle TXCLK Period TXCLK Period Conditions - 100M MII (100Base-TX) 10M MII (10Base-T) Min. Typ. Max. 35 - - 50 40 400 65 - - Units % ns ns Transmit Clock Timing Diagram t1 TXCLK t2x Timing for Receive Clock (RXCLK) Pins The table below lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various interfaces. The Receive Clock Timing Diagram figure shows the timing diagram for the time periods. Time Period t1 t2a t2b Parameter RXCLK Duty Cycle RXCLK Period RXCLK Period Conditions - 100M MII (100Base-TX) 10M MII (10Base-T) Min. Typ. Max. Units 35 - - 50 40 400 65 - - % ns ns Receive Clock Timing Diagram t1 RXCLK t2 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 33 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 100M MII: Synchronous Transmit Timing The table below lists the significant time periods for the 100M MII Interface synchronous transmit timing. The time periods consist of timings of signals on the following pins: * * * * TXCLK TXD[3:0] TXEN TXER The 100M MII/100M Stream Interface Synchronous Transmit Timing Diagram figure shows the timing diagram for the time periods. Time Period t1 t2 Parameter TXD[3:0], TXEN, TXER Setup to TXCLK Rise TXD[3:0], TXEN, TXER Hold after TXCLK Rise Conditions - - Min. 15 0 Typ. - - Max. Units - - ns ns 100M MII/100M Stream Interface Synchronous Transmit Timing Diagram TXCLK TXD[3:0] TXEN TXER t1 t2 10M MII: Synchronous Transmit Timing The table below lists the significant time periods for the 10M MII synchronous transmit timing. The time periods consist of timings of signals on the following pins: TXCLK TXD[3:0] TXEN TXER The 10M MII Synchronous Transmit Timing Diagram figure shows the timing diagram for the time periods. * * * * Time Period t1 t2 Parameter TXD[3:0], TXEN, TXER Setup to TXCLK Rise TXD[3:0], TXEN, TXER Hold after TXCLK Rise Conditions - - Min. 375 0 Typ. - - Max. Units - - ns ns IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 34 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 10M MII Synchronous Transmit Timing Diagram TXCLK TXD[3:0] TXEN TXER t1 t2 100M/MII Media Independent Interface: Synchronous Receive Timing The table below lists the significant time periods for the MII/100M Stream Interface synchronous receive timing. The time periods consist of timings of signals on the following pins: RXCLK RXD[3:0] RXDV RXER The MII Interface: Synchronous Receive Timing figure shows the timing diagram for the time periods. * * * * Time Period t1 t2 Parameter RXD[3:0], RXDV, and RXER Setup to RXCLK Rise RXD[3:0], RXDV, and RXER Hold after RXCLK Rise Min. 10.0 10.0 Typ. - - Max. Units - - ns ns MII Interface: Synchronous Receive Timing RXCLK RXD[3:0] RXDV RXER t1 t2 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 35 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER MII Management Interface Timing The table below lists the significant time periods for the MII Management Interface timing (which consists of timings of signals on the MDC and MDIO pins). The MII Management Interface Timing Diagram figure shows the timing diagram for the time periods. Time Period t1 t2 t3 t4 t5 t6 Parameter MDC Minimum High Time MDC Minimum Low Time MDC Period MDC Rise Time to MDIO Valid MDIO Setup Time to MDC MDIO Hold Time after MDC Conditions - - - - - - Min. 160 160 400 0 10 10 Typ. - - - - - Max. Units - - - 300 - - ns ns ns ns ns ns The ICS1894-40 is tested at 25 MHz (a 40ns period) with a 50pF load. Designs must account for all board loading of MDC. MII Management Interface Timing Diagram MDC t1 t3 MDIO (Output) t2 t4 MDC MDIO (Input) t5 t6 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 36 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 10M Media Independent Interface: Receive Latency The table below lists the significant time periods for the 10M MII timing. The time periods consist of timings of signals on the following pins: * TP_RX (that is, the MII TP_RXP and TP_RXN pins) * RXCLK * RXD The 10M MII Receive Latency Timing Diagram shows the timing diagram for the time periods. Time Period t1 Parameter First Bit of /5/ on TP_RX to /5/D/ on RXD Conditions Min. Typ. Max. 10M MII - 6.5 7 Units Bit times 10M MII Receive Latency Timing Diagram TP_RX RXCLK RXD 5 5 5 D t1 Manchester encoding is not shown. IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 37 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 10M Media Independent Interface: Transmit Latency The table below lists the significant time periods for the 10M MII transmit latency. The time periods consist of timings of signals on the following pins: * * * * TXEN TXCLK TXD (that is, TXD[3:0]) TP_TX (that is, TP_TXP and TP_TXN) The 10M MII Transmit Latency Timing Diagram shows the timing diagram for the time periods. Time Period t1 Parameter TXD Sampled to MDI Output of First Bit Conditions 10M MII Min. Typ. Max. - 1.2 2 Units Bit times 10M MII Transmit Latency Timing Diagram TXEN TXCLK TXD 5 5 5 TP_TX t1 Manchester encoding is not shown. IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 38 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 100M / MII Media Independent Interface: Transmit Latency The table below lists the significant time periods for the MII/100 Stream Interface transmit latency. The time periods consist of timings of signals on the following pins: * * * * TXEN TXCLK TXD (that is, TXD[3:0]) TP_TX (that is, TP_TXP and TP_TXN) The MII/100M Stream Interface Transmit Latency Timing Diagram shows the timing diagram for the time periods. Time Period t1 Parameter TXEN Sampled to MDI Output of First Bit of /J/ Conditions MII mode Min. Typ. - 2.8 Max. 3 Units Bit times The IEEE maximum is 18 bit times. MII/100M Stream Interface Transmit Latency Timing Diagram TXEN TXCLK TXD Preamble /J/ Preamble /K/ TP_TX t1 Shown unscrambled. IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 39 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) The table below lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: * TXEN * TXCLK * CRS The 100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) shows the timing diagram for the time periods. Time Period t1 t2 Parameter TXEN Sampled Asserted to CRS Assert TXEN De-Asserted to CRS De-Asserted Conditions Min. 0 0 Typ. 3 3 Max. 4 4 Units Bit times Bit times 100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) t2 TXEN TXCLK CRS t1 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 40 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) The table below lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: * TXEN * TXCLK * CRS The 10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) shows the timing diagram for the time periods. Time Period t1 t2 Parameter TXEN Asserted to CRS Assert TXEN De-Asserted to CRS De-Asserted Conditions Min. 0 0 Typ. - 2 Max. 2 4 Units Bit times Bit times 10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) t2 TXEN TXCLK CRS t1 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 41 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 100M MII Media Independent Interface: Receive Latency The table below lists the significant time periods for the 100M MII/100M Stream Interface receive latency. The time periods consist of timings of signals on the following pins: * TP_RX (that is, TP_RXP and TP_RXN) * RXCLK * RXD (that is, RXD[3:0]) The 100M MII/100M Stream Interface: Receive Latency Timing Diagram shows the timing diagram for the time periods. Time Period t1 Parameter First Bit of /J/ into TP_RX to /J/ on RXD Conditions 100M MII Min. Typ. - 16 Max. 17 Units Bit times 100M MII/100M Stream Interface: Receive Latency Timing Diagram TP_RX RXCLK RXD t1 Shown unscrambled. IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 42 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion The table below lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: * TP_RX (that is, TP_RXP and TP_RXN) * CRS * COL The 100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram shows the timing diagram for the time periods. Time Period t1 t2 t3 t4 Parameter First Bit of /J/ into TP_RX to CRS Assert First Bit of /J/ into TP_RX while Transmitting Data to COL Assert First Bit of /T/ into TP_RX to CRS De-Assert First Bit of /T/ Received into TP_RX to COL De-Assert Conditions - Half-Duplex Mode - Half-Duplex Mode Min. Typ. Max. 10 9 13 13 - - - - 14 13 18 18 Units Bit times Bit times Bit times Bit times The IEEE maximum is 20 bit times. The IEEE minimum is 13 bit times, and the maximum is 24 bit times. 100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram First bit First bit of /T/ TP_RX t3 t1 CRS COL t2 t4 Shown unscrambled. IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 43 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Reset: Power-On Reset The table below lists the significant time periods for the power-on reset. The time periods consist of timings of signals on the following pins: * VDD * TXCLK The Power-On Reset Timing Diagram shows the timing diagram for the time periods. Time Period t1 Parameter VDD 2.7 V to Reset Complete Conditions - Min. 40 Typ. 45 Max. Units 500 ms Power-On Reset Timing Diagram VDD 2.7 V t1 TXCLK Valid IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 44 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Reset: Hardware Reset and Power-Down The table below lists the significant time periods for the hardware reset and power-down reset. The time periods consist of timings of signals on the following pins: * REF_IN * RESETn * TXCLK The Hardware Reset and Power-Down Timing Diagram shows the timing diagram for the time periods. Time Period t1 t2 t3 Parameter RESETn Active to Device Isolation and Initialization Minimum RESETn Pulse Width RESETn Released to TXCLK Valid Conditions - - - Min. Typ. Max Units . - 200 - 35 60 - - 500 ns ns ms Hardware Reset and Power-Down Timing Diagram REF_IN RESETn t1 t2 t3 TXCLK Valid Power Consumption (AC only) IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 45 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 10Base-T: Heartbeat Timing (SQE) The table below lists the significant time periods for the 10Base-T heartbeat (that is, the Signal Quality Error). The time periods consist of timings of signals on the following pins: * TXEN * TXCLK * COL The 10Base-T Heartbeat (SQE) Timing Diagram shows the timing diagram for the time periods. Note: 1. For more information on 10Base-T SQE operations, see the section "10Base-T Operation: SQE Test". 2. In 10Base-T mode, one bit time = 100 ns. Time Period t1 t2 Parameter COL Heartbeat Assertion Delay from TXEN De-Assertion COL Heartbeat Assertion Duration Conditions 10Base-T Half Duplex 10Base-T Half Duplex Min. - - Typ. 850 1000 Max. Units 1500 1500 ns ns 10Base-T Heartbeat (SQE) Timing Diagram TXEN TXCLK COL t1 t2 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 46 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 10Base-T: Jabber Timing The table below lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of signals on the following pins: * TXEN * TP_TX (that is, TP_TXP and TP_TXN) * COL The 10Base-T Jabber Timing Diagram shows the timing diagram for the time periods. Note: For more information on 10Base-T jabber operations, see the section, "10Base-T Operation: Jabber". Time Period t1 t2 Parameter Jabber Activation Time Jabber De-Activation Time Conditions 10Base-T Half Duplex 10Base-T Half Duplex Min. 20 300 Typ. - - Max. Units 35 325 ms ms 10Base-T Jabber Timing Diagram TXEN t1 TP_TX t2 COL IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 47 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER 10Base-T: Normal Link Pulse Timing The table below lists the significant time periods for the 10Base-T Normal Link Pulse (which consists of timings of signals on the TP_TXP pins). The 10Base-T Normal Link Pulse Timing Diagram shows the timing diagram for the time periods. Time Period t1 t2 Parameter Normal Link Pulse Width Normal Link Pulse to Normal Link Pulse Period Conditions 10Base-T 10Base-T Min. - 8 Typ. Max. 100 20 - 25 Units ns ms 10Base-T Normal Link Pulse Timing Diagram TP_TXP t1 t2 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 48 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Auto-Negotiation Fast Link Pulse Timing The table below lists the significant time periods for the ICS1894-40 Auto-Negotiation Fast Link Pulse. The time periods consist of timings of signals on the following pins: * TP_TXP * TP_TXN The Auto-Negotiation Fast Link Pulse Timing Diagram shows the timing diagram for one pair of these differential signals, for example TP_TXP minus TP_TXN. Time Period t1 t2 t3 t4 t5 t6 Parameter Clock/Data Pulse Width Clock Pulse-to-Data Pulse Timing Clock Pulse-to-Clock Pulse Timing Fast Link Pulse Burst Width Fast Link Pulse Burst to Fast Link Pulse Burst Number of Clock/Data Pulses in a Burst Conditions - - - - - - Min. - 55 110 - 10 15 Typ. 90 60 125 5 15 20 Max. - 70 140 - 25 30 Units ns s s ms ms pulses Auto-Negotiation Fast Link Pulse Timing Diagram Clock Pulse Differential Twisted Pair Transmit Signal Data Pulse Clock Pulse t1 t2 t1 t3 FLP Burst Differential Twisted Pair Transmit Signal t4 FLP Burst t5 IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 49 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER RMII Timing Time Param tcyc t1 t2 tOD Clock Cycle Setup time Hold time Output delay Description Min. - 4 2 2.8 Typ. 20 Max. Units ns ns ns 10 ns IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 50 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Package Outline and Package Dimensions (40-pin 6mm x 6mm QFN) Package dimensions are kept current with JEDEC Publication No. 95 Seating Plane Index Area N 1 2 A1 A3 (ND-1)x e (Ref) L N 1 2 Sawn Singulation Top View A E2 (Ref) ND & NE Even e (Typ) If ND & NE 2 are Even (NE-1)x e (Ref) E E2 2 b D (Ref) ND & NE Odd e D2 2 D2 Thermal Base C 0.08 C Symbol Min Millimeters Max A A1 A3 b e N ND NE D x E BASIC D2 E2 L 0.80 1.00 0 0.05 0.25 Reference 0.18 0.30 0.50 BASIC 40 10 10 6.00 x 6.00 1.75 4.80 1.75 4.80 0.30 0.50 Ordering Information Part / Order Number 1894-40KLF 1894-40KLFT Marking TBD Shipping Packaging Tubes Tape and Reel Package 40-pin QFN 40-pin QFN Temperature 0 to +70 C 0 to +70 C "LF" after the two-letter package code are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDTTM / ICSTM 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 51 ICS1894-40 REV C 092909 ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA |
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