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ES51991
11,000 Counts ADC
Features
* Max. 11,000 counts resolution * Conversion rate selectable by MPU command: 1.6/s 128/s * Input signal full scale: 110mV * 50/60Hz line noise rejection selectable by MPU command * Low battery detection * 3-wire serial bus and EOC signal for MPU I/O port * -3V power operation with internal charge pumping circuit * MPU I/O power level selectable by external control pin * Zero calibration for eliminating offset error * On-chip buzzer driving and frequency selectable by MPU command * Support sleep mode by external CS(chipselect) pin
Description
ES51991 is an 11000-count dual-slope analogto-digital converter (ADC). The conversion rate and buzzer frequency can be selected or decided by an external microprocessor. The conversion rate can be varied from 1.6 time/sec to 128 times/sec under 4MHz/12MHz crystal oscillation clock. Besides, ES51991 also provides low battery detection, power-down mode, 50/60Hz line noise rejection selection, and I/O port level selection for flexible design.
Application
Clamp meter Thermometer Portable instrumentation
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ES51991
11,000 Counts ADC
Pin Assignment
SSOP-28L
VAGND V12 CAZ CINT CREF+ CREFREF+ REFBUF RAZ VIN+ VINNC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
V+ DGND LBAT IO_control CS C+ COSC1 OSC2 uP_VCC BUZOUT EOC SCLK SDATA
ES51991
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11,000 Counts ADC
Pin Description
Pin No
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Symbol
VAGND V12 CAZ CINT CREF+ CREFREF+ REFBUF RAZ VIN+ VINNC SDATA SCLK EOC BUZout uP_VCC OSC2 OSC1 CC+ CS I/O_control LBAT
Type
P G O I O I/O I/O I I O O
Description
27 28
DGND V+
Negative supply voltage. Connecting to 3V battery negative terminal. Analog ground Output of band-gap voltage reference. Typically -1.23V Auto-zero capacitor connection. Integrator output. Connect to integral capacitor Positive connection for reference capacitor. Negative connection for reference capacitor. Differential reference high voltage input. Differential reference low voltage input. Buffer output pin. Connect to integral resistor Buffer output pin in high-speed mode. Connect to high-speed integral resistor. I Analog differential high signal input. I Analog differential low signal input. Not connected I/O Serial data I/O pin. Nch open-drain output. I Serial clock input pin. O An indicator for ADC conversion ending. O Buzzer frequency output I MPU I/O port power level selection O Crystal oscillation connection I Crystal oscillation connection O Negative capacitor connection for on-chip DC-DC converter. O Positive capacitor connection for on-chip DC-DC converter. I Chip select input pin. Pull to Low to enter power down mode. I MPU I/O port ground level selection I Low battery configuration. If 3V battery is used, connect it to AGND. The default low-battery threshold voltage is -2.3V. If 9V or other battery voltage is used, the low battery annunciator is displayed when the voltage of this pin is less than V12 G Digital ground O/P Output of on-chip DC-DC converter.
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ES51991
11,000 Counts ADC
Function description 1. Dual Slope A/DFour Phases Timing
ES51991 is a dual-slope analog-to-digital converter (ADC). Figure 1 is a structure of dual-slope integrator. Its measurement cycle has two distinct phases: input signal integration (INT) phase and reference voltage integration (DINT) phase. In INT phase, the input signal is integrated for a fixed time period, then A/D enters DINT phase in which an opposite polarity constant reference voltage is integrated until the integrator output voltage becomes to zero. Since both the time period for input signal integration and the amount of reference voltage are fixed, thus the de-integration time is proportional to the input signal. Hence, we can define the mathematical equation about input signal, reference voltage integration (see Figure 1.): TINT 1 1 0 V IN (t )dt = Buf x C int x VREF x TDINT Buf x C int where, V IN (t ) = input signal V REF = reference voltage T INT = integration time (fixed) TDINT = de-integration time (proportional to V IN (t ) )
input signal reference voltage Cint Buf
RAZ BufX10 RAZ
input signal > 0
integrator output
integrator output
input signal < 0
different input fixed slope
integration time fixed slope
different input
integrator output
Fixed Variable integration deintegration time time
Fixed Variable integration deintegration time time
integration time
Figure 1. the structure of dual-slope integrator and its output waveform. If V IN (t ) is a constant, we can rewrite above equation: TDINT = T INT x V IN V REF
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11,000 Counts ADC
Besides the INT phase and DINT phase, ES51991 exploits auto zero (AZ) phase and zero integration (ZI) phase to achieve accurate measurement. In AZ phase, the system offset is stored. The offset error will be eliminated in DINT phase. Thus a higher accuracy could be obtained. In ZI phase, the internal status will be recovered quickly to that of zero input. Thus the succeeding measurements won't be disturbed by current measurement especially in case of overload. As mentioned above, the measurement cycle of ES51991 contains four phases: (1) auto zero phase (AZ) (2) input signal integration phase (INT) (3) reference voltage integration phase (DINT) (4) zero integration phase (ZI) The time ratios of these four phases, AZ, INT, DINT and ZI to the entire measurement cycle are 8.8%, 32%, 35.2% and 24% respectively. However the actual duration of each phase depends on conversion rate. An example is shown in the table below. A user can easily deduce other cases based on the table. Voltage: CR (times/sec) ZI (ms) AZ (ms) INT (ms) DINT (ms)
8
Voltge+PEAK: CR (times/sec)
30
11
40
44
Note: reference voltage = -100 mV. ZI (ms) AZ (ms) INT (ms) DINT (ms)
8
30
11
40
60
Note: reference voltage = -100 mV.
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ES51991
11,000 Counts ADC
2. Component Value Selection for ADC
For various application requirements on conversion rate and input full range, we suggest nominal values for external components of ADC in Figure 1 to obtain better performance. Under default condition with operating clock = 12 MHz: (1) conversion rate = 8 times/sec (2) reference voltage = -100 mV (3) input signal full scale = 110 mV (sensitivity = 10 uV) We suggest that Cint = 68 nF, Buf = 56 k If a user selects a different conversion rate rather than default, the integration capacitor Cint value must be changed according to the following rule for better performance: Cint x (conversion rate) = (68 nF) x (8 times/sec). A smaller Cint reduces the input full range. However a larger Cint might have weaker noise immunity than the suggested one. A user could enlarge the input full range by changing reference voltage (Vref) and the amount of integration resistor (Buf). For example, if Vref & Buf are enlarged as twice than the default values then the input full range becomes 220 mV. The input full range can be enlarged up to 1.1V (10 times than the default case). We list general rules in below which might be helpful in determining component values. Buf / (reference voltage) = 56 k / (-100 mV)
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11,000 Counts ADC
3. Special function
3.1 Zero and RZero Calibration
The Zero and RZero calibration are designed for removing the error rise from the propagation delay of internal component. In Zero or RZero calibration mode, ES51991 outputs a calibration value. The normal measurement value must minus the calibration value to cancel the error and obtain a more accurate value. The following block diagram performs the difference between basic structures of normal mode, Zero calibration and RZero Calibration. We suggest users to do zero-calibration in most applications.
IN +
V IN + (a ) N o rm a l m o d e V IN -
D u a l S lo p e ADC
IN -
IN +
V IN + (b ) Z ero m o d e V IN -
D u a l S lo p e ADC
IN -
IN +
V IN + (c ) R Z ero m o d e V IN -
D u a l S lo p e ADC
IN -
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11,000 Counts ADC
3.2 Buzzer Setup
When the bit BUZ of ID Byte is set to "H", the BUZOUT will output a square signal of MPU I/O swing level to drive a external buzzer. The buzzer frequency is determined by the bits B0/B1/B2 of STATUS Byte3. The configuration of buzzer frequency is listed at the following table. B2/B1/B0 111 110 101 100 011 010 001 000 BUZout (kHz) 4.00 3.33 3.08 2.67 2.22 2.00 1.33 1.00
3.3 Low Battery Detection
In a case of 3V battery power, the pin LBAT must be shorted to AGND. And the system will have low battery detection level about 2.3V. In another case of 9V or other battery power, the low battery detection happens when the voltage of LBAT is less than -1.23V below GND. And the bit LBAT of STATUS Byte3 will be set to high. A recommended application is shown as following:
Low battery test (9V)
9V BA TT 230K 0V 680K LBAT 0.1u AGND V-
The low battery detection level is around 7V
3.4 Sleep Mode
When the pin CS is connected to V- or GND (depended on I/O_control level), the ES51991 will enter sleep mode. In Sleep mode, the chip draws a little supply current. It could extend the battery life. To leave sleep mode or stay in normal mode, the pin CS must be connected to AGND or floating.
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11,000 Counts ADC
4. MPU I/O function definition
Write command: ID byte, Status byte1, Status byte2, Status byte3
START BIT B U Z0 A C K A C K A C K A C K STOP BIT
1
1
000
1
WRITE
Read command: ID byte, Status byte1, Status byte2, Status byte3, Data byte1, Data byte2
START BIT 1 1 000 B U 1Z1 A C K A C K A C K A C K
READ A C K
N A K STOP BIT
ID byte: 1 1 0 Status byte1: 0 0 C0 Status byte2: S60 RZERO ZERO Status byte3: 0 0 B0 Data byte1: D0 D1 D2 Data byte2: D8 D9 D10
0 C1 0 B1 D3 D11
0 C2 X B2 D4 D12
9
1 SIGN X LBAT D5 D13
BUZ SEL4M X X D6 X
R/W X X X D7 X
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11,000 Counts ADC
R/W: set to "H" is in read mode, set to "L" is in write mode C2/C1/C0/S60: Conversion rate selection, the default is [0000] S60 C2/C1/C0 L H 101 128/s 128/s 100 96/s 96/s 011 64/s 76.8/s 010 32/s 38.4/s ! 001 16/s 19.2/s* ! 000 8/s 9.6/s* 110 3.2/s!* 3.84/s* !* 111 1.6/s 1.92/s* Crystal: 12MHz !: 50Hz line noise rejection, *: 60Hz line noise rejection SEL4M: "H" is XTAL is 4MHz version, "L" is default 12MHz XTAL S60 C2/C1/C0 X 101 128/s 100 64/s 011 64/s 010 32/s 001 16/s! 000 8/s! 110 3.2/s!* 111 1.6/s!* Crystal :4MHz
SIGN: "H" is negative, "L" is positive LBAT: "H" is low battery detection flag active, the default is "L" RZERO: "H" is RZero calibration mode "ON", the default is "L" ZERO: "H" is Zero calibration mode "ON", the default is "L" B2/B1/B0: Buzzer frequency selection (independent with conversion rate) BUZ: "H" is buzzer turn on and "L" is turn off, the default is turn off.
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ES51991
11,000 Counts ADC
Buzzer ON
START BIT A C K STOP BIT
1
1
000
1
1
Buzzer OFF
START BIT A C K STOP BIT
1
1
000
1
0
D13-D0: ADC output data. Binary code format.
5. Power and I/O output level selection
Power Charge pump output for positive supply voltage(V+) External DC source to V+ is available by floating the charge pump capacitor I/O output level selectable uP_VCC provided by external DC source (the same high level with MPU) A control pin (I/O_control) selects the low level to -3V(V-) or 0V(DGND) I/O level uP_VCC I/O_control Example H L 3 H +3V 0V Ex.1 3 L +3V -3V Ex.2 0 L 0V -3V Ex.3
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ES51991
11,000 Counts ADC
ES5199X CC+ I/O_control SCLK SDATA EOC BUZOUT CS GND VV+ uP_VCC
+3V
+3V 0V
-3V
Ex.1
ES5199X CC+ V+ uP_VCC
+3V
I/O_control SCLK SDATA EOC BUZOUT CS GND V-
+3V -3V
-3V
Ex.2
ES5199X CC+ I/O_control SCLK SDATA EOC BUZOUT CS GND VV+ uP_VCC
0V -3V
-3V
Ex.3
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ES51991
11,000 Counts ADC
Absolute Maximum Ratings
Characteristic Supply Voltage (V- to AGND) Analog Input Voltage V+ AGND/DGND Digital Input Power Dissipation. Flat Package Operating Temperature Storage Temperature
Rating -3.6V V- -0.6 to V+ +0.6 V+ (AGND/DGND+0.5V) AGND/DGND (V- -0.5V) V- -0.6 to DGND +0.6 or V+ +0.6 500mW 0 to 70 -25 to 125
DC Electrical Characteristics
TA=25, VCM=0V, V- = -3V
Parameter Power supply Operating supply current Conversion rate = 8/sec. Voltage roll-over error Voltage nonlinearity Input Leakage Low battery flag voltage Internal pull-high to uP_Vcc current Internal pull-low to V- current Zero input reading Reference voltage and open circuit voltage for 110 measurement Reference voltage temperature coefficient VREF TCRF Symbol Test Condition VIDD Normal operation (XTAL=12MHz) ISS In sleep mode REV NLV Best case straight line V- to AGND CS (uP_Vcc=3V) CS(uP_Vcc=0V) I/O_control (V-=-3V) 10M input resistor zero cal. by MPU 100K resistor between VRH and AGND 100K resister Between VRH 0Note: 1.Full Scale
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ES51991
11,000 Counts ADC
AC Electrical Characteristics
Parameter SCLK clock frequency SCLK clock time "L" SLCK clock time "H" SDATA output delay time SDATA output hold time Start condition setup time Start condition hold time Data input setup time Data input hold time Stop condition setup time SCLK/SDATA rising time SCLK/SDATA falling time Bus release time EOC setup time in read mode EOC hold time in read mode Symbol fSCLK tLOW tHIGH tAA tDH tSU.STA tHD.STA tSU.DAT tHD.DAT tSU.STO tR tF tBUF tSU.EOC tHD.EOC Min. 4.7 4.0 0.1 100 4.7 4.0 200 0 4.7 4.7 0 0 Typ. Max. 100 3.5 1.0 0.3 Unit kHz us ns us ns us ns ns
I/O timing diagram
SCLK
SDATA IN
SDATA OUT
Read mode EOC timing diagram
EOC
t t
S U .E O C
H D .E O C
SD A TA
SCLK
S tart co n d itio n S to p co n d itio n
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ES51991
11,000 Counts ADC
Application example
7.5V ZD 5.6V ZD + 10uF *4 0.1uF + 0.1uF 470 nF
VAGND V12 1 2 3 4 5 28 27 26 25 24 V+ DGND LBAT IO_control CS C+ COSC1 OSC2 uP_VCC BUZOUT EOC SCLK SDATA
*1 MPU power *2 V- or DGND 10uF
VDD
MPU
VSS I/O port
**68nF 91k 220 nF
CAZ CINT CREF+ CREFREF+ REFBUF RAZ
12M or 4MHz 470nF ***R *3
ES51991
6 7 8 9 10 11 12 13 14
23 22 21 20 19 18 17 16 15
10k VR **56k
VIN+ VIN-
15k
5.6V ZD 1 uF 100k
**10nF
V-
Input
Note: Zener diodes in above circuit are used for IC protection, so MUST be soldered on PCB first. *1*2*3*4: Depend on power design ** Depends on conversion rates setting: V-=-3.0V
(a)Conversion rate 128/s 96/s 76.8/s 64/s 38.4/s 32/s 19.2/s (b)CINT(uF) 0.01 0.01 0.01 0.022 0.022 0.033 0.033 (c)RBUF(k) 22 30 39 22 36 27 47 (a)Conversion rate 16/s 9.6/s 8/s 3.84/s 3.2/s 1.92/s 1.6/s (b)CINT(uF) 0.068 0.047 0.068 0.1 0.1 0.22 0.22 (c)RBUF(k) 27 68 56 82 91 68 91
*** R=10~22M resistor is optional
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11,000 Counts ADC
Product Outline: SSOP-28L
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