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Silicon Monolithic Integrated Circuit 6 Channel Switching Regulator control system BD9831AMWV Fig. 1 (Plastic Mold) Fig. 2 Step Down 5CH, Step Up 1CH total 6CH included. FET 4ch (CH1~CH4) for Synchronous Switching Regulator Short Circuit Protection (SCP) Under Voltage Lockout Function (UVLO) Thermal Shut Down Function (TSD) Independent ON/OFF Function Each Channel(Stand_by Current Is Under 5uA) UQFN056V7070 Package Absolute Maximum RatingsTa=25
Parameter Power Supply Voltage Input Voltage BOOT-Lx Voltage Power Dissipation Operating Temperature Storage Temperature Junction Temperature Symbol VCC,PVCC16 BOOT14 Lx14,OUT5,6 BOOT14 Pd Topr Tstg Tjmax Limits 12 17.5 12 5.5 420(*1) 930(*2) -30+85 -55+125 125 Units V V V V mW mW
STURUCTURE Type PRODUCUT SERIES THYSICAL DIMENSIONS BLOCK DIAGRAM FEATURES
(*1) Without external heat sink, the power dissipation degrades by 4.2mW/ above 25. (*2)Power dissipation degrades by 9.3mW/ above 25, when mounted on a PCB (74.2mmx74.2mmx1.6mm).
Recommended Operating ConditionsTa=25
Parameter Power Supply Voltage BOOT-Lx Voltage CH14 H NMOS Drain Current CH14 L NMOS Drain Current Frequency Stability (*4) VREGA - GND Capacitor VCC - VREGD Capacitor BOOT - Lx Capacitor Symbol VCC,PVCC156 BOOT14 BOOT14 Idhnl Idlnl fosc CVREGA CVREGD CBOOT Min 4 3.5 3.5 300 0.47 0.47 0.047 Spec. Typ 7 500 1.0 1.0 0.1 Max 11 16 5.0 1.5(*3) 1.5(*3) 2000 2.2 2.2 0.22 Units V V V A A KHz uF uF uF
(*3) FET Drain Current Max value.Set the current value within Power dissipation in the application. (*4) Max 1MHz for Ch1 ~ Ch4.
Status of this document The Japanese language version of this document shall be the official specification. Any translation of this document shall be for reference only.
REV.B
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Electrical Characteristics Ta=25VCC=7Vfosc=500kHz with no designation
Parameter Whole Device Standby Current Ciucuit Current Reference Voltage Output Voltage Line regulation Load Reguration Output current at VREGA PIN shorted Bias Voltage Output Voltage Oscillator Oscillator Frequency CH1-CH6 Oscillator Frequency cofficient Current Mode Circuit Minimum OFF time of H Nch (CH1) Minimum OFF time of H Nch (CH2) Minimum OFF time of H Nch (CH3) Minimum OFF time of H Nch (CH4) SEL control voltage PWM Comparatpr 0 Duty threshold (CH5,6) 100Duty threshold (CH5) Max Duty cycle CH6 ERRORAMP1(CH1) Threshold Voltage Output Voltage L Output Voltage H Output Sink Current Output Source Current Input Bias Current Voltage Gain Frequency Bandwidth ERRORAMP2(CH26) Threshold Voltage Output Voltage L Output Voltage H Output Sink Current Output Source Current Input Bias Current Voltage Gain Frequency Bandwidth Driver Lx Pull-down resistor (CH14) Simultaneous off time setting (CH14) H Nch resistor(CH1) L Nch resistor(CH1) H Nch resistor(CH2) L Nch resistor(CH2) H Nch resistor(CH3) L Nch resistor(CH3) H Nch resistor(CH4) L Nch resistor(CH4) Output ON resistor(CH5) Output ON resistor(CH6) Control Block CTL vol ON OFF Symbol Ist Icc VREGA DVli DVlo Ios VREGD fosc Df Toffmin1 Toffmin2 Toffmin3 Toffmin4 VSELH VSELL Vt0 Vt100 Dmax6 VETH VOL VOH ISINK IBIAS AV BW Min. 2.475 -30 4.90 450 2 -0.3 1.00 81 0.790 2.2 1.8 -150 60 1 0.990 2.2 1.8 -150 60 1 300 2 -0.3 250 Limits Typ. 0.1 6.0 2.500 5.00 500 0 1.10 1.60 90 0.800 0.03 2.4 3.6 -100 -50 80 4 1.000 0.03 2.4 3.6 -100 -50 80 4 500 25 25 0.38 0.18 0.28 0.28 0.27 0.22 0.28 0.28 9 9 9 9 400 Max. 5 9.0 2.525 10 10 -5 5.10 550 2 100 100 100 100 VCC 0.8 1.70 99 0.810 0.2 -50 1.010 0.2 -50 700 50 50 0.65 0.31 0.48 0.48 0.46 0.37 0.48 0.48 16 16 16 16 VCC 0.8 700 Units uA mA V mV mV mA V kHz nsec nsec nsec nsec V V V V V V V mA uA nA dB MHz V V V mA uA nA dB MHz nsec nsec V V k mV uA V V uA mV V uA V mV V V SOFT16=0.1V FB16 Voltage SCP=0.1V INV=0.9V INV=0.7V INV=0.9V, FB=1.25V INV=0.7V, FB=1.25V INV=0V open loop gain Condition
FB=0V VREGA=-1mA VCC=4V10V, VREGA=-1mA VREGA=-1mA-5mA VREGA=0V VREGD=-10mA RT=10k, CT=220pF, SEL="L" VCC=4V10V
(fosc'=fosc/2)(CH14)
ISOURCE
ISOURCE
VETH VOL VOH ISINK IBIAS AV BW
INV=1.1V INV=0.9V INV=1.1V, FB=1.25V INV=0.9V, FB=1.25V INV=0V open loop gain CTL=0V Lx1=-50mA Lx1=50mA Lx2=-50mA Lx2=50mA Lx3=-50mA Lx3=50mA Lx4=-50mA Lx4=50mA IOUT5=-15mA IOUT5=15mA IOUT6=-15mA IOUT6=15mA
RLx TUPPER TLOWER RonH1 RonL1 RonH2 RonL2 RonH3 RonL3 RonH4 RonL4 RonH5 RonL5 RonH6 RonL6 VCTLH VCTLL RCTL
CTL16 Pull-Down resistor Soft Start block Standby Voltage Vstsc 10 100 Input Charge Current ISOFT -1.4 -1.0 -0.6 Short Circuit Protection (SCP) Timer Timer Start Voltage Vtime 2.1 2.2 2.3 Threshold Voltage Vtsc 0.9 1.0 1.1 Source Current Iscp -1.4 -1.0 -0.6 Standby Voltage Vstsc 10 100 Short Circuit Detective Comparator Threshold Voltage VTH 0.95 1.0 1.05 Input Bias Current IBIAS -15 -10 -5 Under Voltage Lockout (UVLO) Threshold Voltage1 Vstd1 3.3 3.4 3.5 Hysteresis Voltage 25 100 200 Vst Threshold Voltage2 Vstd2 1.8 2.0 2.2 Threshold Voltage3 Vstd3 2.8 3.0 3.2 This product is not designed for normal operation within a radioactive environment.
SCP1=0V VCC voltage VCC voltage VREGA voltage VREGD voltage
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Package
A
Lot No.
Fig. 1 Block Diagram
BOOT1
ERRORAMP1
Pin Description
Pin No.
Pin Name SEL SOFT1 INV1 FB1 SOFT2 INV2 FB2 SOFT3 INV3 FB3 SOFT4 INV4 FB4 SOFT5 INV5 FB5 SOFT6 INV6 FB6 SCP1 SCP OUT6 PGND56 OUT5 PVCC56 CTL6 CTL5 CTL4
Pin Descriptions CH1CH4 Oscillator Frequency Cotrol Pin CH1 Soft Start Delay time Setting Pin with External Capacitor CH1Error Amplifier Negative Input Pin CH1 Error Amplifier Output Pin CH2 Soft Start Delay time Setting Pin with External Capacitor CH2 Error Amplifier Negative Input Pin CH2 Error Amplifier Output Pin CH3 Soft Start Delay time Setting Pin with External Capacitor CH3 Error Amplifier Negative Input Pin CH3 Error Amplifier Output Pin CH4 Soft Start Delay time Setting Pin with External Capacitor CH4 Error Amplifier Negative Input Pin CH4 Error Amplifier Output Pin CH5 Soft Start Delay time Setting Pin with External Capacitor CH5 Error Amplifier Negative Input Pin CH5 Error Amplifier Output Pin CH6 Soft Start Delay time Setting Pin with External Capacitor CH6 Error Amplifier Negative Input Pin CH6 Error Amplifier Output Pin Short Detective Comparator Negative Input Pin Short Circuit Protection Delay time Setting Pin with External Capacitor CH6 NchFET Driver Output Pin Ground Pin for CH56 Driver Output Pin for CH5 PchFET Driver Input Supply Voltage Pin for CH56 Driver CH6 ON/OFF Control Pin CH5 ON/OFF Control Pin CH4 ON/OFF Control Pin
Pin No.
Pin Name BOOT4 PVCC4 Lx4 PGND34 PGND34 Lx3 Lx3 PVCC3 BOOT3 BOOT2 PVCC2 Lx2 CTL3 CTL2 CTL1 PGND12 PGND12 Lx1 Lx1 PVCC1 BOOT1 VREGD VCC VREGA GND SLOPE RT CT
Pin Descriptions Input Supply Voltage Pin for CH4 Output Input Supply Voltage Pin for CH4 Output Pin for Connecting to Inductor Ground Pin for CH34 Output Ground Pin for CH34 Output Pin for Connecting to Inductor Pin for Connecting to Inductor Input Supply Voltage Pin for CH3 Output Input Supply Voltage Pin for CH3 Output Input Supply Voltage Pin for CH2 Output Input Supply Voltage Pin for CH2 Output Pin for Connecting to Inductor CH3 ON/OFF Control Pin CH2 ON/OFF Control Pin CH1 ON/OFF Control Pin Ground Pin for CH12 Output Ground Pin for CH12 Output Pin for Connecting to Inductor Pin for Connecting to Inductor Input Supply Voltage Pin for CH1Output Input Supply Voltage Pin for CH1Output Bias Output Voltage Pin Input Supply Voltage Pin Reference Output Voltage Pin Ground Pin Slope Setting Pin with external Resistor Oscillator Frequency Adjustment Pin with external Resistor Oscillator Frequency Adjustment Pin with external Capacitor
PVCC1
CH1 Step Down DC/DC (Current mode)
INV1 SOFT1 FB1
SS TIMER

1 2
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
Lx1(2pin) PGND12(2pin)
3
BOOT2
4
INV2 SOFT2 FB2
SS TIMER ERRORAMP2
PVCC2
CH2 Step Down DC/DC (Current mode)
Lx2
5 6 7
BOOT3
ERRORAMP3 SS TIMER
PVCC3
CH3 Step Down DC/DC (Current mode)
8 9 10 11 12 13 14 15
INV3 SOFT3 FB3
Lx3(2pin) PGND34(2pin)
BOOT4
ERRORAMP4
PVCC4
CH4 Step Down DC/DC (Current mode)
INV4 SOFT4 FB4
SS TIMER

Lx4
ERRORAMP5
16
PVCC56
CH5 Step Down DC/DC (Voltage mode)
INV5 SOFT5 FB5
SS TIMER

OUT5 PGND56
17 18 19
INV6 SOFT6 FB6
SS TIMER
ERRORAMP6
20
CH6 Step Up DC/DC (Voltage mode)
OUT6
21 22 23
PROTECTION
SCP1

2.2V
24 25 26 27
SCP
SCP TIMER
CTL1 CTL2 CTL3 CTL4 CTL5 CTL6
VREGA UVLO SHUT DOWN OSC VREGD
VCC
28
GND
RT
CT SLOPE
SEL
VREGA VREGD
Fig. 2
REV.B
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Operation Notes
.) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC deterioration or damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. .) GND potential Ensure a minimum GND pin potential in all operating conditions. In addition, ensure that no pins other than the GND pin carry a voltage lower than or equal to the GND pin, including during actual transient phenomena. .) Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. .) Inter-pin shorts and mounting errors Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pin caused by the presence of a foreign object may result in damage to the IC. .) Operation in a strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. .) Common impedance Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize ripple as much as possible (by making wiring as short and thick as possible or rejecting ripple by incorporating inductance and capacitance). .) Voltage of CTL pin The threshold voltages of CTL pin are 0.8V and 2.0V. STB state is set below 0.8V while action state is set beyond 2.0V. The region between 0.8V and 2.0V is not recommended and may cause improper operation. The rise and fall time must be under 10msec. In case to put capacitor to STB pin, it is recommended to use under 0.01F. .) Thermal shutdown circuit (TSD circuit) This IC incorporates a built-in thermal shutdown circuit (TSD circuit). The TSD circuit is designed only to shut the IC off to prevent runaway thermal operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of the thermal shutdown circuit is assumed. .) Applications with modes that reverse VCC and pin potentials may cause damage to internal IC circuits. For example, such damage might occur when VCC is shorted with the GND pin while an external capacitor is charged. diode for preventing back current flow in series with VCC or bypass diodes between VCC and each pin. 10.) Relationship between PVCC - VCC Because diode was connecting between PVCC (Anode) - VCC (Cathode) for prevent electrostatic breakdown, it must be set PVCC - VCC < 0.3V voltage relationship. 11.) Rush current at the time of power supply injection. An IC which has plural power supplies, or CMOS IC could have momentaly rush current at the time of power supply injection. Because there exists inside logic uncertainty state. Please take care about power supply coupling capacity and width of power Supply and GND pattern wiring. 12.) Please use it so that VCC and PVCC terminal should not exceed the absolute maximum ratings. Ringing might be caused by L element of the pattern according to the position of the input capacitor, and ratings be exceeded. Please will assume the example of the reference ,the distance of IC and capacitor, use it by 5.0mm or less when thickness of print pattern are 35um, pattern width are 1.0mm. 13.) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 14.) IC pin input This monolithic IC contains P+ isolation and PCB layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when a resistor and transistor are connected to pins as shown in following chart, the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN). Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other adjacent elements to operate as a parasitic NPN transistor. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (PCB) voltage to input and output pins.
Resistance (PinA) (PinB) Transistor (NPN)

It is recommended to insert a
(PinA) Parasitic diode

(PinB)

P substrate Parasitic diode
P substrate
Parasitic elementals
Other adiacent components
Parasitic diode
REV.B
Notice
Notes
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