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Rev PrB, 05-Mar-08 Advanced Product InformationAll Information Subject to Change
ACT5830
Twelve Channel PMU for Mobile Phones FEATURES
* Multiple Patents Pending * 350mA, PWM Step-Down DC/DC Converter * Eight I2C-Programmable, Low Noise LDOs - Three Optimized for RF Section Power - Five Optimized for BB Section Power * Li+ Battery Charger with Integrated MOSFET - Charger Current Monitor Output (VICHG) - Charger ON/OFF Control Pin * Two N-channel Open Drain Switches * Minimal External Components * I2CTM Serial Interface - Configurable Operating Modes * AC-OK and RESET Outputs * 5x5mm, Thin-QFN (TQFN55-40) Package - Only 0.75mm Height - RoHS Compliant
GENERAL DESCRIPTION
The patent-pending ACT5830 is a complete, integrated power management solution that is ideal for mid-high and mobile phones. This device integrates a linear Li+ battery charger with an internal power MOSFET, a high efficiency 350mA DC/DC converter, eight low dropout linear regulators, a reset output, and two N-Channel open drain switches, and an I2C Serial Interface to achieve flexibility for programming LDO outputs and individual on/off control. The charger is a complete, thermally-regulated, stand-alone single-cell linear Li+ battery charger that incorporates an internal power MOSFET for constant-current/constant-voltage control. The charger includes a variety of value-added features, and it is programmable via the I2C-Interface to control charging current, termination voltage, along with safety features and operation modes. The ACT5830 is available in a compact 5mm x 5mm 40-pin Thin-QFN package that is just 0.75mm thin.
APPLICATIONS
* GSM or CDMA Mobile Phones
SYSTEM BLOCK DIAGRAM
CHG_IN nENCHG VICHG ACOK SCL SDA PWR_HOLD nON HF_PWR PWR_ON TX_EN RX_EN TCXO_EN nRST OD1 OD2 Open-Drain Drivers System Control Single Cell Li+ Battery Charger
REG
Step-Down DC/DC Low-Noise LDOs LDO1 LDO2 LDO3 LDO4 LDO5 LDO6 LDO7 LDO8
Single Cell Li+ Battery Charger 1.1V to 4.4V Up to 350mA
1.4V to 3.7V Up to 300mA 1.4V to 3.7V Up to 300mA 1.4V to 3.7V Up to 100mA 1.4V to 3.7V Up to 100mA 1.4V to 3.7V Up to 150mA 1.4V to 3.7V Up to 150mA 0.645V to 3.7V Up to 250mA 1.4V to 3.7V Up to 250mA
Pb-free
ACT5830
Active
PMU
TM
ODI1
ODI2
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ACT5830
TABLE OF CONTENTS
GENERAL INFORMATION ...................................................................................... P. 01
Functional Block Diagram ................................................................................................. p. 03 Ordering Information ......................................................................................................... p. 04 Pin Configuration .............................................................................................................. p. 04 Pin Descriptions ................................................................................................................ p. 05 Absolute Maximum Ratings .............................................................................................. p. 07
Rev PrB, 05-Mar-08
SYSTEM MANAGEMENT ........................................................................................ P. 08
Electrical Characteristics................................................................................................... p. 08 I2C Interface Electrical Characteristics .............................................................................. p. 09 System Management Register Descriptions ..................................................................... p. 10 Functional Descriptions..................................................................................................... p. 11
STEP-DOWN DC/DC CONVERTER ....................................................................... P. 13
Electrical Characteristics .................................................................................................. p. 13 Register Descriptions ........................................................................................................ p. 14 Typical Performance Characteristics ............................................................................... p. 16 Functional Description ...................................................................................................... p. 17
LOW-DROPOUT LINEAR REGULATORS .............................................................. P. 19
Register Descriptions ........................................................................................................ p. 19 Typical Performance Characteristics ................................................................................ p. 23 Functional Description ...................................................................................................... p. 24 LDO1................................................................................................................................. p. 25 LDO2................................................................................................................................. p. 26 LDO3................................................................................................................................. p. 27 LDO4................................................................................................................................. p. 28 LDO5................................................................................................................................. p. 29 LDO6................................................................................................................................. p. 30 LDO7................................................................................................................................. p. 31 LDO8................................................................................................................................. p. 32
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) ................................................. P. 33
Electrical Characteristics ................................................................................................... p. 33 Li+ Battery Charger Register Descriptions ........................................................................ p. 35 Typical Performance Characteristics ................................................................................ p. 37 Functional Description....................................................................................................... p. 38
PACKAGE INFORMATION ...................................................................................... P. 41
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ACT5830
FUNCTIONAL BLOCK DIAGRAM
Active-Semi
ACT5830
BAT Li+ Battery +
CURRENT SENSE VOLTAGE SENSE PRECONDITION
Rev PrB, 05-Mar-08
BODY AND VSYS CONTROL
AC Adaptor 4.3V to 6V or USB
CHG_IN
VINUVLO
4.0V nENCHG nACOK Charge Control
2.9V BATID
THERMAL REGULATION
VICHG OUT1 nRST
110C
VP To Battery
REG Step-Down DC/DC
SW VBUCK VBUCK GP OUT1
Reset
REF PWR_HOLD nON HF_PWR PWR_ON SDA SCL IN1 IN2 TCXO_EN BAT OUT1 RX_EN TX_EN
Voltage Reference
LDO1
OUT1
System Control
LDO2
OUT2
OUT2
LDO3 To LDOs To LDOs LDO5
OUT3
OUT3
LDO4
OUT4
OUT4
OUT5
OUT5
LDO6 ODI1 OD1 ODI2 OD2 Open-Drain #2 LDO8 Open-Drain #1 LDO7
OUT6
OUT6
OUT7
OUT7
OUT8
OUT8
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ACT5830
ORDERING INFORMATION
PART NUMBER VBUCK VLDO1 VLDO2 VLDO3 VLDO4 VLDO5 VLDO6 VLDO7 VLDO8 ICHARGER PACKAGE PINS ACT5830QJCGN-T 1.2V 3.0V 1.8V 3.0V 3.0V 3.0V 3.0V 1.3V 3.0V ACT5830QJCES-T 1.2V 1.8V 2.8V 2.8V 3.0V 3.3V 1.8V 3.0V 2.8V 0.45A TQFN55-40 40 0.45A TQFN55-40 40 TEMPERATURE RANGE -40C to +85C -40C to +85C
Rev PrB, 05-Mar-08
: Output voltage options detailed in this table represent standard voltage options, and are available for samples or production orders. Additional output voltage options, as detailed in the Output Voltage Codes table, are available for production subject to minimum order quantities. Contact Active-Semi for more information regarding semi-custom output voltage combinations. : All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
PIN CONFIGURATION
nENCHG
nACOK
VICHG
BATID
SW
SW
NC
NC
GP
VP
CHG_IN BAT REF nRST IN2 OUT4 OUT6 OUT8 OUT2 TX_EN
VBUCK HF_PWR G nON IN1
ACT5830
OUT3 OUT5 OUT7 OUT1 RX_EN
TCXO_EN
5x5mm QFN (TQFN55-40)
SDA
SCL
ODI1
OD1
OD2
ODI2
PWR_ON
PWR_HOLD
NC
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ACT5830
PIN DESCRIPTIONS
PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Rev PrB, 05-Mar-08
NAME
CHG_IN BAT REF nRST IN2 OUT4 OUT6 OUT8 OUT2 TX_EN TCXO_EN SDA SCL ODI1 OD1 OD2 ODI2 PWR_ON
DESCRIPTION
Battery Charge Supply Input. Connect a 1F ceramic capacitor from CHG_IN to G. Battery Charger Output. Connect this pin directly to the battery anode (+ terminal), and to IN1 and IN2 pins. Bypass with 10F ceramic capacitor to G. Reference Noise Bypass. Connect a 0.01F ceramic capacitor from REF to G. This pin is discharged to G in shutdown. Active Low Reset Output. nRST asserts low for the reset timeout period of 65ms whenever the ACT5830 is first enabled. This output is internally connected to OUT1 via a 15k pull-up resistor. Input supply to LDO2, LDO4, LDO6, and LDO8. Connect to BAT and IN1. LDO4 Output. Capable of delivering up to 100mA of output current. Output is discharged to ground with 1k when disabled. LDO6 Output. Capable of delivering up to 150mA of output current. Output is discharged to ground with 1k when disabled. LDO8 Output. Capable of delivering up to 250mA of output current. Output has high impedance when disabled. LDO2 Output. Capable of delivering up to 300mA of output current. Output has high impedance when disabled. LDO6 Independent On/Off Control. Drive to a logic high for normal operation, and to a logic low to disable. LDO4 Independent On/Off Control. Drive to a logic high for normal operation, and to a logic low to disable. Data Input for I2C Serial Interface. Data is read on the rising edge of the clock. Clock Input for I2C Serial Interface. Data is read on the rising edge of the clock. Digital Control for Open Drain N-channel Switch 1. Drive to a logic high to turn on the switch. Drive to a logic low to turn off the switch. N-channel Open-Drain Output 1. State of output controlled by ODI1. N-channel Open-Drain Output 2. State of output controlled by ODI2. Digital Control for Open Drain N-channel Switch 2. Drive to a logic high to turn on the switch. Drive to a logic low to turn off the switch. Push Button On/Off Input. Connect a push-button between this pin and BAT. There is an internal 200k pull down resistor to G. See the System Startup & Shutdown section for more information.
Power Hold Input for REG and LDO1. Drive PWR_HOLD to a logic high to complete the startup PWR_HOLD sequence. Drive the pin to a logic low to disable REG and LDO1. See the System Startup & Shutdown section for more information. NC RX_EN No Connect. Not internally connected. LDO5 Independent On/Off Control. Drive to a logic high for normal operation, and to a logic low to disable.
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ACT5830
PIN DESCRIPTIONS CONT'D
PIN
22 23 24 25 26 27 28 29 30 31 32 33, 34 35 36 37 38 39 40
Rev PrB, 05-Mar-08
NAME
OUT1 OUT7 OUT5 OUT3 IN1 nON G
DESCRIPTION
LDO1 Output. Capable of delivering up to 300mA of output current. Output has high impedance when disabled. LDO7 Output. Capable of delivering up to 250mA of output current. Output has high impedance when disabled. LDO5 Output. Capable of delivering up to 150mA of output current. Output is discharged to ground with 1k when disabled. LDO3 Output. Capable of delivering up to 100mA of output current. Output has high impedance when disabled. Input Supply to LDO1, LDO3, LDO5, and LDO7. Connect to BAT and IN2. Push Button Active Low Open Drain Output. When PWR_ON is low, nON is open drain. When PWR_ON is high or when in shutdown, nON is asserted low. This output is internally connected to OUT1 via a 15k pull-up resistor. Ground. Connect G and GP together at a single point place as close to the IC as possible.
Hands Free Input. A high level indicates availability of hands free input. This pin is internally HF_PWR pulled down to G via a 200k resistor. Connect to a 0.1F capacitor to G to achieve TBDkV (typ) ESD protection. VBUCK NC VP SW GP NC nACOK nENCHG BATID VICHG Output Feedback Sense for REG. Connect this pin directly to the output node to connect the internal feedback network to the output voltage. No Connect. Not internally connected. Power Input for REG. Connect to BAT, IN1, and IN2. Bypass to GP with a high quality ceramic capacitor placed as close as possible to the IC. Switching Node Output for REG. Connect this pin to the switching end of the inductor. Power Ground for REG. Connect G and GP together at a single point place as close to the IC as possible. No Connect. Not internally connected. CHG_IN Active Low Status Output. nACOK is asserted low when VCHG_IN > 4.0V. Charge Enable Active Low Input. Drive low or leave floating to enable the charger. Drive high to disable the charger. This pin has an internal 200k pull-down resistor. Battery ID pin to detect the presence of the battery. When the battery is present, the voltage at this pin is lower than 2V, otherwise, it is higher than 2V. Charge Current Monitor. The voltage at this pin is proportional to the charger current, with a gain of 2.47mV/mA. This output becomes high impedance in shutdown.
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ACT5830
ABSOLUTE MAXIMUM RATINGS
PARAMETER
CHG_IN to G t < 1ms and duty cycle <1% Steady State IN1, IN2, BAT, BATID, VICHG, SCL, SDA, PWR_HOLD, nRST, PWR_ON, nON, nACOK, nENCHG, TCXO_EN, RX_EN, TX_EN, ODIx, ODx to G VP, SW, VREG to GP REF, HF_PWR to G OUT1, OUT3, OUT5, OUT7 to G OUT2, OUT4, OUT6, OUT8 to G GP to G Junction to Ambient Thermal Resistance (JA) RMS Power Dissipation (TA = 70C) Operating Junction Temperature (TJ) Operating Temperature Range (TA) Store Temperature Lead Temperature (Soldering, 10 sec)
Rev PrB, 05-Mar-08
VALUE
-0.3 to +7 -0.3 to +6 -0.3 to +6 -0.3 to +6 -0.3 to VBAT + 0.3 -0.3 to VIN1 + 0.3 -0.3 to VIN2 + 0.3 -0.3 to +0.3 30 2.7 -40 to 150 -40 to 85 -55 to 150 300
UNIT
V V V V
V V V C/W W C C C C
: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect device reliability. : Derate 33mW/C above TA = 70C.
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ACT5830
SYSTEM MANAGEMENT ELECTRICAL CHARACTERISTICS
(VBAT = VIN1 = VIN2 = 3.6V, TA = 25C, unless otherwise specified.)
Rev PrB, 05-Mar-08
PARAMETER
BAT Operating Voltage Range BAT UVLO Threshold BAT UVLO Hysteresis BAT UVLO Delay nRST Delay No Load BAT Supply Current REF Output Voltage Reference PSRR ODx Output On Resistance ODx Output Leakage Current Logic High Input Voltage Logic Low Input Voltage Logic Low Output Voltage Logic Leakage Current Thermal Shutdown Temperature Thermal Shutdown Hysteresis
TEST CONDITIONS
BAT Voltage Rising BAT Voltage Falling BAT Rising BAT Falling
MIN
2.6 2.2
TYP
2.35 80 0.1 5 65
MAX UNIT
5.5 2.5 V V mV ms ms 0.5 0.75 1.26 mA mA V dB 10 A V 0.4 V V A C C
REG, LDO1, LDO2 and LDO3 Enabled with No Load and CHGR Disabled REG, All LDOs Enabled and CHGR Disabled. 1.24 CREF = 0.01F 100mA Sink Current VODx = VBAT 1.4
0.26 0.45 1.25 75 4
nON, nRST, ISINK = 5mA VnON = VnRST = VCHG_IN = 4.2V Temperature rising Temperature falling 160 20
0.3 1
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ACT5830
SYSTEM MANAGEMENT I2C INTERFACE ELECTRICAL CHARACTERISTICS
PARAMETER
SCL, SDA Low Input Voltage SCL, SDA High Input Voltage SCL, SDA Leakage Current SDA Low Output Voltage SCL Clock Period, tSCL SDA Data In Setup Time to SCL High, tSU SDA Data Out Hold Time after SCL Low, tHD SDA Data Low Setup Time to SCL Low, tST SDA Data High Hold Time after Clock High, tSP Start Condition Stop Condition VCHG_IN = 4.2V IOL = 5mA fSCL clock freq = 400kHz 2.5 100 300 100 100 1.4 1 0.3
Rev PrB, 05-Mar-08
TEST CONDITIONS
MIN
TYP
MAX
0.4
UNIT
V V A V s ns ns ns ns
Figure 1: I2C Serial Bus Timing
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ACT5830
SYSTEM MANAGEMENT SYSTEM MANAGEMENT REGISTER DESCRIPTIONS
Table 1: Global Register Map ADDRESS HEX
08h 09h 0Ah 0Bh 0Ch 0Dh 07h 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h
Rev PrB, 05-Mar-08
OUTPUT
CHGR CHGR CHGR CHGR LDO3 LDO5 LDO7 LDO7 LDO1 LDO4 LDO6 LDO8 LDO2 REG REG REG REG
KEY:
DATA (DEFAULT VALUES) A2
0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1
A7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A6
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A5
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A4
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A3
1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0
A1
0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1
A0
0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1
D7
0 0 R R 0 1 R 0 0 1 1 0 0 R R R R
D6
0 0 R R R R V R R R R R R V R R R
D5
0 R R R 1 0 V 1 1 0 0 1 1 V R R R
D4
0 R R R V V V R V V V V V V R R R
D3
R R R R V V V R V V V V V V R R R
D2
V R R R V V V R V V V V V V R R R
D1
V R R R V V V R V V V V V V R R R
D0
V R R 0 V V V R V V V V V V 0 R 1
R: Read-Only bit. No Default Assigned. V: Default Values Depend on Voltage Option. Default Values May Vary. Note: Addresses other than those specified in Table 1 may be used for factory settings. Do not access any registers other than those specified in Table 1.
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ACT5830
SYSTEM MANAGEMENT FUNCTIONAL DESCRIPTIONS
The ACT5830 offers a wide array of system management functions that allow it to be configured for optimal performance in a wide range of applications. Once the power-up routine is completed, the remaining LDOs can be enabled/disabled via either the I2C interface or the TCXO_EN (LDO4), RX_EN (LDO5), TX_EN (LDO6), and PWR_HOLD (REG and LDO1) pins. This start-up procedure requires that the pushbutton be held until the microprocessor assumes control of PWR_HOLD, providing protection against inadvertent momentary assertions of the pushbutton. If desired, longer "push-and-hold" times can be easily implemented by simply adding an additional delay before assuming control of PWR_HOLD. If the microprocessor is unable to complete its power-up routine successfully before the user lets go of the push-button, the ACT5830 will automatically shut itself down. Once a successful power-up routine is completed, the user can initiate a shutdown process by pressing the push-button a second time. Upon detecting a second assertion of PWR_ON (by depressing the push-button), the ACT5830 asserts nON to interrupt the microprocessor which initiates an interrupt service routine that will reveal that the user pressed the push-button. If HF_PWR and CHG_OK are both low, the microprocessor then initiates a power-down routine, the final step of which will be to de-assert PWR_HOLD, disabling REG and LDO1.
Rev PrB, 05-Mar-08
IC Serial Interface
At the core of the ACT5830's flexible architecture is an I2C interface that permits optional programming capability to enhance overall system performance. Use standard I2C write-byte commands to program the ACT5830 and read-byte commands to read the IC's status. Figure 1: I2C Serial Bus Timing provides a standard timing diagram for the I2C protocol. The ACT5830 always operates as a slave device, with address 1010101.
System Startup & Shutdown
The ACT5830 features a flexible enable architecture that allows it to support a variety of push-button enable/disable schemes. Although other startup routines are possible, a typical startup and shutdown process would proceed as follows (referring to Figure 2): System startup is initiated whenever one of the following conditions occurs: 1) The user presses the push-button, asserting PWR_ON high, 2) A valid supply (>4V) is connected to the charger input (CHG_IN), or 3) a headset is connected, asserting HF_PWR high. The ACT5830 begins its system startup procedure by enabling REG, LDO2 and LDO3, then LDO1 are enabled when VBUCK or VOUT2 reaches 87% of its final value. nRST is asserted low when VOUT1 reaches 87% of its final value, holding the microprocessor in reset for a user-selectable reset period of 65msec. If (VBUCK or VOUT2) and VOUT1 are within 13% of their regulation voltages when the reset timer expires, the ACT5830 de-asserts nRST so that the microprocessor can begin its power up sequence. Once the power-up routine is successfully completed, the microprocessor asserts PWR_HOLD high to keep the ACT5830 enabled after the push-button is released by the user.
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ACT5830
SYSTEM MANAGEMENT
Figure 2: Startup and Shutdown Sequence
CHG_DETECT OR HF_PWR
Rev PrB, 05-Mar-08
PWR_ON (PUSH-BUTTON) REG, LDO2, LDO3 ENABLE VBUCK, OUT2, OUT3 LDO1 ENABLE OUT1
87% of VREG or VOUT2
87% of VOUT1
RESET TIMER ENABLE nRST TCXO_EN, RX_EN, TX_EN OUT4, OUT5, OUT6 I2C PROGRAMMING
65ms
PWR_HOLD nON
Open Drain Outputs
The ACT5830 includes two n-channel open drain outputs (OD1 and OD2) that can be used for driving external loads such as WLEDs or a vibrator motor, as shown in the functional diagram. Each of the OD output are enabled when either it's respective ODIx pin in driven to a logic high.
Thermal Overload Protection
The ACT5830 integrates thermal overload protection circuitry to prevent damage resulting from excessive thermal stress that may be encountered under fault conditions, for example. This circuitry disables all regulators if the ACT5830 die temperature exceeds 160C, and prevents the regulators from being enabled until the die temperature drops by 20C (typ), after which a normal startup routine may commence.
nACOK Output
The ACT5830's nACOK output provides a logic-level indication of the status of the voltage at CHG_IN. nACOK is an open-drain output which sinks current whenever VCHG_IN > 4V.
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ACT5830
STEP-DOWN DC/DC CONVERTER ELECTRICAL CHARACTERISTICS
(VVP = 3.6V, TA = 25C, unless otherwise specified.)
Rev PrB, 05-Mar-08
PARAMETER
VP Operating Voltage Range VP UVLO Threshold VP UVLO Hysteresis Standby Supply Current Shutdown Supply Current Output Voltage Regulation Accuracy Line Regulation Load Regulation Current Limit Oscillator Frequency PMOS On-Resistance NMOS On-Resistance SW Leakage Current Power Good Threshold Minimum On-Time
TEST CONDITIONS
Input Voltage Rising Input Voltage Falling
MIN
3.1 2.9
TYP
3 80 110
MAX
5.5 3.1
UNIT
V V mV
200 1 +1.8% +1.8%
A A V %/V %/mA A
REG/ON[ ] = [0], VVP = 4.2V VNOM < 1.3V, IOUT = 10mA VNOM 1.3V, IOUT = 10mA VVP = Max(VNOM + 1V, 3.2V) to 5.5V IOUT = 10mA to 350mA 0.45 VREG 20% of VNOM VREG = 0V ISW = -100mA ISW = 100mA VVP = 5.5V, VSW = 5.5V or 0V 1.35 -2.4% -1.2%
0.1 VNOM VNOM 0.15 0.0017 0.6 1.6 530 0.45 0.3
1.85
MHz kHz
0.75 0.5 1
A %VNOM ns
94 70
: VNOM refers to the nominal output voltage level for VREG as defined by the Ordering Information section.
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ACT5830
STEP-DOWN DC/DC CONVERTER REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Rev PrB, 05-Mar-08
Table 2: Control Register Map ADDRESS
14h 15h 16h 17h
DATA D7
R R R R
D6
VRANGE R R R
D5
R R R
D4
R R R
D3
VSET R R R
D2
R R R
D1
R R OK
D0
MODE R ON
R: Read-Only bits. Default Values May Vary.
Table 3: Control Register Bit Descriptions ADDRESS
14h 14h 14h 15h 15h 16h 17h 17h 17h 17h ON OK MODE
NAME
VSET VRANGE
BIT
[5:0] [6] [7] [0] [7:1] [7:0] [0] [1] [2] [7:3]
ACCESS
R/W R/W R R/W R R R R R R
FUNCTION
REG Output Voltage Selection REG Voltage Range Selection 0 1 0 1
DESCRIPTION
See Table 4 Min VOUT = 1.1V Min VOUT = 1.25V READ ONLY PWM/PFM Forced PWM READ ONLY READ ONLY 0 1 0 1 REG Disable REG Enable Output is not OK Output is OK READ ONLY READ ONLY
Mode Selection
REG Enable REG Power-OK
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ACT5830
STEP-DOWN DC/DC CONVERTER REGISTER DESCRIPTIONS CONT'D
Table 4: REG/VSET[ ] Output Voltage Setting REG/VSET[5:4] REG/VSET [3:0] 00
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
(N/A): Not Available
Rev PrB, 05-Mar-08
REG/VRANGE[ ] = [0] 01
N/A N/A 1.100 1.125 1.150 1.175 1.200 1.225 1.255 1.280 1.305 1.330 1.355 1.380 1.405 1.430
REG/VRANGE[ ] = [1] 11
1.860 1.890 1.915 1.940 1.965 1.990 2.015 2.040 2.065 2.090 2.115 2.140 2.165 2.190 2.200 2.245
10
1.455 1.480 1.505 1.530 1.555 1.585 1.610 1.635 1.660 1.685 1.710 1.735 1.760 1.785 1.810 1.835
00
1.250 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 1.850 1.900 1.950 2.000
01
2.050 2.100 2.150 2.200 2.250 2.300 2.350 2.400 2.450 2.500 2.550 2.600 2.650 2.700 2.750 2.800
10
2.850 2.900 2.950 3.000 3.050 3.100 3.150 3.200 3.250 3.300 3.350 3.400 3.450 3.500 3.550 3.600
11
3.650 3.700 3.750 3.800 3.850 3.900 3.950 4.000 4.050 4.100 4.150 4.200 4.250 4.300 4.350 4.400
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 15 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
STEP-DOWN DC/DC CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS
(VINx = 3.6V, COUTx = 1F, TA = 25C unless otherwise specified.)
REG Efficiency vs. Load
95 90 85 3.6V 4.0V 0.2
Rev PrB, 05-Mar-08
REG Load Regulation
ACT5830-002
Load Regulation Error (%)
ACT5830-001
0.0 -0.2 -0.4 -0.6 -0.8 4.2V
Efficiency (%)
80 75 70 65 60 55 50 1 10
3.6V
100
1000
0
50
100
150
200
250
300
350
400
Output Current (mA)
Output Current (mA)
VREG Regulation Voltage
1.812 1.810 1.808 IOUT1 = 35mA 600 550 500 ACT5830-003
REG MOSFET Resistance
ACT5830-004
VREG Voltage (V)
1.806 1.804 1.802 1.800 1.798 1.796 1.794 1.792 1.790 1.788 -40 -20 0 20 40 60
RDSON (m)
450 400 350 300 250 200 150 100 50 0
PMOS
NMOS
85
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Temperature (C)
VP1 Voltage (V)
REG Load Transient Response
ACT5830-005 CH1
REG Load Transient Response
ACT5830-006
CH1
CH2 0mA
CH2 0mA
CH1: VOUT1, 50mV/div (AC Coupled) CH2: IOUT1, 200mA/div TIME: 200s/div
CH1: VOUT1, 50mV/div (AC Coupled) CH2: IOUT1, 200mA/div TIME: 200s/div
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 16 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
STEP-DOWN DC/DC CONVERTER FUNCTIONAL DESCRIPTIONS
General Description
REG is a fixed-frequency, current-mode, synchronous PWM step-down converters that achieves a peak efficiency of up to 97%. REG is capable of supplying up to 350mA of output current and operates with a fixed frequency of 1.6MHz, minimizing noise in sensitive applications and allowing the use of small external components. REG is available with a variety of standard and custom output voltages, and may be software-controlled via the I2C interface by systems that require advanced power management functions.
Rev PrB, 05-Mar-08
Program the output voltage via the I2C serial interface by writing to the REG/VSET[ ] register.
Programmable Operating Mode
By default, REG operates in fixed-frequency PWM mode at medium to heavy loads, then transitions to a proprietary power-saving mode at light loads in order to save power. In applications where low noise is critical, force fixed-frequency PWM operation across the entire load current range, at the expense of light-load efficiency, by setting the REG/MODE[ ] bit to [1].
100% Duty Cycle Operation
REG is capable of operating at up to 100% duty cycle. During 100% duty-cycle operation, the highside power MOSFET is held on continuously, providing a direct connection from the input to the output (through the inductor), ensuring the lowest possible dropout voltage in battery-powered applications.
Power-OK
REG features a power-OK status bit that can be read by the system microprocessor. If the output voltage is lower than the power-OK threshold, typically 6% below the programmed regulation voltage, REG/OK[ ] will clear to 0.
Soft-Start
REG includes internal soft-start circuitry, and enabled its output voltage tracks an internal 80s softstart ramp so that it powers up in a monotonic manner that is independent of loading.
Synchronous Rectification
REG features an integrated n-channel synchronous rectifier, which maximizes efficiency and minimizes the total solution size and cost by eliminating the need for an external rectifier.
Compensation
REG utilizes current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over its full operating range. No compensation design is required, simply follow a few simple guidelines described below when choosing external components.
Enabling and Disabling REG
Enable/disable functionality is typically implemented as part of a controlled enable/disable scheme utilizing nMSTR and other system control features of the ACT5830. REG is automatically enabled whenever either of the following conditions are met: 1) HF_PWR is asserted high, or 2) PWR_ON is asserted high, or 3) PWR_HOLD is asserted high. When none of these conditions are true, or if REG/ON[ ] bit is set to [0], REG is disabled, and its quiescent supply current drops to less than 1A.
Input Capacitor Selection
The input capacitor reduces peak currents and noise induced upon the voltage source. A 2.2F ceramic input capacitor is recommended for most applications.
Output Capacitor Selection
For most applications, a 10F ceramic output capacitor is recommended. Although REG was designed to take advantage of the benefits of ceramic capacitors, namely small size and very-low ESR, low-ESR tantalum capacitors can provide acceptable results as well.
Programming the Output Voltage
By default, REG powers up and regulates to its default output voltage. Once the system is enabled, REG's output voltage may be programmed to a different value, typically in order to reduce the power consumption of a microprocessor in standby mode.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 17 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
STEP-DOWN DC/DC CONVERTER FUNCTIONAL DESCRIPTIONS CONT'D
Inductor Selection
REG utilizes current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over its full operating range. REG was optimized for operation with a 3.3H inductor, although inductors in the 2.2H to 4.7H range can be used. Choose an inductor with a low DC-resistance, and avoid inductor saturation by choosing inductors with DC ratings that exceed the maximum output current of the application by at least 30%.
Rev PrB, 05-Mar-08
PCB Layout Considerations
High switching frequencies and large peak currents make PC board layout an important part of stepdown DC/DC converter design. A good design minimizes excessive EMI on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. Stepdown DC/DC exhibits discontinuous input current, so the input capacitors should be placed as close as possible to the IC, and avoiding the use of vias if possible. The inductor, input filter capacitor, and output filter capacitor should be connected as close together as possible, with short, direct, and wide traces. The ground nodes for each regulator's power loop should be connected at a single point in a star-ground configuration, and this point should be connected to the backside ground plane with multiple vias. The output node should be connected to the VBUCK pin through the shortest possible route, while keeping sufficient distance from switching nodes to prevent noise injection. Finally, the exposed pad should be directly connected to the backside ground plane using multiple vias to achieve low electrical and thermal resistance.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 18 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
LOW-DROPOUT LINEAR REGULATORS REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Rev PrB, 05-Mar-08
Table 5: LDO Control Register Map ADDRESS
07h 0Fh 13h 0Eh 12h 0Ch 10h 0Dh 11h
DATA D7
R DIS1 DIS2 DIS7 DIS8 DIS3 DIS4 DIS5 DIS6
D6
VRANGE7 OK1 OK2 OK7 OK8 OK3 OK4 OK5 OK6
D5
ON1 ON2 ON7 ON8 ON3 ON4 ON5 ON6
D4
D3
VSET7
D2
VSET1 VSET2
D1
D0
R
R
R VSET8 VSET3 VSET4 VSET5 VSET6
R
R
Table 6: LDO Control Register Bit Descriptions ADDRESS
07h 07h 07h 0Fh 0Fh 0Fh 0Fh 13h 13h 13h 13h VSET1 ON1 OK1 DIS1 VSET2 ON2 OK2 DIS2
NAME
VSET7 VRANGE7
BIT
[5:0] [6] [7] [4:0] [5] [6] [7] [4:0] [5] [6] [7]
ACCESS
W/R W/R R W/R W/R R W/R W/R W/R R W/R
FUNCTION
LDO7 Output Voltage Selection REG Voltage Range Selection 0 1
DESCRIPTION
See Table 8 Min VOUT = 0.645V Min VOUT = 1.25V READ ONLY See Table 7 0 1 0 1 0 1 0 1 0 1 0 1 LDO1 Disable LDO1 Enable Output Out of Regulation Output In Regulation Output High-Z In Shutdown Output Discharge Enabled See Table 7 LDO2 Disable LDO2 Enable Output Out of Regulation Output In Regulation Output High-Z In Shutdown Output Discharge Enabled
LDO1 Output Voltage Selection LDO1 Enable LDO1 Power-OK LDO1 Output Discharge Enable LDO2 Output Voltage Selection LDO2 Enable LDO2 Power-OK LDO2 Output Discharge Enable
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 19 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
LOW-DROPOUT LINEAR REGULATORS REGISTER DESCRIPTIONS CONT'D
Table 6: LDO Control Register Bit Descriptions (Cont'd) ADDRESS
12h 12h 12h 12h 0Ch 0Ch 0Ch 0Ch 10h 10h 10h 10h 0Dh 0Dh
Rev PrB, 05-Mar-08
NAME
VSET8 ON8 OK8 DIS3 VSET3 ON3 OK3 DIS3 VSET4 ON4 OK4 DIS4 VSET5 ON5
BIT
[4:0] [5] [6] [7] [4:0] [5] [6] [7] [4:0] [5] [6] [7] [4:0] [5]
ACCESS
W/R W/R R W/R W/R W/R R W/R W/R W/R R W/R W/R W/R
FUNCTION
LDO8 Output Voltage Selection LDO8 Enable LDO8 Power-OK LDO8 Output Discharge Enable LDO3 Output Voltage Selection LDO3 Enable LDO3 Power-Ok LDO3 Output Discharge Enable LDO4 Output Voltage Selection LDO4 Enable LDO4 Power-OK LDO4 Output Discharge Enable LDO5 Output Voltage Selection LDO5 Enable 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
DESCRIPTION
See Table 7 LDO8 Disable LDO8 Enable Output Out of Regulation Output In Regulation Output High-Z In Shutdown Output Discharge Enabled See Table 7 LDO3 Disable LDO3 Enable Output Out of Regulation Output In Regulation Output High-Z In Shutdown Output Discharge Enabled See Table 7 LDO4 Disable LDO4 Enable Output Out of Regulation Output In Regulation Output High-Z In Shutdown Output Discharge Enabled See Table 7 LDO5 Disable LDO5 Enable Output Out of Regulation Output In Regulation Output High-Z In Shutdown Output Discharge Enabled
0Dh
OK5
[6]
R
LDO5 Power-OK
1 0 1
0Dh
DIS5
[7]
W/R
LDO5 Output Discharge Enable
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 20 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
LOW-DROPOUT LINEAR REGULATORS REGISTER DESCRIPTIONS CONT'D
Table 6: LDO Control Register Bit Descriptions (Cont'd) ADDRESS
11h 11h 11h 11h 0Eh 0Eh 0Eh 0Eh ON7 OK7 DIS7
Rev PrB, 05-Mar-08
NAME
VSET6 ON6 OK6 DIS6
BIT
[4:0] [5] [6] [7] [4:0] [5] [6] [7]
ACCESS
W/R W/R R W/R R W/R R W/R
FUNCTION
LDO6 Output Voltage Selection LDO6 Enable LDO6 Power-OK LDO6 Output Discharge Enable 0 1 0 1 0 1 0 1 0 1 0 1
DESCRIPTION
See Table 7 LDO6 Disable LDO6 Enable Output Out of Regulation Output In Regulation Output High-Z In Shutdown Output Discharge Enabled READ ONLY LDO7 Disable LDO7 Enable Output Out of Regulation Output In Regulation Output High-Z In Shutdown Output Discharge Enabled
LDO7 Enable LDO7 Power-OK LDO7 Output Discharge Enable
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 21 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
LOW-DROPOUT LINEAR REGULATORS REGISTER DESCRIPTIONS CONT'D
Table 7: LDO1234568/VSET[ ] Output Voltage Settings LDOx/VSETx[2:0] 000 001 010 011 100 101 110 111 LDOx/VSETx[4:3] 00
1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1
Rev PrB, 05-Mar-08
01
2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50
10
2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
11
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
Table 8: LDO7/VSET[ ] Output Voltage Settings LDO7/VSET[5:4] LDO7/VSET [3:0] 00
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
(N/A): Not Available
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
LDO7/VRANGE[ ] = [0] 01
1.050 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.255 1.280 1.305 1.330 1.355 1.380 1.405 1.430
LDO7/VRANGE[ ] = [1] 11
1.860 1.890 1.915 1.940 1.965 1.990 2.015 2.040 2.065 2.090 2.115 2.140 2.165 2.190 2.200 2.245
10
1.455 1.480 1.505 1.530 1.555 1.585 1.610 1.635 1.660 1.685 1.710 1.735 1.760 1.785 1.810 1.835
00
1.250 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 1.850 1.900 1.950 2.000
01
2.050 2.100 2.150 2.200 2.250 2.300 2.350 2.400 2.450 2.500 2.550 2.600 2.650 2.700 2.750 2.800
10
2.850 2.900 2.950 3.000 3.050 3.100 3.150 3.200 3.250 3.300 3.350 3.400 3.450 3.500 3.550 3.600
11
3.650 3.700 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
0.645 0.670 0.695 0.720 0.745 0.770 0.795 0.820 0.845 0.870 0.895 0.920 0.950 0.975 1.000 1.025
- 22 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
LOW-DROPOUT LINEAR REGULATORS TYPICAL PERFORMANCE CHARACTERISTICS
(VINx = 3.6V, COUTx = 1F, TA = 25C unless otherwise specified.)
Power Supply Rejection Ratio
80 70 60 50 40 30 20 0.1 1 10 100 COUT = 1F ILOAD = 150mA LDO5 250 LDO5 LDO8 LDO1 ACT5830-007
Rev PrB, 05-Mar-08
Dropout Voltage vs. Load Current
ACT5830-008
Dropout Voltage (mV)
200 LDO3 150
PSRR (dB)
100
50
0 0 50 100 150 200 250 300 350
Frequency (kHz)
Load Current (mA)
LDO Load Regulation
ACT5830-009 0.0% LDO5 LDO8
LDO Enable
ACT5830-010
CH1
-0.5%
VOUT (V)
LDO3 -1.0% LDO1
CH2 CH3 CH4
-1.5% 0 50 100 150 200 250 300 350 CH1: PWR_ON, 2V/div CH2: LDO1, 2V/div CH3: LDO2, 1V/div CH4: REG, 1V/div TIME: 200s/div
IOUT (mA)
LDO Disable
ACT5830-011
LDO Output Voltage Noise
ACT5830-012
CH1 CH2 CH3 CH4
CH1
LDO1, 2
CH1: PWR_ON, 2V/div CH2: LDO1, 2V/div CH3: LDO2, 1V/div CH4: REG, 1V/div TIME: 2ms/div
CH1: VOUTx, 1mV/div TIME: 10ms/div
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 23 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
LOW-DROPOUT LINEAR REGULATORS FUNCTIONAL DESCRIPTIONS
General Description
The ACT5830 features eight high performance, lowdropout, low-noise and low quiescent current LDOs with high PSRR.
Rev PrB, 05-Mar-08
Capacitor Selection
The input capacitor reduces peak currents and noise at the voltage source. Connect a low ESR bulk capacitor (>1F suggested) to the input. Select this bulk capacitor to meet the input ripple requirements and voltage rating, rather than capacitor size.
Programming Output Voltages (VSET)
All LDOs feature independently-programmable output voltages that are set via the I2C serial interface, increasing the ACT5830 flexibility while reducing total solution size and cost. Set the output voltage by writing to the LDOx/VSET[_] register. See Table 7: LDO1234568/VSET[4:0] and Table 8: LDO7/VSET[_] Output Voltage Settings for a detailed description of voltage programming options.
PCB Layout Considerations
The ACT5830's LDOs provide good DC, AC, and noise performance over a wide range of operating conditions, and are relatively insensitive to layout considerations. When designing a PCB, however, careful layout is necessary to prevent other circuitry from degrading LDO performance. A good design places input and output capacitors as close to the LDO inputs and output as possible, and utilizes a star-ground configuration for all regulators to prevent noise-coupling through ground. Output traces should be routed to avoid close proximity to noisy nodes, particularly the SW nodes of the DC/DC. REFBP is a filtered reference noise, and internally has a direct connection to the linear regulator controller. Any noise injected onto REFBP will directly affect the outputs of the linear regulators, and therefore special care should be taken to ensure that no noise is injected to the outputs via REFBP. As with the LDO output capacitors, the REFBP by pass capacitor should be placed as close to the IC as possible, with short, direct connections to the starground. Avoid the use of vias whenever possible. Noisy nodes, such as from the DC/DC, should be routed as far away from REFBP as possible.
Enabling and Disabling LDOs
For information regarding enabling and disabling the LDOs during the startup and shutdown sequence section. Once the startup routine is completed the remaining LDOs can be enabled/disabled via either the I2C interface or the TCXO_EN (LDO4), RX_EN (LDO5), TX_EN (LDO6), and PWR_HOLD (LDO1, LDO2, LDO3, LDO7, and LDO8).
Reference Bypass Pin
The ACT5830 contains a conference bypass pin which filters noise from the reference, providing a low-noise voltage reference to the LDOs. Bypass REF to G with a 0.01F ceramic capacitor.
Compensation and Stability
The LDOs need an output capacitor for stability. This capacitor should be connected as close to the OUT and G pins as possible to maximize device's performance. To ensure best performance for the device, the output capacitor should have a minimum capacitance of 1F, and ESR value between 10m and 500m. High quality ceramic capacitors such as X7R and X5R dielectric types are strongly recommended. See the Capacitor Selection sections for more information.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 24 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
LDO1 ELECTRICAL CHARACTERISTICS
(VIN1 = 3.6V, COUT1 = 1F, TA = 25C unless otherwise specified.)
Rev PrB, 05-Mar-08
PARAMETER
Input Supply Range Input Under Voltage Lockout UVLO Hysteresis Output Voltage Accuracy Line Regulation Error Load Regulation Error Power Supply Rejection Ratio
TEST CONDITIONS
VIN1 Input Rising VIN1 Input Falling TA = 25C TA = -40C to 85C VIN1 = Max (VNOM1 + 0.5V, 3.1V) to 5.5V IOUT1 = 1mA to 300mA f = 1kHz, IOUT1 = 300mA, COUT1 = 1F f = 10kHz, IOUT1 = 300mA, COUT1 = 1F LDO1 Enabled LDO1 Disabled IOUT1 = 150mA
MIN
3.1 2.9
TYP
3 0.1
MAX
5.5 3.1
UNIT
V V V
-1.2 -2.5
0 0 0 -0.004 60 50 20 0 100
2 3
% mV %/mA dB
Supply Current per Output Dropout Voltage2 Output Current Current Limit Current Limit Short Circuit Foldback Internal Soft-Start Power Good Flag High Threshold Output Noise Stable COUT1
A 200 300 mV mA mA
VOUT1 = 95% of Regulation Voltage VOUT1 = 0V
330
580 0.45 x ILIM 100
s % VRMS 20 F
VOUT1, Hysteresis = -1% COUT1 = 10F, f = 10Hz to 100kHz 1
89 40
: VNOM refers to the nominal output voltage level for LDO1 as defined by the Ordering Information section.
2: Dropout Voltage is defined as the different voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 25 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
LDO2 ELECTRICAL CHARACTERISTICS
(VIN2 = 3.6V, COUT2 = 1F, TA = 25C unless otherwise specified.)
Rev PrB, 05-Mar-08
PARAMETER
Input Supply Range Input Under Voltage Lockout UVLO Hysteresis Output Voltage Accuracy Line Regulation Error Load Regulation Error Power Supply Rejection Ratio
TEST CONDITIONS
VIN2 Input Rising VIN2 Input Falling TA = 25C TA = -40C to 85C VIN2 = Max (VNOM1 + 0.5V, 3.1V) to 5.5V IOUT2 = 1mA to 300mA f = 1kHz, IOUT2 = 300mA, COUT2 = 1F f = 10kHz, IOUT2 = 300mA, COUT2 = 1F LDO2 Enabled LDO2 Disabled IOUT2 = 150mA
MIN
3.1 2.9
TYP
3 0.1
MAX
5.5 3.1
UNIT
V V V
-1.2 -2.5
0 0 0 -0.004 60 50 20 0 100
2 3
% mV %/mA dB
Supply Current per Output Dropout Voltage2 Output Current Current Limit
A 200 300 mV mA mA
VOUT2 = 95% of Regulation Voltage
330
580 0.45 x ILIM 100
Current Limit Short Circuit Foldback VOUT2 = 0V Internal Soft-Start Power Good Flag High Threshold Output Noise Stable COUT2 VOUT2, Hysteresis = -1% COUT2 = 10F, f = 10Hz to 100kHz 1
s % VRMS 20 F
89 40
: VNOM refers to the nominal output voltage level for LDO2 as defined by the Ordering Information section.
2: Dropout Voltage is defined as the different voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 26 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
LDO3 ELECTRICAL CHARACTERISTICS
(VIN1 = 3.6V, COUT3 = 1F, TA = 25C unless otherwise specified.)
Rev PrB, 05-Mar-08
PARAMETER
Input Supply Range Input Under Voltage Lockout UVLO Hysteresis Output Voltage Accuracy Line Regulation Error Load Regulation Error Power Supply Rejection Ratio
TEST CONDITIONS
VIN1 Input Rising VIN1 Input Falling TA = 25C TA = -40C to 85C VIN3 = Max (VNOM1 + 0.5V, 3.1V) to 5.5V IOUT3 = 1mA to 100mA f = 1kHz, IOUT3 = 100mA, COUT3 = 1F f = 10kHz, IOUT3 = 100mA, COUT3 = 1F LDO3 Enabled LDO3 Disabled IOUT3 = 50mA
MIN
3.1 2.9
TYP
3 0.1
MAX
5.5 3.1
UNIT
V V V
-1.2 -2.5
0 0 0 -0.004 70 60 40 0 100
2 3
% mV %/mA dB
Supply Current per Output Dropout Voltage2 Output Current Current Limit Current Limit Short Circuit Foldback Internal Soft-Start Power Good Flag High Threshold Output Noise Stable COUT3
A 200 100 mV mA mA
VOUT3 = 95% of Regulation Voltage VOUT3 = 0V
115
180 0.45 x ILIM 100
s % VRMS 20 F
VOUT3, Hysteresis = -1% COUT3 = 10F, f = 10Hz to 100kHz 1
89 40
: VNOM refers to the nominal output voltage level for LDO3 as defined by the Ordering Information section.
2: Dropout Voltage is defined as the different voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 27 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
LDO4 ELECTRICAL CHARACTERISTICS
(VIN2 = 3.6V, COUT4 = 1F, TA = 25C unless otherwise specified.)
Rev PrB, 05-Mar-08
PARAMETER
Input Supply Range Input Under Voltage Lockout UVLO Hysteresis Output Voltage Accuracy Line Regulation Error Load Regulation Error Power Supply Rejection Ratio
TEST CONDITIONS
VIN2 Input Rising VIN2 Input Falling TA = 25C TA = -40C to 85C VIN4 = Max (VNOM1 + 0.5V, 3.1V) to 5.5V IOUT4 = 1mA to 100mA f = 1kHz, IOUT4 = 100mA, COUT4 = 1F f = 10kHz, IOUT4 = 100mA, COUT4 = 1F LDO4 Enabled LDO4 Disabled IOUT4 = 50mA
MIN
3.1 2.9
TYP
3 0.1
MAX
5.5 3.1
UNIT
V V V
-1.2 -2.5
0 0 0 -0.004 70 60 40 0 100
2 3
% mV %/mA dB
Supply Current per Output Dropout Voltage2 Output Current Current Limit Current Limit Short Circuit Foldback Internal Soft-Start Power Good Flag High Threshold Output Noise Stable COUT4
A 200 100 mV mA mA
VOUT4 = 95% of Regulation Voltage VOUT4 = 0V
115
180 0.45 x ILIM 100
s % VRMS 20 F
VOUT4, Hysteresis = -1% COUT4 = 10F, f = 10Hz to 100kHz 1
89 40
: VNOM refers to the nominal output voltage level for LDO4 as defined by the Ordering Information section.
2: Dropout Voltage is defined as the different voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 28 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
LDO5 ELECTRICAL CHARACTERISTICS
(VIN1 = 3.6V, COUT5 = 1F, TA = 25C unless otherwise specified.)
Rev PrB, 05-Mar-08
PARAMETER
Input Supply Range Input Under Voltage Lockout UVLO Hysteresis Output Voltage Accuracy Line Regulation Error Load Regulation Error Power Supply Rejection Ratio
TEST CONDITIONS
VIN1 Input Rising VIN1 Input Falling TA = 25C TA = -40C to 85C VIN5 = Max (VNOM1 + 0.5V, 3.1V) to 5.5V IOUT5 = 1mA to 150mA f = 1kHz, IOUT5 = 150mA, COUT5 = 1F f = 10kHz, IOUT5 = 150mA, COUT5 = 1F LDO5 Enabled LDO5 Disabled IOUT5 = 80mA
MIN
3.1 2.9
TYP
3 0.1
MAX
5.5 3.1
UNIT
V V V
-1.2 -2.5
0 0 0 -0.004 70 60 40 0 100
2 3
% mV %/mA dB
Supply Current per Output Dropout Voltage2 Output Current Current Limit
A 200 150 mV mA mA
VOUT5 = 95% of Regulation Voltage
165
260 0.45 x ILIM 100
Current Limit Short Circuit Foldback VOUT5 = 0V Internal Soft-Start Power Good Flag High Threshold Output Noise Stable COUT5 VOUT5, Hysteresis = -1% COUT5 = 10F, f = 10Hz to 100kHz 1
s % VRMS 20 F
89 40
: VNOM refers to the nominal output voltage level for LDO5 as defined by the Ordering Information section.
2: Dropout Voltage is defined as the different voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 29 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
LDO6 ELECTRICAL CHARACTERISTICS
(VIN2 = 3.6V, COUT6 = 1F, TA = 25C unless otherwise specified.)
Rev PrB, 05-Mar-08
PARAMETER
Input Supply Range Input Under Voltage Lockout UVLO Hysteresis Output Voltage Accuracy Line Regulation Error Load Regulation Error Power Supply Rejection Ratio
TEST CONDITIONS
VIN2 Input Rising VIN2 Input Falling TA = 25C TA = -40C to 85C VIN6 = Max (VNOM1 + 0.5V, 3.1V) to 5.5V IOUT6 = 1mA to 150mA f = 1kHz, IOUT6 = 150mA, COUT6 = 1F f = 10kHz, IOUT6 = 150mA, COUT6 = 1F LDO6 Enabled LDO6 Disabled IOUT6 = 80mA
MIN
3.1 2.9
TYP
3 0.1
MAX
5.5 3.1
UNIT
V V V
-1.2 -2.5
0 0 0 -0.004 70 60 40 0 100
2 3
% mV %/mA dB
Supply Current per Output Dropout Voltage2 Output Current Current Limit
A 200 150 mV mA mA
VOUT6 = 95% of Regulation Voltage
165
260 0.45 x ILIM 100
Current Limit Short Circuit Foldback VOUT6 = 0V Internal Soft-Start Power Good Flag High Threshold Output Noise Stable COUT6 VOUT6, Hysteresis = -1% COUT6 = 10F, f = 10Hz to 100kHz 1
s % VRMS 20 F
89 40
: VNOM refers to the nominal output voltage level for LDO6 as defined by the Ordering Information section.
2: Dropout Voltage is defined as the different voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 30 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
LDO7 ELECTRICAL CHARACTERISTICS
(VIN1 = 3.6V, COUT7 = 1F, TA = 25C unless otherwise specified.)
Rev PrB, 05-Mar-08
PARAMETER
Input Supply Range Input Under Voltage Lockout UVLO Hysteresis
TEST CONDITIONS
VIN1 Input Rising VIN1 Input Falling TA = 25C VNOM < 1.3V, IOUT = 10mA VNOM 1.3V, IOUT = 10mA VNOM < 1.3V, IOUT = 10mA VNOM 1.3V, IOUT = 10mA
MIN
3.1 2.9
TYP
3 0.1
MAX
5.5 3.1
UNIT
V V V
-2.4 -1.2 -5 -2.5
0 0 0 0 0 -0.004 60 50 20 0 100
2 2 3 3 mV %/mA dB %
Output Voltage Accuracy TA = -40C to 85C Line Regulation Error Load Regulation Error Power Supply Rejection Ratio
VIN7 = Max (VNOM1 + 0.5V, 3.1V) to 5.5V IOUT7 = 1mA to 250mA f = 1kHz, IOUT7 = 250mA, COUT7 = 1F f = 10kHz, IOUT7 = 250mA, COUT7 = 1F LDO7 Enabled LDO7 Disabled IOUT7 = 100mA
Supply Current per Output Dropout Voltage2 Output Current Current Limit Current Limit Short Circuit Foldback Internal Soft-Start Power Good Flag High Threshold Output Noise Stable COUT7
A 200 250 mV mA mA
VOUT7 = 95% of Regulation Voltage VOUT7 = 0V
275
410 0.45 x ILIM 100
s % VRMS 20 F
VOUT7, Hysteresis = -1% COUT7 = 10F, f = 10Hz to 100kHz 1
89 40
: VNOM refers to the nominal output voltage level for LDO7 as defined by the Ordering Information section.
2: Dropout Voltage is defined as the different voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 31 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
LDO8 ELECTRICAL CHARACTERISTICS
(VIN2 = 3.6V, COUT8 = 1F, TA = 25C unless otherwise specified.)
Rev PrB, 05-Mar-08
PARAMETER
Input Supply Range Input Under Voltage Lockout UVLO Hysteresis Output Voltage Accuracy Line Regulation Error Load Regulation Error Power Supply Rejection Ratio
TEST CONDITIONS
VIN2 Input Rising VIN2 Input Falling TA = 25C TA = -40C to 85C VIN8 = Max (VNOM1 + 0.5V, 3.1V) to 5.5V IOUT8 = 1mA to 250mA f = 1kHz, IOUT8 = 250mA, COUT8 = 1F f = 10kHz, IOUT8 = 250mA, COUT8 = 1F LDO8 Enabled LDO8 Disabled IOUT8 = 100mA
MIN
3.1 2.9
TYP
3 0.1
MAX
5.5 3.1
UNIT
V V V
-1.2 -2.5
0 0 0 -0.004 60 50 20 0 100
2 3
% mV %/mA dB
Supply Current per Output Dropout Voltage2 Output Current Current Limit Current Limit Short Circuit Foldback Internal Soft-Start Power Good Flag High Threshold Output Noise Stable COUT8
A 200 250 mV mA mA
VOUT8 = 95% of Regulation Voltage VOUT8 = 0V
275
410 0.45 x ILIM 100
s % VRMS 20 F
VOUT8, Hysteresis = -1% COUT8 = 10F, f = 10Hz to 100kHz 1
89 40
: VNOM refers to the nominal output voltage level for LDO8 as defined by the Ordering Information section.
2: Dropout Voltage is defined as the different voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 32 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) ELECTRICAL CHARACTERISTICS
(VCHG_IN = 5V, VBAT = 3.6V, VSET[ ] = [0101], ISET[ ] = [0101], TA = 25C, unless otherwise specified.)
Rev PrB, 05-Mar-08
PARAMETER
CHG_IN Operating Range UVLO Threshold UVLO Hysteresis Battery Termination Voltage Line Regulation PMOS On Resistance Charge Current VICHG Voltage Precondition Charge Current Precondition Threshold Voltage Precondition Threshold Hysteresis End-of-Charge Current Threshold End-of-Charge Qualification Period Charge Restart Threshold BATID High Input Voltage BATID Low Input Voltage BATID Leakage Current Thermal Regulation Threshold BAT Reserve Leakage Current
TEST CONDITIONS
CHG_IN Voltage Rising CHG_IN Voltage Falling
MIN
4.2 3.75
TYP
4 500
MAX
6 4.25
UNIT
V V mV
4.179 VCHG_IN = 4.5V to 5.5V, IBAT = 10mA
4.200 0.2 0.3
4.221
V %/V
0.5 550
mA mV/mA
VBAT = 3.8V VVICHG /IBAT VBAT = 2.8V VBAT Voltage Rising VBAT Voltage Falling VBAT = 4.1V
450
500 2.3
35 2.75
50 2.9 150 50 32
65 3.0
mA V mV mA ms mV V
VSET[ ] - VBAT, VBAT Falling VBATID Voltage Rising VBATID Voltage Falling VCHG_IN = 4.5V 2.5
200
2 1 105
V A C
SLEEP, SUSPEND, or TIMER-FAULT state VnENCHG > 1.4V
0.4 65 200 0.8 60 No timer 30 45 3.0 No timer 1.5 2.2
5 100 500 1.2
A A A mA min
CHG_IN Supply Current
SLEEP, SUSPEND, or TIMER-FAULT state PRECONDITION, FAST-CHARGE, or TOP-OFF state TIMOSET[ ] = [00]
Precondition Timeout Period
TIMOSET[ ] = [01] TIMOSET[ ] = [10] TIMOSET[ ] = [11] TIMOSET[ ] = [00]
min min hr
Total Charging Timeout Period
TIMOSET[ ] = [01] TIMOSET[ ] = [10] TIMOSET[ ] = [11]
hr hr
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 33 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
SINGLE-CELL Li+ BATTERY CHARGER (CHGR)
Figure 3: Battery Charger Algorithm
Rev PrB, 05-Mar-08
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 34 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) Li+ BATTERY CHARGER REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Rev PrB, 05-Mar-08
Table 8: Battery Charger (CHGR) Control Register Map ADDRESS
08h 09h 0Ah 0Bh R R TIMOSET R R
DATA D7 D6
ISET R R R BATFLT R R
D5
D4
D3
R TIMOFLT R R
D2
R R R
D1
VSET CHGRSTAT R CHGROK
D0
VINPOK R SUSCHG
R: Read-Only bits. Default Values May Vary.
Table 9: Battery Charger (CHGR) Control Register Bit Descriptions ADDRESS
08h 08h 08h 09h 09h 09h 09h 09h 09h 09h 0Ah 0Bh 0Bh 0Bh
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
NAME
VSET
BIT
[2:0] [3]
ACCESS
R/W R R/W R R R R R R R/W R R/W R R
FUNCTION
Charge Termination Voltage Selection Maximum Charge Current Selection Input Supply Power-OK Charging Status 0 1 0 1 0 1 0 1
DESCRIPTION
See Table 11 READ ONLY See Table 10 Input Power is not OK Input Power is OK Not Charging Charging READ ONLY No Timeout Fault Timeout Fault Battery Not Removed Battery Removed READ ONLY See Table 12 READ ONLY 0 1 0 1 Charging Enabled Charging Disabled Charging Error Occurred Charging OK READ ONLY
ISET VINPOK CHGRSTAT
[7:4] [0] [1] [2]
TIMOFLT BATFLT
[3] [4] [5]
Timeout Fault Battery Removed Fault
TIMOSET
[7:6] [7:0]
Charge Timeout Select
SUSCHG CHGROK
[0] [1] [7:2]
Suspend Charging Charge Status
- 35 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) Li+ BATTERY CHARGE REGISTER DESCRIPTIONS CONT'D
Table 10: CHGR Charge Current Settings CHGR/ISET[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Rev PrB, 05-Mar-08
Table 11: Charge Termination Voltage Settings CHGR/VSET[3:0]
000 001 010 011 100 101 110 111
FAST CHARGE CURRENT SETTINGS (mA)
100 300 350 400 450 (default) 500 550 600 650 700 750 800 850 900 950 1000
CHARGE TERMINATION VOLTAGE (V)
4.10 4.12 4.14 4.16 4.18 4.20 (default) 4.22 4.24
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 36 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) TYPICAL PERFORMANCE CHARACTERISTICS
(COUTx = 1F X7R, VBAT = VINx = VOUTx + 0.5V, TA = 25C, unless otherwise specified.)
Rev PrB, 05-Mar-08
Battery Termination Voltage vs. Temperature
4.31 4.28 4.25 2250 2000 1750 ACT5830-013
VICHG Voltage vs. IBAT
ACT5830-014
4.22 4.19 4.16 4.13 4.10 -40 -20 0 20 40 60 ISET[3:0] = [1111] 80 100 120
VVICHG (mV)
1500 1250 1000 750 500 250 0 0 200 400 600 VCHG_IN = 5V VBATID = 2.5V ISET[3:0] = [1111] 800
VBAT (V)
1000
Temperature (C)
IBAT (mA)
Precondition Threshold Voltage vs. Temperature
3.1 325 320 315 ACT5830-015
MOSFET Resistance vs. Temperature
ACT5830-016
3.0
VPRECONDITION (V)
2.9
RDSON (m)
VBAT Rising
310 305 300 295 290 285
2.8 VBAT Falling 2.7 2.6 -40 -20 0 20 40 60 80 100 120
280 -40 -20 0 20 40 60 80 100 120
Temperature (C)
Temperature (C)
BAT Reverse Leakage Current vs. Temperature
5 ACT5830-017
4
IBAT (A)
3
2 -40 -20 0 20 40
VCHG_IN = 0V or Floating VBAT = 5V 60 80 100 120
Temperature (C)
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 37 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) FUNCTIONAL DESCRIPTIONS
General Description
The ACT5830's internal battery charger is an intelligent, stand-alone CC/CV (constantcurrent/constant-voltage), linear-mode single-cell charger for Lithium-based cell-chemistries. This device incorporates current and voltage sense circuitry, an internal power MOSFET, thermalregulation circuitry, a complete state-machine to implement charge safety features, and circuitry that eliminates the reverse-blocking diode required by conventional charger designs. The ACT5830 battery charger operates independently of the regulators, and is automatically enabled whenever a valid input supply is available. The ACT5830's battery charger features softwareprogrammable fast-charge current, charge termination voltage, charge safety timeout period. The ACT5830's battery charger can accept input supplies in the 4.3V to 6V range, making it compatible with lower-voltage inputs such as 5-6V wallcubes and USB ports. The battery charger, along with LDO1, LDO2, and LDO3, is enabled and initiates a charging cycle whenever an input supply is present.
Rev PrB, 05-Mar-08
CC/CV Regulation Loop
At the core of the ACT5830's battery charger is a CC/CV regulation loop, which regulates either current or voltage as necessary to ensure fast and safe charging of the battery. In a normal charge cycle, this loop regulates the current to the value set in the CHGR/ISET register. Charging continues at this current until the battery cell voltage reaches the the programmed termination voltage, as defined in the CHGR/VSET register. At this point the CV loop takes over, and charge current is allowed to decrease as necessary to maintain charging at the termination voltage.
Programming the Charge Current (ISET[_])
In order to accommodate both USB and ACpowered inputs with a minimum of external components, the ACT5830 features a I2C-programmable fast-charge current that requires no external current-setting components. The CHGR/ISET register sets ISET to any value greater than [0000] to program the maximum charge current to values in the 300mA to 1A via software. See for a detailed list of programmable charge currents. Note that the actual charging current may be lower than the programmed fast-charge current, due to the ACT5830's thermal regulation loop. See the section for more information.
Enabling/Disabling the Charger
The ACT5830 is enabled when the voltage applied to CHG_IN is greater than the voltage at BAT and is greater than 4.0V, and nENCHG is asserted low. The charger is disabled whenever nENCHG is high, independent of the voltages at battery and CHG_IN. The charger may also be disabled via the I2C interface. For more information about enabling and disabling the charger, see the System Startup & Shutdown section.
Measuring the Charge Current
In order to ease monitoring of the charge current, the ACT5830 generates a voltage at VICHG that is proportional to the charge current. The gain is typically 2.47mV/mA, and this voltage can be easily read by a system ADC. VICHG is high-impedance in shutdown.
Operation Without a battery
The ACT5830's charger is designed to operate with or without a battery connected. When a battery is connected, a normal charging cycle is performed as described below. If no battery is present, however, the charger will regulate the voltage at BAT to the voltage programmed by CHGR/VSET[_] to power the system.
Thermal Regulation
The ACT5830 features an internal thermal feedback loop that reduces the charging current as necessary to ensure that the die temperature does not rise beyond the thermal regulation threshold of 115C. This feature protects the ACT5830 against excessing JUNCTION temperature, and allows the ACT5830 to be used in aggressive thermal designs without risk of damage. Note that attention to good thermal design is still required to achieve the fastest possible charge time.
- 38 www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
ACT5830
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) FUNCTIONAL DESCRIPTIONS CONT'D
Charge Safety Timer
While monitoring the charge cycle, the ACT5830 utilizes a charge safety timer to help identify damaged cells and to ensure that the cell is charged safely. Three timeout options of 60 minutes, 30 minutes, and 45minutes are available, as programmed by the CHGR/TIMOSET register, and a timerdisable option is also available for systems that do not require the ACT5830 to control charge timeouts. The bit assignments for each timeout period are set as follows: Table 12: TIMOSET[ ] Timeout Period Options TIMOSET PRECONDITION TOTAL CHARGING TIMEOUT TIMEOUT [1:0 ]
0 0 1 1 0 1 0 1 60 mins (default) TIMER DISABLED 30 mins 45 mins 3.0 hours (default) TIMER DISABLED 1.5 hours 2.2 hours
Rev PrB, 05-Mar-08
TOP-OFF State In the TOP-OFF state, the cell is charged in constant-voltage (CV) mode. With the charge current limited by the internal chemistry of the cell, decreases as charging continues. During a normal charging cycle charging proceeds until the charge current decreases beyond the End-Of-Charge (EOC) threshold, defined as 10% of ISET. When this happens, the state machine terminates the charge cycle and jumps to the SLEEP state. SLEEP State In SLEEP mode the ACT5830 presents a highimpedance to the battery, allowing the cell to "relax" and minimizing battery leakage current. The ACT5830 continues to monitor the cell voltage, however, so that it can re-initiate charging cycles as necessary to ensure that the cell remains fully charged. Under normal operation, the state machine initiates a new charging cycle by jumping to the FAST-CHARGE state when VBAT drops below the Charge Termination Threshold (programmed by VSET) by more than the Charge Restart Threshold of 200mV (typ). SUSPEND State PRECONDITION State The ACT5830 features a user-selectable suspendcharge mode (SUSCHG), which disables the charger but keeps other circuitry functional. Charging continues in the SUSPEND state until CHGR/SUSPEND is cleared, at which point the charge timer is reset and the state machine jumps to the PRECHARGE state. Suspend charge by setting CHGR/SUSCHG = [1]. Permit charging by clearing CHGR/SUSCHG to [0]. TIMEOUT-FAULT State In order to prevent continued operation with a damaged ce ll, there is no direct path to resume charging once a Timeout Fault occurs. In order to resume charging, the state machine must jump to the SUSPEND state as a result of any of the following events: microprocessor sets CHGR/SUSCHG to [1], microprocessor pulls nENCHG high, the input supply is removed or the input suppl voltage drops below the UVLO threshold (4V), or the battery is removed. Once any of these events
CHGR State-Machine
A new charging cycle begins with the PRECONDITION state. In this state, the cell is charged at a reduced current of 10% of ISET, the programmed fast charge current. During a normal charge cycle, charging continues at this rate until VBAT reaches the Precondition Threshold Voltage of 2.9V (typ), at which point the charging state machine jumps to its FAST-CHARGE state. If VBAT does not reach the Precondition Threshold Voltage before the charge timeout period expires, then a damaged cell is detected and the state machine jumps to the TIMEOUT-FAULT State. FAST-CHARGE State In FAST-CHARGE mode, the charger operates in constant-current (CC) mode and charges the cell at the current programmed by CHGR/ISET. During a normal charge cycle fast-charge continues until VBAT reaches the termination voltage programmed by VSET, at which point the state machine jumps to the TOPOFF state.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 39 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) FUNCTIONAL DESCRIPTIONS CONT'D
occur, the state machine jumps to the SUSPEND state and charging can resume as defined by Figure 4. NO BAT State The ACT5830 charger has been designed so that it will provide system power when there is no battery present. If the battery is not present at any time while a valid input voltage (>4V) is applied to CHG_IN, the ACT5830 will enable the charger and regulate the output at the voltage programmed by CHGR/VSET[ ], simulating a battery-present condition. The output current of the charger in this state is default to 1000mA to ensure full operation of the phone. When operating in this state, the charge timers are disabled but the thermal regulation loop is active. It is important for the application designer to consider both the power available from the charger as well as the thermal design in order to ensure proper system operation in this state. The Figure 4: Charger State Diagram
ANY STATE
V BATID > 2.5V AND V CHG _IN > UVLO AND CHGR/SUSCHG[ ] = [0]
Rev PrB, 05-Mar-08
user can prevent this operation by either: pull nENCHG high, or setting SUSCHG = [1]. If the battery is reconnected while operating in the NO BAT state, the state machine resets the charge timers and jumps to the PRECONDITION state.
Reverse Battery
The ACT5830 includes internal circuitry that eliminates the need for series blocking diodes, reducing solution size and cost as well as dropout voltage relative to conventional battery chargers. When the input supply is removed, when VIN goes below the ACT5830's under voltage-lockout (UVLO) voltage, or when VIN drops below VBAT, the ACT5830 automatically goes into SUSPEND mode and reconfigures its power switch to minimize current drain from the battery.
ANY STATE
V CHG_IN < V BAT OR V CHG_IN < UVLO OR CHGR/SUSCHG[ ] = [1]
LDO-MODE
V
BA TI D
SUSPEND
<
2.
0V
BATTERY PRESENT AND V CHG_IN > V BAT AND V CHG_IN > UVLO AND CHGR/SUSCHG[ ] = [0]
T > TIMOSET[ ] AND V BAT < 2.9V
TIMEOUT-FAULT
PRECONDITION
V BAT > 2.9V Charge Timers Cleared
FAST-CHARGE
V BAT = VSET[ ]
T > TIMOSET[ ] Charge Timers not Cleared or I BAT > ISET[ ]/10
TOP-OFF
I BAT < ISET[ ]/10 or T > TIMOSET[ ]
DELAY
T > 32ms
SLEEP
V BAT < VSET[ ] - 200mV
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 40 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT5830
PACKAGE OUTLINE AND DIMENSIONS PACKAGE OUTLINE
TQFN55-40 PACKAGE OUTLINE AND DIMENSIONS
D D/2
Rev PrB, 05-Mar-08
SYMBOL
A
E/2
DIMENSION IN MILLIMETERS MIN
0.700 0.000
DIMENSION IN INCHES MIN
0.028 0.000
MAX
0.800 0.050
MAX
0.031 0.002
A1 A3
E
0.200 REF 0.150 4.900 4.900 3.450 3.450 0.250 5.100 5.100 3.750 3.750
0.008 REF 0.006 0.193 0.193 0.136 0.136 0.010 0.201 0.201 0.148 0.148
b D E D2 E2 e
0.400 BSC 0.300 0.500
0.016 BSC 0.012 0.020
A A3 D2 L b A1
L R
0.300
0.012
e E2
R
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 41 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.

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