View ISL9016IRUJCZ-T_4519201.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL9016
Data Sheet January 22, 2009 FN6832.0
150mA Dual LDO with Low Noise, High PSRR, and Low IQ
ISL9016 is a high performance dual LDO capable of providing up to 150mA current on each channel. It features a low standby current and very high PSRR and is stable with output capacitance of 1F to 4.7F with an ESR of up to 200m. The device integrates a separate enable function for each output. The quiescent current is typically 49A when only one LDO is enabled and typically 80A when both LDOs are enabled. When both LDOs are under shutdown condition, the drawing current is typically less than 1A. ISL9016 provides a wide input voltage range from 1.8V to 6.5V. It also has a high PSRR of 80dB at 1kHz and 45dB at 1MHz. ISL9016 also provides output current limit, overheat protection, reverse current protection, as well as excellent load transient response. ISL9016 is offered in a tiny 1.6mmx1.6mm 6 Ld TDFN package. Output voltage options are available from 1.2V to 3.3V. Several combinations of voltage outputs are standard and others may be available upon request.
Features
* Dual Integrated 150mA High Performance LDOs * High PSRR: 80dB @ 1kHz and 45dB @ 1MHz * Reverse Current Protection * Low Quiescent Current - 49A (Single LDO Enabled)/80A (Dual LDOs Enabled) * Excellent Load Transient Response * Typically 0.8% Output Voltage Accuracy * Low Output Noise: Typically 25VRMS * Wide Input Voltage Capability: 1.8V to 6.5V * Low Dropout Voltage: Typically 120mV @ 150mA * Separate Enable Control for each LDO * Stable with 1F to 4.7F Ceramic Output Capacitors * Soft-start to Limit Input Current Surge During Enable * Current Limit and Overheat Protection * Tiny 6 Ld 1.6mmx1.6mm TDFN package * Pb-free (RoHS Compliant)
Pinout
ISL9016 (6 LD 1.6x1.6 TDFN) TOP VIEW
VIN 1 GND 2 EN2 3 6 VOUT1 5 VOUT2 4 EN1
Applications
* PDAs, Cell Phones and Smart Phones * Portable Instruments, MP3/4 Players, PMP, DSC * Handheld Devices including Medical Handhelds
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2009. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL9016
Ordering Information
PART NUMBER (Notes 1, 3) ISL9016IRUWCZ-T ISL9016IRUWGZ-T ISL9016IRUWJZ-T ISL9016IRUWKZ-T ISL9016IRUBWZ-T ISL9016IRUBBZ-T ISL9016IRUCWZ-T ISL9016IRUCBZ-T ISL9016IRUFWZ-T ISL9016IRUFBZ-T ISL9016IRUFCZ-T ISL9016IRUFFZ-T ISL9016IRUGWZ-T ISL9016IRUGCZ-T ISL9016IRUGGZ-T ISL9016IRUJWZ-T ISL9016IRUJBZ-T ISL9016IRUJCZ-T ISL9016IRUJJZ-T ISL9016IRUKWZ-T ISL9016IRUKFZ-T ISL9016IRUKKZ-T ISL9016IRUMWZ-T ISL9016IRUMBZ-T ISL9016IRUMCZ-T ISL9016IRUMKZ-T ISL9016IRUNWZ-T ISL9016IRUNCZ-T NOTES: 1. Please refer to TB347 for details on reel specifications. 2. For other output voltages, contact Intersil marketing or local sales office. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PART MARKING N7 N6 N2 N1 R7 R6 R5 R4 R3 N8 N9 P0 P1 R2 N3 P2 P3 N4 N0 P5 P4 N5 P6 P7 P8 P9 R0 R1 VO1 VOLTAGE (V) (Note 2) 1.2 1.2 1.2 1.2 1.5 1.5 1.8 1.8 2.5 2.5 2.5 2.5 2.7 2.7 2.7 2.8 2.8 2.8 2.8 2.85 2.85 2.85 3.0 3.0 3.0 3.0 3.3 3.3 VO2 VOLTAGE (V) (Note 2) 1.8 2.7 2.8 2.85 1.2 1.5 1.2 1.5 1.2 1.5 1.8 2.5 1.2 1.8 2.7 1.2 1.5 1.8 2.8 1.2 2.5 2.85 1.2 1.5 1.8 2.85 1.2 1.8 TEMP RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN PKG DWG. # L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A
2
FN6832.0 January 22, 2009
ISL9016
Absolute Maximum Ratings
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.1V All Other Pins to GND . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)V
Thermal Information
Thermal Resistance JA (C/W) 6 Ld TDFN Package (Note 4) . . . . . . . . . . . . . . . 117.5 Junction Temperature Range . . . . . . . . . . . . . . . . .-40C to +125C Operating Temperature Range . . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 6.5V Each LDO Load Current . . . . . . . . . . . . . . . . . . . . . . . .up to 150mA Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specifications are measured at the following conditions: TA = +25C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 1.8V; CIN = 1F; CO = 1F. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER DC CHARACTERISTICS Supply Voltage UVLO Threshold
VIN VUV+ VUV-
1.8 1.710 1.55 Quiescent condition: IO1 = 0A; IO2 = 0A 1.62
6.5 1.775
V V
Input Quiescent Current IDD1 IDD2 Shutdown Current Regulation Voltage Accuracy IDDS
One LDO active Both LDO active @ +25C VIN = VO + 0.5V to 6.5V, IO = 10A to 150mA, TA = +25C VIN = VO + 0.5V to 6.5V, IO = 10A to 150mA, TA = -40C to +85C -0.8 -1.8 150 175 IO = 150mA; 1.2V VO 2.1V IO = 150mA; 2.1V VO 2.8V IO = 150mA; 2.8V VO
49 80 0.1
67 100 1.0 +0.8 +1.8
A A A % % mA
Maximum Output Current Internal Current Limit Dropout Voltage (Note 5)
IMAX ILIM VDO1 VDO2 VDO3
Each LDO, Continuous
265 250 200 120 145 110
355 425 325 200
mA mV mV mV C C
Thermal Shutdown Temperature
TSD+ TSD-
AC CHARACTERISTICS Ripple Rejection IO = 10mA, VIN = 3.7V(min), VO = 2.7V, TA = +25C @ 1kHz @ 10kHz @ 100kHz @ 1MHz Output Noise Voltage DEVICE START-UP CHARACTERISTICS Device Enable Time tEN Time from assertion of the ENx pin to when the output voltage reaches 95% of the VO(nom) 400 600 s VIN = 4.2V, IO = 10mA, TA = +25C, BW = 10Hz to 100kHz 80 60 50 45 25 dB dB dB dB VRMS
3
FN6832.0 January 22, 2009
ISL9016
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specifications are measured at the following conditions: TA = +25C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 1.8V; CIN = 1F; CO = 1F. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL tSSR TEST CONDITIONS Slope of linear portion of LDO output voltage ramp during start-up MIN TYP 30 MAX 60 UNITS s/V
PARAMETER LDO Soft-Start Ramp Rate EN PIN CHARACTERISTICS Input Low Voltage Input High Voltage Input Leakage Current
VIL VIH IIL, IIH
TA = -20C to +85
-0.3 1.1
0.4 VIN + 0.3 0.1
V V A
REVERSE CURRENT CHARACTERISTICS Output Reverse Leakage Current (Note 6) NOTES: 5. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.80V. 6. Output reverse leakage current is measured with VIN pin grounded and VOUT pin connected to 5.5V. IORLC VIN = 0V, VOUT = 5.5V 8 15 A
4
FN6832.0 January 22, 2009
ISL9016 Typical Operating Performance
55 QUIESCENT CURRENT (A) QUIESCENT CURRENT (A) 50 T = +50C T = +25C T = +85C 55 T = +85C 50 45 40 T = 0C 35 T = -40C 30 2.4 3.6 4.8 6.0 T = -25C T = +50C T = +25C
45 40 T = 0C T = -25C T = -40C 30 2.4 3.6 4.8 6.0
35
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 1. QUIESCENT CURRENT vs INPUT VOLTAGE (VOUT1 = 2.1V, ONLY LDO1 ENABLED)
FIGURE 2. QUIESCENT CURRENT vs INPUT VOLTAGE (VOUT2 = 2.1V, ONLY LDO2 ENABLED)
85 QUIESCENT CURRENT (A) T = +50C T = +25C 75
55 T = +85C QUIESCENT CURRENT (A) T = +25C 50 T = +50C T = +85C
80
45
70 T = 0C 65 T = -25C T = -40C 60 2.4 3.6 4.8 6.0
40 T = 0C 35 T = -40C 30 3.6 4.4 5.2 6.0 T = -25C
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 3. QUIESCENT CURRENT vs INPUT VOLTAGE (VOUT1 = VOUT2 = 2.1V, LDO1 AND LDO2 ENABLED)
FIGURE 4. QUIESCENT CURRENT vs INPUT VOLTAGE (VOUT1 = 3.3V, ONLY LDO1 ENABLED)
55 QUIESCENT CURRENT (A) QUIESCENT CURRENT (A) T = +25C 50 T = +50C T = +85C
85 T = +25C 80 T = +85C T = +50C 75
45
40 T = -25C 35 T = -40C 30 3.6 4.4
T = 0C
70 T = -25C T = -40C 60 3.6 4.4
T = 0C
65
5.2
6.0
5.2
6.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 5. QUIESCENT CURRENT vs INPUT VOLTAGE (VOUT2 = 3.3V, ONLY LDO2 ENABLED)
FIGURE 6. QUIESCENT CURRENT vs INPUT VOLTAGE (VOUT1 = VOUT2 = 3.3V, LDO1 AND LDO2 ENABLED)
5
FN6832.0 January 22, 2009
ISL9016 Typical Operating Performance
15 10 5 VO (mV) VO (mV) 0 -5 -10 T = -40C -15 1.5 -20 3.0 4.5 6.0 1.5 2.5 3.5 INPUT VOLTAGE (V) 4.5 5.5 INPUT VOLTAGE (V) T = +25C T = +85C 10 5 0 -5 -10 -15 T = +85C T = +25C
T = -40C
FIGURE 7. VOUT vs INPUT VOLTAGE (VOUT_NOMINAL = 1.2V, IOUT = 50mA)
FIGURE 8. VOUT vs INPUT VOLTAGE (VOUT_NOMINAL = 1.2V, IOUT = 150mA)
1.22 T = +85C OUTPUT VOLTAGE (V) 1.21 OUTPUT VOLTAGE (V)
3.32 3.31 3.30 3.29 3.28 3.27 3.26 T = -40C T = -40C T = +85C T = +25C
1.20
1.19
T = +25C
1.18 0 30 60 90 120 150 LOAD CURRENT (mA)
3.25 0 30 60 90 LOAD CURRENT (mA) 120 150
FIGURE 9. LOAD REGULATION (VIN = 1.8V, VOUT = 1.2V)
FIGURE 10. LOAD REGULATION (VIN = 4.5V, VOUT = 3.3V)
EN1 = EN2 5V/DIV
5V/DIV
VIN
VOUT1 (AC COUPLED) 50mV/DIV 1V/DIV VOUT1 50mV/DIV VOUT2 (AC COUPLED)
1V/DIV VOUT2 100s/DIV
200mA/DIV
IOUT1 1ms/DIV
FIGURE 11. ENABLE OPERATION (VIN = 3.6V, VOUT1 = VOUT1 = 1.2V)
FIGURE 12. LOAD TRANSIENT RESPONSE (VIN = 3.6V, VOUT1 = VOUT2 = 1.2V, IOUT1 0.01mA TO 150mA)
6
FN6832.0 January 22, 2009
ISL9016 Typical Operating Performance
5V/DIV VIN 5V/DIV VIN
VOUT1 (AC COUPLED) 50mV/DIV VOUT1 (AC COUPLED) 1ms/DIV VOUT2 (AC COUPLED) 50mV/DIV
50mV/DIV
50mV/DIV
VOUT2 (AC COUPLED) IOUT1
IOUT1 200mA/DIV 1ms/DIV 200mA/DIV
1ms/DIV
FIGURE 13. LOAD TRANSIENT RESPONSE (VIN = 3.6V, VOUT1 = VOUT2 = 1.2V, IOUT2 0.01mA TO 150mA)
FIGURE 14. LOAD TRANSIENT RESPONSE (VIN = 3.6V, VOUT1 = VOUT2 = 3.3V, IOUT1 0.01mA TO 150mA)
VOUT1 (AC COUPLED) 50mV/DIV 100mV/DIV
VOUT (AC COUPLED)
VOUT2 (AC COUPLED) 20mV/DIV
IOUT1 100mA/DIV 1ms/DIV di/dt = 150mA/s 100mA/DIV
IOUT 1ms/DIV di/dt = 150mA/s
FIGURE 15. LOAD TRANSIENT RESPONSE (VIN = 1.8V, VOUT1 = VOUT2 = 1.2V, IOUT1 0.01mA TO 150mA)
FIGURE 16. LOAD TRANSIENT RESPONSE (VIN = 3.3V, VOUT1 = VOUT2 = 1.2V, IOUT1 0.01mA TO 150mA)
7
FN6832.0 January 22, 2009
ISL9016 Pin Descriptions
PIN # 1 2 3 4 5 6 PIN NAME VIN GND EN2 EN1 VOUT2 VOUT1 E-Pad DESCRIPTION Supply Voltage/LDO Input. Connect a 1F capacitor to GND. GND is the connection to system ground. Connect to PCB Ground plane. LDO2 Enable pin. Enable = High, Disable = Low. A 100k resistor should be connected between EN2 and the control voltage rail. Do NOT leave it floating. LDO1 Enable pin. Enable = High, Disable = Low. A 100k resistor should be connected between EN1 and the control voltage rail. Do NOT leave it floating. LDO2 Output. Connect capacitor with a value from 1F to 4.7F to GND (1F recommended). LDO1 Output. Connect capacitor with a value from 1F to 4.7F to GND (1F recommended). Connect the e-pad to the system ground.
Typical Application Diagram
ISL9016 VIN (1.8V TO 6.5V) VIN VOUT1 VOUT2 1.2V~3.3V, 0~150mA GND VOUT2 VOUT1 1.2V~3.3V, 0~150mA
C1 R1 ON OFF
EN2
EN1 ON OFF
C2 R2
C3
C1, C2, C3:1F, X5R (or X7R) CERAMIC CAPACITOR R1, R2: 100k
8
FN6832.0 January 22, 2009
ISL9016 Block Diagram
VOUT2 VOUT1
VIN VIN
REVERSE CURRENT PROTECTION
VOUT1
EN1 UNDERVOLTAGE LOCKOUT CONTROL LOGIC SHORT CIRCUIT THERMAL PROTECTION SOFT-START
EN2
EN1 VREF1 +
LDO-2 LDO-1 VREF1 BANDGAP TEMP-SENSOR VREF2 VREF3
REFERENCE VOLTAGES
GND
Functional Description
ISL9016 contains two high performance LDO's. High performance is achieved through a circuit which delivers fast transient response to varying load conditions. In a quiescent condition, the ISL9016 adjusts its biasing to achieve the lowest standby current consumption. The device also integrates current limit protection, thermal shutdown protection, reverse current protection and soft-start. Thermal shutdown protects the device against overheating. Soft-start limits the start-up input current surges. In some certain application circuits, the output voltage may be externally held up, meanwhile, the input voltage could be connected to ground, or connected to some voltage lower than the output side, or be left open circuit. ISL9016 features the reverse current protection; it can limit the current flow from output to input. This protection will automatically initiate when VOUT is detected to be higher than VIN. When VIN is pulled to ground and VOUT is held at 5.5V, the current flow from VOUT to VIN is typically less than 8A.
LDO1 and/or LDO2 will be enabled accordingly based on the voltage signal applied on its related EN pin and start from the soft-start. Likewise, when one or both EN pins go low, LDO1 and/or LDO2 will be disabled based on the signal applied on its related EN pin. A 100k (or above) pull-up resistor should be connected between ENx pin and the external control voltage (as shown in the "Typical Application Diagram" on page 8).
LDO Protections
ISL9016 offers several protections which make it ideal for using in battery-powered application circuits. ISL9016 provides short-circuit protection by limiting the output current to typical 265mA. When short circuit happens, the circuit is limited at 265mA (typical). If the short circuit lasts long enough, the die temperature increases, and the over-temperature protection circuit will turn off the output. When the die temperature reaches about +145C, the thermal protection starts working. Under the overheat condition, only the LDO sourcing more than 50mA will be shut off. This does not affect the operation of the other LDO. If both LDOs source more than 50mA and an overheat condition occurs, both LDO outputs will be disabled. Once the die temperature falls back to about +110C, the disabled LDO(s) are re-enabled and soft-start automatically takes place. In certain applications, the following input/output situations may occur:
Enable Control
The ISL9016 has two separate enable pins, EN1 and EN2, which independently enable/disable each of the LDO outputs. When both EN1 and EN2 are low, the whole device is in shutdown mode. In this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1mA. When one or both the EN pins go high, the
9
FN6832.0 January 22, 2009
ISL9016
With output voltage externally held up higher than the input voltage: 1. Input is pulled to ground; 2. input is left open circuit; and 3. input is pulled to some intermediate voltage ISL9016 provides the reverse current protection to limit the current flow from output to input under these situations. When input is pulled to ground and output is held to 5.5V, the typical reverse current from output to input side is less than 8A.
Input and Output Capacitors
The ISL9016 provides a linear regulator that has low quiescent current, fast transient response, and overall stability across the recommended operating conditions. A ceramic capacitor (X5R or X7R) with a capacitance of 1F to 4.7F with an ESR up to 200m is suitable for ISL9016 to maintain its output stability. The ground connection of the output capacitor should be connected directly to the GND pin of the device, and also placed close to the device. Similarly for the input capacitor, usually a 1F ceramic capacitor (X5R or X7R) is suitable for most cases, but if large, fast rising-time load transient condition is expected, a higher value input capacitor may be necessary to achieve better performance.
Board Layout Recommendations
A good PCB layout will be an important step to achieve good performance. It is recommended to design the board with separate ground planes for input and output, and connect both ground planes at the GND pin of the device. Consideration should be taken when placing the components and route the trace to minimize the ground impedance, as well as keep the parasitic inductance low. Usually the input/output capacitors should be placed close to the device with good ground connection.
10
FN6832.0 January 22, 2009
ISL9016 Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
E 6 4 A A B
L6.1.6x1.6A
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN 0.45 NOMINAL 0.50 0.127 REF 0.15 1.55 0.40 1.55 0.95 0.20 1.60 0.45 1.60 1.00 0.50 BSC 0.25 0.30 0.35 0.25 1.65 0.50 1.65 1.05 MAX 0.55 0.05 NOTES 4 4 Rev. 1 6/06 NOTES: 1. Dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall not exceed 0.08mm. 3. Warpage shall not exceed 0.10mm. 4. Package length/package width are considered as special characteristics. 5. JEDEC Reference MO-229.
PIN 1 REFERENCE 2X 0.15 C 1 2X 0.15 C TOP VIEW e 1.00 REF 4 6 3
D
A A1 A3
A1
b D D2
L D2 CO.2 DAP SIZE 1.30 x 0.76
E E2 e L
3 E2
1
b 6X 0.10 M C A B
BOTTOM VIEW
DETAIL A 0.10 C 6X 0.08 C A3 SIDE VIEW C SEATING PLANE
6. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
0.1270.008 0.127 +0.058 -0.008 TERMINAL THICKNESS A1 DETAIL A 0.25 0.50
1.00
0.45
1.00 2.00
0.30
1.25
LAND PATTERN
6
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN6832.0 January 22, 2009

▲Up To Search▲

Price & Availability of ISL9016IRUJCZ-T

	To Download ISL9016IRUJCZ-T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .