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HB52E648EN-A6B/B6B, HB52E649EN-A6B/B6B
512 MB Unbuffered SDRAM DIMM, 100 MHz Memory Bus (HB52E648EN) 64-Mword x 64-bit, 2-Bank Module (16 pcs of 32 M x 8 Components) (HB52E649EN) 64-Mword x 72-bit, 2-Bank Module (18 pcs of 32 M x 8 Components) PC100 SDRAM
E0013H10 (1st edition) (Previous ADE-203-1116A (Z)) Preliminary Jan. 19, 2001 Description
The HB52E648EN, HB52E649EN belong to 8-byte DIMM (Dual In-line Memory Module) family, and have been developed as an optimized main memory solution for 8-byte processor applications. They are synchronous Dynamic RAM Module, mounted 256-Mbit SDRAMs (HM5225805BTT) sealed in TSOP package, and 1 piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). The HB52E648EN is organized 32M x 64 x 2-bank mounted 16 pieces of 256-Mbit SDRAM. The HB52E649EN is organized 32M x 72 x 2-bank mounted 18 pieces of 256-Mbit SDRAM. An outline of the products is 168-pin socket type package (dual lead out). Therefore, they make high density mounting possible without surface mount technology. They provide common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.
Features
* Fully compatible with : JEDEC standard outline 8-byte DIMM : Intel PCB Reference design (Rev. 1.0) * 168-pin socket type package (dual lead out) Outline: 133.37 mm (Length) x 34.925 mm (Height) x 4.00 mm (Thickness) Lead pitch: 1.27 mm * 3.3 V power supply * Clock frequency: 100 MHz (max) * LVTTL interface * Data bus width : x 64 Non parity (HB52E648EN)
Preliminary: The specification of this device are subject to change without notice. Please contact your nearest Elpida Memory, Inc. regarding specification. Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB52E648EN/HB52E649EN-A6B/B6B
* * * * * : x 72 ECC (HB52E649EN) Single pulsed RAS 4 Banks can operates simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 1/2/4/8 2 variations of burst sequence Sequential Interleave Programmable CE latency : 2/3 (HB52E648EN/52E649EN-A6B) : 3 (HB52E648EN/52E649EN-B6B) Byte control by DQMB Refresh cycles: 8192 refresh cycles/64 ms 2 variations of refresh Auto refresh Self refresh
* * * *
Ordering Information
Type No. HB52E648EN-A6B HB52E648EN-B6B HB52E649EN-A6B HB52E649EN-B6B Frequency 100 MHz 100 MHz 100 MHz 100 MHz CE latency 2/ 3 3 2/ 3 3 Package 168-pin dual lead out soc ket ty pe Contact pad Gold
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
Preliminary Data Sheet E0013H10 2
HB52E648EN/HB52E649EN-A6B/B6B
(HB52E648EN)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin name VSS DQ0 DQ1 DQ2 DQ3 VC C DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VC C DQ14 DQ15 NC NC VSS NC NC Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Pin name VSS NC S2 DQMB2 DQMB3 NC VC C NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VC C DQ20 NC NC NC (CKE1)* 1 VSS DQ21 DQ22 DQ23 Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Pin name VSS DQ32 DQ33 DQ34 DQ35 VC C DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VC C DQ46 DQ47 NC NC VSS NC NC Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 Pin name VSS CKE0 NC (S3)* 2 DQMB6 DQMB7 NC VC C NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 VC C DQ52 NC NC NC VSS DQ53 DQ54 DQ55
Preliminary Data Sheet E0013H10 3
HB52E648EN/HB52E649EN-A6B/B6B
Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin name VC C W DQMB0 DQMB1 S0 NC VSS A0 A2 A4 A6 A8 A10 (AP) BA1 VC C VC C CK0 Pin No. 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Pin name VSS DQ24 DQ25 DQ26 DQ27 VC C DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VC C Pin No. 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Pin name VC C CE DQMB4 DQMB5 NC (S1)* RE VSS A1 A3 A5 A7 A9 BA0 A11 VC C CK1 A12
3
Pin No. 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
Pin name VSS DQ56 DQ57 DQ58 DQ59 VC C DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VC C
Not es : 1. CKE1: HB52E648EN 2. S3: HB52E648EN 3. S1: HB52E648EN
Preliminary Data Sheet E0013H10 4
HB52E648EN/HB52E649EN-A6B/B6B
(HB52E649EN)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Pin name VSS DQ0 DQ1 DQ2 DQ3 VC C DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VC C DQ14 DQ15 CB0 CB1 VSS NC NC VC C W DQMB0 DQMB1 S0 NC VSS A0 Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin name VSS NC S2 DQMB2 DQMB3 NC VC C NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VC C DQ20 NC NC NC (CKE1)* 1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VC C DQ28 DQ29 Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 Pin name VSS DQ32 DQ33 DQ34 DQ35 VC C DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VC C DQ46 DQ47 CB4 CB5 VSS NC NC VC C CE DQMB4 DQMB5 NC (S1)* RE VSS A1
3
Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159
Pin name VSS CKE0 NC (S3)* 2 DQMB6 DQMB7 NC VC C NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VC C DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VC C DQ60 DQ61
Preliminary Data Sheet E0013H10 5
HB52E648EN/HB52E649EN-A6B/B6B
Pin No. 34 35 36 37 38 39 40 41 42 Pin name A2 A4 A6 A8 A10 (AP) BA1 VC C VC C CK0 Pin No. 76 77 78 79 80 81 82 83 84 Pin name DQ30 DQ31 VSS CK2 NC WP SDA SCL VC C Pin No. 118 119 120 121 122 123 124 125 126 Pin name A3 A5 A7 A9 BA0 A11 VC C CK1 A12 Pin No. 160 161 162 163 164 165 166 167 168 Pin name DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VC C
Not es : 1. CKE1: HB52E649EN 2. S3: HB52E649EN 3. S1: HB52E649EN
Pin Description (HB52E648EN)
Pin name A0 to A12 Function Address input Row address Column address BA0/ BA1 DQ0 to DQ63 S0 to S3 RE CE W DQMB0 t o DQMB7 CK0 to CK3 CKE0, CKE1 WP SDA SCL SA0 to SA2 VC C VSS NC Bank selec t addres s Dat a i put / out put n Chip selec t input Row enable (RAS) input Column enable (CAS) input Writ e enable input By t e d a mas k at Cloc k input Cloc k enable input Writ e prot ec t for serial P D Dat a i put / out put for serial PD n Cloc k input for s erial PD Serial addres s i put n Primary pos it iv e power supply Ground No connec t ion A0 to A12 A0 to A9
Preliminary Data Sheet E0013H10 6
HB52E648EN/HB52E649EN-A6B/B6B
Pin Description (HB52E649EN)
Pin name A0 to A12 Function Address input Row address Column address BA0/ BA1 DQ0 to DQ63 CB0 to CB7 S0 to S3 RE CE W DQMB0 t o DQMB7 CK0 to CK3 CKE0, CKE1 WP SDA SCL SA0 to SA2 VC C VSS NC Bank selec t addres s Dat a i put / out put n Chec k bit (Dat a input / out put ) Chip selec t input Row enable (RAS) input Column enable (CAS) input Writ e enable input By t e d a mas k at Cloc k input Cloc k enable input Writ e prot ec t for serial P D Dat a i put / out put for serial PD n Cloc k input for s erial PD Serial addres s i put n Primary pos it iv e power supply Ground No connec t ion A0 to A12 A0 to A9
Preliminary Data Sheet E0013H10 7
HB52E648EN/HB52E649EN-A6B/B6B
Serial PD Matrix*1
Byte No. Function described 0 1 2 3 4 5 6 Number of bytes used by module manufacturer Total SPD memory size Memory type Number of row addresses bits Number of column addresses bits Number of banks Module data width (HB52E648EN) (HB52E649EN) 7 8 9 Module data width (continued) Module interface signal levels SDRAM cycle time (highest CE latency) 10 ns SDRAM access from Clock (highest CE latency) 6 ns Module configuration type (HB52E648EN) (HB52E649EN) 12 Refresh rate/type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 80 08 04 0D 0A 02 40 48 00 01 A0 128 256 byte SDRAM 13 10 2 64 72 0 (+) LVTTL CL = 3
10
0
1
1
0
0
0
0
0
60
11
0 0 1
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 1 1
0 0 0
00 02 82
Non parity ECC Normal (7.8125 s) Self refresh 32M x 8 -- x8 1 CLK
13 14
SDRAM width
0
0 0 0 0
0 0 0 0
0 0 0 0
1 0 1 0
0 0 0 0
0 0 0 0
0 0 0 1
08 00 08 01
Error checking SDRAM width (HB52E648EN) 0 (HB52E649EN) 0 0
15
SDRAM device attributes: minimum clock delay for back-to-back random column addresses SDRAM device attributes: Burst lengths supported
16
0
0
0
0
1
1
1
1
0F
1, 2, 4, 8
Preliminary Data Sheet E0013H10 8
HB52E648EN/HB52E649EN-A6B/B6B
Byte No. Function described 17 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 0 1 0 0 04 4 SDRAM device attributes: 0 number of banks on SDRAM device SDRAM device attributes: CE latency SDRAM device attributes: S latency SDRAM device attributes: W latency SDRAM module attributes SDRAM device attributes: General SDRAM cycle time (2nd highest CE latency) (-A6B) 10 ns SDRAM cycle time (2nd highest CE latency) (-B6B) 15 ns 24 SDRAM access from Clock (2nd highest CE latency) (-A6B) 6 ns SDRAM access from Clock (2nd highest CE latency) (-B6B) 9 ns 25 SDRAM cycle time (3rd highest CE latency) Undefined SDRAM access from Clock (3rd highest CE latency) Undefined 0 0 0 0 0 1
18 19 20 21 22 23
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0 0 0
0 0 0 0 1 0
1 0 0 0 1 0
1 0 0 0 1 0
0 1 1 0 0 0
06 01 01 00 0E A0
2, 3 0 0 Non buffer VCC 10% CL = 2
1
1
1
1
0
0
0
0
F0
0
1
1
0
0
0
0
0
60
CL = 2
1
0
0
1
0
0
0
0
90
0
0
0
0
0
0
0
0
00
26
0
0
0
0
0
0
0
0
00
27 28 29 30 31 32 33 34
Minimum row precharge time 0 Row active to row active min 0 RE to CE delay min Minimum RE pulse width Density of each bank on module Address and command signal input setup time Address and command signal input hold time 0 0 0 0 0
0 0 0 0 1 0 0 0
0 0 0 1 0 1 0 1
1 1 1 1 0 0 1 0
0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0
14 14 14 32 40 20 10 20
20 ns 20 ns 20 ns 50 ns 2 bank 256 M byte 2.0 ns 1.0 ns 2.0 ns
Data signal input setup time 0
Preliminary Data Sheet E0013H10 9
HB52E648EN/HB52E649EN-A6B/B6B
Byte No. Function described 35 Data signal input hold time Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 1 0 1 0 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 x 1 1 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0 0 0 0 0 1 1 0 0 0 0 x 0 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 x 0 0 1 1 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 x 1 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 x 0 0 1 0 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 1 1 1 0 0 1 0 x 0 1 0 1 0 1 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 x 0 0 1 0 1 0 0 0 1 1 0 1 1 0 0 0 0 0 10 00 12 BA 3A CC 4C 07 00 xx 48 42 35 32 45 36 34 38 39 45 4E 2D 41 42 36 42 20 20 * 3 (ASCII8bit code) H B 5 2 E 6 4 8 9 E N -- A B 6 B (Spac e) (Spac e) 1.0 ns Future use Rev.1.2A 186 58 204 76 HITACHI
36 to 61 Superset information 62 63 SPD data revision code Checksum for bytes 0 to 62 (HB52E648EN-A6B) (HB52E648EN-B6B) (HB52E649EN-A6B) (HB52E649EN-B6B) 64 Manufacturer's JEDEC ID code
65 to 71 Manufacturer's JEDEC ID code 72 73 74 75 76 77 78 79 80 Manufacturing location Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number (HB52E648EN) (HB52E649EN) 81 82 83 84 Manuf ac t urer's p t number ar Manuf ac t urer's p t number ar Manuf ac t urer's p t number ar
Manuf ac turer's part number (HB52E648EN/ 649EN-A6B) 0 (HB52E648EN/ 649EN-B6B) 0
85 86 87 88
Manuf ac t urer's p t number ar Manuf ac t urer's p t number ar Manuf ac t urer's p t number ar Manuf ac t urer's p t number ar
0 0 0 0
Preliminary Data Sheet E0013H10 10
HB52E648EN/HB52E649EN-A6B/B6B
Byte No. Function described 89 90 91 92 93 94 Manuf ac t urer's p t number ar Manuf ac t urer's p t number ar Rev is ion code Rev is ion code Manuf ac t uring dat e Manuf ac t uring dat e Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 0 x x *6 -- -- 1 -- 1 -- 0 -- 0 -- 1 -- 0 -- 0 -- 64 *5 100 MHz 0 0 0 0 x x 1 1 1 1 x x 0 0 1 0 x x 0 0 0 0 x x 0 0 0 0 x x 0 0 0 0 x x 0 0 0 0 x x 20 20 30 20 xx xx (Spac e) (Spac e) I nit ial (Spac e) Year code (BCD)*4 Week code (BCD)*4
95 to 98 As s embly serial number 99 to 125 Manuf ac t urer spec if ic dat a 126 127
I nt el s pec if ic ation frequenc y 0 I nt el s pec ific ation CE# lat enc y s upport (HB52E648EN/ 649EN-A6B) 1 (HB52E648EN/ 649EN-B6B) 1
1 1
1 1
1 1
1 1
1 1
1 0
1 1
FF FD
CL = 2 3 , CL = 3
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" These SPD are based on Intel specification (Rev.1.2A). 2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119. 3. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 4. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is "Binary Coded Decimal". 5. All bits of 99 through 125 are not defined ("1" or "0"). 6. Bytes 95 through 98 are assembly serial number.
Preliminary Data Sheet E0013H10 11
HB52E648EN/HB52E649EN-A6B/B6B
Block Diagram (HB52E648EN)
A0 to A12, BA0, BA1 RE, CE, W S1 S0 CS DQMB0 DQ0 to DQ7 DQM 8 N0, N1 I/O0 to I/O7 CS DQM 8 N2, N3 I/O0 to I/O7 CS CS CS
D0
DQM I/O0 to I/O7 CS DQM I/O0 to I/O7
D8
DQMB4 8 N8, N9 DQ32 to DQ39
DQM I/O0 to I/O7 CS DQM
D4
DQM I/O0 to I/O7 CS DQM I/O0 to I/O7
D12
DQMB1 DQ8 to DQ15
D1
D9
DQMB5
8 N10, N11 I/O0 DQ40 to I/O7 to DQ47
D5
D13
S3 S2 CS DQMB2 DQ16 to DQ23 DQM 8 N4, N5 I/O0 to I/O7 CS DQM 8 N6, N7 I/O0 to I/O7 CS CS CS
D2
DQM I/O0 to I/O7 CS DQM I/O0 to I/O7
D10
DQMB6
DQM
8 N12, N13 I/O0 DQ48 to I/O7 to DQ55 CS DQM
D6
DQM I/O0 to I/O7 CS DQM I/O0 to I/O7
D14
DQMB3 DQ24 to DQ31
D3
D11
DQMB7
8 N14, N15 I/O0 DQ56 to I/O7 to DQ63 VCC
D7
D15
VCC (D0 to D15, U0) C16 to C31 VSS (D0 to D15, U0) CKE (D0 to D7) VCC
R100 CK0 R101 CK1 R102 CK2 R103 CK3 CLK; 4 SDRAMs + 3.3 pF cap CLK; 4 SDRAMs + 3.3 pF cap CLK; 4 SDRAMs + 3.3 pF cap
C0 to C15 VSS
CLK; 4 SDRAMs + 3.3 pF cap CKE0
R0 CKE1 Serial PD SCL SCL SDA SDA WP R1 SA0 SA1 SA2 VSS Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. * D0 to D15: HM5225805 U0: 2-kbit EEPROM C0 to C15: 0.33 F, C16 to C31: 0.10 F R0: 10 k, R1: 47 k N0 to N15: Network registor 10 R100 to R103: 10 CKE (D8 to D15)
U0
A0 A1 A2
Preliminary Data Sheet E0013H10 12
HB52E648EN/HB52E649EN-A6B/B6B
Block Diagram (HB52E649EN)
A0 to A12, BA0, BA1 RE, CE, W S1 S0 CS DQMB0 DQ0 to DQ7 DQM 8 N0, N1 I/O0 to I/O7 CS DQM 8 N2, N3 I/O0 to I/O7 CS DQM CB0 to CB7 S3 S2 CS DQMB2 DQ16 to DQ23 DQM 8 N6, N7 I/O0 to I/O7 CS DQM 8 N8, N9 I/O0 to I/O7 CS CS CS 8 N4, N5 I/O0 to I/O7 CS CS CS
D0
DQM I/O0 to I/O7 CS DQM I/O0 to I/O7 CS
D9
DQMB4
DQM
8 N10, N11 I/O0 DQ32 to I/O7 to DQ39 CS DQM
D5
DQM I/O0 to I/O7 CS DQM I/O0 to I/O7
D14
DQMB1 DQ8 to DQ15
D1
D10
DQMB5
8 N12, N13 I/O0 DQ40 to I/O7 to DQ47
D6
D15
DQM
D2
I/O0 to I/O7
D11
D3
DQM I/O0 to I/O7 CS DQM I/O0 to I/O7
D12
DQMB6
DQM
8 N14, N15 I/O0 DQ48 to I/O7 to DQ55 CS DQM
D7
DQM I/O0 to I/O7 CS DQM I/O0 to I/O7
D16
DQMB3 DQ24 to DQ31
D4
D13
DQMB7
8 N16, N17 I/O0 DQ56 to I/O7 to DQ63 VCC
D8
D17
R100 CK0 R101 CK1 R102 CK2 R103 CK3 CLK (4 SDRAMs + 3.3 pF cap) CLK (4 SDRAMs + 3.3 pF cap) CLK (5 SDRAMs) CLK (5 SDRAMs)
VCC (D0 to D17, U0) C18 to C35 VSS (D0 to D17, U0) CKE (D0 to D8) VCC R0
C0 to C17 VSS CKE0
CKE1 Serial PD SCL SCL SDA
CKE (D9 to D17)
SDA WP R1
U0
A0 A1 A2
VSS SA0 SA1 SA2 Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. 3. SDRAM D11 DQMB input is wired to DQMB5 * D0 to D17: HM5225805 U0: 2-kbit EEPROM C0 to C17: 0.33 F, C18 to C35: 0.10 F R0: 10 k, R1: 47 k N0 to N17: Network registor 10
R100 to R103: 10
Preliminary Data Sheet E0013H10 13
HB52E648EN/HB52E649EN-A6B/B6B
Absolute Maximum Ratings
Parameter Volt age on any pn relat ive to VSS i Supply volt age r at iv e to VSS el Short c irc uit out put current Power dis s ipat ion (HB52E648EN) Power dis s ipat ion (HB52E649EN) Operating temperat ure St orage temperature Not e: 1. Res pect to VSS Symbol VT VC C I out PT PT Topr Ts t g Value -0. 5 to VC C + 0. 5 ( 4. 6 (max )) -0. 5 to +4. 6 50 8. 0 9. 0 0 to + 65 -55 to +125 Unit V V mA W W C C Note 1 1
DC Operating Conditions (Ta = 0 to +65C)
Parameter Supply volt age Symbol VC C VSS I nput high volt age I nput low volt age Not es : 1. 2. 3. 4. 5. VIH VIL Min 3. 0 0 2. 0 -0. 3 Max 3. 6 0 VC C + 0. 3 0. 8 Unit V V V V Notes 1, 2 3 1, 4 1, 5
All volt age ref erred to VSS The supply volt age wit h all VC C pins mus t be on the same lev el. The supply volt age wit h all VSS pins mus t be on the same lev el. VIH (max ) = VC C + 2. 0 V for puls e wit h 3 ns at VC C . VIL (min) = VSS - 2. 0 V for puls e widt h 3 ns at VSS.
Preliminary Data Sheet E0013H10 14
HB52E648EN/HB52E649EN-A6B/B6B
VIL/VIH Clamp (Component characteristic)
This SDRAM component has VIL and V IH clamp for CK, CKE, S, DQMB and DQ pins. Minimum VIL Clamp Current
VIL (V) -2 -1. 8 -1. 6 -1. 4 -1. 2 -1 -0. 9 -0. 8 -0. 6 -0. 4 -0. 2 0 I (mA) -32 -25 -19 -13 -8 -4 -2 -0. 6 0 0 0 0
0 -5 -10 I (mA) -15 -20 -25 -30 -35
-2
-1.5
-1
-0.5
0
VIL (V)
Preliminary Data Sheet E0013H10 15
HB52E648EN/HB52E649EN-A6B/B6B
Minimum VIH Clamp Current
VIH (V) VC C + 2 VC C + 1. 8 VC C + 1. 6 VC C + 1. 4 VC C + 1. 2 VC C + 1 VC C + 0. 8 VC C + 0. 6 VC C + 0. 4 VC C + 0. 2 VC C + 0 I (mA) 10 8 5. 5 3. 5 1. 5 0. 3 0 0 0 0 0
10 8 I (mA) 6 4 2 0 VCC + 0 VCC + 0.5 VCC + 1 VIH (V) VCC + 1.5 VCC + 2
Preliminary Data Sheet E0013H10 16
HB52E648EN/HB52E649EN-A6B/B6B
IOL/IOH Characteristics (Component characteristic)
Output Low Current (IOL)
I OL Vout ( V) 0 0. 4 0. 65 0. 85 1 1. 4 1. 5 1. 65 1. 8 1. 95 3 3. 45 Mi n (mA) 0 27 41 51 58 70 72 75 77 77 80 81 I OL Max (mA) 0 71 108 134 151 188 194 203 209 212 220 223
250
200 IOL (mA)
150 min max 100
50
0 0 0.5 1 1.5 2 Vout (V) 2.5 3 3.5
Preliminary Data Sheet E0013H10 17
HB52E648EN/HB52E649EN-A6B/B6B
Output High Current (I OH ) (Ta = 0 to 65C, V CC = 3.0 V to 3.45 V, VSS = 0 V)
I OH Vout ( V) 3. 45 3. 3 3 2. 6 2. 4 2 1. 8 1. 65 1. 5 1. 4 1 0 Mi n (mA) -- -- 0 -21 -34 -59 -67 -73 -78 -81 -89 -93 I OH Max (mA) -3 -28 -75 -130 -154 -197 -227 -248 -270 -285 -345 -503
0
0
0.5
1
1.5
2
2.5
3
3.5
-100
IOH (mA)
-200 min -300 max
-400
-500
-600 Vout (V)
Preliminary Data Sheet E0013H10 18
HB52E648EN/HB52E649EN-A6B/B6B
DC Characteristics (Ta = 0 to 65C, VCC = 3.3 V 0.3 V, VSS = 0 V) (HB52E648EN)
HB52E648EN -A6B/B6B Parameter Operating current (CE lat enc y = 2) (CE lat enc y = 3) St andby current in power d own St andby current in power d own (input signal stable) St andby current in non power down Symbol Min ICC1 ICC1 I C C 2P I C C 2PS I C C 2N -- -- -- -- -- -- -- Max 1000 1000 48 32 320 64 480 Unit mA mA mA mA mA mA mA CKE = VIL, tC K = 12 ns CKE = VIL, tC K = CKE, S = VIH , t C K = 12 ns CKE = VIL, tC K = 12 ns CKE, S = VIH , t C K = 12 ns t C K = min, BL = 4 ICC4 ICC4 ICC5 ICC6 I LI I LO VOH VOL -- -- -- -- -10 -10 2. 4 -- 1040 1040 2000 48 10 10 -- 0. 4 mA mA mA mA A A V V t R C = min VIH VC C - 0. 2 V VIL 0. 2 V 0 Vin VC C 0 Vout VC C DQ = ds able i I OH = -4 mA I OL = 4 m A 3 8 6 7 4 1, 2, 6 1, 2, 4 1, 2, 5 Test conditions Burs t lengt h = 1 t R C = min Notes 1, 2, 3
Ac t iv e st andby current in power I C C 3P down Ac t iv e st andby current in non power down Burs t operat ing c urrent (CE lat enc y = 2) (CE lat enc y = 3) Ref resh current Self r res h current ef I nput leak age current Out put leak age current Out put high voltage Out put low volt age I C C 3N
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK operating current. 7. After power down mode, no CK operating current. 8. After self refresh mode set, self refresh current.
Preliminary Data Sheet E0013H10 19
HB52E648EN/HB52E649EN-A6B/B6B
DC Characteristics (Ta = 0 to 65C, VCC = 3.3 V 0.3 V, VSS = 0 V) (HB52E649EN)
HB52E649EN -A6B/B6B Parameter Operating current (CE lat enc y = 2) (CE lat enc y = 3) St andby current in power d own St andby current in power d own (input signal stable) St andby current in non power down Symbol Min ICC1 ICC1 I C C 2P I C C 2PS I C C 2N -- -- -- -- -- -- -- Max 1125 1125 54 36 360 72 540 Unit mA mA mA mA mA mA mA CKE = VIL, tC K = 12 ns CKE = VIL, tC K = CKE, S = VIH , t C K = 12 ns CKE = VIL, tC K = 12 ns CKE, S = VIH , t C K = 12 ns t C K = min, BL = 4 ICC4 ICC4 ICC5 ICC6 I LI I LO VOH VOL -- -- -- -- -10 -10 2. 4 -- 1170 1170 2250 54 10 10 -- 0. 4 mA mA mA mA A A V V t R C = min VIH VC C - 0. 2 V VIL 0. 2 V 0 Vin VC C 0 Vout VC C DQ = ds able i I OH = -4 mA I OL = 4 m A 3 8 6 7 4 1, 2, 6 1, 2, 4 1, 2, 5 Test conditions Burs t lengt h = 1 t R C = min Notes 1, 2, 3
Ac t iv e st andby current in power I C C 3P down Ac t iv e st andby current in non power down Burs t operat ing c urrent (CE lat enc y = 2) (CE lat enc y = 3) Ref resh current Self r res h current ef I nput leak age current Out put leak age current Out put high voltage Out put low volt age I C C 3N
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK operating current. 7. After power down mode, no CK operating current. 8. After self refresh mode set, self refresh current.
Preliminary Data Sheet E0013H10 20
HB52E648EN/HB52E649EN-A6B/B6B
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V) (HB52E648EN)
Parameter I nput c apac it ance (Addres s) I nput c apac it ance (RE, CE, W) I nput c apac it ance (CKE) I nput c apac it ance (S) I nput c apac it ance (CK) I nput c apac it ance (DQMB) I nput /Out put capac it anc e ( DQ) Not es : 1. 2. 3. 4. Symbol CI1 CI2 CI3 CI4 CI5 CI6 CI/O1 Max 105 90 68 38 50 23 22 Unit pF pF pF pF pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
Capac it anc e measured wit h Boont on Met er or ef fec t iv e capac it anc e m uring m hod. eas et Meas urement condit ion: f = 1 MHz , 1 4 V bias , 200 mV swing. . DQMB = VIH to dis able Dat a-out . This p amet er i sampled and not 100% tes t ed. ar s
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V) (HB52E649EN)
Parameter I nput c apac it ance (Addres s) I nput c apac it ance (RE, CE, W) I nput c apac it ance (CKE) I nput c apac it ance (S) I nput c apac it ance (CK) I nput c apac it ance (DQMB) I nput /Out put capac it anc e ( DQ) Not es : 1. 2. 3. 4. Symbol CI1 CI2 CI3 CI4 CI5 CI6 CI/O1 Max 112 97 70 40 50 27 22 Unit pF pF pF pF pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
Capac it anc e measured wit h Boont on Met er or ef fec t iv e capac it anc e m uring m hod. eas et Meas urement condit ion: f = 1 MHz , 1. 4 V bias , 200 mV swing. DQMB = VIH to dis able Dat a-out . This p amet er i sampled and not 100% tes t ed. ar s
Preliminary Data Sheet E0013H10 21
HB52E648EN/HB52E649EN-A6B/B6B
AC Characteristics (Ta = 0 to 65C, VCC = 3.3 V 0.3 V, VSS = 0 V)
HB52E648EN/649EN -A6B/B6B Parameter Sy s t em cloc k cy cle time (CE lat enc y = 2) (CE lat enc y = 3) CK high puls e widt h CK low puls e widt h Ac c es s time from CK (CE lat enc y = 2) (CE lat enc y = 3) Dat a-out hold time CK to Dat a-out l w impedanc e o CK to Dat a-out hgh impedanc e i Dat a-in set up time Dat a i hold time n Address set up time Address hold time CKE set up time CKE set up time for power d own ex it CKE hold time Command set up time Command hold time Ref / Act iv e to Ref / Ac t iv e command period Ac t iv e to prec harge command period Ac t iv e command to column command (s ame bank ) Prec harge to ac tiv e command period Symbol tCK tCK t C KH t C KL t AC t AC t OH t LZ tHZ tDS tDH t AS t AH t C ES t C ESP t C EH tCS tCH tRC t R AS tRCD tRP Ts i Thi Ts i Thi Ts i Tpde Thi Ts i Thi Trc Tras Trc d Trp Tdpl Trrd PC100 Symbol Tc lk Tc lk Tc h Tc l Tac Tac Toh Min 10 10 3 3 -- -- 3 2 -- 2 1 2 1 2 2 1 2 1 70 50 20 20 20 20 1 -- Max -- -- -- -- 6 6 -- -- 6 -- -- -- -- -- -- -- -- -- -- 120000 -- -- -- -- 5 64 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 1, 2 1, 2, 3 1, 4 1 1 1 1 1, 5 1 1 1 1 1 1 1 1 1 1 1 1 1, 2 Notes 1
Writ e rec ov ery o dat a-in t o prec harge t D PL r lead time Ac t iv e (a) to Act iv e (b) command period Trans it ion time (ris e and f all) Ref resh period tRRD tT t R EF
Preliminary Data Sheet E0013H10 22
HB52E648EN/HB52E649EN-A6B/B6B
Notes: 1. 2. 3. 4. 5. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is C L = 50 pF. t LZ (min) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions * Input and output timing reference levels: 1.5 V * Input waveform and output load: See following figures
2.4 V
input
0.4 V
2.0 V 0.8 V
DQ CL t
T
tT
Preliminary Data Sheet E0013H10 23
HB52E648EN/HB52E649EN-A6B/B6B
Relationship Between Frequency and Minimum Latency
HB52E648EN/649EN Parameter Frequency (MHz) tCK (ns) -A6B/B6B 100 PC100 Symbol Symbol 10 2 7 5 2 Tdpl 2 2 Ts rx Tdal 1 4 7 Notes 1 = [I R AS + IR P] 1 1 1 1 1 2 = [I D PL + IR P] = [I R C ] 3
Ac t iv e command to column command (s ame bank ) I R C D Ac t iv e command to ac t iv e command (s ame bank ) I R C Ac t iv e command to prec harge command (s ame bank ) Prec harge command to ac t ive command (s ame bank ) Writ e rec ov ery o dat a-in to prec harge command r (s ame bank ) Ac t iv e command to ac t iv e command (dif f erent bank ) Self r res h ex it time ef Las t d a in to ac t iv e command at (Aut o prec harge, same bank) Self r res h ex it to command input ef Prec harge command to high impedanc e (CE lat enc y = 2) (CE lat enc y = 3) I R AS IRP I D PL IRRD I SR EX I APW I SEC
I H ZP I H ZP
Troh Troh
2 3 1
Las t d a out to ac t iv e command (auto prec harge) I APR at (s ame bank ) Las t d a out to prec harge (early prec harge) at (CE lat enc y = 2) (CE lat enc y = 3) Column command to column command Writ e c ommand to dat a in l t enc y a DQMB to dat a in DQMB to dat a out CKE to CK dis able Regis ter set to ac t iv e command S to command dis able Power down ex it t o command input I EP I EP ICCD I WC D I D ID I D OD I C LE I R SA ICDD I PEC Tc c d Tdwd Tdqm Tdqz Tc k e Tmrd
-1 -2 1 0 0 2 1 1 0 1
Preliminary Data Sheet E0013H10 24
HB52E648EN/HB52E649EN-A6B/B6B
Not es : 1. I R C D to IR R D are r ommended value. ec 2. Be valid [DSEL] or [NOP] a nex t command of self ref res h ex it . t 3. Ex c ept [DSEL] and [NOP]
Preliminary Data Sheet E0013H10 25
HB52E648EN/HB52E649EN-A6B/B6B
Pin Functions
CK0 to CK3 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK rising edge. S0 to S3 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or write command cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1 (BS) is precharged. BA0/BA1 (input pin): BA0/BA1 are bank select signal (BS). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA1 is Low and BA0 is Low, bank 0 is selected. If BA1 is High and BA0 is Low, bank 1 is selected. If BA1 is Low and BA0 is High, bank 2 is selected. If BA1 is High and BA0 is High, bank 3 is selected. CKE0, CKE1 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down and clock suspend modes. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z. Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written. DQ0 to DQ63 (input/output pins): Data is input to and output from these pins. CB0 to CB7 (input/output pins): Data is input to and output from these pins. VCC (power supply pins): 3.3 V is applied. VSS (power supply pins): Ground is connected.
Detailed Operation Part
Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet.
Preliminary Data Sheet E0013H10 26
HB52E648EN/HB52E649EN-A6B/B6B
Physical Outline
Unit: mm inch 133.37 0.15 5.251 0.006 (DATUM -A-) 4.00 max 0.157 max
Front side
3.00 typ 0.118 typ (63.67) (2.51)
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Front) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 84 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
C 11.43 0.450 36.83 1.450 B 54.61 2.150 A
, , , , , , ,
3.00 0.10 0.118 0.004
1.27 0.10 0.050 0.004
Back side 4.00 0.10 0.157 0.004 2 - 3.00 0.10 2 - 0.118 0.003 85
127.35 0.15 5.014 0.006
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Back) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (DATUM -A-)
Detail A 2.50 0.20 0.098 0.008 0.20 0.15 0.010 0.0004 1.27 0.050 Detail B R FULL (DATUM -A-) Detail C 1.00 0.039 168
17.80 0.70
R FULL
3.125 0.125 0.123 0.005
1.00 0.05 0.039 0.002
Note: Tolerance on all dimensions 0.15/0.006 unless otherwise specified.
Preliminary Data Sheet E0013H10 27
3.125 0.125 0.123 0.005
6.35 0.250 2.00 0.10 0.079 0.004
6.35 0.250 4.175 0.164 2.00 0.10 0.079 0.004
34.925 1.375
4.00 min 0.157 min
HB52E648EN/HB52E649EN-A6B/B6B
Cautions
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products.
Preliminary Data Sheet E0013H10 28

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