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| SPT9110 100 MSPS SINGLE-TO-DIFFERENTIAL TRACK-AND-HOLD FEATURES * 400 MHz Sampling Bandwidth * 100 MHz Sampling Rate * Excellent Hold Mode Distortion -66 dB @ 50 MSPS (fIN = 25 MHz) -58 dB @ 100 MSPS (fIN = 50 MHz) * Track Mode Slew Rate: 700 V/s * Low Power: 120 mW Differential Mode 75 mW Single-Ended Mode * Single +5 V Supply * Internal +2.5 V Reference APPLICATIONS * * * * THA for Differential ADCs RF Demodulation Systems Test Instrumentation Digital Sampling Oscilloscopes GENERAL DESCRIPTION The SPT9110 is a single-to-differential track-and-hold amplifier. It can be operated as a single-end THA only or, in full configuration, as a single-to-differential THA. An internal reference provides the common-mode voltage for the singleto-differential output stage. The THA, inverter and reference have separate power supply pins so each can be optionally powered up and used. This device provides an analog designer with a low cost single-to-differential THA amplifier for interfacing differential and single-ended ADCs. The SPT9110 is offered in a 28-lead SOIC package in the industrial temperature range. BLOCK DIAGRAM AVCC (THA) AVCC Out+ (INV) Analog In (VIN) 1X 1X Invert InA CHOLD 1 k R1 1 k R2 Out+ Invert InB +2.5 V Reference CLK NCLK AVCC (Ref) Ref Out Ref In AGND ABSOLUTE MAXIMUM RATING (Beyond which damage may occur)1 Supply Voltages AVCC Supplies ............................................. -0.5 to +6 V Input Voltages Analog Input Voltage .................................... -0.5 to +6 V CLK, NCLK Input .......................................... -0.5 to +6 V Ref In ............................................................ -0.5 to +6 V Output Currents2 Continuous Output Current ................................. 15 mA Temperature Operating Temperature .............................. -40 to +85 C Junction Temperature ......................................... +150 C Lead, Soldering (10 seconds) ............................. +220 C Storage ..................................................... -65 to +150 C Note 1: Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal applied conditions in typical application. Note 2: Outputs are short circuit protected. ELECTRICAL SPECIFICATIONS AVCC = +5.0 V, AGND = 0.0 V, Output Load = 1 k and 10 pF, VIN = 2.0 Vp-p,Internal Reference, unless otherwise specified. PARAMETERS DC Performance Gain VIN = 2.0 Vp-p Single Ended Out Differential Out Offset VIN = +2.5 V Out+ Differential1 Output Drive Capacity2 Output Load at 10 pF Analog Input/Output Output Voltage Range Input Capacitance Input Resistance Reference Voltage Output Reference Output Current3 Reference Voltage Tempco Clock Inputs Input Type/Logic Family Input Bias Current Input Low Voltage (Differential) Input High Voltage (differential) TEST CONDITIONS TEST LEVEL MIN SPT9110 TYP MAX UNITS +25 C Full Temperature +25 C Full Temperature +25 C Full Temperature +25 C, Ref In=Out+ CM Full Temperature Full Temperature Full Temperature Full Temperature +25 C +25 C +25 C Full Temperature I V I V I V I V IV V VI V I I V V V I I I 0.95 1.80 0.97 0.96 1.93 1.92 50 55 5 10 1 1 0.99 2.00 V/V V/V V/V V/V mV mV mV mV mA k V pF k V A ppm/C -100 -15 +100 15 10 1.5 100 2.35 5 140 2.45 100 75 3.5 2.55 +25 C +25 C +25 C Differential PECL 2 3.3 3.9 4.1 10 3.5 A V V 1Differential offset is specified with Ref In equal to the common mode output voltage of OUT+ and so includes the offset error of the inverter only. 2This part is intended to drive a high impedance load. AC performance is degraded at 10 mA. See the Typical Performance Graphs. 3Ref Out has a typical output impedance of 1 k and should be buffered for driving loads other than Ref In. SPT9110 2 11/12/98 ELECTRICAL SPECIFICATIONS AVCC = +5.0 V, AGND = 0.0 V, Output Load = 1 k and 10 pF, VIN = 2.0 Vp-p,Internal Reference, unless otherwise specified. PARAMETERS Track Mode Dynamics Bandwidth (-3 dB) Single Ended Out Differential Out Slew Rate 2.0 Vp-p Output Step Single Ended Out Differential Out7 Input RMS Spectral Noise Track-to-Hold Switching Aperture Delay Aperture Jitter Pedestal Offset Hold Mode Dynamics4 (VIN = 1 Vp-p) Worst Harmonic 5 MHz, 50 MSPS, Single-Ended Worst Harmonic 5 MHz, 50 MSPS, Differential Worst Harmonic 25 MHz, 50 MSPS, Single-Ended Worst Harmonic 25 MHz, 50 MSPS, Differential Worst Harmonic 50 MHz, 100 MSPS, Single-Ended Worst Harmonic 50 MHz, 100 MSPS, Differential Sampling Bandwidth5 (-3 dB) VIN = 2.0 Vp-p Hold Noise6 (RMS) Droop Rate, VIN = +2.5 V Feedthrough Rejection (50 MHz) VIN= 2 Vp-p TEST CONDITIONS +25 C TEST LEVEL MIN SPT9110 TYP MAX UNITS V V +25 C 20 pF Load 20 pF Load Single Ended Differential +25 C +25 C +25 C Full Temperature 220 140 580 800 3.5 13.0 250 <1 12 12 MHz MHz V/s V/s nV/ Hz IV IV V V V V IV V nV/ Hz ps ps rms mV mV TA = +25 C TA = -40 C to +85 C TA = +25 C TA = -40 C to +85 C TA = +25 C TA = -40 C to +85 C TA = +25 C TA = -40 C to +85 C TA = +25 C TA = -40 C to +85 C TA = +25 C TA = -40 C to +85 C +25 C +25 C +25 C Full Temperature Full Temperature IV V IV V V V V V IV V IV V V V IV IV V -64 -68 -64 -65 -63 -66 -63 -64 -60 dB dB dB dB dB dB dB dB dB dB dB dB MHz mV/s mV/s mV/s dB -61 -54 -58 -54 -54 -50 400 300 x tH 40 80 -65 -50 4. For hold times longer than 50 ns, the input common mode voltage may affect the hold mode distortion. (This is due to nonlinear droop that varies with VCM.) For optimal performance, CADEKA recommends that the held output signal be used within 50 ns of the application of the hold signal. 5. Sampling bandwidth is defined as the -3 dB frequency response of the input sampler to the hold capacitor when operating in the sampling mode. It is greater than tracking bandwidth because it does not include the bandwidth of the output amplifier. 6. Hold mode noise is proportional to the length of time a signal is held. This value must be combined with the track mode noise to obtain total noise. 7. Optimized for hold mode performance and low power. SPT9110 3 11/12/98 ELECTRICAL SPECIFICATIONS AVCC = +5.0 V, AGND = 0.0 V, RLoad = 1 k and 10 pF, VIN = 2.0 Vp-p, Internal Reference, unless otherwise specified. PARAMETERS Hold-to-Track Switching8 Acquisition Time to 0.1% 1 V Output Step Acquisition Time to 0.025% 1 V Output Step Power Supplies Supply Voltage Supply Current Single Ended Output Mode9 Differential Output Mode Power Dissipation Single Ended Output Mode9 Differential Output Mode Power Supply Rejection Ratio Single-Ended Output 8. Measured at the hold capacitor. 9. Inverter powered down. TEST CONDITIONS +25 C +25 C TEST LEVEL V V MIN SPT9110 TYP 3.5 4.0 MAX UNITS ns ns IV I 4.75 5 15 24 75 120 44 5.25 20 30 100 150 V mA mA mW mW dB I I +25 C VCC = 0.5 VP-P I V TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/ max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 C. Parameter is guaranteed over specified temperature range. SPT9110 4 11/12/98 TIMING SPECIFICATION DEFINITIONS ACQUISITION TIME This is the time it takes the SPT9110 to acquire the analog signal at the internal hold capacitor when it makes a transition from hold mode to track mode. (See figure 1.) The acquisition time is measured from the 50% input clock transition point to the point when the signal is within a specified error band at the internal hold capacitor (ahead of the output amplifier). It does not include the delay and settling time of the output amplifier. Because the signal is internally acquired and settled at the hold capacitor before the output voltage has settled, the sampler can be put in hold mode before the output has settled. TRACK-TO-HOLD SETTLING TIME The time required for the output to settle to within 4 mV of its final value. APERTURE DELAY The aperture delay time is the interval between the leading edge transition of the clock input and the instant when the input signal was equal to the held value. It is the difference in time between the digital hold switch delay and the analog signal propagation time. Figure 1 - Timing Diagram Aperture Delay Input Acquisition Time Observed at Hold Capacitor Output Observed at Amplifier Output Track-to-Hold Settling CLK Hold Track Hold NCLK SPT9110 5 11/12/98 Figure 2 - Typical Output Response to Step Input Out- 500 mV/ Division Inp ut Out+ Out+ -- Out- 1.0 ns/Division GENERAL DESCRIPTION The SPT9110 is a low cost 100 MSPS track-and-hold amplifier with single ended (75 mW) or differential output (120 mW). It consists of three components. The first is a single-ended track-and-hold amplifier (THA) with a 1.5 to 3.5 V input range and PECL clock inputs. The second is an inverting op amp with gain of -1 to provide the differential output (OUT-). The third component is a 2.5 V bandgap reference for the inverter. PARTITIONED POWER SUPPLY MANAGEMENT Three separate +5 V supply connections power the THA, inverting the op amp and bandgap reference. Unused components can be powered off to minimize power dissipation. The single-ended mode requires use of only the THA and output on the OUT+ pin. In this mode the reference and inverter may be powered down. The differential mode requires use of all three components (unless an external reference is supplied). The output is measured between OUT+ and OUT- in this mode. SPT9110 6 11/12/98 Figure 3 - Typical Interface Circuit (Single-Ended Operational Design) 1 F (TTL to PECL Translator) A+5V 300 + 50 1 GND(THA) XUF (Dependent on Frequency) Analog In A+5V 0.01 F 3 + 7 OP191 4 6 22 0.1 F 50 2 GND(THA) 3 Analog IN 4 GND(SUB) 5 GND(THA) 6 GND(CAP) CLK CLK AVCC(THA) AVCC(THA) AVCC(THA) 28 27 26 4.7 F 25 24 23 22 21 20 19 18 17 16 15 0.01 F 22 N/C N/C N/C N/C N/C A+5V 0.01 F OUT + A+5V 10 50 1 2 3 4 MC100ELT22 0.01 F (+3.0 V) (Optional Level-Shift Circuit) Q0 Q0 Q1 Q1 VCC 8 7 DO D1 GND 6 5 0.1 F TTL Clock (Sample Clock, up to 100 MHz) 2- 7 GND(THA) (+2.5 V) N/C + SPT9110 AVCC(THA) AVCC(THA) OUT+ INV A INV B OUTAVCC(INV) AVCC(INV) AVCC(ESD) 8 GND(THA) 9 REF IN 10 REF OUT 11 AVCC(Ref) 12 GND(Ref) 0.01 F 13 GND(SUB) 14 GND(INV) 4.7 F 0.01 F A+5V 4.7 F + Notes: 1. Input signal is typically at a +2.5 V offset. The optional level-shift circuit may be eliminated if driving from a source that already provides for this offset. 2. The device may be operated from -5 V supply on GND pins and 0 V on AVCC pins. All input and output pins will be shifted by -5 V. The use of an ECL level may be used to drive the clock inputs. 3. VCC (ESD) is the high voltage for the ESD protection diodes and must be connected in all applications. NOTE: It should be tied to VCC (THA), not to VCC (INV). Figure 4 - Typical Interface Circuit (Differential Operational Design) 1 F (TTL to PECL Translator) A+5V 300 + 50 1 GND(THA) XUF (Dependent on Frequency) Analog In A+5V 0.01 F 3 + 7 OP191 4 6 22 0.1 F 50 2 GND(THA) 3 Analog IN 4 GND(SUB) 5 GND(THA) 6 GND(CAP) CLK CLK AVCC(THA) AVCC(THA) AVCC(THA) 28 27 26 4.7 F 25 + 24 23 22 21 20 19 18 17 16 15 22 OUT0.01 F + 4.7 F A+5V 22 0.01 F OUT+ A+5V 10 50 1 2 3 4 MC100ELT22 0.01 F (+3.0 V) (Optional Level-Shift Circuit) Q0 Q0 Q1 Q1 VCC 8 7 DO D1 GND 6 5 0.1 F TTL Clock (Sample Clock, up to 100 MHz) 2- 7 GND(THA) (+2.5 V) + 4.7 F 0.01 F A+5V 4.7 F 0.01 F + 11 AVCC(Ref) 12 GND(Ref) 13 GND(SUB) 14 GND(INV) 8 GND(THA) 9 REF IN 10 REF OUT SPT9110 AVCC(THA) AVCC(THA) OUT+ INV A INV B OUTAVCC(INV) AVCC(INV) AVCC(ESD) (Differential Output) Notes: 1. Input signal is typically at a +2.5 V offset. The optional level-shift circuit may be eliminated if driving from a source that already provides for this offset. 2. The device may be operated from -5 V supply on GND pins and 0 V on AVCC pins. All input and output pins will be shifted by -5 V. The use of an ECL level may be used to drive the clock inputs. 3. VCC (ESD) is the high voltage for the ESD protection diodes and must be connected in all applications. NOTE: It should be tied to VCC (THA), not to VCC (INV). SPT9110 7 11/12/98 TYPICAL PERFORMANCE CHARACTERISTICS Single-Ended (OUT+) Hold Mode Distortion vs. Sample Rate -65 Input = 25 MHz -60 Track Mode Bandwidth +2 OUT+ 0 Worst Harmonic (dB) -55 dB -50 Input = 50 MHz -45 -2 -4 OUT-40 50 -6 70 90 110 130 150 Sample Rate (MSPS) 170 190 0 40 80 120 Input Frequency (MHz) 160 200 Reference Output Voltage vs. Temperature 2.5 900 Slew Rate vs. Temperature VOUT = 2 VP-P 2.49 700 OUT+ Volts 2.48 V/s 500 2.47 OUT- 2.46 -50 0 Temperature (C) +50 100 300 -50 0 Temperature (C) 50 100 Differential Track Mode Distortion vs. Input Frequency -75 VIN = 1 VP-P Single Ended Track Mode Distortion vs. Input Frequency -75 -70 VIN = 1VP-P -70 -65 OUT+ Worst Harmonics (dB) Worst Harmonic (dB) -65 -60 -55 -50 OUT-45 -60 -55 -40 -50 0 5 10 15 20 25 Input Frequency (MHz) 30 35 40 -35 10 20 30 40 50 Input Frequency (MHz) 60 70 80 SPT9110 8 11/12/98 TYPICAL PERFORMANCE CHARACTERISTICS Track Mode Distortion vs. AC Coupled Resistive Load -70 -65 fIN = 40 MHz, 1 VP-P CLoad = 10 pF Hold Mode Distortion vs. Temperature -78 -76 Worst Harmonic (dB) fIN = 5 MHz, fS = 50 MSPS OUT+ Worst Harmonic (dB) -60 -55 -50 THA RLoad CLoad 0.01 F -74 -72 Out-70 -68 -45 -40 -35 Out+ 2000 1750 1500 1250 1000 750 RLoad (Ohms) 500 250 0 -66 -40 -20 0 20 C 40 60 80 100 Hold Mode Distortion vs. Temperature -70 OUT+ -60 Hold Mode Distortion vs. Temperature -65 fIN = 50 MHz, fS = 100 MSPS fIN = 25 MHz, fS = 50 MSPS -65 Worst Harmonic (dB) Worst Harmonic (dB) -55 -60 OUT- -50 -55 -45 -50 -40 -20 0 20 C 40 60 80 100 -40 -40 -20 0 20 C 40 60 80 100 DC Parameters vs. Temperature 80 (VIN = 2.5 V) 60 Single-Ended Offset mV (mV/s for Droop) 40 20 Differential Offset 0 Pedestal Offset -20 Droop -40 -50 0 Temperature (C) 50 100 SPT9110 9 11/12/98 PACKAGE OUTLINE 28-LEAD SOIC INCHES SYMBOL 28 MILLIMETERS MIN 17.68 0.10 0.00 0.36 0.23 2.03 0.41 10.01 7.39 MAX 18.08 0.30 1.27 0.48 0.30 2.54 1.27 10.64 7.59 0.712 0.012 MIN 0.696 0.004 0.014 0.009 0.080 0.016 0.394 0.291 MAX A B IH C D E F .050 typ 0.019 0.012 0.100 0.050 0.419 0.299 1 G H I A F B C D E H G SPT9110 10 11/12/98 PIN ASSIGNMENTS PIN FUNCTIONS Name Function Single-ended analog input to the THA Inverting input A to inverting amplifier resistor R1 Inverting input B to inverting amplifier resistor R2 Single-ended output of the THA Output from the inverting amplifier Noninverting differential PECL clock input Inverting differential PECL clock input Common-mode reference for the inverting amplifier Internal +2.5 V reference output Track-and-hold analog +5 V supply Inverter +5 V supply Internal reference +5 V supply AGND (THA) AGND (THA) 1 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CLK NCLK AVCC (THA) Analog In Invert InA Invert InB Analog In 3 AGND (Sub) 4 AVCC (THA) AVCC (THA) AVCC (THA) AVCC (THA) Out+ Invert InA Invert InB OutAVCC (INV) AVCC (INV) AVCC (ESD) AGND (THA) 5 AGND (Cap) AGND (THA) AGND (THA) Ref In 6 7 8 9 Out+ OutCLK NCLK Ref In Ref Out AVCC (THA) AVCC (INV) AVCC (Ref) Ref Out 10 AVCC (Ref) 11 AGND (Ref) 12 AGND (Sub) 13 AGND (INV) 14 AVCC (ESD) +5 V supply for ESD protection diodes AGND (THA) Track-and-hold analog ground AGND (Cap) Hold capacitor analog ground AGND (Sub) Substrate analog ground AGND (INV) AGND (Ref) INVERTER analog ground Internal reference analog ground ORDERING INFORMATION PART NUMBER SPT9110SIS TEMPERATURE RANGE -40 to +85 C PACKAGE TYPE 28L SOIC SPT9110 11 11/12/98 |
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