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SPT7824
10-BIT, 40 MSPS, TTL OUTPUT A/D CONVERTER
FEATURES
* * * * * * * Monolithic 40 MSPS Converter On-Chip Track/Hold Bipolar 2.0 V Analog Input 57 dB SNR @ 3.58 MHz Input Low Power (1.0 W Typical) 5 pF Input Capacitance TTL Outputs
APPLICATIONS
* * * * * * Medical Imaging Professional Video Radar Receivers Instrumentation Electronic Warfare Digital Communications
GENERAL DESCRIPTION
The SPT7824 A/D converter is a 10-bit monolithic converter capable of word rates a minimum of 40 MSPS. On board track/hold function assures excellent dynamic performance without the need for external components. Drive requirement problems are minimized with an input capacitance of only 5 pF. Inputs and outputs are TTL compatible to interface with TTL logic systems. An overrange output signal is provided to indicate overflow conditions. Output data format is straight binary. Power dissipation is very low at only 1.0 watt with power supply voltages of +5.0 and -5.2 volts. The SPT7824 also provides a wide input voltage swing of 2.0 volts. The SPT7824 is available in 28-lead ceramic sidebrazed DIP, PDIP and SOIC packages over the commercial, industrial and military temperature ranges. Consult the factory for availability of die and /833 versions.
BLOCK DIAGRAM
Analog Input Coarse A/D 4
Analog Prescaler
T/H Amplifier Bank
Decoding Network
Digital Output 10
Successive Interpolation Stage i
Successive Interpolation Stage i+1
Successive Interpolation Stage N
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 C
Supply Voltages VCC ........................................................................... +6 V VEE ........................................................................... -6 V Input Voltages Analog Input ............................................... VFBVINVFT VFT, VFB .............................................................. +3.0 V, -3.0 V Reference Ladder Current ..................................... 12 mA CLK Input .................................................................. VCC Note: Output Digital Outputs .......................................... +30 to -30 mA Temperature Operating Temperature ............................ -55 to +125 C Junction Temperature1 .............................................. +175 C Lead Temperature, (soldering 10 seconds) ........ +300 C Storage Temperature ................................ -65 to +150 C
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN - TMAX, VCC=+5.0 V, VEE=-5.2 V, DVCC=+5.0 V, VIN=2.0 V, VSB=-2.0 V, VST=+2.0 V, fCLK=40 MHz, 50% clock duty cycle, unless otherwise specified.
PARAMETERS Resolution DC Accuracy (+25 C) Integral Nonlinearity Differential Nonlinearity No Missing Codes Analog Input Input Voltage Range Input Bias Current Input Bias Current Input Resistance Input Resistance Input Capacitance Input Bandwidth +FS Error -FS Error
TEST CONDITIONS
TEST LEVEL
MIN 10
SPT7824A TYP MAX
MIN 10
SPT7824B TYP MAX UNITS Bits LSB LSB
Full Scale 100 kHz Sample Rate
V V VI V VI IV VI IV V V V V VI V VI V IV V V V V
1.0 0.5 Guaranteed 2.0 30 100 75 300 300 5 120 2.0 2.0 800 0.8
1.5 0.75 Guaranteed 2.0 60 75 30 100 75 300 300 5 120 2.0 2.0 800 0.8
fCLK=1 MHz VIN=0 V TA=-55 to +125 C TA=-55 to +125 C 3 dB Small Signal
V 60 A 75 A k k pF MHz LSB LSB /C MHz ns 1 Clock Cycle 18 ns ns ps-RMS ns
Reference Input fCLK=1 MHz Reference Ladder Resistance Reference Ladder Tempco Timing Characteristics Maximum Conversion Rate Overvoltage Recovery Time Pipeline Delay (Latency) Output Delay Aperture Delay Time Aperture Jitter Time Acquisition Time Dynamic Performance Effective Number of Bits fIN=1 MHz fIN=3.58 MHz fIN=10.0 MHz
500
500
40 20 14 1 5 12 1 18
40 20 14 1 5 12
TA=+25 C TA=+25 C TA=+25 C TA=+25 C
8.7 8.7 7.3
8.2 8.2 6.9
Bits Bits Bits
Typical thermal impedances (unsoldered, in free air): 28L sidebrazed DIP: ja = 50 C/W, 28L plastic DIP: ja = 50C/W, 28L SOIC: ja = 100 C/W.
SPT7824
2
3/11/97
ELECTRICAL SPECIFICATIONS
TA=TMIN-TMAX, VCC=+5.0 V, VEE=-5.2 V, DVCC=+5.0 V, VIN=2.0 V, VSB=-2.0 V, VST=+2.0 V, fCLK=40 MHz, 50% clock duty cycle unless otherwise specified.
PARAMETERS Dynamic Performance Signal-To-Noise Ratio (without Harmonics) fIN=1 MHz
TEST CONDITIONS
TEST LEVEL
MIN
SPT7824A TYP MAX
MIN
SPT7824B TYP MAX
UNITS
fIN=3.58 MHz
fIN=10.0 MHz
TA=+25 C TA=0 to +70, -25 to +85 C TA=-55 to +125 C* TA=+25 C TA=0 to 70, -25 to +85 C TA=-55 to +125 C* TA=+25 C TA=0 to 70, -25 to +85 C TA=-55 to +125 C* TA=+25 C TA=0 to 70, -25 to +85 C TA=-55 to +125 C* TA=+25 C TA=0 to 70, -25 to +85 C TA=-55 to +125 C* TA=+25 C TA=0 to 70, -25 to +85 C TA=-55 to +125 C*
I IV IV I IV IV I IV IV I IV IV I IV IV I IV IV I IV IV I IV IV I IV IV V V V VI VI I I IV IV VI VI IV IV IV I I I I V
55 53 49 55 53 49 48 45 41 54 51 50 54 51 50 46 45 44 52 49 48 52 49 48 44 43 40
57 55 51 57 55 51 50 47 43 56 53 52 56 53 52 48 47 46 54
52 50 46 52 50 46 46 43 39 52 49 48 52 49 48 43 41 40 49 46 45 49 46 45 41 40 37
54 52 48 54 52 48 48 45 41 54 51 50 54 51 50 45 44 42 51
dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
Degree
Harmonic Distortion fIN=1 MHz
fIN=3.58 MHz
fIN=10.0 MHz
Signal-to-Noise and Distortion TA=+25 C fIN=1 MHz TA=0 to 70, -25 to +85 C TA=-55 to +125 C* fIN=3.58 MHz TA=+25 C TA=0 to 70, -25 to +85 C TA=-55 to +125 C* fIN=10.0 MHz TA=+25 C TA=0 to 70, -25 to +85 C TA=-55 to +125 C* Spurious Free Dynamic Range TA=+25 C, fIN=1 MHz TA=+25 C, fIN = 3.58 & 4.35 MHz Differential Phase Differential Gain TA=+25 C, fIN = 3.58 & 4.35 MHz Digital Inputs fCLK=1 MHz Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low TA=+25 C Maximum Input Current High TA=+25 C Pulse Width Low (CLK) Pulse Width High (CLK) Digital Outputs Logic "1" Voltage Logic "0" Voltage Power Supply Requirements Voltages VCC DVCC -VEE Currents ICC DICC -IEE Power Dissipation Power Supply Rejection fCLK=1 MHz
54
51
46
43
67 0.2 0.5 2.4 0 0 10 10 2.4 0.6 4.75 4.75 -4.95 5.25 5.25 -5.45 145 55 57 1.3 4.75 4.75 -4.95 +5 +5 4.5 0.8 +20 +20 300 2.4 0 0 10 10 2.4
67 0.2 0.7 4.5 0.8 +20 +20
% V V A A ns 300 ns V 0.6 V 5.25 5.25 -5.45 145 55 57 1.3 V V V mA mA mA W LSB
+5 +5
TA=+25 C TA=+25 C TA=+25 C TA=+25 C +5 V 0.25 V, -5.2 V 0.25 V
5.0 -5.2 118 40 40 1.0 1.0
5.0 -5.2 118 40 40 1.0 1.0
*Temperature tested /883 only.
SPT7824
3
3/11/97
TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
TEST LEVEL I II III IV V VI
TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 C. Parameter is guaranteed over specified temperature range.
Figure 1A - Timing Diagram
N N+1
N+2
tpwH
tpwL
CLK
td
Output Data N-2 N-1 Data Valid N Data Valid N+1
Figure 1B - Single Event Clock
CLK
td
Output Data Data Valid
Table I - Timing Parameters
PARAMETERS td tpwH tpwL DESCRIPTION CLK to Data Valid Prop Delay CLK High Pulse Width CLK Low Pulse Width MIN 10 10 TYP 14 MAX 18 300 UNITS ns ns ns
SPT7824
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3/11/97
TYPICAL PERFORMANCE CHARACTERISTICS
THD vs Input Frequency
80
80
SNR vs Input Frequency
70
70
Total Harmonic Distortion (dB)
Signal-to-Noise Ratio (dB)
60
fs = 40 MSPS
fs = 40 MSPS
60
50
50
40
40
30
30
20 100 101 102
20 100 101 102
Input Frequency (MHz)
Input Frequency (MHz)
SINAD vs Input Frequency
80
SNR, THD, SINAD vs Sample Rate
80
Signal-to-Noise and Distortion (dB)
70
70
fs =40 MSPS
60
SNR, THD, SINAD (dB)
SNR
60
50
50
SINAD fIN = 1 MHz THD
40
40
30
30
20 100 101 102
20 100 101 102
Input Frequency (MHz)
Sample Rate (MSPS)
Spectral Response
0
SNR, THD, SINAD vs Temperature
65
fS = 40 MSPS fIN = 1 MHz
-30
SNR, THD, SINAD (dB)
60
SNR
55
Amplitude (dB)
THD SINAD
-60
50
-90
fS = 40 MSPS fIN = 1 MHz
45
-120 0 1 2 3 4 5 6 7 8 9 10
40
-25
0
+25
+50
+75
Input Frequency (MHz)
Temperature (C)
SPT7824
5
3/11/97
TYPICAL INTERFACE CIRCUIT
The SPT7824 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT7824 in normal circuit operation. The following section provides a description of the pin functions and outlines critical performance criteria to consider for achieving the optimal device performance. POWER SUPPLIES AND GROUNDING The SPT7824 requires -5.2 V and +5 V analog supply voltages. The +5 V supply is common to analog VCC and digital DVCC. A ferrite bead in series with each supply line is intended to reduce the transient noise injected into the analog VCC. These beads should be connected as closely as possible to the device. The connection between the beads and the SPT7824 should not be shared with any other device. Each power supply pin should be bypassed as closely as possible to the device. Use 0.1 F for VEE and VCC, and 0.01 F for DVCC (chip caps are preferred). Figure 2 - Typical Interface Circuit
R1 CLK
(TTL) CLK
AGND and DGND are the two grounds available on the SPT7824. These two internal grounds are isolated on the device. The use of ground planes is recommended to achieve optimum device performance. DGND is needed for the DVCC return path (40 mA typical) and for the return path for all digital output logic interfaces. AGND and DGND should be separated from each other and connected together only at the device through a ferrite bead. A Schottky or hot carrier diode connected between AGND and VEE is required. The use of separate power supplies between VCC and DVCC is not recommended due to potential power supply sequencing latch-up conditions. Using the recommended interface circuit shown in figure 2 will provide optimum device performance for the SPT7824.
100
VIN
(2 V)
2.5 V Max
VIN
COARSE A/D
4
D10 (Overrange) D9 (MSB)
D I G IT A L O U
DECODING NETWORK
+5V
C19 1 F
2
+
VIN
IC1
6
VOUT
+2.5 V
VFT
D8 D7 D6 D5 D4 D3 D2 D1
(REF-03) 4
GND
5
10 k
+
1 F 30 k
Trim
C1 .01 F
C2 .01 F
VST
R
ANALOG PRESCALER
2R
C3 .01 F
VRM
2R 2R 2R
3 1 10 k
2 4
+IC2
OP-07 8 7
- 5.2 V
SUCCESSIVE INTERPOLATION STAGE # 1
.01 F
30 k
+5 V
.01 F
C4 .01 F
VSB
D0 (LSB) R SUCCESSIVE INTERPOLATION STAGE # N
6 -2.5 V VFB
VCC
+
VCC
VEE
VEE
1 F
AGND
C6 .1 F C7 .1 F
C8 C9
C10 .01 F C11 .01 F
Notes to prevent latch-up due to power sequencing:
FB
1) D1 = Schottky or hot carrier diode, P/N IN5817. D1 2) FB = Ferrite bead, Fair Rite P/N 2743001111 10 F to be mounted as close to the device as possible. The ferrite bead to the ADC connection should not be shared with any other device. 3) C1-C11 = Chip cap (recommended) mounted as close to the device's pin as possible. 4) Use of a separate supply for VCC and DVCC is not recommended. -5.2 V (Analog) 5) R1 provides current limiting to 45 mA. 6) C6, C7, C8 and C9 should be ten times larger than C10 and C11. 7) C8 = C9 = a 0.1 F cap in parallel with a 4.7 F cap.
10 F
+
+
FB
AGND
+5 V (Analog)
FB
DGND
DGND
AGND
DVCC
DVCC
C5 .01 F
DGND
SPT7824
6
3/11/97
VOLTAGE REFERENCE The SPT7824 requires the use of two voltage references: VFT and VFB. VFT is the force for the top of the voltage reference ladder (+2.5 V typ), VFB (-2.5 V typ) is the force for the bottom of the voltage reference ladder. Both voltages are applied across an internal reference ladder resistance of 800 ohms. The +2.5 V voltage source for reference VFT must be current limited to 20 mA maximum if a different driving circuit is used in place of the recommended reference circuit shown in figures 2 and 3. In addition, there are three reference ladder taps (VST, VRM and VSB). VST is the sense for the top of the reference ladder (+2.0 V), VRM is the midpoint of the ladder (0.0 V typ) and VSB is the sense for the bottom of the reference ladder (-2.0 V). The voltages seen at VST and VSB are the true full scale input voltages of the device when VFT and VFB are driven to the recommended voltages (+2.5 V and -2.5 V typical respectively). These points should be used to monitor the actual full scale input voltage of the device and should not be driven to the expected ideal values as is commonly done with standard flash converters. When not being used, a decoupling capacitor of .01 uF (chip carrier preferred) connected to AGND from each tap is recommended to minimize high frequency noise injection. Figure 3 - Analog Equivalent Input Circuit
VCC
ever, because the device is laser trimmed to optimize performance with 2.5 V references, the accuracy of the device will degrade if operated beyond a 2% range. The following errors are defined: +FS error = top of ladder offset voltage = (+FS -VST+1 LSB) -FS error = bottom of ladder offset voltage = (-FS -VSB -1 LSB) where the +FS (full scale) input voltage is defined as the output transition between 1-10 and 1-11 and the -FS input voltage is defined as the output transition between 0-00 and 0-01. ANALOG INPUT VIN is the analog input. The full scale input range will be 80% of the reference voltage or 2 V with VFB=-2.5 V and VFT=+2.5 V. The drive requirements for the analog inputs are minimal when compared to conventional Flash converters due to the SPT7824's extremely low input capacitance of only 5 pF and very high input resistance of 300 k. For example, for an input signal of 2 V p-p with an input frequency of 10 MHz, the peak output current required for the driving circuit is only 628 A. CLOCK INPUT The SPT7824 is driven from a single-ended TTL input (CLK). The CLK pulse width (tpwH) must be kept between 10 ns and 300 ns to ensure proper operation of the internal track-andhold amplifier. (See timing diagram.) When operating the SPT7824 at sampling rates above 3 MSPS, it is recommended that the clock input duty cycle be kept at 50% to optimize performance. (See figure 4.) The analog input signal is latched on the rising edge of the CLK. The clock input must be driven from fast TTL logic (VIH 4.5 V, TRISE <6 ns). In the event the clock is driven from a high current source, use a 100 resistor in series to current limit to approximately 45 mA. Figure 4 - SNR vs Clock Duty Cycle
59 57
VIN
Analog Prescaler
VFT
VEE
An example of a reference driver circuit recommended is shown in figure 2. IC1 is REF-03, the +2.5 V reference with a tolerance of 0.6% or +/- 0.015 V. The potentiometer R1 is 10 k and supports a minimum adjustable range of up to 150 mV. IC2 is recommended to be an OP-07 or equivalent device. R2 and R3 must be matched to within 0.1% with good TC tracking to maintain a 0.3 LSB matching between VFT and VFB. If 0.1% matching is not met, then potentiometer R4 can be used to adjust the VFB voltage to the desired level. VFT and VFB should be adjusted such that VST and VSB are exactly +2.0 V and -2.0 V respectively. The analog input range will scale proportionally with respect to the reference voltage if a different input range is required. The maximum scaling factor for device operation is 20% of the recommended reference voltages of VFT and VFB. How-
Signal-to-Noise Ratio (dB)
55 53 51 49 tpwH 47 45 43 30 35 40 45 50 55 60 65 70 75 tpwL
Duty tpwH = Cycle tpwL
Duty Cycle of Positive Clock Pulse (%)
SPT7824
7
3/11/97
DIGITAL OUTPUTS The format of the output data (D0-D9) is straight binary. (See table II.) The outputs are latched on the rising edge of CLK with a propagation delay of 14 ns (typ). There is a one clock cycle latency between CLK and the valid output data. (See timing diagram.) Table II - Output Data Information
ANALOG INPUT >+2.0 V + 1/2 LSB +2.0 V -1 LSB 0.0 V -2.0 V +1 LSB <-2.0 V OVERRANGE D1O 1 O O O O OUTPUT CODE D9-DO 11 1111 11 1111 1111 111O
OVERRANGE OUTPUT The OVERRANGE OUTPUT (D10) is an indication that the analog input signal has exceeded the positive full scale input voltage by 1 LSB. When this condition occurs, D10 will switch to logic 1. All other data outputs (D0 to D9) will remain at logic 1 as long as D10 remains at logic 1. This feature makes it possible to include the SPT7824 into higher resolution systems. EVALUATION BOARD The EB7824 Evaluation Board is available to aid designers in demonstrating the full performance of the SPT7824. This board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. An application note describing the operation of this board as well as information on the testing of the SPT7824 is also available. Contact the factory for price and availability.
OO OOOO OOOO OO OOOO OOOO OO OOOO OOOO
(O indicates the flickering bit between logic 0 and 1). The rise times and fall times of the digital outputs are not symmetrical. The propagation delay of the rise time is typically 14 ns and the fall time is typically 6 ns. (See figure 5.) The nonsymmetrical rise and fall times create approximately 8 ns of invalid data.
Figure 5 - Digital Output Characteristics
N
N+1
CLK In
2.4 V 6 ns typ. Rise Time 6 nsec
Data Out (Actual)
3.5 V 2.4 V
(N-2)
0.8 V 0.5 V
Invalid Data
(N-1)
Invalid Data
(N)
tpd1 (14 ns typ.)
Data Out (Equivalent)
(N-2)
Invalid Data
(N-1)
Invalid Data
(N-1)
SPT7824
8
3/11/97
PACKAGE OUTLINES
28-Lead Sidebrazed
28
H
SYMBOL A B C D E F G H I J
INCHES MIN MAX 0.077 0.016 0.095 0.040 0.215 1.388 0.585 0.009 0.600 0.093 0.020 0.105 .050 typ 0.060 0.235 1.412 0.605 0.012 0.620
MILLIMETERS MIN MAX 1.96 0.41 2.41 0.00 1.02 5.46 35.26 14.86 0.23 15.24 2.36 0.51 2.67 1.27 1.52 5.97 35.86 15.37 0.30 15.75
I 1 G A E F C B D J
28-Lead Plastic DIP
SYMBOL A
K
INCHES MIN MAX 0.200 0.120 0.135 0.020 0.100 0.067 0.013 0.180 0.622 0.555 1.460 0.085
MILLIMETERS MIN MAX 5.08 3.05 3.43 0.51 2.54 1.70 0.33 4.57 15.80 14.10 37.08 2.16
B C D E F G H I J K
H
28
I
0.170
4.32
1
J
A
G
B
F
C
D
E
SPT7824
9
3/11/97
PACKAGE OUTLINES
28-Lead SOIC
SYMBOL A B C D E F G H I
INCHES MIN MAX 0.696 0.004 0.014 0.009 0.080 0.016 0.394 0.291 0.712 0.012 .050 typ 0.019 0.012 0.100 0.050 0.419 0.299
MILLIMETERS MIN MAX 17.68 0.10 0.00 0.36 0.23 2.03 0.41 10.01 7.39 18.08 0.30 1.27 0.48 0.30 2.54 1.27 10.64 7.59
28
IH
1
A F B C D E G
SPT7824
10
3/11/97
PIN ASSIGNMENTS
PIN FUNCTIONS
Name Function Digital Ground TTL Outputs (D0=LSB) TTL Output Overrange Clock -5.2 V Supply (Analog) Analog Ground +5.0 V Supply (Analog) Analog Input Digital +5.0 V Supply Middle of Voltage Reference Ladder Force for Top of Reference Ladder Sense for Top of Reference Ladder Force for Bottom of Reference Ladder Sense for Bottom of Reference Ladder
DGND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 DGND DV CC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
DVCC V EE
DGND D0-D9 D10
AGND V V
CC
CLK
FB
V SB V V RM IN
VEE AGND VCC VIN DVCC VRM VFT VST VFB VSB
DIP/PDIP/SOIC
22 21 20 19 18 17 16 15
V ST V FT V CC
AGND V EE
CLK
ORDERING INFORMATION
PART NUMBER
SPT7824AIJ SPT7824BIJ SPT7824ACN SPT7824BCN SPT7824ACS SPT7824BCS SPT7824AMJ SPT7824BMJ
TEMPERATURE RANGE
-25 to +85 C -25 to +85 C 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C -55 to +125 C -55 to +125 C
PACKAGE TYPE
28L Sidebrazed DIP 28L Sidebrazed DIP 28L Plastic DIP 28L Plastic DIP 28L SOIC 28L SOIC 28L Sidebrazed DIP 28L Sidebrazed DIP
SPT7824
11
3/11/97

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