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September 2006 rev 0.4 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
Features
* * 12 LVCMOS compatible clock outputs Selectable LVCMOS and differential LVPECL compatible clock inputs * * * Maximum clock frequency of 350MHz Maximum clock skew of 150pS Synchronous output stop in logic low state eliminates output runt pulses * * * * * * High-impedance output control 3.3V or 2.5V power supply Drives up to 24 series terminated clock lines Ambient temperature range -40C to +85C 32-Lead LQFP & TQFP packaging Supports clock distribution in networking,
PCS2I99448
The PCS2I99448 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350MHz. Each output provides a precise copy of the input signal with a near zero skew. The outputs buffers support driving of 50 terminated transmission lines on the incident edge: each output is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable, independent clock inputs are available, providing support of LVCMOS and differential LVPECL clock distribution systems. The PCS2I99448 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force the outputs into high-impedance mode. All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a 2.5V or 3.3V power supply and an ambient temperature range of -40C to +85C. The PCS2I99448 is pin and function compatible but
telecommunication and computing applications * Pin and Function compatible to MPC9448 and MPC948
Functional Description
The PCS2I99448 is a 3.3V or 2.5V compatible, 1:12 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz and output skews less than 150 pS, the device meets the needs of most demanding clock applications.
performance-enhanced to the MPC948.
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
September 2006 rev 0.4
Block Diagram
PCS2I99448
VCC
PCLK PCLK CCLK Q0 Q1 Q2 Q3 Q4
0 1
CLK STOP
VCC
CLK_SEL
Q5 Q6
VCC
CLK_STOP SYNC Q7 Q8 Q9 Q10
VCC
OE (All input resistors have a value of 25K)
Q11
Pin Diagram
GND VCC GND VCC 18 Q4 Q5 Q6 Q7 17 16 15 14 GND Q8 VCC Q9 GND Q10 VCC Q11 13 12 11 10 9 1 2 3 4 5 6 7 8 GND
24 Q3 VCC Q2 GND Q1 VCC Q0 GND 25 26 27 28 29 30 31 32
23
22
21
20
19
PCS2I99448
CCLK
PCLK
CLK_SEL
PCLK
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
CLK_STOP
VCC
OE
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Table 1. FUNCTION TABLE Control
CLK_SEL OE CLK_STOP
PCS2I99448
Default
1 1 1
0
PECL differential input selected Outputs disabled (high-impedance state)
1
1
CCLK input selected Outputs enabled Outputs active
Outputs synchronously stopped in logic low state
Note: 1. OE=0 will high-impedance tristate all outputs independent on CLK_STOP.
Table 2. PIN CONFIGURATION Pin#
4,3 2 1 5 6 31,29,27,25,23,21,19,17,15,13,11,9 8,12,16,20,24,28,32 7,10,14,18,22,26,30
Pin Name
PCLK, PCLK CCLK CLK_SEL CLK_STOP OE Q0 - Q11 GND VCC
I/O
Input Input Input Input Input Output Supply Supply
Type
LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC
Function
LVPECL Clock Inputs Alternative clock signal input Clock input select Clock output enable/disable Output enable/disable (high-impedance tristate) Clock output Negative power supply (GND) for I/O and core. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation
Table 3. ABSOLUTE MAXIMUM RATINGS1 Symbol
VCC VIN VOUT IIN IOUT TStor Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Range -65
Parameter
Min
-0.3 -0.3 -0.3
Max
3.9 VCC + 0.3 VCC + 0.3 20 50 125
Unit
V V V mA mA C
Note: 1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability.
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
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Table 4. GENERAL SPECIFICATIONS Symbol
VTT MM HBM LU CPD CIN
PCS2I99448
Characteristic
Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-up Immunity Power Dissipation Capacitance Input Capacitance
Min
200 2000 200
Typ
VCC/2
Max
Unit
V V V mA
Condition
10 4.0
pF pF
Per Output Inputs
Table 5. DC CHARACTERISTICS (VCC = 3.3V 5%, TA = -40C to +85C) Symbol
VIH VIL VPP VCMR1 IIN VOH VOL ZOUT ICCQ
4
Characteristic
Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Input Current
2
Min
2.0 -0.3 PCLK PCLK 250 1.1 2.4
Typ
Max
VCC + 0.3 0.8 VCC - 0.6 300 0.55 0.30
Unit
V V mV V A V V V mA
Condition
LVCMOS LVCMOS LVPECL LVPECL VIN = VCC or GND IOH = -24mA3 IOL = 24mA3 IOL = 12mA All VCC Pins
Output HIGH Voltage Output LOW Voltage Output Impedance Maximum Quiescent Supply Current
17 2.0
Note: 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. Input pull-up / pull-down resistors influence input current. 3. The PCS2I99448 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines (for VCC=3.3V) or one 50 series terminated transmission line (for VCC=2.5V). 4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
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Table 6. AC CHARACTERISTICS (VCC = 3.3V 5%, TA = -40C to +85C)1 Symbol
fref fMAX VPP VCMR2 tP, REF tr, tf tPLH/HL tPLH/HL tPLZ, HZ tPZL, LZ tS
PCS2I99448
Characteristics Min
0 0 PCLK PCLK 400 1.3 1.4 1.03 PCLK to any Q CCLK to any Q 1.6 1.3 3.6 3.3 11 11 CCLK to CLK_STOP PCLK to CLK_STOP 0.0 0.0 1.0 1.5 150 PCLK or CCLK to any Q Using CCLK Using PCLK fQ<170 MHz 45 0.1 50 2.0 300 400 55 1.0
Typ
Max
350 350 1000 VCC-0.8
Unit
MHz MHz mV V nS nS nS nS nS nS nS nS nS nS pS nS pS pS % nS
Condition
Input Frequency Maximum Output Frequency Peak-to-peak input voltage Common Mode Range Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation delay Output Disable Time Output Enable Time Setup time
LVPECL LVPECL 0.8 to 2.0V
tH tsk(O) tsk(PP) tSK(P) DCQ tr, tf
Hold time Output-to-output Skew Device-to-device Skew Output pulse skew4 Output Duty Cycle Output Rise/Fall Time
CCLK to CLK_STOP PCLK to CLK_STOP
DCREF = 50% 0.55 to 2.4V
Note: 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP). 3. Violation of the 1.0 nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
Table 7. DC CHARACTERISTICS (VCC = 2.5V 5%, TA = -40C to +85C) Symbol
VIH VIL VPP VCMR IIN VOH VOL ZOUT ICCQ4
1
Characteristics
Input high voltage Input low voltage Peak-to-peak input voltage Common Mode Range Input current2 Output High Voltage Output Low Voltage Output impedance Maximum Quiescent Supply Current PCLK PCLK
Min
1.7 -0.3 250 1.0
Typ
Max
VCC + 0.3 0.7 VCC-0.7 300
Unit
V V mV V A V V mA
Condition
LVCMOS LVCMOS LVPECL LVPECL VIN=GND or VIN=VCC IOH= -15 mA3 IOL= 15 mA3 All VCC Pins
1.8 0.6 19 2.0
Note: 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. Input pull-up / pull-down resistors influence input current. 3. The PCS2I99448 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives one 50 series terminated transmission lines at VCC=2.5V. 4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
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Table 8. AC CHARACTERISTICS (VCC = 2.5V 5%, TA = -40C to +85C)1 Symbol
fref fMAX VPP VCMR2 tP, REF tr, tf tPLH/HL tPLH/HL tPLZ, HZ tPZL, LZ tS Input Frequency Maximum Output Frequency Peak-to-peak input voltage Common Mode Range Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation delay Output Disable Time Output Enable Time 0.0 Setup time CCLK to CLK_STOP PCLK to CLK_STOP CCLK to CLK_STOP tH Hold time PCLK to CLK_STOP tsk(O) tsk(PP) tSK(p) DCQ tr, tf Output-to-output Skew Device-to-device Skew 4 Output pulse skew PCLK or CCLK to any Q Using CCLK Using PCLK fQ< 350 MHz and using CLK fQ<200 MHz and using PCLK 45 45 0.1 50 50 1.5 150 2.7 200 300 55 55 1.0 0.0 1.0 PCLK to any Q CCLK to any Q 1.5 1.7 PCLK PCLK
PCS2I99448
Characteristics
Min
0 0 400 1.2 1.4
Typ
Max
350 350 1000 VCC-0.8 1.03 4.2 4.4 11 11
Unit
MHz MHz mV V nS nS nS nS nS nS nS nS nS nS pS nS pS pS % % nS
Condition
LVPECL LVPECL 0.8 to 2.0V
Output Duty Cycle Output Rise/Fall Time
DCREF = 50% 0.6 to 1.8V
Note: 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP). 3. Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
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APPLICATIONS INFORMATION
CCLK or PCLK CLK _ STOP Q0 to Q11
2.5 VOLTAGE (V)
PCS2I99448
The waveform plots in Figure 3 "Single versus Dual Line Termination Waveforms" show the simulation results of an output driving a single line versus two lines. In both
3.0 OutA tD = 3.8956 OutB tD = 3.9386
Timing Diagram Figure 1. Output Clock Stop (CLK_STOP) Driving Transmission Lines
The PCS2I99448 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of 17 (VCC=3.3V), the outputs can drive either parallel or series terminated transmission lines. In most high performance clock networks, point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2.
PCS2I99448 OUTPUT BUFFER 17 RS=33 Z0=50
2.0 In 1.5
1.0
0.5
0 2 4 6 8 10 12 14
TIME (nS)
Figure 3 . Single versus Dual Line Termination Waveforms
cases, the drive capability of the PCS2I99448 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43pS exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the PCS2I99448. The output waveform in Figure 3 "Single versus Dual Line Termination Waveforms" shows a step in the waveform; this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 33 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Z0 / (RS+R0 +Z0)) Z0 = 50|| 50 RS = 33|| 33 R0 = 17 VL = 3.0 ( 25 / (16.5+17+25) = 1.28V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0nS). Since this step is well above the threshold region it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving
PCS2I99448 OUTPUT BUFFER 17
RS=33
Z0=50
RS=33
Z0=50
Figure 2. Single versus Dual Transmission Lines
This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the PCS2I99448 clock driver. For the series terminated case, however, there is no DC current draw; thus, the outputs can drive multiple series terminated lines. Figure 2 "Single versus Dual Transmission Lines" illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the PCS2I99448 clock driver is effectively doubled due to its capability to drive multiple lines at VCC=3.3V.
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
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multiple lines, the situation in Figure 4 "Optimized Dual Line Termination" should be used. In this case, the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
PCS2I99448 OUTPUT BUFFER 17 RS=16 RS=16 Z0=50
PCS2I99448
Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the PCS2I99448 needs to be controlled and the thermal impedance of the board/package should be optimized.The power dissipated in the PCS2I99448 is represented in equation 1. Where ICCQ is the static current consumption of the PCS2I99448, CPD is the power dissipation capacitance per output, ()CL represents the external capacitive output load, N is the number of active outputs (N is always 12 in case of the PCS2I99448). The PCS2I99448 supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, CL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used CL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 9, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the PCS2I99448 in a series terminated transmission line system, equation 4.
Z0=50
17 + 16 || 16 = 50 || 50 25 = 25
Figure 4. Optimized Dual Line Termination Power Consumption of the PCS299448 and Thermal Management
The PCS2I99448 AC specification is guaranteed for the entire operating frequency range up to 350MHz. The PCS2I99448 power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the PCS2I99448 die junction temperature and the associated device reliability.
Table 9. Die junction temperature and MTBF Junction temperature (C)
100 110 120 130
MTBF (Years)
20.4 9.1 4.2 2.0
PTOT = I CCQ + VCC f CLOCK N C PD + C L VCC M PTOT = VCC I CCQ + VCC f CLOCK N C PD + C L + DC Q I OH (VCC - VOH ) + (1 - DC Q ) I OL VOL M P T J = T A + PTOT Rthja
Equation 1
[
]
Equation 2 Equation 3 Equation 4
f CLOCKMAX =
C PD
T - TA 1 JMAX - (I CCQ VCC ) 2 N VCC Rthja
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
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TJ, MAX should be selected according to the MTBF system requirements and Table 9. Rthja can be derived from Table 10. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in lower thermal impedance than indicated below.
PCS2I99448
If the calculated maximum frequency is below 350 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the PCS2I99448. The charts were calculated for a maximum tolerable die junction temperature of 110C (120C), corresponding to an estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made.
Table 10. Thermal package impedance of the 32LQFP Convection, Rthja (1P2S Rthja (2P2S board), C/W board), C/W LFPM
Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm 86 76 71 68 66 60 61 56 54 53 52 49
350 Operating frequency (MHz) 300 250 200 150 100 50 0 500 400 300 200 100 Convection Ifpm 0
fMAX (AC) Operating frequency (MHz)
350 300 250 200 150 100 50 0 500 400 300 200 100 Convection Ifpm 0
fMAX (AC) TA = 75C
TA = 85C
TA = 85C
Safe operation
Safe operation
Figure 5. Maximum PCS2I99448 frequency VCC = 3.3V, MTBF 9.1 years, driving series terminated transmission lines, 2s2p board
Figure 6. Maximum PCS2I99448 frequency VCC= 3.3V, MRBF 9.1 years, 4pF load per line, 2s2p board
350 Operating frequency (MHz) 300 250 200 150 100 50 0 500 400 300 200 100 Convection Ifpm 0
fMAX (AC) Operating frequency (MHz)
350 300 250 200 150 100 50 0 500 400 300 200 100 Convection Ifpm 0
fMAX (AC)
TA = 85C
Safe operation
Safe operation
Figure 7. No maximum frequency limitation for VCC = 3.3V, MTBF 4 years, driving series terminated transmission lines, 2s2p board
Figure 8. Maximum PCS2I99448 frequency VCC = 3.3V, MRBF 4 years, 4pF load per line, 2s2p board
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
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PCS2I99448
The Following Figures illustrate the Measurement Reference for the PCS2I99448 Clock Driver Circuit
Pulse Generator Z=50
Z0=50
Z0=50
RT=50
RT=50
VTT
TT
Figure 9. CCLK PCS2I99448 AC Test Reference for VCC = 3.3V and VCC
Z0=50 Differential Pulse Generator Z=50 Z0=50
RT=50 RT=50 VTT VTT
Figure 10. PCLK PCS2I99448 AC Test Reference
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
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PCLK PCLK VPP VCMR CCLK
PCS2I99448
VCC VCC /2 GND VCC VCC /2 QX tP(LH) tP(HL) VCC VCC /2 GND
QX
tP(LH)
tP(HL)
GND
Figure 11. Propagation Delay (tPD) Test Reference
VCC VCC /2 GND VCC VCC /2 tSK(LH) tSK(HL) GND QX CCLK
Figure 12. Propagation Delay (tPD) Test Reference
VCC VCC /2 GND VCC VCC /2 tP(LH) tP(HL) tSK(P) =| tPHL - tPHL | GND
The pin-to-pin skew is defined as the worst case difference in propagation between any similar delay path within a single device
Figure 14. Output Pulse Skew (tSK(P) Test Reference
Figure 13. Output-to-Output Skew tSK(LH, HL)
VCC VCC /2 GND tP T0 DC (tP /T0 100%) tF tR VCC = 3.3V VCC = 2.5V 2.4 0.5 1.8V 0.6V
Figure 16. Output Transition Time Test Reference
The time from the output controlled edge to the non-controlled edge, divided by the time output controlled edge, expressed as a percentage.
Figure 15. Output Duty Cycle (DC)
CCLK PCLK
VCC VCC /2 GND
TJIT(CC) = |TN -TN + 1| TN TN + 1
VCC CLK_STOP tS tH VCC /2 GND
The variation in cycle time of a single between adjacent cycles, over a random sample of adjacent cycle pairs
Figure 17. Cycle-to-Cycle Jitter Reference Figure 18. Setup and Hold Time (tS, tH) Test
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
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Package Information 32-lead TQFP
PCS2I99448
SECTION A-A
Symbol
A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 a e
Dimensions Inches Millimeters Min Max Min Max
.... 0.0020 0.0374 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0 0.0472 0.0059 0.0413 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7 ... 0.05 0.95 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0 0.8 BASE 1.2 0.15 1.05 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.2 7
0.03937 REF
1.00 REF
0.031 BASE
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
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32-lead LQFP
PCS2I99448
SECTION A-A
Dimensions Symbol
A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 e a
Inches Min Max
.... 0.0020 0.0531 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0 0.0630 0.0059 0.0571 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7
Millimeters Min Max
... 0.05 1.35 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0 1.6 0.15 1.45 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.20 7
0.03937 REF
1.00 REF
0.031 BASE
0.8 BASE
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Ordering Information
Part Number PCS2P99448G-32-LT PCS2P99448G-32-LR PCS2P99448G-32-ET PCS2P99448G-32-ER PCS2I99448G-32-LT PCS2I99448G-32-LR PCS2I99448G-32-ET PCS2I99448G-32-ER Marking PCS2P99448GL PCS2P99448GL PCS2P99448GE PCS2P99448GE PCS2I99448GL PCS2I99448GL PCS2I99448GE PCS2I99448GE Package Type 32-pin LQFP, Tray, Green 32-pin LQFP -Tape and Reel, Green 32-pin TQFP, Tray, Green 32-pin TQFP -Tape and Reel, Green 32-pin LQFP, Tray, Green 32-pin LQFP -Tape and Reel, Green 32-pin TQFP, Tray, Green 32-pin TQFP -Tape and Reel, Green
PCS2I99448
Operating Range Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial
Device Ordering Information
PCS2I99448G-32-LR
R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT G = GREEN PACKAGE, LEAD FREE, and RoHS U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70
PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
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PCS2I99448
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com
Copyright (c) PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2I99448 Document Version: 0.4
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
(c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
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