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ML5825
2.4GHz to 5.8GHz Frequency Translator ADVANCED Datasheet
GENERAL DESCRIPTION
The ML5825 is a high integration 2.4GHz - 5.8GHz frequency translator (transverter). It upconverts 2.4GHz signals to 5.8GHz and downconverts received 5.8GHz signals to 2.4GHz. Transmit and receive utilize the same low noise fixed local oscillator (LO). It is intended to be used in conjunction with a 2.4GHz transceiverbased solution to quickly and easily develop a 5.8GHz solution while fully leveraging previous development. The ML5825 receive chain contains a Low Noise Amplifier (LNA), bandpass filter and image reject down conversion mixer. A digitally controlled 18dB gain step in the receive chain provides an innovative solution for optimizing IIP3 (low gain mode) and Noise Figure (high gain mode). On the transmit side, the ML5825 buffers and upconverts a differential 2.4GHz signal to 5.8GHz, where it is filtered and amplified. The ML5825's PLL accepts two industry-standard input clock frequencies. The ML5825's low STANDBY MODE current maximizes battery life. Power supply regulation is included in the ML5825, providing circuit isolation and consistent performance over supply voltages between 2.8V-3.6V.
FEATURES
High Integration 2.4GHz to 5.8GHz Transverter Receive LNA, Image Reject Filter & Mixer Transmit Pre-Driver, Filters & Mixers Fully Integrated PLL-Based Synthesizer Selectable Receive Gain Optimizes NF and IIP3 Interfaces Directly with Many 2.4GHz Transceivers 4dB (typ. High Gain Mode) Noise Figure -14dBm Input IP3 (Low Gain Mode) Selectable Transmit Output Power 10A Standby Mode Space-saving 28 pin QFN package
APPLICATIONS
5.8GHz Digital Cordless Telephones 5.8GHz Streaming Audio & Video Upconverted 2.4GHz Standards o o Bluetooth Zigbee/802.15.4
PIN CONFIGURATION
VREG4 VBG1 VLNA TXO RXI
Top View
VMIX VSSMX RXON RXOP RFISET RXGN VCCA FREF
PIN 1 *
VTXB
TXISET TXIN TXIP VREG3 VBG2 VREG2 VTUNE VSSLO
BLOCK DIAGRAM
QPO VTUNE
2
TXIN, TXIP 2383-2508 MHz
TXISET
REFSEL XCEN TXON Control Logic TX Subsystem
TXO 5725-5850 MHz
REFSEL
VREG1
VSSPLL
TXON
XCEN
QPO
FREF
PLL
Supply Regulation & Voltage Reference
* GROUND/RETURN ON EXPOSED PADDLE
VCCA VBG1 VBG2 VREGn RFISET
ORDERING INFORMATION
GAIN CONTROL
RX Subsystem RXI 5725-5850 MHz
2
PART NUMBER TEMP RANGE ML5825DM ML5825DM-T -10oC to +60oC -10oC to +60oC
PACKAGE 28QFN 4x5x0.9 mm 28QFN 4x5x0.9 mm
PACK (QTY) Antistatic Tray (490) Tape & Reel (2500)
RXGN RXON, RXOP 2383-2508 MHz
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TABLE OF CONTENTS
GENERAL DESCRIPTION ........................................................................................................................................... 1 PIN CONFIGURATION ................................................................................................................................................. 1 ORDERING INFORMATION ........................................................................................................................................ 1 FEATURES ................................................................................................................................................................... 1 APPLICATIONS ............................................................................................................................................................ 1 BLOCK DIAGRAM ........................................................................................................................................................ 1 TABLE OF CONTENTS ................................................................................................................................................ 2 SIMPLIFIED APPLICATIONS DIAGRAM ..................................................................................................................... 2 ELECTRICAL CHARACTERISTICS............................................................................................................................. 3 PIN DESCRIPTIONS.................................................................................................................................................... 5 FUNCTIONAL DESCRIPTION ..................................................................................................................................... 9 MODES OF OPERATION............................................................................................................................................. 9 PHYSICAL DIMENSIONS .......................................................................................................................................... 11 WARRANTY................................................................................................................................................................ 12
SIMPLIFIED APPLICATIONS DIAGRAM
Figure 1: ML5825 Typical Application Schematic
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ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Operating the device for any length of time beyond the operating conditions may degrade device performance and/or shorten operating lifetime. VCCA.......................................................................................................................................................................... 3.6 V Maximum Receive RF Input Power....................................................................................................................... +13dBm Maximum Transmit RF Input Power........................................................................................................................ +3dBm Junction Temperature............................................................................................................................................... 150C Storage Temperature Range ...................................................................................................................... -65C to 150C Lead Temperature (Soldering, 10s).......................................................................................................................... 260C Thermal Resistance (JA) ........................................................................................................................................ 39C/W
OPERATING CONDITIONS
Ambient Temperature Range ....................................................................................................................... -10C to 60C VCCA Range ...................................................................................................................................................2.8V to 3.6V Unless otherwise specified, VCCA=3.2V, TA=-10C to +60C, XCEN=VIH, PINRX=-40dBm, PINTX=-3dBm, PLL Loop Filter Bandwidth=40 KHz, and gain control in either state.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES VCCA ISTBY IRX ITX Analog supply voltage Supply current, STANDBY mode Supply current, RECEIVE mode Supply current, TRANSMIT mode VCCA=3.6V, XCEN=VIL, TXON= VIL OR VIH TXON= VIL TXON= VIH RTXISET=7.5K RTXISET=5.5K SUPPLY REGULATION VR27 VR25 VBG Regulated Output Voltage Regulated Output Voltage Bandgap Voltage Pins 12, 19, 26 Pin 17 Pins 18 & 25 2.7 2.5 1.25 V V V 45 95 100 60 110 115 mA mA mA 2.8 3.2 3.6 10 V A
SYNTHESIZER fLO IP Local Oscillator Frequency Charge Pump sink/source current This is a function of VTUNE to compensate for the change in KV VTUNE =0.3V VTUNE =1.2V VTUNE =1.9V N Phase noise at driver output fo=10KHz offset from fc fo=1.2MHz offset from fc KV FPULL FPTR FPUSH tWAKE VCO Tuning sensitivity Frequency pulling Frequency pulling TX to RX and RX to TX Frequency pushing Settling time from standby Vary VCCA from 2.9V to 3.6V XCEN=VIH, to within 10KHz <.5 200 MHz/V s 70s after PIN -50dBm to +12dBm 70s after transition 100 400mVp-p sine wave reference -65 -115 230 +/-20 +/-20 -110 350 dBc/Hz dBc/Hz MHz/V KHz KHz 0.49 0.90 0.60 0.38 0.71 mA mA mA FOUT = FIN+/- FLO 3342.336 MHz
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SYMBOL fFREF VFREF RECEIVER FRXI FRXO ZRIN ZRXO NF GRX IIP3 Receiver Input Frequency Range Receiver Output Frequency Range Receiver Input Impedance Receiver Output Impedance Input noise figure RX Power Gain Input IP3 High Gain Mode Low Gain Mode High Gain Mode Low Gain Mode P1dB PRXI PSPUR RX Input 1dB compression RX conducted emissions from RF input port Out of Band Spurious, High Gain Mode Low Gain Mode IRR RX Image Rejection Spurs outside Receive Output Frequency Range From RXI to RXO, Pin=-50dBm, FRXI= 835-965MHz 20 -25 -5 dBc dBc dB Over FRXI Differential Impedance RXON/RXOP Over FRXO High Gain Mode Low Gain Mode Pin=-50dBm Pin=-30dBm For Pin=-50dBm each tone spaced +/-1MHz from 5800MHz For Pin=-30dBm each tone spaced +/1MHz from 5800MHz High Gain Mode Low Gain Mode RXI terminated in 50 ohm -25 -14 -35 -25 -50 8 5.725 - 5.850 2.382664 - 2.507664 37 + j2 100 4.0 14 13 -8 7.0 22 GHz GHz dB dB dB dB dBm dBm dBm dBm dBm PARAMETER Reference signal frequency Reference signal level CONDITIONS REFSEL=VIL REFSEL=VIH AC coupled 400 MIN TYP 18.432 24.576 1200 MAX UNITS MHz MHz mVp-p
TRANSMITTER FTXI FTXO ZTXI ZTXO POUT RTXH RLO RRFIF R2LO R3LO R4LO RTSB Transmitter Input Frequency Range Transmitter Output Frequency Range Transmitter Input Impedance Transmitter Output Impedance TX buffer output power at 5.85 GHz Matched into 50 ohms, Transmit harmonic output rejection Transmit LO feed thru Transmit IF feed thru Transmit 2xLO feed thru Transmit 3xLO feed thru Transmit 4xLO feed thru Transmit lower sideband rejection Differential Impedance TXIN/TXIP Over FTXI Over FTXO RTXISET=7.5K, Pin=-6dBm RTXISET=5.5K, Pin=-3dBm 50 Ohm load Measured at TXO port with CW signal at FTXI and PTXI Measured at TXO port with CW signal at FTXI and PTXI Measured at TXO port with CW signal at FTXI and PTXI Measured at TXO port with CW signal at FTXI and PTXI Measured at TXO port with CW signal at FTXI and PTXI From TXI to TXO ports at PTXI for FTXO= 835-960MHz 25 -30 -30 <-30 <-20 <-20 3.5 5.5 <-20 2.382664 - 2.507664 5.725-5.850 100 43 + j88 GHz GHz dBm dBm dBc dBc dBc dBc dBc dBc dBc
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SYMBOL RMXN PARAMETER Mixer products rejection at output port CONDITIONS From TXI to TXO ports at PTXI for FTXO= 960-970MHz MIN TYP >55 MAX UNITS dBc
INTERFACE LOGIC LEVELS Input pins (XCEN, TXON, RXGN, REFSEL) VIH VIL IB CIN Input high voltage Input low voltage Input bias current Input capacitance All states 1MHz test frequency
VCCA*0.7 -0.4 VCCA+0.4 VCCA*0.3
V V A pF
-5 4
5
PIN DESCRIPTIONS
PIN NAME I/O FUNCTION DIAGRAM
POWER & GROUND
2 7 14 15 24 X VSSMX VCCA VSSPLL VSSLO VTXB VSSDB GROUND POWER GROUND GROUND INPUT GROUND Mixer Ground Regulated External Supply, Requires Proper Decoupling Components PLL Ground VCO and LO Ground TX Buffer Supply Voltage, Connect to Pin 7 Exposed Paddle. Ground/Return N/A N/A N/A N/A N/A N/A
SUPPLY REGULATION
1 12 17 18 19 25 26 28 VMIX VREG1 VREG2 VBG2 VREG3 VBG1 VREG4 VLNA INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT 2.7V Supply Decoupling Point, Connect to Pin 26 2.7V Regulated Supply Output 2.5V Regulated Supply Output 1.24V Bandgap2 Supply Decoupling Point 2.7V Regulated Supply Decoupling Point 1.24V Bandgap1 Supply Decoupling Point 2.7V Regulated Supply Output, Connect to Pins 1 and 28 2.7V LNA Supply Decoupling Point, Connect to Pin 26 N/A N/A N/A N/A N/A N/A N/A N/A
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RF TRANSMIT/RECEIVE DATA
27 RXI I (analog) 5.8GHz RX Input. A simple matching network is required for optimum noise figure. This input connects to the base of an NPN transistor and should be AC coupled.
VLNA 28 0.7V 3.9K RXI 27
VSSDB
23
TXO
O (analog)
5.8GHz TX Output into a matched load over the 5725 to 5850 MHz range.
VTXB 24
TXO 23
VSSDB
4 3
RXOP RXON
O (analog)
Differential 2.4GHz RX Output.
VCCA 7
56 RXOP 4
2 VSSMX
VSSDB
20 21
TXIP TXIN
I (analog)
Differential 2.4GHz TX Input
VCCA 7
TXIP 20 TXIN 21
22
82
2 VSSMX
X VSSDB
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RF CONTROL & OTHERS
11 XCEN I (CMOS) Transceiver Enable Input. Enables the bandgap reference and voltage regulators when high. Consumes only leakage current in STANDBY mode when low. This is a CMOS input, and the thresholds are referenced to VCCA and VSSMX.
XCEN 11 168 VCCA 7
2 VSSMX
10
TXON
I (CMOS)
TX/RX Control Input. Switches the transceiver between TRANSMIT and RECEIVE modes. Circuits are powered up and signal paths reconfigured according to the operating mode. This is a CMOS input, and the thresholds are referenced to VCCA and VSSMX.
TXON 10
VCCA 7
168
2 VSSMX
5
RFISET
I (analog)
Connect to a 255 +/-1% resistor to ground.
VCCA 7
RFISET 5
2 VSSMX
6
RXGN
I (CMOS)
Gain Step Input Control. Switches the receiver between high gain (when HIGH) and low gain (when LOW). This dual-gain design allows the system designer to achieve low noise figure for low input signals while maintaining a good IIP3 under high input signal conditions. This is a CMOS input, and the thresholds are referenced to VCCA and VSSMX.
RXGN 6
VCCA 7
168
2 VSSMX
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13 QPO O (analog) Charge Pump Output. This output is connected to the external PLL loop filter. Sources current when the LO frequency is lower than desired.
VREG1 12
QPO 13 9.2
14 VSSPLL
16
VTUNE
I (analog)
VCO Tuning Voltage. This input from the PLL loop filter determines the output frequency and is very sensitive to noise coupling and leakage currents.
VTUNE 16
VREG3 19
VREG2 17 10
15 VSSLO
22
TXISET
I (analog)
A resistor between this pin and ground establishes the PA output power compression point by setting a bias current.
VCCA 7
VTXB 24
TXISET 22 522
2 VSSMX
8
FREF
I (analog)
Input Reference Frequency. Depending on the state of the REFSEL pin this input is divided by 3 or 4 to generate the PLL reference frequency.
VCCA 7
VREG1 12
FREF 8
2 VSSMX 14 VSSPLL
9
REFSEL
I (CMOS)
Reference Divider Control. If REFSEL is HIGH, FREF is divided by 4, otherwise FREF is divided by 3. This is a CMOS input, and the thresholds are referenced to VCCA and VSSMX.
VCCA 7
REFSEL 9 168
2 VSSMX
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FUNCTIONAL DESCRIPTION
The ML5825 is a monolithic, bilateral 2.4GHz to 5.8GHz frequency translator. It provides a simple and straightforward solution for designers of 2.4GHz products who want to develop advanced products for the relatively interference-free 5.8GHz band, especially digital cordless telephones. The ML5825 can implement "dual band" solutions that use both the 2.4GHz and 5.8GHz bands as well as "hybrid" products where one link (say, basestation transmission) is at 5.8GHz, while the other link (basestation receive) is at 2.4GHz. 5.8GHz signals enter the RXI pin and then are fed to an LNA and bandpass filter. An image-reject downconvert mixer translates the signal to the 2.4GHz ISM band where it is then buffered and sent off chip differentially on RXON/RXOP. The receive signal path can be configured for either a "High Gain" mode (about 13dB) or "Low Gain" mode (-8dB). Gain mode is selected via the RXGN digital input pin. High Gain mode is used for low-level input signals to minimize Noise Figure while Low Gain mode optimizes input IP3 for stronger signals. 2.4GHz signals come into the ML5825 differentially on the TXIP/TXIN pins, where they are upconverted to 5.8GHz, bandpass filtered, and then amplified and exit via TXO. The predriver/buffer output power compression point is programmed by an external resistor that sets the preamp bias level. A fully integrated phase locked loop (PLL) generates the fixed local oscillator (LO) at 3342.336 MHz which is used for upconverting and downconverting the RF signals. The comparison frequency of the PLL is derived from the frequency reference present on the FREF pin and the state of REFSEL as shown in Table 1. The PLL loop filter is external to the ML5825 so that lock time and in-band phase noise can be optimized for the system of interest.
REFSEL
VIL VIH
REFERENCE DIVISION
3 4
FREF
18.432 MHz 24.576 MHz
Table 1: ML5825 Frequency References
The ML5825 contains two separate bandgap references and several low dropout (LDO) voltage regulators to insure consistent performance over supply voltage and minimize crosstalk on chip. The device is enabled by bringing XCEN to VIH and is placed in transmit mode by setting TXON to VIH. With XCEN at VIL the ML5825 enters a low power standby mode.
MODES OF OPERATION
The ML5825 has three key modes of operation. The two operational modes are RECEIVE and TRANSMIT, controlled by TXON. XCEN is the chip enable/disable control pin, which sets the device in operational or STANDBY modes. The relationship between the parallel control lines and the mode of operation of the IC is summarized in Table 2.
XCEN
0 1 1
TXON
X 0 1
MODE NAME
STANDBY RECEIVE TRANSMIT
FUNCTION
Standby. All circuits powered down Receive Chain Active Transmit Chain Active
Table 2: Modes of Operation
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STANDBY MODE
In STANDBY mode, the ML5825 transverter is powered down. When exiting STANDBY mode, the transmitter is disabled for 200s. However, the receive path is not similarly locked out and so will receive invalid data for up to 200s. Therefore, the system should wait 200s after exiting STANDBY mode before actively processing signals to allow the PLL to lock. A timing diagram for the ML5825 is shown in Figure 2. VCCA
200uS
XCEN
TXON
200uS
170uS 350uS 100uS RX Valid Data Output TX Valid Data Output TX Valid Data Output Supply Settling And TX Timer 170uS Time to valid TX data is 400uS 100uS RX Valid Data Output
Data Output (RX & TX)
Supply and PLL Settling 200uS
PLL Settling 100uS
PLL Settling 100uS
Figure 2: ML5825 Control Timing Diagram, assuming a 40 KHz loop bandwidth.
RECEIVE MODE
In RECEIVE mode, the received signal at 5.8GHz is amplified, filtered, and downconverted to 2.4GHz. The receiver has two gain modes; High Gain (about 13dB) and Low Gain (about -8dB). Gain mode is set via the state of the RXGN input, with High Gain Mode corresponding to a logic "1" on RXGN.
TRANSMIT MODE
In TRANSMIT mode, the transmitted signal at 2.4GHz is upconverted, filtered, and amplified at 5.8GHz. The transmit output power compression point is programmable via an external resistor on the TXISET pin.
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PHYSICAL DIMENSIONS
Figure 3: 28 Pin QFN Package Dimensions
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WARRANTY
Sirenza Microdevices makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this document. The circuits contained in this document are offered as possible applications only. Particular uses or applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged to perform its own engineering review before deciding on a particular application. Sirenza Microdevices assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Sirenza Microdevices products including liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Sirenza Microdevices products are not designed for use in medical, life saving, or life sustaining applications. If this document is "Advanced", its contents describe a Sirenza Microdevices product that is currently under development. All detailed specifications including pinouts and electrical specifications may be changed without notice. If this document is "Preliminary", its contents are based on early silicon measurements. Typical data is representative of the product but is subject to change without notice. Pinout and mechanical dimensions are final. Preliminary documents supersede all Advanced documents and all previous Preliminary versions. If this document is "Final", its contents are based on a characterized product, and it is believed to be accurate at the time of publication. Final Data Sheets supersede all previously published versions. This document is Advanced. (c) 2007 Sirenza Microdevices Corporation. All rights reserved. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.
Sirenza Microdevices, Inc., 303 S. Technology Court, Broomfield, CO 80021, USA North America 1- 303-327-3030 www.sirenza.com China +86-21-5835-4840 India +91-80-32902348 transceiver-sales@sirenza.com transceiver-apps@sirenza.com
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