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M66257FP
5120 x 8-Bit x 2 Line Memory (FIFO)
REJ03F0251-0200 Rev.2.00 Sep 14, 2007
Description
The M66257FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word x 8-bit double configuration which uses high-performance silicon gate CMOS process technology. It allows simultaneous output of 1-line delay data and 2-line delay data, and is most suitable for data correction over multiple lines. It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between devices with different data processing throughput.
Features
* * * * * * * * Memory configuration: 5120 words x 8 bits x 2 (dynamic memory) High-speed cycle: 25 ns (Min) High-speed access: 18 ns (Max) Output hold: 3 ns (Min) Fully independent, asynchronous write and read operations Output: 3 states 1-line delay Q00 to Q07: Q10 to Q17: 2-line delay
Application
Digital photocopiers, high-speed facsimile, laser beam printers.
Block Diagram
Data input D0 to D7
27 26 25 24 23 22 21 20
Data output Q00 to Q07
23456789
Data output Q10 to Q17
10 11 12 13 14 15 16 17
Input buffer
Output buffer
Read address counter
Write address counter
Read control circuit
Write control circuit
WE 32 Write enable input WRES 31 Write reset input WCK 30 Write clock input VCC 18 VCC 28
VCC 36
35 RE
Read enable input
(
Memory array of 5120-word x 8-bit x 2 configuration 1-line delay data only memory/ 2-line delay data only memory
34 RRES
)
Read reset input
33 RCK
Read clock input
1 GND
19 GND
29 GND
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 1 of 12
M66257FP
Pin Arrangement
M66257FP
Data output
GND Q00 Q01 Q02 Q03 Q04 Q05 Q06 Q07 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
VCC RE RRES RCK WE WRES WCK GND VCC D0 D1 D2 D3 D4 D5 D6 D7 GND
Read enable input Read reset input Read clock input Write enable input Write reset input Write clock input
Data input
(Top view) Outline: PRSP0036GA-A (36P2R-A)
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 2 of 12
M66257FP
Absolute Maximum Ratings
(Ta = 0 to 70C, unless otherwise noted)
Item Supply voltage Input voltage Output voltage Power dissipation Storage temperature Symbol VCC VI VO Pd Tstg Ratings -0.5 to +7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 660 -65 to 150 Unit V V V mW C Conditions A value based on GND pin Ta = 25C
Recommended Operating Conditions
Item Supply voltage Supply voltage Operating ambient temperature Symbol VCC GND Topr Min 4.5 0 Typ 5 0 Max 5.5 70 Unit V V C
Electrical Characteristics
(Ta = 0 to 70C, VCC = 5 V 10%, GND = 0 V, unless otherwise noted)
Item "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" input current Symbol VIH VIL VOH VOL IIH Min 2.0 VCC - 0.8 Typ Max 0.8 0.55 1.0 Unit V V V V A Test Conditions
IOH = -4 mA IOL = 4 mA VI = VCC WE, WRES, WCK, RE, RRES, RCK, D0 to D7 VI = GND WE, WRES, WCK, RE, RRES, RCK, D0 to D7
"L" input current
IIL
-1.0
A
Off state "H" output current Off state "L" output current Operating mean current dissipation Input capacitance Off state output capacitance
IOZH IOZL ICC CI CO

5.0 -5.0 120 10 15
A A mA pF pF
VO = VCC VO = GND VI = VCC, GND, Output open tWCK, tRCK = 25 ns f = 1 MHz f = 1 MHz
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 3 of 12
M66257FP
Function
When write enable input WE is "L", the contents of data inputs D0 to D7 are written into 1-line delay data only memory in synchronization with rise edge of write clock input WCK. At this time, the write address counter of 1-line delay data only memory is also incremented simultaneously. The write functions given below are also performed in synchronization with rise edge of WCK. When WE is "H", a write operation to 1-line delay data only memory is inhibited and the write address counter of 1-line delay data only memory is stopped. When write reset input WRES is "L", the write address counter of 1-line delay data only memory is initialized. When read enable input RE is "L", the contents of 1-line delay data only memory are output to data outputs Q00 to Q07 and those of 2-line delay data only memory to data outputs Q10 to Q17 in synchronization with the rise of read clock input RCK. At this time, the read address counters of 1-line and 2-line delay data only memories is also incremented simultaneously. Moreover, data of Q00 to Q07 are written into 2-line delay data only memory in synchronization with rise edge of RCK. At this time, the write address of 2-line delay data only memory is incremented. The read functions given below are also performed in synchronization with rise edge of RCK. When RE is "H", a read operation from both of 1-line delay data only memory and 2-line delay data only memory is inhibited and the read address counter of each memory is stopped. The outputs of Q00 to Q07 and Q10 to Q17 are in the high impedance state. Moreover, a write operation to 2-line delay data only memory is inhibited and the write address counter of 2-line delay data only memory is stopped. When read reset input RRES is "L", the read address counter of 1-line delay data only memory, and the write address counter and read address counter of 2-line delay data only memory are initialized.
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 4 of 12
M66257FP
Switching Characteristics
(Ta = 0 to 70C, VCC = 5 V 10%, GND = 0 V, unless otherwise noted)
Item Access time Output hold time Output enable time Output disable time Symbol tAC tOH tOEN tODIS Min 3 3 3 Typ Max 18 18 18 Unit ns ns ns ns
Timing Conditions
(Ta = 0 to 70C, VCC = 5 V 10%, GND = 0 V, unless otherwise noted)
Item Write clock (WCK) cycle Write clock (WCK) "H" pulse width Write clock (WCK) "L" pulse width Read clock (RCK) cycle Read clock (RCK) "H" pulse width Read clock (RCK) "L" pulse width Input data setup time to WCK Input data hold time to WCK Reset setup time to WCK or RCK Reset hold time to WCK or RCK Reset nonselect setup time to WCK or RCK Reset nonselect hold time to WCK or RCK WE setup time to WCK WE hold time to WCK WE nonselect setup time to WCK WE nonselect hold time to WCK RE setup time to RCK RE hold time to RCK RE nonselect setup time to RCK RE nonselect hold time to RCK Input pulse rise/fall time Data hold time* Symbol tWCK tWCKH tWCKL tRCK tRCKH tRCKL tDS tDH tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH tr, tf tH Min 25 11 11 25 11 11 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Typ Max 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Notes: Reset the IC after power is turned on. * For 1-line access, the following should be satisfied: WE "H" level period < 20 ms - 5120 tWCK - WRES "L" level period RE "H" level period < 20 ms - 5120 tRCK - RRES "L" level period
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 5 of 12
M66257FP
Test Circuit
VCC RL = 1 k Qn SW1 CL = 30 pF: tAC, tOH Qn SW2 CL = 5 pF: tOEN, tODIS RL = 1 k
Input pulse level:
0 to 3 V
Input pulse rise/fall time: 3 ns Decision voltage input: Decision voltage output: 1.3 V 1.3 V (However, tODIS (LZ) is 10% of output amplitude and tODIS (HZ) is 90% of that for decision)
The load capacitance CL includes the floating capacitance of connection and the input capacitance of probe.
Parameter tODIS (LZ) tODIS (HZ) tOEN (ZL) tOEN (ZH) SW1 Closed Open Closed Open SW2 Open Closed Open Closed
tODIS/tOEN Test Condition
3V RCK 1.3 V 1.3 V GND
RE tODIS (HZ) Q0n Q1n 90% 1.3 V tODIS (LZ) Q0n Q1n tOEN (ZL) tOEN (ZH)
3V GND
VOH
1.3 V 10%
VOL
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 6 of 12
M66257FP
Operating Timing
Write Cycle
Cycle n Cycle n + 1 Cycle n + 2 Disable cycle Cycle n + 3 Cycle n + 4
WCK
tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES
WE
tDS tDH tDS tDH
Dn
(n)
(n + 1)
(n + 2)
(n + 3)
(n + 4)
WRES = "H"
Write Reset Cycle
Cycle n - 1 Cycle n Reset cycle Cycle 0 Cycle 1 Cycle 2
WCK
tWCK tNRESH tRESS tRESH tNRESS
WRES
tDS tDH tDS tDH
Dn
(n - 1)
(n)
(0)
(1)
(2)
WE = "L"
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 7 of 12
M66257FP Read Cycle
Cycle n Cycle n + 1 Cycle n + 2 Disable cycle Cycle n + 3 Cycle n + 4
RCK
tRCK tRCKH tRCKL tREH tNRES tNREH tRES
RE
tODIS
tAC
tOEN
Q0n
(n) (n + 1) (n + 2)
HIGH-Z
(n + 3) tOH
(n + 4)
Q1n
RRES = "H"
Read Reset Cycle
Cycle n - 1 Cycle n Reset cycle Cycle 0 Cycle 1 Cycle 2
RCK
tRCK tNRESH tRESS tRESH tNRESS
RRES
tAC
Q0n
(n - 1) (n)
tON
(0)
(0)
(0) tON
(1)
(2)
Q1n
tON
RE = "L"
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 8 of 12
M66257FP Note at WCK Stop
n cycle n + 1 cycle n cycle Disable cycle
WCK
tWCK tNWES
WE
tDS tDH
tDS tDH
Dn
(n)
(n)
Period of writing data (n) into memory
Period of writing data (n) into memory WRES = "H"
Input data Dn of n cycle is read at the rising edge after WCK of n cycle. Writing operation starts in the "L" period of WCK of n + 1 cycle and ends at the rising edge after n + 1 cycle. To stop reading write data at n cycle, input WCK for up to the rising edge of n + 1 cycle. When the cycle next to n cycle is a disable cycle, input of WCK for a cycle is required after a disable cycle as well.
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 9 of 12
M66257FP Shortest Read of Data "n" Written in Cycle n (Cycle n - 1 on read side should be started after end of cycle n + 1 on write side) When the start of cycle n - 1 on read side is earlier than the end of cycle n + 1 on write side, output Qn of cycle n becomes invalid. In the figure shown below, the read of cycle n - 1 is invalid.
Cycle n
Cycle n + 1
Cycle n + 2
Cycle n + 3
WCK
Dn
(n)
(n + 1)
(n + 2)
(n + 3)
Cycle n - 2
Cycle n - 1
Cycle n
RCK
Qn
Invalid
(n)
Longest Read of Data "n" Written in Cycle n: 1-line Delay (Cycle n <1>* on read side should be started when cycle n <2>* on write is started) Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each other.
Cycle n <1>*
Cycle 0 <2>*
Cycle n <2>*
WCK
Dn
(n - 1) <1>*
(n) <1>*
(0) <2>*
(n - 1) <2>*
(n) <2>*
Cycle n <0>*
Cycle 0 <1>*
Cycle n <1>*
RCK
Qn
(n - 1) <0>*
(n) <0>*
(0) <1>*
(n - 1) <1>*
(n) <1>*
Note: <0>*, <1>* and <2>* indicates a line value.
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 10 of 12
M66257FP
Application Example
Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction
N Line n image data
M66257 D0 to D7 Q00 to Q07
B Line (n + 1) image data
x2
Adder N + K {2N - (A + B) }
1-line delay
Corrected image data
Subtractor 2N - (A + B)
xK
2-line delay
Secondary scanning direction
Primary scanning direction
A N B
Line (n - 1) Line n Line (n + 1) N' = N + K { (N - A) + (N - B) } = N + K {2N - (A + B)} K: Laplacian coefficient
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 11 of 12
Adder A+B
Q10 to Q17
A Line (n - 1) image data
M66257FP
Package Dimensions
JEITA Package Code P-SSOP36-8.4x15-0.80 RENESAS Code PRSP0036GA-A Previous Code 36P2R-A MASS[Typ.] 0.5g
36
19
HE
*1
E
F
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
1 Index mark 18
c
*2
D
A2
A1
Reference Symbol
Dimension in Millimeters
*3
e
y
bp
D E A2 A A1 bp c HE e y L
Detail F
Min Nom Max 14.8 15.0 15.2 8.2 8.4 8.6 2.0 2.4 0.05 0.35 0.4 0.5 0.13 0.15 0.2 0 10 11.63 11.93 12.23 0.65 0.8 0.95 0.15 0.3 0.5 0.7
A
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 12 of 12
L
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