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Features
* * * * * * * * * * * * * * *
16 Mbit SRAM Multi Chip Module Allows 32-, 16- or 8-bit access configuration Operating Voltage: 3.3V + 0.3V Access Time - 20 ns, 18 ns for AT68166F - <18 ns for AT68166G (in development prototypes in Q4 2007) Power Consumption - Active: 620 mW per byte (Max) @ 18ns - 415 mW per byte (Max) @ 50ns (1) - Standby: 13 mW (Typ) Military Temperature Range: -55 to +125C TTL-Compatible Inputs and Outputs Asynchronous Die manufactured on Atmel 0.25 m Radiation Hardened Process No Single Event Latch Up below LET Threshold of 80 MeV/mg/cm2 Tested up to a Total Dose of 300 krads (Si) according to MIL-STD-883 Method 1019 ESD Better than 4000V Quality Grades: - QML-Q or V with SMD 5962-06229 - ESCC 950 Mils Wide MQFP 68 Package Mass : 8.5 grams 1. Only for AT68166F-18. 450mW for AT68166F-20.
Rad Hard 16 MegaBit 3.3V SRAM MultiChip Module AT68166F AT68166G
Note:
Description
The AT68166F/G is a 16Mbit SRAM packaged in a hermetic Multi Chip Module (MCM) for space applications. The AT68166F/G MCM incorporates four 4Mbit AT60142FT SRAM dice. It can be organized as either one bank of 512Kx8, two banks of 512Kx16 or four banks of 512Kx8. It combines rad-hard capabilities, a latch-up threshold of 80MeV.cm/mg, a Multiple Bit Upset immunity and a total dose tolerance of 300Krads, with a fast access time. The MCM packaging technology allows a reduction of the PCB area by 50% with a weight savings of 75% compared to four 4Mbit packages. Thanks to the small size of the 4Mbit SRAM die, Atmel has been able to accommodate the assembly of the four dice on one side of the package which facilitates the power dissipation. The compatibility with other products allows designers to easily migrate to the Atmel AT68166F/G memory. The AT68166F/G is powered at 3.3V. The AT68166F/G is processed according to the test methods of the latest revision of the MIL-PRF-38535 or the ESCC 9000.
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Block Diagram
Figure 1. AT68166F/G Block Diagram CS3 WE3 CS2 WE2 CS1 WE1 CS0 WE0
A[18:0] OE BANK3 512k x 8 BANK2 512k x 8 BANK1 512k x 8 BANK0 512k x 8
I/O[31:24] or I/O2[31:16] or I/O3[7:0]
I/O[23:16] or I/O2[15:0] or I/O2[7:0]
I/O[15:8] or I/O1[31:16] or I/O1[7:0]
I/O[7:0] or I/O1[15:0] or I/O[7:0]
Figure 2. 512K x 8 Banks Block Diagram (AT60142F/G)
A0 A10
I/Ox0 I/Ox7
CSx WEx OE
Packages
AT68166F and AT68166G are packed in MQFP68.
Access Time 20 ns AT68166F AT68166G YM 18 ns YS YS <18 ns
The pin assignment depends on the access time. There are 2 versions: - - YM package where 3 pins are not connected. YS package where the 3 above pins are connected to GND or VCC.
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AT68166F/G
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AT68166F/G
Pin Configuration
Table 1. AT68166F/G pin assignment in YS package
Lead 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Notes: Signal I/O0[0] I/O0[1] I/O0[2] I/O0[3] I/O0[4] I/O0[5] I/O0[6] I/O0[7] GND I/O1[0] I/O1[1] I/O1[2] I/O1[3] I/O1[4] I/O1[5] I/O1[6] I/O1[7] Lead 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal VCC A11 A12 A13 A14 A15 A16 CS0 OE CS1 A17 WE1 WE2 WE3 A18 GND VCC Lead 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Signal I/O3[7] I/O3[6] I/O3[5] I/O3[4] I/O3[3] I/O3[2] I/O3[1] I/O3[0] GND I/O2[7] I/O2[6] I/O2[5] I/O2[4] I/O2[3] I/O2[2] I/O2[1] I/O2[0] Lead 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Signal VCC A10 A9 A8 A7 A6 WE0 CS3 GND CS2 A5 A4 A3 A2 A1 A0 VCC
1. In YM package leads 33, 34 and 68 are not connected.
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Figure 3. AT68166F pin assignment in YM package
NC A0 A1 A2 A3 A4 A5 CS2 GND CS3 WE0 A6 A7 A8 A9 A10 VCC I/O0[0] I/O0[1] I/O0[2] I/O0[3] I/O0[4] I/O0[5] I/O0[6] I/O0[7] GND I/O1[0] I/O1[1] I/O1[2] I/O1[3] I/O1[4] I/O1[5] I/O1[6] I/O1[7]
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
Figure 4. AT68166F/G pin assignment in YS package
VCC A0 A1 A2 A3 A4 A5 CS2 GND CS3 WE0 A6 A7 A8 A9 A10 VCC
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AT68166F/G
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VCC A11 A12 A13 A14 A15 A16 CS0 0E CS1 A17 WE1 WE2 WE3 A18 GND VCC
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
I/O0[0] I/O0[1] I/O0[2] I/O0[3] I/O0[4] I/O0[5] I/O0[6] I/O0[7] GND I/O1[0] I/O1[1] I/O1[2] I/O1[3] I/O1[4] I/O1[5] I/O1[6] I/O1[7]
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
VCC A11 A12 A13 A14 A15 A16 CS0 0E CS1 A17 WE1 WE2 WE3 A18 NC NC
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
AT68166F
(top view)
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
I/O2[0] I/O2[1] I/O2[2] I/O2[3] I/O2[4] I/O2[5] I/O2[6] I/O2[7] GND I/O3[0] I/O3[1] I/O3[2] I/O3[3] I/O3[4] I/O3[5] I/O3[6] I/O3[7]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
AT68166F/G
(top view)
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
I/O2[0] I/O2[1] I/O2[2] I/O2[3] I/O2[4] I/O2[5] I/O2[6] I/O2[7] GND I/O3[0] I/O3[1] I/O3[2] I/O3[3] I/O3[4] I/O3[5] I/O3[6] I/O3[7]
AT68166F/G
Pin Description
Table 2. Pin Names
Name A0 - A18 I/O0 - I/O31 CS0 - CS3 WE0 - WE3 OE VCC GND(1) Note: 1. The package lid is connected to GND Description Address Inputs Data Input/Output Chip Select Write Enable Output Enable Power Supply Ground
Table 3. Truth Table(1)
CSx H L L L Note: WEx X H L H OE X L X H Inputs/Outputs Z Data Out Data In Z Mode Standby Read Write Output Disable
1. L=low, H=high, X= H or L, L=high impedance.
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Electrical Characteristics
Absolute Maximum Ratings*
Supply Voltage to GND Potential:.........................-0.5V + 4.6V DC Input Voltage:........................................GND -0.5V to 4.6V DC Output Voltage High Z State: ................GND -0.5V to 4.6V Storage Temperature: ................................... -65C to + 150C Output Current Into Outputs (Low): ............................... 20 mA Electro Statics Discharge Voltage:..... .........> 4000V (MIL STD 883D Method 3015.3) *NOTE:
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Military Operating Range
Operating Voltage 3.3 + 0.3V Operating Temperature -55C to + 125C
Recommended DC Operating Conditions
Parameter Vcc GND VIL VIH Description Supply voltage Ground Input low voltage Input high voltage Min 3 0.0 GND - 0.3 2.2 Typ 3.3 0.0 0.0 - Max 3.6 0.0 0.8 VCC + 0.3 Unit V V V V
Capacitance
Parameter Cin(1) (OE and Ax) Cin(1) (CSx and WEx) Cio(1) Note: Description Input capacitance Input capacitance I/O capacitance Min - - - Typ - - - Max 48 12 12 Unit pF pF pF
1. Guaranteed but not tested.
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AT68166F/G
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AT68166F/G
DC Parameters
Parameter IIX
(1)
Description Input leakage current Output leakage current Output low voltage Output high voltage
Minimum -1 -1 - 2.4
Typical - - - -
Maximum 1 1 0.4 -
Unit A A V V
IOZ(1) VOL(2) VOH Notes:
(3)
1. GND < VIN < VCC, GND < VOUT < VCC Output Disabled. 2. VCC min. IOL = 8 mA 3. VCC min. IOH = -4 mA
Consumption
Symbol ICCSB(1) ICCSB1(2) Description Standby Supply Current Standby Supply Current TAVAV/TAVAW Test Condition - AT68166F-20 AT68166F-18 Unit 10 7 mA Value max
- 18 ns 20 ns 50 ns 1 s 18 ns 20 ns 50 ns 1 s
8 - 170 85 15 - 150 125 110
6 170 165 80 12 145 140 115 105
mA
max
ICCOP Read per byte
(3)
Dynamic Operating Current
mA
max
ICCOP(4) Write per byte
Dynamic Operating Current
mA
max
Notes:
1. 2. 3. 4.
All CSx >VIH All CSx > VCC - 0.3V F = 1/TAVAV, Iout = 0 mA, WEx = OE = VIH, VIN = GND/VCC, VCC max. F = 1/TAVAW, Iout = 0 mA, WEx = VIL, OE = VIH , VIN = GND/VCC, VCC max.
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Data Retention Mode
Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention: 1. During data retention chip select CSx must be held high within VCC to VCC -0.2V. 2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation. 3. During power-up and power-down transitions CSx and OE must be kept between VCC + 0.3V and 70% of VCC. 4. The RAM can begin operation > tR ns after VCC reaches the minimum operation voltages (3V). Figure 5. Data Retention Timing
vcc
CSx
Data Retention Characteristics
Parameter VCCDR tCDR tR ICCDR (2) 1. 2. Description VCC for data retention Chip deselect to data retention time Operation recovery time Data retention current TAVAV = Read cycle time. All CSx = VCC, VIN = GND/VCC. Min 2.0 0.0 tAVAV
(1)
Typ TA = 25C - - -
Max - - - 6 (AT68166F-20)
Unit V ns ns
-
3 4.5 (AT68166F-18)
mA
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AT68166F/G
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AT68166F/G
AC Characteristics
Temperature Range:................................................ -55 +125C Supply Voltage: ....................................................... 3.3 +0.3V Input Pulse Levels: .................................................. GND to 3.0V Input Rise and Fall Times:....................................... 3ns (10 - 90%) Input and Output Timing Reference Levels: ............ 1.5V Output Loading IOL/IOH:............................................ See Figure 3 Figure 6. AC Test Loads Waveforms
General
Specific (TWLQZ, TWHQX, TELQX, TEHQZ TGLQX, TGHQZ)
Write Cycle
Table 4. Write cycle timings(1)
AT68166F-20 AT68166F-18
Symbol TAVAW TAVWL TAVWH TDVWH TELWH TWLQZ TWLWH TWHAX TWHDX TWHQX
Parameter Write cycle time Address set-up time Address valid to end of write Data set-up time CS low to write end Write low to high Z(2) Write pulse width Address hold from end of write Data hold time Write high to low Z(2)
min 20 2 14 9 12 12 0 2 5
max 10 -
min 18 2 11 8 12 9 0 1 3
max 8 -
Unit ns ns ns ns ns ns ns ns ns ns
Notes:
1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode. 2. Parameters guaranteed, not tested, with output loading 5 pF. (See "AC Test Loads Waveforms" on page 9.)
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Figure 7. Write Cycle 1. WE Controlled, OE High During Write
ADDRESS CSx
E WEx E
OE I/Os
Figure 8. Write Cycle 2. WE Controlled, OE Low
ADDRESS
CSx
WEx E
E
I/Os
Figure 9. Write Cycle 3. CS Controlled
ADDRESS CSx
WEx E
I/Os
The internal write time of the memory is defined by the overlap of CS Low and WE LOW. Both signals must be activated to initiate a write and either signal can terminate a write by going in active mode. The data input setup and hold timing should be referenced to the active edge of the signal that terminates the write. Data out is high impedance if OE= VIH.
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AT68166F/G
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AT68166F/G
Read Cycle
Table 5. Read cycle timings(1)
AT68166F-20 AT68166F-18
Symbol TAVAV TAVQV TAVQX TELQV TELQX TEHQZ TGLQV TGLQX TGHQZ Notes:
Parameter Read cycle time Address access time Address valid to low Z Chip-select access time CS low to low Z(2) CS high to high Z(2) Output Enable access time OE low to low Z(2) OE high to high Z (2)
min 20 5 5 2 -
max 20 20 9 11 9
min 18 5 5 2 -
max 18 18 8 8 8
Unit ns ns ns ns ns ns ns ns ns
1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode. 2. Parameters guaranteed, not tested, with output loading 5 pF. (See "AC Test Loads Waveforms" on page 9.)
Figure 10. Read Cycle nb 1: Address Controlled (CS = OE = VIL, WE = VIH)
ADDRESS
DOUT
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Figure 11. Read Cycle nb 2: Chip Select Controlled (WE = VIH)
CSx
OE
DOUT
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AT68166F/G
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AT68166F/G
Typical Applications
32-bit mode application
This section presents some standard implementations of the AT68166F/G in application.
When used on a 32-bit (word) application, the module shall be connected as follow : * * * The 32 lines of data are connected to distinct data lines The four CSx are connected together and linked to a single host CS output Each one of the four WEx is connected to a dedicated WE line on the host to allow byte, half word and word format write.
Figure 12. 32-bit typical application ( 1 SRAM bank)
AT68166F/G
RAMS0* RAMOE0* RWE[3:0]* CS[3:0] OE WE[3:0] A[17:0] I/O[31:0] A A[19:2] D[31:0] A[19:2] D[31:0] D
AT697E
A[27:0] D[31:0]
16-bit mode application
When used on a 16-bit (half word) application, the module can be connected as presented in the following figure. This allows use of a single AT68166F/G part for two SRAM memory banks. All input controls of the AT68166F/G not used in the application shall be pulled-up. Figure 13. 16-bit typical application (two SRAM banks)
RAMOE[1:0]* RAMS1* RWE0* RAMS0* RWE0* OE
AT68166F/G
A[17:0] I/O[31:16] I/O[15:0] A[18:1] D[31:16] D[31:16] A[18:1] D[31:0]
A D
CS[3:2] WE[3:2] CS[1:0] WE[1:0]
AT697E
A[27:0] D[31:0]
8-bit mode application
When used on a 8-bit (byte) application, the module can be connected as presented in the following figure. This allows use of a single AT68166F/G part for up to four SRAM memory banks. All input controls of the AT68166F/G not used in the application shall be pulled-up.
13
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Figure 14. 8-bit typical application (two SRAM banks)
RAMOE[1:0]* RAMS2* RWE0* RAMS2* RWE0* RAMS1* RWE0* OE CS[3] WE[3] CS[2] WE[2] CS[1] WE[1] CS[0] WE[0]
AT68166F/G
A[17:0] A[17:0] D[31:24] D[31:24] D[31:24] D[31:24] A[17:0] D[31:0]
A D
I/O[31:24] I/O[23:16] I/O[15:8] I/O[7:0]
AT697E
RAMS0* RWE0*
A[27:0] D[31:0]
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AT68166F/G
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AT68166F/G
Ordering Information
Part Number AT68166F AT68166F-YM20-E 5962-0622902QXC 5962-0622902VXC 5962R0622902VXC AT68166F-YM20-SCC AT68166F-YS18-E AT68166F-YS18-MQ(1) AT68166F-YS18-SV
(1) (1) (1)
Temperature Range
Speed
Package
Flow
25C -55 to +125C -55 to +125C -55 to +125C -55 to +125C 25C -55 to +125C -55 to +125C -55 to +125C -55 to +125C Note:
20 ns 20 ns 20 ns 20 ns 20 ns 18 ns 18 ns 18 ns 18 ns 18 ns
MQFP68 MQFP68 MQFP68 MQFP68 MQFP68 MQFP68 MQFP68 MQFP68 MQFP68 MQFP68
Engineering Samples QML Q QML V QML V RHA ESCC Engineering Samples QML Q QML V QML V RHA ESCC
AT68166F-YS18-SR
AT68166F-YS18-SCC
1. Will be replaced by SMD part number when available.
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Package Drawings
68-lead Quad Flat Pack (950 Mils) with non conductive tie bar
Note: Note:
Lid is connected to Ground. YM and YS package drawings are identical.
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AT68166F/G
7747A-AERO-07/07
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7747A-AERO-07/07

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