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DAC1201D125
Dual 12-bit DAC, up to 125 Msps
Rev. 01 -- 27 November 2008 Product data sheet
1. General description
The DAC1201D125 is a dual-port, high-speed, 2-channel CMOS Digital-to-Analog Converter (DAC), optimized for high dynamic performance with low power dissipation. Supporting an update rate of up to 125 Msps, the DAC1201D125 is suitable for Direct IF applications. Separate write inputs allow data to be written to the two DAC ports independently of one another. Two separate clocks control the update rate of each DAC port. The DAC1201D125 can interface two separate data ports or one single interleaved high-speed data port. In Interleaved mode, the input data stream is demultiplexed into its original I and Q data and latched. The I and Q data is then converted by the two DACs and updated at half the input data rate. Each DAC port has a high-impedance differential current output, suitable for both single-ended and differential analog output configurations. The DAC1201D125 is pin compatible with the AD9765, DAC2902 and DAC5662.
2. Features
I I I I Typical 185 mW power dissipation 16 mW power-down SFDR: 81 dBc; fo = 1 MHz; fs = 52 Msps SFDR: 78 dBc; fo = 10.4 MHz; fs = 78 Msps I 1.8 V, 3.3 V and 5 V compatible digital I SFDR: 74 dBc; fo = 1 MHz; inputs fs = 52 Msps; -12 dBFS I Internal and external reference I LQFP48 package I 2 mA to 20 mA full-scale output current I Industrial temperature range of -40 C to +85 C Dual 12-bit resolution 125 Msps update rate Single 3.3 V supply Dual-port or Interleaved data modes I I I I
3. Applications
I Quadrature modulation I Medical/test instrumentation I Direct IF applications I Direct digital frequency synthesis I Arbitrary waveform generator
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
4. Ordering information
Table 1. Ordering information Package Name DAC1201D125HL LQFP48 Description plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm Version SOT313-2 Type number
5. Block diagram
DA11 to DA0 WRTA/IQWRT CLKA/IQCLK
12
INPUT A LATCH
12
DAC A LATCH
12
DAC A
IOUTAP IOUTAN REFIO
REFERENCE
AVIRES BVIRES GAINCTRL PWD
DAC1201D125
CLKB/IQRESET WRTB/IQSEL DB11 to DB0
12
CONTROL AMPLIFIER
INPUT B LATCH
12
DAC B LATCH
12
DAC B
IOUTBP IOUTBN
VDDA
AGND
VDDD
DGND
001aai976
Fig 1.
Block diagram
DAC1201D125_1
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Product data sheet
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2 of 26
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
6. Pinning information
6.1 Pinning
42 GAINCTRL
40 IOUTBN
45 IOUTAN
46 IOUTAP
39 IOUTBP
44 AVIRES
41 BVIRES
43 REFIO
48 MODE
38 AGND
47 VDDA
DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3
1 2 3 4 5 6 7 8 9
37 PWD 36 n.c. 35 n.c. 34 DB0 33 DB1 32 DB2 31 DB3 30 DB4 29 DB5 28 DB6 27 DB7 26 DB8 25 DB9 DB10 24
001aai975
DAC1201D125HL
DA2 10 DA1 11 DA0 12 n.c. 13 n.c. 14 DGND 15 VDDD 16 WRTA/IQWRT 17 CLKA/IQCLK 18 CLKB/IQRESET 19 WRTB/IQSEL 20 DGND 21 VDDD 22 DB11 23
Fig 2.
Pin configuration SOT313-2 (LQFP48)
6.2 Pin description
Table 2. Symbol DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 n.c.
DAC1201D125_1
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 Type[1] I I I I I I I I I I I I Description DAC A, data input bit 11 (MSB) DAC A, data input bit 10 DAC A, data input bit 9 DAC A, data input bit 8 DAC A, data input bit 7 DAC A, data input bit 6 DAC A, data input bit 5 DAC A, data input bit 4 DAC A, data input bit 3 DAC A, data input bit 2 DAC A, data input bit 1 DAC A, data input bit 0 (LSB) not connected
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Product data sheet
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NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
Pin description ...continued Pin 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I S O O I I I/O I O O S I G S I I I I G S I I I I I I I I I I I I Type[1] Description not connected digital ground digital supply voltage input write port A/input write IQ in Interleaved mode input clock port A/input clock IQ in Interleaved mode input clock port B/reset IQ in Interleaved mode input write port B/select IQ in Interleaved mode digital ground digital supply voltage DAC B, data input bit 11 (MSB) DAC B, data input bit 10 DAC B, data input bit 9 DAC B, data input bit 8 DAC B, data input bit 7 DAC B, data input bit 6 DAC B, data input bit 5 DAC B, data input bit 4 DAC B, data input bit 3 DAC B, data input bit 2 DAC B, data input bit 1 DAC B, data input bit 0 (LSB) not connected not connected Power-down mode enable input analog ground DAC B current output complementary DAC B current output adjust DAC B for full-scale output current gain control mode enable input reference voltage input/output adjust DAC A for full-scale output current complementary DAC A current output DAC A current output analog supply voltage select between Dual-port or Interleaved mode
Table 2. Symbol n.c. DGND VDDD
WRTA/IQWRT CLKA/IQCLK CLKB/IQRESET WRTB/IQSEL DGND VDDD DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 n.c. n.c. PWD AGND IOUTBP IOUTBN BVIRES GAINCTRL REFIO AVIRES IOUTAN IOUTAP VDDA MODE
[1]
Type description: S = Supply; G = Ground; I = Input; O = Output; I/O = Input/Output.
DAC1201D125_1
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Product data sheet
Rev. 01 -- 27 November 2008
4 of 26
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
7. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDD VDDA VDD VI Parameter digital supply voltage analog supply voltage supply voltage difference input voltage between analog and digital supply voltage digital inputs referenced to DGND pins REFIO, AVIRES, BVIRES referenced to AGND VO Tstg Tamb Tj
[1]
Conditions
[1] [1]
Min -0.3 -0.3 -150 -0.3 -0.3 -0.3 -55 -40 -
Max +5.0 +5.0 +150 +5.5 +5.5
Unit V V mV V V
output voltage storage temperature ambient temperature junction temperature
All supplies are connected together.
pins IOUTAP, IOUTAN, IOUTBP and IOUTBN referenced to AGND
VDDA + 0.3 V +150 +85 125 C C C
8. Thermal characteristics
Table 4. Symbol Rth(j-a) Rth(c-a) Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from case to ambient Conditions in free air in free air Typ 89.3 60.6 Unit K/W K/W
9. Characteristics
Table 5. Characteristics VDDD = VDDA = 3.3 V; AGND and DGND connected together; IO(fs) = 20 mA and Tamb = -40 C to +85 C; typical values measured at Tamb = 25 C. Symbol Supplies VDDD VDDA IDDD IDDA Ptot Ppd digital supply voltage analog supply voltage digital supply current analog supply current total power dissipation power dissipation in power-down mode fs = 65 Msps, fo = 1 MHz, VDD = 3.0 V to 3.6 V fs = 65 Msps, fo = 1 MHz, VDD = 3.0 V to 3.6 V fs = 65 Msps, fo = 1 MHz, VDD = 3.0 V to 3.6 V 3.0 3.0 3.3 3.3 6 50 185 16.5 3.65 3.65 7 65 260 V V mA mA mW mW Parameter Conditions Min Typ Max Unit
DAC1201D125_1
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Product data sheet
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NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
Table 5. Characteristics ...continued VDDD = VDDA = 3.3 V; AGND and DGND connected together; IO(fs) = 20 mA and Tamb = -40 C to +85 C; typical values measured at Tamb = 25 C. Symbol VIL VIH IIL IIH Ci IO(fs) VO Ro Co VO(ref) IO(ref) Vi Ri fs tw(WRT) tw(CLK) th(i) tsu(i) td tt ts INL DNL Eoffset EG G Parameter LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input capacitance full-scale output current output voltage output resistance output capacitance reference output voltage reference output current input voltage input resistance sampling frequency WRT pulse width CLK pulse width input hold time input set-up time delay time transition time settling time integral non-linearity differential non-linearity offset error gain error gain mismatch with external reference with internal reference between DAC A and DAC B rising or falling transition (10 % to 90 % or 90 % to 10 %) 1 LSB 25 C -40 C to +85 C -40 C to +85 C Static accuracy (relative to full-scale) -0.02 -1.9 -2.9 -0.36 1.5 2.1 0.05 +0.02 +2.5 +2.9 +0.36 % % % %
[1] [1]
Conditions
Min DGND 1.3
Typ 5 5 5 150 3 1.26 100 1 1 0.6 40 0.55 0.2
Max 0.9 VDDD 20 +1.25 1.27 1.26 125 0.70 0.75 0.3
Unit V V A A pF mA V k pF V nA V M Msps ns ns ns ns ns ns ns LSB LSB LSB
Digital inputs
VIL = 0.9 V VIH = 1.3 V
[1]
2
[1] [1] [1]
Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN) differential outputs compliance range -1 1.25 1.0 pins WRTA, WRTB pins CLKA, CLKB 2 2 1 1.8 0.4 0.3 0.15 compliance range
Reference voltage input/output (REFIO)
Input timing, see Figure 18
Output timing (IOUTAP, IOUTAN, IOUTBP and IOUTBN)
[1]
Static linearity
DAC1201D125_1
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Product data sheet
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6 of 26
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
Table 5. Characteristics ...continued VDDD = VDDA = 3.3 V; AGND and DGND connected together; IO(fs) = 20 mA and Tamb = -40 C to +85 C; typical values measured at Tamb = 25 C. Symbol SFDR Parameter spurious free dynamic range Conditions B = Nyquist fs = 52 Msps; fo = 1 MHz 0 dBFS -6 dBFS -12 dBFS fs = 52 Msps; 0 dBFS fo = 5.24 MHz fs = 78 Msps; 0 dBFS fo = 10.4 MHz fo = 15.7 MHz fs = 100 Msps; 0 dBFS fo = 5.04 MHz fo = 20.2 MHz fs = 125 Msps; 0 dBFS fo = 20.1 MHz within a window fs = 52 Msps; fo = 1 MHz; 2 MHz span fs = 52 Msps; fo = 5.24 MHz; 10 MHz span fs = 78 Msps; fo = 5.26 MHz; 2 MHz span fs = 125 Msps; fo = 5.04 MHz; 10 MHz span THD total harmonic distortion fs = 52 Msps; fo = 1 MHz fs = 78 Msps; fo = 5.26 MHz fs = 100 Msps; fo = 5.04 MHz fs = 125 Msps; fo = 20.1 MHz MTPR multitone power ratio fs = 65 Msps; 2 MHz < fo < 2.99 MHz; 8 tones at 110 kHz spacing at 0 dB full-scale fs = 100 Msps; fo = 5.04 MHz fs = 78 Msps; fo = 10.4 MHz fs = 125 Msps; fo = 20.1 MHz
[1] Guaranteed by design.
Min
Typ
Max
Unit
Dynamic performance
60 79 -
81 80 74 79 78 71 77 69 68 89 87 90 90 -78 -76 -74 -64 80
-60 -
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
NSD cs
noise spectral density channel separation
-
-148.7 88.0 83.5 -
dBm/Hz dBc dBc
DAC1201D125_1
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Product data sheet
Rev. 01 -- 27 November 2008
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NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
80 SFDR (dBc) 76
(2)
001aai997
(1)
72
(3)
68
(4)
64 -60
-20
0
20
60 T (C)
100
(1) fo = 5 MHz (2) fo = 10 MHz (3) fo = 15 MHz (4) fo = 20 MHz
Fig 3.
SFDR as a function of the ambient temperature at 125 Msps
DAC1201D125_1
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Product data sheet
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NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
0 (dBm) -20
001aai985
-40
-60
-80
-100 0 10 20 f (MHz) 30
a. fs = 52 Msps; fc = 5.24 MHz; = 0 dBFS
0 (dBm) -20
001aai987
-40
-60
-80
-100 0 10 20 30 40 f (MHz) 50
b. fs = 100 Msps; fc = 20 MHz; = 0 dBFS Fig 4. 1-tone SFDR
DAC1201D125_1
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Product data sheet
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NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
0 (dBm) -20
001aai988
-40
-60
-80
-100 0 10 20 30 f (MHz) 40
fs = 78 Msps; fc = 9.44 MHz, fc = 10.44 MHz; = 0 dBFS
Fig 5.
2-tone SFDR
0 (dBm) -20
001aai989
-40
-60
-80
-100 0 10 20 f (MHz) 30
fs = 52 Msps; fc = 6.25 MHz, fc = 6.75 MHz, fc = 7.25 MHz, fc = 7.75 MHz; = 0 dBFS
Fig 6.
4-tone SFDR
DAC1201D125_1
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Product data sheet
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NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
0 (dBm) -20
001aai990
-40
-60
-80
-100 0 10 20 30 f (MHz) 40
fs = 78 Msps; from fc = 9.5 MHz, 110 kHz spacing; = 0 dBFS
Fig 7.
8-tone SFDR
0.8 INL (dB) 0.4
001aaj002
0
-0.4
-0.8 0 744 1488 2232 2976 3720 input code 4464
Fig 8.
INL as a function of the input code
DAC1201D125_1
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Product data sheet
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NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
0.2 DNL (dB) 0.1
001aaj001
0
-0.1
-0.2 0 756 1512 2268 3024 3780 input code 4536
Fig 9.
DNL as a function of the input code
85 SFDR (dBc) 80
001aaj040
75
(1)
70
(2)
65
(3)
60 0 5 10 15 fo (MHz) 20
(1) fo = 0 dBFS (2) fo = -6 dBFS (3) fo = -12 dBFS
Fig 10. SFDR full-scale at 78 Msps as a function of the output frequency
DAC1201D125_1
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Product data sheet
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NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
85 SFDR (dBc) 80
001aaj044
75
70
(1)
65
(2) (3)
60 0 5 10 15 20 fo (MHz) 25
(1) fo = 0 dBFS (2) fo = -6 dBFS (3) fo = -12 dBFS
Fig 11. SFDR full-scale at 125 Msps as a function of the output frequency
16 IDDD (mA) 12
001aai938
(1) (2) (3)
8
(4)
4
0 0 0.1 0.2 0.3 0.4 fo/fs 0.5
(1) fs = 125 Msps (2) fs = 100 Msps (3) fs = 78 Msps (4) fs = 52 Msps
Fig 12. Digital supply current as a function of fo/fs
DAC1201D125_1
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Product data sheet
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NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
60 IDDA (mA) 40
001aaj032
20
0 0 5 10 15 lO (mA) 20
Fig 13. Analog supply current as a function of the output current
10. Application information
10.1 General description
The DAC1201D125 is a dual 12-bit DAC operating up to 125 Msps. Each DAC consists of a segmented architecture, comprising a 7-bit thermometer sub-DAC and a 5-bit binary weighted sub-DAC. Two modes are available for the digital input depending on the status of pin MODE. In Dual-port mode, each DAC uses its own data input line at the same frequency as the update rate. In Interleaved mode, both DACs use the same data input line at twice the update rate. Each DAC generates on pins IOUTAP/IOUTAN and IOUTBP/IOUTBN two complementary current outputs. This provides a full-scale output current (IO(fs)), up to 20 mA. A single common or two independent full-scale current controls can be selected for both channels using pin GAINCTRL. An internal reference voltage is available for the reference current which is externally adjustable using pin REFIO. The DAC1201D125 operates at 3.3 V and has separate digital and analog power supplies. Pin PWD is used to power-down the device. The digital input is 1.8 V compliant, 3.3 V compliant and 5 V tolerant.
10.2 Input data
The DAC1201D125 input follows a straight binary coding where DA11 and DB11 are the Most Significant Bits (MSB) and DA0 and DB0 are the Least Significant Bits (LSB). The setting applied to pin MODE defines whether the DAC1201D125 operates in Dual-port mode or in Interleaved mode, (see Table 6).
DAC1201D125_1
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Product data sheet
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NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
Mode selection DA11 to DA0 DB11 to DB0 active active off active Pin 17 IQWRT WRTA Pin 18 Pin 19 IQCLK IQRESET CLKA CLKB Pin 20 IQSEL WRTB
Table 6. LOW
Mode Function Interleaved mode HIGH Dual-port mode
10.2.1 Dual-port mode
The data and clock circuit for Dual-port mode operation is shown in Figure 14.
DA11 to DA0 WRTA CLKA CLKB WRTB DB11 to DB0
12
INPUT A 12 LATCH
DAC A LATCH
12
INPUT B 12 LATCH
DAC B LATCH
001aai977
Fig 14. Dual-port mode operation
Each DAC has its own independent data and clock inputs. The data enters the input latch on the rising edge of the WRTA/WRTB signal and is transferred to the DAC latch. The output is updated on the rising edge of the CLKA/CLKB signal.
DA11 to DA0/ DB11 to DB0
N
N+1
N+2
N+3
WRTA/ WRTB
CLKA/ CLKB
IOUTAP, IOUTAN/ IOUTBP, IOUTBN N-2 N-1 N N+1 N+2
001aaj115
Fig 15. Dual-port mode timing
DAC1201D125_1
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Product data sheet
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NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
10.2.2 Interleaved mode
The data and clock circuit for Interleaved mode operation is illustrated in Figure 16.
DA11 to DA0
12
INPUT A 12 LATCH
DAC A LATCH
12
INPUT B 12 LATCH
DAC B LATCH
IQWRT IQSEL IQCLK IQRESET /2
001aai978
Fig 16. Interleaved mode
In Interleaved mode, both DACs use the same data and clock inputs at twice the update rate. Data enters the latch on the rising edge of IQWRT. The data is sent to either latch A or latch B, depending on the value of IQSEL. The IQSEL transition must occur when IQWRT and IQCLK are LOW. The IQCLK is divided by 2 internally and the data is transferred to the DAC latch. It is updated on its rising edge. When IQRESET is HIGH, IQCLK is disabled, see Figure 17.
DA11 to DA0/ DB11 to DB0
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
IQSEL
IQWRT
IQCLK
IQRESET
N IOUTAP, IOUTAN XX N+2 N+4
IOUTBP, IOUTBN
N+1 XX N+3 N+5
001aaj116
Fig 17. Interleaved mode timing
DAC1201D125_1
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Product data sheet
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NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
10.3 Timing
The DAC1201D125 can operate at an update rate up to 125 Msps. This generates an input data rate of 125 MHz in Dual-port mode and 250 MHz in Interleaved mode. The timing of the DAC1201D125 is shown in Figure 18.
tsu(i) DA11 to DA0/ DB11 to DB0
th(i)
WRTA/ WRTB tw(WRT) CLKA/ CLKB tw(CLK) IOUTAP, IOUTAN/ IOUTBP, IOUTBN td 90 % 10 % tt ts
001aaj117
td(clk)
Fig 18. Timing of the DAC1201D125
The typical performances are measured at 50 % duty cycle but any timing within the limits of the characteristics will not alter the performance.
* A configuration resulting in the same timing for the signals WRTA/WRTB and
CLKA/CLKB, can be achieved either by synchronizing them or by connecting them together.
* The rising edge of the CLKA/CLKB signal can also be placed in a range from half a
period in front of the rising edge of the WRTA/WRTB signal to half a period minus 1 ns after the rising edge of the WRTA/WRTB signal. A typical set-up time of 0 ns and a hold time of 0.6 ns enables the DAC1201D125 to be easily integrated into any application.
10.4 DAC transfer function
The full-scale output current for each DAC is the sum of the two complementary current outputs: I O ( fs ) = I IOUTP + I IOUTN The output current depends on the digital input data: DATA I IOUTP = I O ( fs ) x --------------- 4096- ( 4095 - DATA ) I IOUTN = I O ( fs ) x -------------------------------------- 4096 (1)
DAC1201D125_1
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Product data sheet
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NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
Table 7 shows the output current as a function of the input data, when IO(fs) = 20 mA.
Table 7. Data 0 ... 2047 ... 4095 DAC transfer function DA11/DB11 to DA0/DB0 0000 0000 0000 ... 1000 0000 0000 ... 1111 1111 1111 IOUTAP/IOUTBP 0 mA ... 10 mA ... 20 mA IOUTAN/IOUTBN 20 mA ... 10 mA ... 0 mA
10.5 Full-scale current adjustment
The DAC1201D125 integrates one 1.25 V reference and two current sources to adjust the full-scale current in both DACs. The internal reference configuration is shown in Figure 19.
CURRENT SOURCE
AVIRES
RA
AGND 1.25 V REFERENCE REFIO
100 nF
AGND CURRENT SOURCE BVIRES
RB
AGND
001aai822
Fig 19. Internal reference configuration
The bias current is generated by the output of the internal regulator connected to the inverting input of the internal operational amplifiers. The external resistors RA and RB are connected to pins AVIRES and BVIRES, respectively. This configuration is optimal for temperature drift compensation because the band gap can be matched with the voltage on the feedback resistors. The relationship between full-scale output current (IO(fs)) at the output of channel A or channel B and the resistor is: 24V REFIO I O ( fs ) = -----------------------RA (2)
The output current of the two DACs is typically fixed at 20 mA when both resistors RA and RB are set to 1.5 k. The operational range of DAC1201D125 is from 2 mA to 20 mA. It is recommended to decouple pin REFIO using a 100 nF capacitor.
DAC1201D125_1
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Product data sheet
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NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
An external reference can also be used for applications requiring higher accuracy or precise current adjustment. Due to the high input impedance of pin REFIO, applying an external source disables the band gap.
10.6 Gain control
Table 8 shows how to select the different gain control modes.
Table 8. Gain control Mode independent gain control common gain control DAC A full-scale control AVIRES AVIRES DAC B full-scale control BVIRES AVIRES
GAINCTRL LOW HIGH
In Independent gain mode, both full-scale currents can be adjusted independently using resistors RA on pin AVIRES and RB on pin BVIRES. In Common gain mode, both full-scale currents are adjusted with the same resistor and divided by two in both DACs.
10.7 Analog outputs
See Figure 20 for the analog output circuit of one DAC. This circuit consists of a parallel combination of PMOS current sources and associated switches for each segment.
IOUTAP/IOUTBP IOUTAN/IOUTBN
RL RL
AGND
AGND
001aai821
Fig 20. Equivalent analog output circuit
Cascode source configuration enables the output impedance of the source to be increased, thus improving the dynamic performance by reducing distortion. The DAC1201D125 can be used with either:
* a differential output, coupled to a transformer (or operational amplifier) to reduce
even-order harmonics and noise
* a single-ended output for applications requiring unipolar voltage
A typical configuration is to use a 1 V p-p level on each output IOUTAP/IOUTBP and IOUTAN/IOUTBN. Several combinations can be used but they must respect the voltage compliance range.
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Product data sheet
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NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
10.7.1 Differential output using transformer
The use of a differential-coupled transformer output (see Figure 21) provides optimum distortion performance, and it helps to match the impedance and provides electrical isolation.
IOUTAP/ IOUTBP
Rdiff
T1-1T
Rload
IOUTAN/ IOUTBN
1:1
001aai935
Fig 21. Differential output with transformer
The center tap is grounded to allow the DC current flow to/from both outputs. If the center tap is open, the differential resistor must be replaced by two resistors connected to ground.
10.7.2 Single-ended output
Using a single load resistor on one current output will provide a unipolar output range, typically from 0 V to 0.5 V with a 20 mA full-scale current at a 50 load.
20 mA IOUTAP/ IOUTBP
Z = 50
50
50
0 V to 0.5 V
IOUTAN/ IOUTBN
25
001aai936
Fig 22. Single-ended output
The resistor on the other current output is 25 .
10.8 Power-down function
The DAC1201D125 has a power-down function to reduce the power consumption when it is not active.
Table 9. PWD LOW HIGH Power-down Device function active not active Power dissipation (typ) 185 mW 16.5 mW
DAC1201D125_1
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Product data sheet
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NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
10.9 Alternative devices
The following alternative devices are also available.
Table 10. Alternative devices Pin compatible Type number DAC1001D125 DAC1401D125 Description dual 10-bit DAC dual 14-bit DAC Sampling frequency up to 125 Msps up to 125 Msps
DAC1201D125_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 27 November 2008
21 of 26
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
10.10 Application diagram
RL
AGND
AGND
RL
AGND AGND
100 1.5 k
AGND
100 nF 1.5 k 100
3.3 V GAINCTRL AGND IOUTBN IOUTBP BVIRES AGND IOUTAN IOUTAP AVIRES
REFIO
MODE VDDA
DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 WRTA/IQWRT DGND CLKA/IQCLK WRTB/IQSEL CLKB/IQRESET DGND n.c. n.c. VDDD VDDD DB11 DB10 36 35 34 33 32
PWD
n.c. n.c. DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9
DAC1201D125
31 30 29 28 27 26 25
100 nF
100 nF
DGND
3.3 V
DGND
3.3 V
001aaj125
Dual-port mode (MODE = HIGH) DAC active (PWD = LOW) Independent channel gain (GAINCTRL = LOW)
Fig 23. Application diagram
DAC1201D125_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 27 November 2008
22 of 26
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
11. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 24. Package outline SOT313-2 (LQFP48)
DAC1201D125_1 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 27 November 2008
23 of 26
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
12. Abbreviations
Table 11. Acronym DNL dBFS IF INL LSB MSB PMOS SFDR Abbreviations Description Differential Non-Linearity deciBel Full-Scale Intermediate Frequency Integral Non-Linearity Least Significant Bit Most Significant Bit Positive-channel Metal-Oxide Semiconductor Spurious-Free Dynamic Range
13. Revision history
Table 12. Revision history Release date 20081127 Data sheet status Product data sheet Change notice Supersedes Document ID DAC1201D125_1
DAC1201D125_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 27 November 2008
24 of 26
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
14. Legal information
14.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
14.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
DAC1201D125_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 27 November 2008
25 of 26
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
16. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.2.1 10.2.2 10.3 10.4 10.5 10.6 10.7 10.7.1 10.7.2 10.8 10.9 10.10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application information. . . . . . . . . . . . . . . . . . 14 General description. . . . . . . . . . . . . . . . . . . . . 14 Input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Dual-port mode. . . . . . . . . . . . . . . . . . . . . . . . 15 Interleaved mode . . . . . . . . . . . . . . . . . . . . . . 16 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DAC transfer function . . . . . . . . . . . . . . . . . . . 17 Full-scale current adjustment . . . . . . . . . . . . . 18 Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Analog outputs . . . . . . . . . . . . . . . . . . . . . . . . 19 Differential output using transformer. . . . . . . . 20 Single-ended output . . . . . . . . . . . . . . . . . . . . 20 Power-down function . . . . . . . . . . . . . . . . . . . 20 Alternative devices . . . . . . . . . . . . . . . . . . . . . 21 Application diagram . . . . . . . . . . . . . . . . . . . . 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contact information. . . . . . . . . . . . . . . . . . . . . 25 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 November 2008 Document identifier: DAC1201D125_1

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