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| w Mobile Multimedia CODEC with Dual-Mode Class AB/D Speaker Driver DESCRIPTION The WM8991 is a highly integrated ultra-low power hi-fi codec designed for handsets rich in multimedia features such as mobile TV, digital audio playback and gaming. Ultra-low power and low noise interfaces to many other audio components in the system are provided. A powerful 1W speaker driver can operate in class D or AB modes, providing total flexibility to the system designer. Low leakage, high PSRR and pop/click suppression enable direct battery connection for the speaker supply. A very highly flexible input configuration supports multiple microphone or line inputs (mono or stereo, single-ended or differential). Four headphone drivers support fully differential headset drive, providing excellent crosstalk performance and bass response, maximising stereo effects, and allowing the removal of large and expensive headphone capacitors. Stereo 24-bit sigma-delta ADCs and DACs provide hi-fi quality audio record and playback, with a flexible digital audio interface supporting most commonly-used clocking schemes. An integrated low power PLL, an alternative DAC interface and TDM support provide additional flexibility. The WM8991 is supplied in very small and thin 5x5mm 65-ball BGA package, ideal for use in portable systems. WM8991 FEATURES DAC SNR 99dB (`A' weighted), THD -84dB at 48kHz, 3.3V ADC SNR 94dB (`A' weighted), THD -82dB at 48kHz, 3.3V Microphone interface (Up to four differential microphones) 1W Speaker driver - 1W into 8 BTL speaker at <0.1% THD - 80dB PSRR @217Hz - <1uA leakage with direct battery connection - Software-selectable class D or AB mode - Filterless connection supported - Pop/Click suppression Headphone / ear speaker drivers - 40mW output power into 16 at 3.3V - Fully differential and capless modes supported - Pop/Click suppression 4 Mono or stereo differential line outputs Powerful GPIO functions Ultra-low power consumption - 8.3mW analogue voice call - 13.7mW DAC playback to headphones On-chip PLL provides flexible clocking scheme Sample rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48kHz 65-ball 5x5mm BGA package APPLICATIONS Multimedia phones GPS WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ Pre-Production, May 2008, Rev 3.1 Copyright (c)2008 Wolfson Microelectronics plc WM8991 TABLE OF CONTENTS Pre-Production DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 TABLE OF CONTENTS .........................................................................................2 BLOCK DIAGRAM .................................................................................................4 PIN CONFIGURATION...........................................................................................5 ORDERING INFORMATION ..................................................................................5 PIN DESCRIPTION ................................................................................................6 ABSOLUTE MAXIMUM RATINGS.........................................................................8 RECOMMENDED OPERATING CONDITIONS .....................................................8 SPEAKER POWER DE-RATING CURVE............................................................10 ELECTRICAL CHARACTERISTICS ....................................................................12 TYPICAL POWER CONSUMPTION ....................................................................24 SPEAKER DRIVER PERFORMANCE .................................................................25 HEADPHONE DRIVER PERFORMANCE............................................................25 PSRR PERFORMANCE.......................................................................................26 AUDIO SIGNAL PATHS.......................................................................................28 SIGNAL TIMING REQUIREMENTS .....................................................................29 SYSTEM CLOCK TIMING............................................................................................ 29 TEST CONDITIONS .................................................................................................... 29 AUDIO INTERFACE TIMING - MASTER MODE ......................................................... 30 AUDIO INTERFACE TIMING - SLAVE MODE ............................................................ 31 AUDIO INTERFACE TIMING - TDM MODE ................................................................ 32 CONTROL INTERFACE TIMING - 2-WIRE MODE ..................................................... 33 CONTROL INTERFACE TIMING - 3-WIRE MODE ..................................................... 34 CONTROL INTERFACE TIMING - 4-WIRE MODE ..................................................... 35 INTERNAL POWER ON RESET CIRCUIT ..........................................................36 DEVICE DESCRIPTION.......................................................................................38 INTRODUCTION.......................................................................................................... 38 INPUT SIGNAL PATH.................................................................................................. 39 ANALOGUE TO DIGITAL CONVERTER (ADC) .......................................................... 54 DIGITAL MIXING ......................................................................................................... 57 DIGITAL TO ANALOGUE CONVERTER (DAC) .......................................................... 61 OUTPUT SIGNAL PATH.............................................................................................. 65 ANALOGUE OUTPUTS ............................................................................................... 76 THERMAL SHUTDOWN .............................................................................................. 81 GENERAL PURPOSE INPUT/OUTPUT ...................................................................... 82 DIGITAL AUDIO INTERFACE.................................................................................... 101 DIGITAL AUDIO INTERFACE CONTROL ................................................................. 113 CLOCKING AND SAMPLE RATES ............................................................................ 119 CONTROL INTERFACE ............................................................................................ 127 POWER MANAGEMENT ........................................................................................... 131 POP SUPPRESSION CONTROL............................................................................... 134 POWER DOMAINS.................................................................................................... 139 REGISTER MAP.................................................................................................140 REGISTER BITS BY ADDRESS ........................................................................142 DIGITAL FILTER CHARACTERISTICS .............................................................166 ADC FILTER RESPONSES ....................................................................................... 167 w PP, May 2008, Rev 3.1 2 Pre-Production WM8991 ADC HIGH PASS FILTER RESPONSES ................................................................... 167 DAC FILTER RESPONSES ....................................................................................... 168 DE-EMPHASIS FILTER RESPONSES ...................................................................... 169 APPLICATIONS INFORMATION .......................................................................170 RECOMMENDED EXTERNAL COMPONENTS......................................................... 170 PACKAGE DIMENSIONS ..................................................................................173 IMPORTANT NOTICE ........................................................................................174 ADDRESS:................................................................................................................. 174 w PP, May 2008, Rev 3.1 3 WM8991 LONMIX Mixer L Mixer R + Line 0dB, -6dB MIC R + Line -1 INPUT PGAs MIC L Record L Mixer L INPUT MIXERS LOP LOPMIX Left Line Input to Speaker Rx Voice Left Line Input to Left Output Mixer Left MIC Left ADC Bypass Mixer L LIN3 RXN LIN3/GPI7 0dB, +30dB 0dB, +30dB R MIC R ADC Bypass L ADC Bypass LADC bypass -12dB to +6dB -12dB to +6dB + RXVOICE AINLMUX MONO MIX DIFFINL -73dB to +6dB, 1dB steps -12dB to +6dB -12dB to +6dB + RXVOICE AINRMUX 0 -71.625dB to +17.625dB, 0.375dB steps DIFFINR ADC R R ADC Bypass L ADC Bypass L MIC R MIC LIN3 RIN3 -12dB to 0dB, 3dB steps Right ADC Bypass Right MIC Right Line Input to Right Output Mixer Rx Voice + Right Line Input to Speaker Record R + - -16.5dB to +30dB, 0.75dB steps 0dB, +30dB 0dB, +30dB MICBIAS Current Detect MICBIAS GPIO Alternative DAC Interface Alternative MCLK Button Control / Accessory Detect Clock Output Inverted ADCLRC + RIN1 RIN2 + RIN3/GPI8 RIN4/RXP en RIN34 + -12dB to +6dB -16.5dB to +30dB, 0.75dB steps -12dB to +6dB RIN12 VREF Inverted Out R Mixer L Mixer R 50k 50k 250k 250k 5k 5k + - + LIN4/RXN INMIXL -71.625dB to +17.625dB, 0.375dB steps -36dB to 0dB, 3dB steps + LIN1 LIN2 + + RIN3 - - - - w BLOCK DIAGRAM LON W WM8991 Inverted Out L OUTPUT MIXERS -16.5dB to +30dB, 0.75dB steps OUT3MIX 0dB, -6dB HP OUT3 LIN12 -12dB to +6dB -16.5dB to +30dB, 0.75dB steps -12dB to +6dB DIGITAL CORE L MIC -73dB to +6dB, 1dB steps + LOPGA LIN2 Mixer L DAC L HP LOUT LIN34 ADC L -12dB to 0dB, 3dB steps 0 -71.625dB to 0dB, 0.375dB steps SPKMIX SPKPGA -73dB to +6dB, 1dB steps SPK + DAC L LOMIX DAC L HIGH PASS FILTER (Voice or Hi-Fi) 1x, 1.27x, 1.4x, 1.52x, 1.67x 1.8x DAC R Mixer R + DAC R + RIN2 RADC bypass 0dB, -6dB, -12dB SPKN SPKP ROMIX -73dB to +6dB, 1dB steps INMIXR HIGH PASS FILTER (Voice or Hi-Fi) + DAC R -71.625dB to 0dB, 0.375dB steps 1xVMID, 1.27xVMID, 1.4xVMID, 1.52xVMID, 1.67xVMID 1.8xVMID ROPGA HP -73dB to +6dB, 1dB steps + ROUT 0dB, +6dB, +12dB, +18dB Mixer R RXP + HP OUT4 OUT4MIX 0dB, -6dB Mixer R MIC L MIC R ROPMIX + 0dB, -6dB Line -1 ROP AVDD DCVDD POR A-law and u-law support TDM Support DIGITAL AUDIO INTERFACE + Line RON RONMIX MCLK2 MCLK POR PLL SYSCLK CONTROL INTERFACE VMID AGND BCLK DGND DCVDD DBVDD HPVDD HPGND DACLRC DACDAT ADCDAT SPKVDD SPKGND ADCLRC/GPIO1 AVDD MCLK CSB/ADDR SDIN SCLK MODE GPIO6/ADCLRCB GPIO5/DACDAT2 GPIO4/DACLRC2 GPIO3/BCLK2 GPIO2/MCLK2 PP, May 2008, Rev 3.1 Pre-Production 4 Pre-Production WM8991 PIN CONFIGURATION 1 A B C D E F G H J AVDD 2 HPVDD 3 HPVDD 4 HPGND 5 HPGND 6 AGND 7 SPK VDD 8 SPK VDD 9 SPKP AVDD ROUT OUT4 OUT3 LOUT AGND VMID MIC BIAS SPKP LIN3/ GPI7 LIN4/ RXN SPK GND SPKN LIN1 LIN2 AGND AGND AGND SPK GND SPKN RIN1 RIN2 AGND AGND AGND LON LOP RIN3/ GPI8 RIN4/ RXP AGND AGND AGND RON ROP DGND DGND MODE SCLK DCVDD NC NC ADC LRC/ GPIO1 DAC LRC GPIO3/ BCLK2 GPIO5/ DAC DAT2 SDIN CSB/ ADDR DBVDD MCLK BCLK ADC DAT DAC DAT GPIO2/ MCLK2 GPIO4/ DAC LRC2 GPIO6/ ADC LRCB N/C ORDERING INFORMATION ORDER CODE WM8991GEB/V WM8991GEB/RV Note: Reel quantity = 3500 TEMPERATURE RANGE -40C to +85C -40C to +85C PACKAGE 65-ball BGA (Pb-free) 65-ball BGA (Pb-free, Tape and reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 PEAK SOLDERING TEMPERATURE 260C 260C w PP, May 2008, Rev 3.1 5 WM8991 PIN DESCRIPTION PIN NO B8 D1 D2 C1 NAME MICBIAS LIN1 LIN2 LIN3 / GPI7 LIN4 / RXN RIN1 RIN2 RIN3 / GPI8 RIN4 / RXP DCVDD DGND DBVDD AVDD AGND TYPE Analogue Output Analogue Input Analogue Input Analogue Input / Digital Input Analogue Input Microphone bias Left channel single-ended MIC input / Left channel negative differential MIC input Left channel line input / Left channel positive differential MIC input Left channel line input / Left channel negative differential MIC input / Accessory or button detect input pin Left channel line input / Left channel positive differential MIC input / Mono differential negative input (Rx voice -) Right channel single-ended MIC input / Right channel negative differential MIC input Right channel line input / Right channel positive differential MIC input Right channel line input / Right channel negative differential MIC input / Accessory or button detect input pin Left channel line input / Left channel positive differential MIC input / Mono differential positive input (Rx voice +) Digital core supply Digital ground (Return path for both DCVDD and DBVDD) Digital buffer (I/O) supply Analogue supply Analogue ground (Return path for AVDD) DESCRIPTION Pre-Production C2 E1 E2 F1 Analogue Input Analogue Input Analogue Input / Digital Input Analogue Input F2 H1 G1 G2 J1 A1 B1 A6 B6 D4 D5 D6 E4 E5 E6 F4 F5 F6 A2 A3 A4 A5 A7 A8 C8 D8 J2 J3 H5 J5 H4 J4 Supply Supply Supply Supply Supply Note: D4 to F6 are GND_PADDLES for thermal conduction and must be connected on the PCB for thermal reasons. HPVDD HPGND SPKVDD SPKGND MCLK BCLK DACLRC DACDAT ADCLRC / GPIO1 ADCDAT Supply Supply Supply Supply Digital Input Digital Input / Output Digital Input / Output Digital Input Digital Input / Output Digital Output Headphone supply Headphone ground (Return path for HPVDD) Supply for speaker driver Ground for speaker driver (Return path from SPKVDD) Master clock Audio interface bit clock Audio interface DAC left / right clock DAC digital audio data Audio interface ADC left / right clock / GPIO1 pin ADC digital audio data PP, May 2008, Rev 3.1 6 w Pre-Production PIN NO G8 H9 G9 H8 A9 B9 C9 D9 B5 B2 B4 B3 E8 E9 F8 F9 B7 J6 H6 J7 H7 J8 H2 H3 J9 NAME MODE CSB / ADDR SCLK SDIN SPKP SPKN LOUT ROUT OUT3 OUT4 LON LOP RON ROP VMID GPIO2 / MCLK2 GPIO3 / BCLK2 GPIO4 / DACLRC2 GPIO5 / DACDAT2 GPIO6 / ADCLRCB NC TYPE Digital Input Digital Input Digital Input Digital Input / Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Digital Input / Output Digital Input / Output Digital Input / Output Digital Input / Output Digital Input / Output Not connected DESCRIPTION Selects 2-wire or 3/4 -wire control 3/4 -wire chip select or 2-wire address select Control interface clock input Control interface data input / 2-wire acknowledge output Speaker positive output Speaker negative output Left headphone output Right headphone output Inverted left headphone output / Mono inverted output Inverted right headphone output / Mono non-inverted output Negative left line output / Positive right line output Positive left line output Negative right line output / Positive left line output Positive right line output Mid-rail voltage decoupling capacitor Alternative MCLK / GPIO pin Alternative BCLK / GPIO pin Alternative DACLRC / GPIO pin Alternative DACDAT / GPIO pin Inverted ADCLRC / GPIO pin WM8991 w PP, May 2008, Rev 3.1 7 WM8991 ABSOLUTE MAXIMUM RATINGS Pre-Production Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Supply voltages (excluding SPKVDD) SPKVDD Voltage range digital inputs Voltage range analogue inputs Operating temperature range, TA Junction temperature, TJMAX Storage temperature after soldering MIN -0.3V -0.3V DGND -0.3V AGND -0.3V -40C -40C -65C MAX +4.5V +7V DBVDD +0.3V AVDD +0.3V +85C +150C +150C RECOMMENDED OPERATING CONDITIONS PARAMETER Digital supply range (Core) Digital supply range (Buffer) Analogue supplies range Speaker supply range Ground Notes 1. 2. 3. 4. 5. 6. 7. Analogue, digital and speaker grounds must always be within 0.3V of each other. All digital and analogue supplies are completely independent from each other (i.e. not internally connected). DCVDD must be less than or equal to AVDD. DCVDD must be less than or equal to DBVDD. AVDD must be less than or equal to SPKVDD. SPKVDD must be high enough to support the peak output voltage when using DCGAIN and ACGAIN functions, to avoid output waveform clipping. Peak output voltage is AVDD*(DCGAIN+ACGAIN)/2. HPVDD must be equal to AVDD SYMBOL DCVDD DBVDD AVDD, HPVDD SPKVDD DGND, AGND, HPGND, SPKGND MIN 1.71 1.71 2.7 2.7 0 TYP MAX 3.6 3.6 3.6 5.5 UNIT V V V V V w PP, May 2008, Rev 3.1 8 Pre-Production WM8991 THERMAL PERFORMANCE Thermal analysis should be performed in the intended application to prevent the WM8991 from exceeding maximum junction temperature. Several contributing factors affect thermal performance most notably the physical properties of the mechanical enclosure, location of the device on the PCB in relation to surrounding components and the number of PCB layers. Connecting the GND balls through thermal vias and into a large ground plane will aid heat extraction. Three main heat transfer paths exist to surrounding air as illustrated below in Figure 1: Package top to air (radiation). Package bottom to PCB (radiation). Package balls to PCB (conduction). Figure 1 Heat Transfer Paths The temperature rise TR is given by TR = PD * JA PD is the power dissipated in the device. JA is the thermal resistance from the junction of the die to the ambient temperature and is therefore a measure of heat transfer from the die to surrounding air. JA is determined with reference to JEDEC standard JESD51-9. The junction temperature TJ is given by TJ = TA +TR, where TA is the ambient temperature. PARAMETER Operating temperature range Operating junction temperature Thermal Resistance SYMBOL TA TJ JA MIN -40 -40 TYP MAX 85 100 UNIT C C C/W 57 w PP, May 2008, Rev 3.1 9 WM8991 SPEAKER POWER DE-RATING CURVE Pre-Production The speaker driver has been designed to drive a maximum of 1W into 8 with a 5V supply. However, thermal restrictions defined by the BGA package JA limit the amount of power that can be safely dissipated in the device without exceeding the maximum operating junction temperature. Power dissipated in the device correlates directly with speaker efficiency, hence there are separate de-rating curves for class D and class AB operation. Under no circumstances should the recommended maximum powers be exceeded. CLASS D DE-RATING CURVES The de-rating curves shown in Figure 2 are based on a full scale sinusoidal input. P [W] 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 SPKVDD = 3.6V SPKVDD = 3.3V SPKVDD = 5.5V SPKVDD = 5V SPKVDD = 4.2V SPKVDD = 3V SPKVDD = 2.7V 55 60 65 70 75 80 85 T [C] Figure 2 Class D Speaker Power De-Rating Curve w PP, May 2008, Rev 3.1 10 Pre-Production WM8991 CLASS AB DE-RATING CURVE The de-rating curves shown in Figure 3 are based on a full scale sinusoidal input P [W] 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 SPKVDD = 3.6V SPKVDD = 3.3V SPKVDD = 5.5V SPKVDD = 5V SPKVDD = 4.2V SPKVDD = 3V SPKVDD = 2.7V 55 60 65 70 75 80 85 T [C] Figure 3 Class AB Speaker Power De-Rating Curve w PP, May 2008, Rev 3.1 11 WM8991 ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER A1 Maximum Full-Scale PGA Input Signal Level Note 1: This changes in proportion to AVDD (AVDD/3.3). Note 2: When mixing input PGA outputs and line inputs the total signal must not exceed 1Vrms (0dBV). Note 3: A 1.0Vrms differential signal equates to 0.5Vrms/-6dBV per input. A2 Maximum Full-Scale Line Input Signal Level Note 1: This changes in proportion to AVDD (AVDD/3.3). Note 2: When mixing line inputs, input PGA outputs and DAC outputs the total signal must not exceed 1Vrms (0dBV). Note 3: A 1.0Vrms differential signal equates to 0.5Vrms/-6dBV per input. Line input on LIN2 or RIN2 to SPKMIX 1.0 0 TEST CONDITIONS Single-ended PGA input on LIN1, LIN3, RIN1 or RIN3, output to INMIXL or INMIXR Differential PGA input on LIN1/LIN2, LIN3/LIN4, RIN1/RIN2 or RIN3/RIN4, output to INMIXL or INMIXR Differential input to two single-ended PGA inputs on LIN1/LIN3 or RIN1/RIN3, output to DIFFINL or DIFFINR MIN TYP 1.0 0 Pre-Production MAX UNIT Vrms dBV Analogue Input Pin Maximum Signal Levels (LIN1, LIN2, LIN3, LIN4, RIN1, RIN2, RIN3, RIN4) 1.0 0 Vrms dBV 1.0 0 Vrms dBV Line input on LIN2, LIN4, RIN2 or RIN4 to INMIXL or INMIXR 1.0 0 Vrms dBV Vrms dBV Line input on LIN3 or RIN3 to LOMIX or ROMIX 1.0 0 Vrms dBV Differential mono line input on RXP/RXN to RXVOICE 1.0 0 Vrms dBV Differential mono line input on RXP/RXN to differential output on OUT3/OUT4 1.0 0 Vrms dBV w PP, May 2008, Rev 3.1 12 Pre-Production WM8991 Test Conditions o DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, TA = +25 C, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER B1 PGA Input Resistance Note: this will be seen in parallel with the resistance of other enabled input paths from the same pin TEST CONDITIONS LIN1, LIN3, RIN1 or RIN3 (PGA Gain = -16.5dB) LIN1, LIN3, RIN1 or RIN3 (PGA Gain = 0dB) LIN1, LIN3, RIN1 or RIN3 (PGA Gain = +30dB) LIN2, LIN4, RIN2 or RIN4 (Constant for all gains) MIN TYP 57 33 2 65 MAX UNIT k k k k Analogue Input Pin Impedances (LIN1, LIN2, LIN3, LIN4, RIN1, RIN2, RIN3, RIN4) B2 Line Input Resistance Note: this will be seen in parallel with the resistance of other enabled input paths from the same pin LIN2 or RIN2 to INMIXL or INMIXR (-12dB) LIN2 or RIN2 to INMIXL or INMIXR (0dB) LIN2 or RIN2 to INMIXL or INMIXR (+6dB) LIN2 or RIN2 to SPKMIX (SPKATTN = 0dB) LIN2 or RIN2 to SPKMIX (SPKATTN = -12dB) LIN3 or RIN3 to LOMIX or ROMIX (0dB) LIN3 or RIN3 to LOMIX or ROMIX (-21dB) RXP and RXN via RXVOICE to AINLMUX or AINRMUX (Gain = +6dB) RXP and RXN via RXVOICE to AINLMUX or AINRMUX (Gain = 0dB) RXP and RXN via RXVOICE to AINLMUX or AINRMUX (Gain = -12dB) RXP and RXN via RXVOICE to AINLMUX and AINRMUX (Gain = +6dB) RXP and RXN via RXVOICE to AINLMUX and AINRMUX (Gain = 0dB) RXP and RXN via RXVOICE to AINLMUX and AINRMUX (Gain = -12dB) LIN4 to OUT3 or RIN4 to OUT4 (Gain = -6dB) LIN4 to OUT3 or RIN4 to OUT4 (Gain = 0dB) 60 15 7.5 20 20 k k k k k 20 224 k k 7.5 k 15 k 45 k 3.8 k 7.5 k 25 k 20 20 k k B3 Input Capacitance All analogue input pins 10 pF w PP, May 2008, Rev 3.1 13 WM8991 Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER C1 C2 C3 C4 C5 Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Mute Attenuation Common Mode Rejection Ratio (1kHz input) Guaranteed monotonic Inputs disconnected Single PGA in differential mode, gain = +30dB Single PGA in differential mode, gain = 0dB Single PGA in differential mode, gain = -16.5dB Differential input to DIFFINL or DIFFINR via LIN1/LIN3 or RIN1/RIN3, gain = 0dB Received Voice (RXP-RXN) Differential to Single-Ended Converter RXVOICE C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Mute Attenuation Fixed Gain Mute Attenuation Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Mute attenuation Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Mute attenuation Guaranteed monotonic LOUT and ROUT SPKPGA, LOPGA and ROPGA Output Programmable Gain Amplifiers (PGAs) OUT3, OUT4, LOP and ROP C23 C24 C25 C26 Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Mute attenuation OUT3 and OUT4 LOP and ROP (also applies to LON and RON) Speaker Attenuation (SPKATTN) C27 C28 C29 C30 Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Mute attenuation -12 0 6 80 -6 0 6 80 100 AINLMODE = 01 or AINRMODE = 01 AINLMODE = 01 or AINRMODE = 01 AINLMODE = 01 or AINRMODE = 01 AINLMODE = 01 or AINRMODE = 01 AINLMODE = 10 or AINRMODE = 10 AINLMODE = 10 or AINRMODE = 10 PGA Outputs to INMIXL and INMIXR PGA Outputs to INMIXL and INMIXR PGA Outputs to INMIXL and INMIXR Line Inputs and Record path to INMIXL and INMIXR Line Inputs and Record path to INMIXL and INMIXR Line Inputs and Record path to INMIXL and INMIXR -12 +6 3 95 0 95 0 +30 30 -12 +6 3 95 -73 +6 1 80 70 TEST CONDITIONS MIN TYP -16.5 30 1.5 90 60 50 50 45 Pre-Production MAX UNIT dB dB dB dB dB Input Programmable Gain Amplifiers (PGAs) LIN12, LIN34, RIN12 and RIN34 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB PGA Output Differential to Single Ended Converters DIFFINL and DIFFINR Input Mixers INMIXL and INMIXR Output Programmable Gain Amplifiers (PGAs) SPKPGA, LOPGA, ROPGA, LOUT and ROUT w PP, May 2008, Rev 3.1 14 Pre-Production WM8991 Test Conditions o DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, TA = +25 C, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER ADC Input Path Performance D1 SNR (A-weighted) THD (-1dBFS input) THD+N (-1dBFS input) Crosstalk (L/R) AVDD PSRR (217Hz) DCVDD PSRR (217Hz) SNR (A-weighted) THD (-1dBFS input) THD+N (-1dBFS input) D2 SNR (A-weighted) THD (-1dBFS input) THD+N (-1dBFS input) Crosstalk (L/R) SNR (A-weighted) THD (-1dBFS input) THD+N (-1dBFS input) D3 SNR (A-weighted) THD (-1dBFS input) THD+N (-1dBFS input) Crosstalk (L/R) AVDD PSRR (217Hz) SNR (A-weighted) THD (-1dBFS input) THD+N (-1dBFS input) D4 SNR (A-weighted) THD (-1dBFS input) THD+N (-1dBFS input) Crosstalk (L/R) SNR (A-weighted) THD (-1dBFS input) THD+N (-1dBFS input) D5 SNR (A-weighted) THD (-1dBFS input) THD+N (-1dBFS input) SNR (A-weighted) THD (-1dBFS input) THD+N (-1dBFS input) Input PGAs to ADC via INMIXL or INMIXR, AVDD = 2.7V Input PGAs to ADC via DIFFINL or DIFFINR, AVDD = 3.3V Input PGAs to ADC via DIFFINL or DIFFINR, AVDD = 2.7V RXP-RXN to one ADC via RXVOICE, AVDD = 3.3V RXP-RXN to one ADC via RXVOICE, AVDD = 2.7V 85 Line inputs to ADC via INMIXL and INMIXR, AVDD = 2.7V Record path (DACs to ADCs via INMIXL and INMIXR), AVDD = 3.3V Record path (DACs to ADCs via INMIXL and INMIXR), AVDD = 2.7V Input PGAs to ADC via INMIXL or INMIXR, AVDD = 3.3V 85 Line inputs to ADC via INMIXL and INMIXR, AVDD = 3.3V 85 94 -84 -82 -100 45 80 93 -78 -76 93 -83 -81 -95 92 -78 -76 94 -84 -82 -100 45 92 -78 -76 94 -82 -80 -100 92 -73 -71 94 -81 -79 92 -78 -76 -75 -73 -75 -73 -75 -73 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB TEST CONDITIONS MIN TYP MAX UNIT w PP, May 2008, Rev 3.1 15 WM8991 Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER E1 SNR (A-weighted) THD THD+N Crosstalk (L/R) AVDD PSRR (217Hz) SNR (A-weighted) THD THD+N E2 SNR (A-weighted) THD THD+N Crosstalk (L/R) AVDD PSRR (217Hz) DC Offset at Load SNR (A-weighted) THD THD+N E3 E4 E5 Minimum Line Out Resistance Maximum Line Out Capacitance SNR (A-weighted) THD (PO=20mW) THD+N (PO=20mW) THD (PO=5mW) THD+N (PO=5mW) Crosstalk (L/R) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) SNR (A-weighted) THD (PO=5mW) THD+N (PO=5mW) E6 SNR (A-weighted) THD (PO=20mW) THD+N (PO=20mW) THD (PO=5mW) THD+N (PO=5mW) Crosstalk (L/R) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) SNR (A-weighted) THD (PO=20mW) THD+N (PO=20mW) THD (PO=5mW) THD+N (PO=5mW) DAC to LOUT, or ROUT, RL=16, AVDD=HPVDD= 2.7V DACL or DACR Pre-Production TEST CONDITIONS DAC to singleended line out, 0dBFS input, AVDD = 3.3V MIN TYP 99 -86 -84 -100 45 MAX UNIT dB dB dB dB dB dB dB dB dB dB dB dB dB mV dB dB dB k DAC Output Path (Line Outputs 10k / 50pF Load, Headphone Outputs 16 Load, Speaker Output 8 BTL Load) DAC to singleended line out, 0dBFS input, AVDD = 2.7V DAC to differential line out, 0dBFS input, AVDD = 3.3V 97 -89 -87 99 -86 -84 -100 60 5 DAC to differential line out, 0dBFS input, AVDD = 2.7V LOP, LON, ROP, RON LOP, LON, ROP, RON DAC to LOUT or ROUT, RL=32, AVDD=HPVDD= 3.3V 2 97 -90 -88 10 99 -81 32 AC-Coupled Headphone Outputs -79 -77 -75 -100 45 85 nF dB dB dB dB dB dB dB dB dB dB dB dB DAC to LOUT or ROUT, RL=32, AVDD=HPVDD= 2.7V DAC to LOUT or ROUT, RL=16, AVDD=HPVDD= 3.3V 90 97 -76 -74 99 -77 -75 16 AC-Coupled Headphone Outputs + LOUT or ROUT -72 -70 dB dB dB dB dB dB dB dB dB dB dB dB -73 -71 -100 45 85 97 -74 -72 -72 -70 + LOMIX or ROMIX RLOAD = 16Ohm w PP, May 2008, Rev 3.1 16 Pre-Production Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER E7 SNR (A-weighted) THD (PO=20mW) THD+N (PO=20mW) THD (PO=5mW) THD+N (PO=5mW) Crosstalk (L/R) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) DC Offset at Load SNR (A-weighted) THD (PO=20mW) THD+N (PO=20mW) THD (PO=5mW) THD+N (PO=5mW) E8 SNR (A-weighted) THD (PO=20mW) THD+N (PO=20mW) THD (PO=5mW) THD+N (PO=5mW) Crosstalk (L/R) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) SNR (A-weighted) THD (PO=20mW) THD+N (PO=20mW) THD (PO=5mW) THD+N (PO=5mW) E9 E10 E11 Minimum Headphone Resistance SPKVDD Leakage Current SNR (A-weighted) THD (PO=0.5W) THD+N (PO=0.5W) THD (PO=1.0W) THD+N (PO=1.0W) SPKVDD PSRR(217Hz) SNR (A-weighted) THD (PO=0.5W) THD+N (PO=0.5W) THD (PO=1.0W) THD+N (PO=1.0W) SPKVDD PSRR(217Hz) DC Offset at Load DAC to LOUT, or ROUT Capless (OUT3 or 4 as pseudo GND), RL=16, AVDD=HPVDD= 2.7V LOUT, ROUT, OUT3, OUT4 SPKVDD=5.0V, DAC to Speaker Output (Direct) AVDD=3.3V, SPKVDD=5V, class D, PO controlled using DAC volume, ACGAIN=DCGA IN=1.52 DAC to Speaker Output (Direct) AVDD=3.3V, SPKVDD=5V, class AB, PO controlled using DAC volume 15 1 93 -87 -85 -76 -74 75 97 -78 -76 -76 -74 75 5 DAC to LOUT/OUT3 or ROUT/OUT4, RL=16, AVDD=HPVDD= 2.7V DAC to LOUT or ROUT Capless (OUT3 or 4 as pseudo GND), RL=16, AVDD=HPVDD= 3.3V DAC to LOUT/OUT3 or ROUT/OUT4, RL=16, AVDD=HPVDD= 3.3V TEST CONDITIONS Fully Differential Headphone Outputs MIN TYP 99 -71 -69 -67 -65 -100 60 85 5 98 -70 -68 -66 -64 99 -73 -71 16 Capless Headphone Outputs -69 -67 -45 45 85 97 -70 -68 -67 -65 WM8991 MAX UNIT dB dB dB dB dB dB dB dB mV dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB uA dB dB dB dB dB dB dB -70 -68 -66 -64 dB dB dB dB dB mV w PP, May 2008, Rev 3.1 17 WM8991 Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER F1 SNR (A-weighted) THD (PO=20mW) THD+N (PO=20mW) THD (PO=5mW) THD+N (PO=5mW) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) DC Offset at Load SNR (A-weighted) THD (PO=20mW) THD+N (PO=20mW) THD (PO=5mW) THD+N (PO=5mW) F2 SNR (A-weighted) THD (PO=20mW) THD+N (PO=20mW) THD (PO=5mW) THD+N (PO=5mW) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) SNR (A-weighted) THD (PO=20mW) THD+N (PO=20mW) THD (PO=5mW) THD+N (PO=5mW) F3 SNR (A-weighted) THD (PO=0.5W) THD+N (PO=0.5W) THD (PO=1.0W) THD+N (PO=1.0W) AVDD PSRR (217Hz) SPKVDD PSRR(217Hz) SNR (A-weighted) THD (PO=0.5W) THD+N (PO=0.5W) THD (PO=1.0W) THD+N (PO=1.0W) AVDD PSRR (217Hz) SPKVDD PSRR(217Hz) DC Offset at Load Line Input to SPKMIX, AVDD=3.3V, SPKVDD=5V, Class AB Mode 91 RXVOICE via LOMIX or ROMIX to Headphone Outputs, AVDD=HPVDD= 2.7V Line Input to SPKMIX, AVDD=3.3V, SPKVDD=5V, ACGAIN= DCGAIN=1.52, Class D Mode Differential Input on RXP/RXN to Differential Output on OUT3/OUT4, AVDD=HPVDD= 2.7V RXVOICE via LOMIX or ROMIX to Headphone Outputs, AVDD=HPVDD= 3.3V Differential Input on RXP/RXN to Differential Output on OUT3/OUT4, AVDD=HPVDD= 3.3V TEST CONDITIONS MIN TYP 110 -72 -70 -68 -66 80 90 5 108 -70 -68 -67 -65 100 -77 -75 -73 -71 45 85 98 -74 -72 -72 -70 93 -87 -85 -81 -79 45 80 101 -78 -76 -76 -74 45 80 5 Pre-Production MAX UNIT dB dB dB dB dB dB dB mV dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Bypass Path Performance (Line Outputs 10k / 50pF load, Headphone Outputs 16 load, Speaker Output 8 BTL load) -70 -68 -66 -64 dB dB dB dB dB dB mV w PP, May 2008, Rev 3.1 18 Pre-Production Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER F4 SNR (A-weighted) THD (0dB output) THD+N (0dB output) AVDD PSRR (217Hz) DC Offset at Load SNR (A-weighted) THD (0dB output) THD+N (0dB output) F5 SNR (A-weighted) THD (PO=20mW) THD+N (PO=20mW) THD (PO=5mW) THD+N (PO=5mW) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) Crosstalk (L/R) SNR (A-weighted) THD (PO=20mW) THD+N (PO=20mW) THD (PO=5mW) THD+N (PO=5mW) F6 SNR (A-weighted) THD (PO=20mW) THD+N (PO=20mW) THD (PO=5mW) THD+N (PO=5mW) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) Crosstalk (L/R) SNR (A-weighted) THD (PO=20mW) THD+N (PO=20mW) THD (PO=5mW) THD+N (PO=5mW) Line Input to Headphones via LOMIX and ROMIX, RL=16, AVDD=HPVDD= 2.7V Input PGA via LOMIX or ROMIX to LOUT or ROUT, RL=16, AVDD=HPVDD= 2.7V Line Input to Headphones via LOMIX and ROMIX, RL=16, AVDD=HPVDD= 3.3V Input PGA to Differential Line Out, AVDD=2.7V Input PGA via LOMIX or ROMIX to LOUT or ROUT, RL=16, AVDD=HPVDD= 3.3V 92 Input PGA to Differential Line Out, AVDD=3.3V TEST CONDITIONS MIN 90 TYP 101 -99 -97 45 5 100 -95 -93 102 -77 -75 -73 -71 45 85 -95 100 -74 -72 -72 -70 104 -77 -75 -73 -71 70 85 -95 102 -74 -72 -72 -70 WM8991 MAX -90 -88 UNIT dB dB dB dB mV dB dB dB dB -72 -70 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB w PP, May 2008, Rev 3.1 19 WM8991 Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER Multi-Path Channel Separation G1 Headset Voice Call: DAC/Headset to Tx Voice Separation 1kHz 0dBFS DAC playback to LOUT and ROUT; Quiescent input on LIN12 or RIN12 (Gain=+12dB), differential output to LOP/LON or ROP/RON; Measure crosstalk at LOP/LON or ROP/RON output G2 Headset Voice Call: DAC/Speaker to Tx Voice Separation 1kHz 0dBFS DAC playback to speaker, 1W output; Quiescent input on LIN12 or RIN12 (Gain=+12dB), differential output to LOP/LON or ROP/RON; Measure crosstalk at LOP/LON or ROP/RON output G3 PCM Voice Call: Rx Voice to Tx Voice Separation fs=8kHz for ADC and DAC, DAC_SB_FILT=1; -5dBFS differential mono output from DACs to OUT3/OUT4; Quiescent input on input PGA (Gain=+12dB) to ADC via INMIXL or INMIXR; Measure crosstalk at ADC output G4 Speakerphone PCM Voice Call: DAC/Speaker to ADC Separation fs=8kHz for ADC and DAC, DAC_SB_FILT=1; 0dBFS DAC output to speaker (1W output); ADC record from input PGA (Gain=+30dB); Measure crosstalk on ADC output G5 Ear Speaker Voice Call: Tx Voice and Rx Voice Separation 1kHz Full scale differential input on RXP/RXN, output to OUT3/OUT4; Quiescent input on LIN12 or RIN12 (Gain=+12dB), differential output to LOP/LON or ROP/RON; Measure crosstalk at LOP/LON or ROP/RON output 70 85 90 100 -1 Pre-Production TEST CONDITIONS MIN TYP 85 MAX UNIT dB dB dB dB dB w PP, May 2008, Rev 3.1 20 Pre-Production Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER G6 Headset Voice Call: Tx Voice and Rx Voice Separation LIN1 or RIN1 WM8991 TEST CONDITIONS 0dB LON or RON MIN TYP 75 MAX UNIT dB LIN12 or RIN12 +12dB (Single-ended or differential mode) AL K 1kHz full scale differential input on RXP/RXN via RXVOICE to LOMIX and ROMIX, output to LOUT and ROUT; Quiescent input on LIN12 or RIN12 (Gain=+12dB), differential output to LOP/LON or ROP/RON; Measure crosstalk at LOP/LON or ROP/RON output G7 Stereo Line Record and Playback: DAC/Headset to ADC Separation -5dBFS input to DACs, playback to LOUT and ROUT1; ADC record from line input; Measure crosstalk on ADC output LIN2 or RIN2 LOPMIX or ROPMIX LOAD 0dB LOP or ROP + Quiescent input CR OS ST LOMIX RXN 0dB LOUT Full scale input RXP + RXVOICE + 0dB + ROMIX ROUT LIN2, LIN4, RIN2 or RIN4 INMIXL or INMIXR 90 ADCL or ADCR dB + Quiescent input -5dBFS, 1kHz CROSSTALK 0dB DACL + LOMIX LOUTVOL 0dB LOUT -5dBFS, 1kHz DACR + ROMIX ROUTVOL ROUT w PP, May 2008, Rev 3.1 21 WM8991 Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER Analogue Reference Levels H1 H2 VMID Midrail Reference Voltage Bias Voltage 3mA load current M1BSEL=0 / M2BSEL=0 3mA load current M1BSEL=1 / M2BSEL=1 H3 H4 H5 Bias Current Source Output Noise Density AVDD PSRR (217Hz) 1kHz to 20kHz 100mV pk-pk @217Hz on AVDD 0.7xDBVDD 100 45 -3% -5% -5% AVDD/2 0.9xAVDD 0.65xAVDD TEST CONDITIONS MIN TYP Pre-Production MAX +3% +5% +5% 3 UNIT V V V mA nV/Hz dB Microphone Bias Digital Input / Output H6 H7 Input HIGH Level Input LOW Level V 0.3xDBVDD V Note that digital input pins should not be left unconnected / floating. Internal pull-up/pull-down resistors may be enabled on GPIO1-6 if required. H8 H9 H10 H11 PLL H12 H13 GPIO H14 Clock output duty cycle (Integer OPCLKDIV) SYSCLK=MCLK; OPCLKDIV=0000 SYSCLK=MCLK; OPCLKDIV=1000 SYSCLK=PLL output; OPCLKDIV=0000 SYSCLK=PLL output; OPCLKDIV=1000 H15 Clock output duty cycle (Non-integer OPCLKDIV) SYSCLK=MCLK; OPCLKDIV=0100 SYSCLK=PLL output; OPCLKDIV=0100 H16 Interrupt response time for accessory / button detect Input de-bounced Input de-bounced TOCLKSEL=1 Input not de-bounced 2 19 Output HIGH Level Output LOW Level Input capacitance Input leakage Input Frequency Lock time IOL=1mA IOH=-1mA 0.9xDBVDD 0.1xDBVDD 10 -0.9 0.9 17 34 200 35 45 45 45 33 33 221 / fSYSCLK / fSYSCLK 0 65 55 55 55 66 66 222 / fSYSCLK 220 / fSYSCLK V V pF uA MHz MHz us % % % % % % s s s PRESCALE = 0b PRESCALE = 1b 10 20 w PP, May 2008, Rev 3.1 22 Pre-Production WM8991 TERMINOLOGY 1. 2. 3. 4. Signal-to-Noise Ratio (dB) - SNR is a measure of the difference in level between the maximum theoretical full scale output signal and the output with no input signal applied. Total Harmonic Distortion (dB) - THD is the level of the rms value of the sum of harmonic distortion products relative to the amplitude of the measured output signal. Total Harmonic Distortion plus Noise (dB) - THD+N is the level of the rms value of the sum of harmonic distortion products plus noise in the specified bandwidth relative to the amplitude of the measured output signal. Crosstalk (L/R) (dB) - left-to-right and right-to-left channel crosstalk is the measured signal level in the idle channel at the test signal frequency relative to the signal level at the output of the active channel. The active channel is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the associated idle channel. For example, measured signal level on the output of the idle right channel (RIN2 to ADCR) with a full scale signal level at the output of the active left channel (LIN1 to ADCL). Multi-Path Channel Separation (dB) - is the measured signal level in the idle path at the test signal frequency relative to the signal level at the output of the active path. The active path is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the specified idle path. All performance measurements carried out with 20kHz low pass filter, and where noted an A-weighted filter. Failure to use such a filter will result in higher THD and lower SNR readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. Mute Attenuation - This is a measure of the difference in level between the full scale output signal and the output with mute applied. 5. 6. 7. w PP, May 2008, Rev 3.1 23 WM8991 TYPICAL POWER CONSUMPTION Control Register Mode OFF (default state at power-up) VSEL Other settings AVDD (V) 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 HPVDD (V) 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 SPKVDD DBVDD (V) 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 3.3 3.6 4.2 5.0 (V) 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 DCVDD (V) 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 1.8 2.5 3.3 3.6 IAVDD (mA) 0.028 0.029 0.030 0.031 0.008 0.008 0.009 0.009 0.087 0.096 0.106 0.117 5.272 5.603 5.927 6.261 5.125 5.434 5.738 6.053 2.950 3.315 3.684 4.055 2.951 3.315 3.683 4.055 2.950 3.315 3.684 4.056 2.950 3.315 3.683 4.055 2.952 3.316 3.683 4.055 2.951 3.317 3.684 4.055 2.951 3.315 3.684 4.056 2.950 3.315 3.683 4.055 2.950 3.315 3.683 4.055 2.955 3.319 3.686 4.057 3.934 4.184 4.672 5.166 3.621 4.080 4.548 5.021 3.087 3.470 3.856 4.246 0.442 0.499 0.556 0.613 2.307 2.374 2.660 2.953 5.043 5.512 5.981 6.457 IHPVDD ISPKVDD IDBVDD (mA) 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.705 0.558 0.640 0.726 1.430 1.367 1.544 1.742 0.828 0.743 0.835 0.937 2.563 2.476 2.508 2.556 15.767 15.789 15.675 15.836 0.699 0.550 0.629 0.711 1.019 0.915 1.045 1.180 0.748 0.624 0.704 0.789 1.950 1.868 1.905 1.950 11.421 11.362 11.349 11.406 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.697 0.544 0.621 0.702 0.796 0.615 0.703 0.794 0.382 0.299 0.343 0.389 (mA) 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 3.070 3.652 5.154 7.223 2.823 3.307 4.061 5.057 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 (mA) 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.004 0.008 0.014 0.017 0.023 0.039 0.060 0.063 0.017 0.027 0.061 0.062 0.003 0.007 0.013 0.016 0.004 0.007 0.013 0.016 0.004 0.007 0.013 0.016 0.004 0.007 0.014 0.016 0.004 0.007 0.013 0.016 0.004 0.007 0.013 0.016 0.004 0.007 0.014 0.016 0.004 0.007 0.013 0.016 0.004 0.007 0.014 0.016 0.004 0.007 0.014 0.016 0.004 0.007 0.013 0.016 0.004 0.007 0.013 0.016 0.004 0.007 0.013 0.016 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.011 0.017 0.027 0.032 Pre-Production IDCVDD Total Power (mA) 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.459 0.694 1.025 1.162 2.285 3.317 4.728 5.295 0.758 1.123 1.634 1.841 2.147 3.180 4.544 5.092 2.298 3.380 4.817 5.404 2.263 3.362 4.762 5.344 2.251 3.323 4.736 5.304 2.256 3.343 4.762 5.329 2.147 3.179 4.543 5.089 2.302 3.359 4.806 5.367 2.265 3.337 4.786 5.359 2.253 3.327 4.741 5.312 2.267 3.351 4.777 5.342 2.144 3.179 4.541 5.089 2.138 3.167 4.530 5.073 2.125 3.146 4.496 5.042 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 2.290 3.384 4.820 5.386 (mW) 0.074 0.086 0.099 0.114 0.019 0.024 0.028 0.035 1.067 2.043 3.779 4.667 18.388 25.198 35.357 41.830 15.232 19.176 24.527 28.642 13.739 19.586 29.307 35.600 15.971 22.513 33.189 40.381 14.279 20.596 30.671 37.270 18.943 25.698 36.103 42.951 54.608 65.690 79.640 90.850 13.725 19.565 29.268 35.536 14.868 21.105 31.509 38.228 14.067 20.177 30.314 36.789 17.291 23.883 34.129 40.799 42.901 52.438 65.423 74.956 14.487 20.517 30.446 36.976 23.763 33.322 51.648 72.511 21.482 30.198 44.662 58.780 3.074 3.128 3.884 4.735 8.377 8.966 11.097 13.490 18.789 25.935 36.862 44.150 01 11 11 11 OFF 01 (thermal sensor disabled) 11 11 11 SLEEP 01 (VMID enabled, thermal sensor anabled) 11 11 11 Stereo Line Record 01 (L/RIN2 to INMIXL/R bypassing PGA) 11 11 11 Stereo Line Record 01 (L/RIN2 to INMIXL/R bypassing PGA) 11 11 11 Playback to AC Coupled Headphones 01 (DAC to L/ROUT) 11 16ohm load 11 11 Playback to AC Coupled Headphones 01 (DAC to L/ROUT) 11 -20dBV Pink Noise into 16ohm load 11 11 Playback to AC Coupled Headphones 01 (DAC to L/ROUT) 11 -30dBV Pink Noise into 16ohm load 11 11 Playback to AC Coupled Headphones 01 (DAC to L/ROUT) 11 0.1mW/channel into 16ohm load 11 11 Playback to AC Coupled Headphones 01 (DAC to L/ROUT) 11 5mW/channel into 16ohm load 11 11 Playback to AC Coupled Headphones 01 (DAC to L/ROUT) 11 32ohm load 11 11 Playback to AC Coupled Headphones 01 (DAC to L/ROUT) 11 -20dBV Pink Noise into 32ohm load 11 11 Playback to AC Coupled Headphones 01 (DAC to L/ROUT) 11 -30dBV Pink Noise into 32ohm load 11 11 Playback to AC Coupled Headphones 01 (DAC to L/ROUT) 11 0.1mW/channel into 32ohm load 11 11 Playback to AC Coupled Headphones 01 (DAC to L/ROUT) 11 5mW/channel into 32ohm load 11 11 Playback to Line-Out 01 (DAC to ROP/RON) 11 11 11 Playback to Speaker Class D 01 (DAC to SPK) 11 8ohm load 11 11 Playback to Speaker Class AB 01 (DAC to SPK) 11 8ohm load 11 11 FM Radio to AC Coupled Headphones 01 (L/RIN3 to L/ROUT bypass via LROMIX) 11 16ohm load 11 11 Analogue Voice Call to Handset Ear Speaker 01 (MIC on LIN12 to LOP/LON) 11 (RXP/RXN to OUT3/4 via RXVIOCE & AINLMUX) 11 11 PCM Voice Call 01 (MIC on LIN12 to LADC) 11 (-12dB sidetone to LDAC) 11 (LDAC to OUT3, OUT4=MUTE) 11 No Clocks No Clocks With Clocks fs=44.1kHz fs=8kHz fs=44.1kHz fs=44.1kHz fs=44.1kHz fs=44.1kHz fs=44.1kHz fs=44.1kHz fs=44.1kHz fs=44.1kHz fs=44.1kHz fs=44.1kHz fs=44.1kHz fs=44.1kHz fs=44.1kHz Notes: 1. 2. 3. Power in the load is included. All figures are quoted at TA = +25C All figures are quoted as quiescent current unless otherwise stated. w PP, May 2008, Rev 3.1 24 Pre-Production WM8991 SPEAKER DRIVER PERFORMANCE Typical speaker driver THD+N performance is shown below for both Class D and Class AB modes. Curves are shown for four typical SPKVDD supply voltage and gain combinations. Load RL = 8 + 10H, Frequency = 1kHz, +1dB gain in active path. SPEAKER CLASS D INTO 8 + 10H Speaker Class D (8+10H) THD+N Ratio v Output Power 10 10 SPEAKER CLASS AB INTO 8 + 10H Speaker Class AB (8+10H) THD+N Ratio v Output Power 1 1 THD+N Ratio (%) 0.1 THD+N Ratio (%) 0.1 0.01 0.01 SPKVDD=5.0V, SPKVDD=4.2V, SPKVDD=3.6V, SPKVDD=3.3V, AC=DC=1.52x AC=DC=1.27x AC=DC=1.00x AC=DC=1.00x SPKVDD=5.0V, SPKVDD=4.2V, SPKVDD=3.6V, SPKVDD=3.3V, AC=DC=1.52x AC=DC=1.27x AC=DC=1.00x AC=DC=1.00x 0.001 0 0.25 0.5 0.75 1 1.25 1.5 0.001 0 0.25 0.5 0.75 1 1.25 1.5 Output Power (W) Output Power (W) HEADPHONE DRIVER PERFORMANCE Typical THD+N performance of the Headphone Drivers is shown below (AC coupled to LOUT/ROUT). Curves are shown for four HPVDD/AVDD supply voltages. Load RL = 16 and 32, Frequency = 1kHz, +1dB gain in active path. AC COUPLED HEADPHONE INTO 16 AC Coupled Headphone (16ohm) THD+N Ratio v Output Power 10 AC COUPLED HEADPHONE INTO 32 AC Coupled Headphone (32ohm) THD+N Ratio v Output Power 10 1 1 THD+N Ratio (%) 0.1 THD+N Ratio (%) 0.1 HPVDD=AVDD=3.6V HPVDD=AVDD=3.3V HPVDD=AVDD=3.0V HPVDD=AVDD=2.7V HPVDD=AVDD=3.6V HPVDD=AVDD=3.3V HPVDD=AVDD=3.0V HPVDD=AVDD=2.7V 0.01 0 10 20 30 40 50 60 70 80 0.01 0 10 20 30 40 50 60 70 80 Output Power (mW) Output Power (mW) w PP, May 2008, Rev 3.1 25 WM8991 PSRR PERFORMANCE SPKVDD - LIN2 TO SPEAKER PSRR - SPKVDD 90 80 70 60 PSRR (dB) 50 40 30 20 10 0 0.1 1 Frequency (kHz) 10 100 LIN2-SPK (Class D) - 5V SPKVDD LIN2-SPK (Class AB) - 5V SPKVDD LIN2 to SPK class AB/D Pre-Production AVDD - LIN2 TO SPEAKER PSRR - AVDD 90 80 70 60 PSRR (dB) 50 40 30 20 10 0 0.1 1 Frequency (kHz) 10 100 LIN2-SPK (Class D 5V SPKVDD) - 3.3V AVDD LIN2-SPK (Class AB 5V SPKVDD) - 3.3V AVDD LIN2 to SPK class AB/D SPKVDD - DAC TO SPEAKER PSRR - SPKVDD 90 80 70 60 PSRR (dB) PSRR (dB) AVDD - DAC TO SPEAKER PSRR - AVDD 90 80 70 60 50 40 30 20 DAC to SPK class AB/D DAC to SPK class AB/D 50 40 30 20 10 0 0.1 1 Frequency (kHz) 10 100 DACL-SPK (Class D) - 5V SPKVDD DACL-SPK (Class AB) - 5V SPKVDD 10 0 0.1 DACL-SPK (Class D 5V SPKVDD) - 3.3V AVDD DACL-SPK (Class AB 5V SPKVDD) - 3.3V AVDD 1 Frequency (kHz) 10 100 HPVDD - DAC TO HEADPHONE PSRR - HPVDD 90 80 70 60 PSRR (dB) 50 40 30 20 10 0 0.1 1 Frequency (kHz) 10 100 DAC-OMIX-LOUT/ROUT - 3.3V HPVDD DAC-OMIX-OPGA-Differential HP - 3.3V HPVDD DAC to Headphone AVDD - DAC TO HEADPHONE PSRR - AVDD 90 80 70 60 PSRR (dB) 50 40 30 20 10 0 0.1 1 Frequency (kHz) 10 100 DAC-OMIX-LOUT/ROUT - 3.3V AVDD DAC-OMIX-OPGA-Differential HP - 3.3V AVDD DAC to Headphone DCVDD - DAC TO HEADPHONE PSRR - DCVDD 100 90 80 70 PSRR (dB) 60 50 40 30 20 10 0.1 1 Frequency (kHz) 10 100 DAC-OMIX-LOUT/ROUT - 3.3V DCVDD DAC-OMIX-LOUT/ROUT - 2.0V DCVDD PSRR (dB) AVDD - MICBIAS PSRR - AVDD MICBIAS 90 80 70 60 50 40 30 20 10 0 0.1 1 Frequency (kHz) 10 100 MICBIAS - MBSEL = 0 MICBIAS - MBSEL = 1 DAC to Headphone w PP, May 2008, Rev 3.1 26 Pre-Production DCVDD - LINE-IN TO ADC PSRR - DCVDD 90 80 70 60 PSRR (dB) Line-In to ADC WM8991 AVDD - LINE-IN TO ADC PSRR - AVDD 90 80 70 60 PSRR (dB) 50 40 30 20 IN2-INMIX-ADC - 3.3V DCVDD IN2-INMIX-ADC - 2.0V DCVDD Line-In to ADC 50 40 30 20 10 0 0.1 1 Frequency (kHz) 10 100 10 0 0.1 IN2-INMIX-ADC - 3.3V AVDD IN1PGA-INMIX-ADC - 3.3V AVDD 1 Frequency (kHz) 10 100 HPVDD - IN1 BYPASS PSRR - HPVDD 90 80 70 60 50 40 30 20 10 IN1PGA-OMIX-LOUT/ROUT - 3.3V HPVDD 0 0.1 1 Frequency (kHz) 10 100 IN1 Bypass AVDD - IN1 BYPASS PSRR - AVDD 90 80 70 60 PSRR (dB) 50 40 30 20 10 0 0.1 1 Frequency (kHz) 10 100 IN1PGA-OMIX-LOUT/ROUT - 3.3V AVDD IN1PGA-LINEDIFF - 3.3V AVDD IN1 Bypass PSRR (dB) HPVDD - IN3 BYPASS PSRR - HPVDD 90 80 70 60 PSRR (dB) 50 40 30 20 10 0 0.1 1 Frequency (kHz) 10 100 IN3-OMIX-LOUT/ROUT - 3.3V HPVDD IN3-OMIX-OPGA-OUT3/OUT4 - 3.3V HPVDD IN3-OMIX-OPGA-Differential HP - 3.3V HPVDD IN3 Bypass AVDD - IN3 BYPASS PSRR - AVDD 90 80 70 60 PSRR (dB) 50 40 30 20 10 0 0.1 1 Frequency (kHz) 10 100 IN3-OMIX-LOUT/ROUT - 3.3V AVDD IN3-OMIX-OPGA-OUT3/OUT4 - 3.3V AVDD IN3-OMIX-OPGA-Differential HP - 3.3V AVDD IN3 Bypass HPVDD - IN4 BYPASS PSRR - HPVDD 100 90 80 70 PSRR (dB) 60 50 40 30 20 10 0.1 1 Frequency (kHz) 10 100 RxVOICE-OMIX-LOUT - 3.3V HPVDD IN4-OUT3/OUT4 (16Ohm BTL) - 3.3V HPVDD 10 0.1 PSRR (dB) IN4 Bypass 100 90 80 70 60 50 40 30 20 AVDD - IN4 BYPASS PSRR - AVDD IN4 Bypass RxVOICE-OMIX-LOUT - 3.3V AVDD IN4-OUT3/OUT4 (16Ohm BTL) - 3.3V AVDD 1 10 100 Frequency (kHz) Note: All figures based on 100mVp-p injected on the supply at the relevant test frequency. w PP, May 2008, Rev 3.1 27 WM8991 AUDIO SIGNAL PATHS Pre-Production -1 w -1 CSB/ADDR SDIN SCLK MODE MCLK GPIO6/ADCLRCB GPIO5/DACDAT2 GPIO4/DACLRC2 GPIO3/BCLK2 GPIO2/MCLK2 ADCLRC/GPIO1 ADCDAT DACDAT DACLRC BCLK DGND DCVDD DBVDD HPVDD HPGND SPKVDD SPKGND AVDD VMID AGND PP, May 2008, Rev 3.1 28 Pre-Production WM8991 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING t MCLK (or MCLK2) t MCLKY MCLKL t MCLKH Figure 4 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=3.3V, SPKVDD=5V, DGND=AGND=SPKGND=0V, TA = +25oC PARAMETER System Clock Timing Information MCLK or MCLK2 cycle time MCLK or MCLK2 duty cycle TMCLKY = TMCLKH/TMCLKL 33.33 60:40 40:60 ns SYMBOL CONDITIONS MIN TYP MAX UNIT w PP, May 2008, Rev 3.1 29 WM8991 AUDIO INTERFACE TIMING - MASTER MODE Pre-Production Figure 5 Digital Audio Data Timing - Master Mode (see Control Interface) Test Conditions DCVDD=1.8V, DBVDD=AVDD=3.3V, SPKVDD=5V, DGND=AGND=SPKGND=0V, TA=+25oC, Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Timing Information ADCLRC/ DACLRC (or DACLRC2) propagation delay from BCLK (or BCLK2) falling edge ADCDAT propagation delay from BCLK falling edge DACDAT (or DACDAT2) setup time to BCLK rising edge DACDAT (or DACDAT2) hold time from BCLK rising edge ADCLRC to ADCLRCB delay tDL tDDA tDST tDHT tDLRCB 20 10 10 20 20 ns ns ns ns ns SYMBOL MIN TYP MAX UNIT w PP, May 2008, Rev 3.1 30 Pre-Production WM8991 AUDIO INTERFACE TIMING - SLAVE MODE Figure 6 Digital Audio Data Timing - Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=3.3, SPKVDD=5V, DGND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Timing Information BCLK (or BCLK2) cycle time BCLK (or BCLK2) pulse width high BCLK (or BCLK2) pulse width low ADCLRC/ DACLRC (or DACLRC2) set-up time to BCLK (or BCLK2) rising edge ADCLRC/ DACLRC (or DACLRC2) hold time from BCLK (or BCLK2) rising edge DACDAT (or DACDAT2) hold time from BCLK (or BCLK2) rising edge ADCDAT propagation delay from BCLK falling edge DACDAT (or DACDAT2) set-up time to BCLK (or BCLK2) rising edge ADCLRC to ADCLRCB delay Note: BCLK (or BCLK2) period should always be greater than or equal to MCLK (or MCLK2) period. tBCY tBCH tBCL tLRSU tLRH tDH tDD tDS tDLRCB 20 20 50 20 20 20 10 10 20 ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT w PP, May 2008, Rev 3.1 31 WM8991 AUDIO INTERFACE TIMING - TDM MODE Pre-Production In TDM mode, it is important that two ADC devices to not attempt to drive the ADCDAT pin simultaneously. The timing of the WM8991 ADCDAT tri-stating at the start and end of the data transmission is described in Figure 7 and the table below. Figure 7 Digital Audio Data Timing - TDM Mode Test Conditions DBVDD=AVDD=3.3V, SPKVDD=5V, DGND=AGND=SPKGND=0V, TA=+25oC, Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Timing Information ADCDAT setup time from BCLK falling edge DCVDD = DBVDD = 3.6V DCVDD = DBVDD = 1.71V ADCDAT release time from BCLK falling edge DCVDD = DBVDD = 3.6V DCVDD = DBVDD = 1.71V 5 15 5 15 ns ns ns ns CONDITIONS MIN TYP MAX UNIT w PP, May 2008, Rev 3.1 32 Pre-Production WM8991 CONTROL INTERFACE TIMING - 2-WIRE MODE 2-wire mode is selected by connecting the MODE pin low. t3 SDIN t6 SCLK t1 t9 t7 t2 t5 t4 t8 t3 Figure 8 Control Interface Timing - 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=HPVDD=3.3, SPKVDD=5V, DGND=AGND=HPGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width of spikes that will be suppressed t1 t2 t3 t4 t5 t6 t7 t8 t9 tps 0 600 900 5 1.3 600 600 600 100 300 300 526 kHz us ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT w PP, May 2008, Rev 3.1 33 WM8991 CONTROL INTERFACE TIMING - 3-WIRE MODE 3-wire mode is selected by connecting the MODE pin high. Pre-Production Figure 9 Control Interface Timing - 3-Wire Serial Control Mode (Write Cycle) CSB SCLK SDOUT t DL LSB Figure 10 Control Interface Timing - 3-Wire Serial Control Mode (Read Cycle) Test Conditions DCVDD=1.8V, DBVDD=AVDD=HPVDD=3.3V, SPKVDD=5V, DGND=AGND=HPGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information CSB falling edge to SCLK rising edge SCLK falling edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SDIN to SCLK hold time Pulse width of spikes that will be suppressed SCLK falling edge to SDOUT transition tCSU tCHO tSCY tSCL tSCH tDSU tDHO tps tDL 40 40 200 80 80 40 10 0 5 40 ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT w PP, May 2008, Rev 3.1 34 Pre-Production WM8991 CONTROL INTERFACE TIMING - 4-WIRE MODE 4-wire mode supports readback via SDOUT which is available as a GPIO pin function. t CSU CSB t SCY SCLK t CHO SDIN t DSU t DHO LSB Figure 11 Control Interface Timing - 4-Wire Serial Control Mode (Write Cycle) CSB SCLK SDOUT t DL LSB Figure 12 Control Interface Timing - 4-Wire Serial Control Mode (Read Cycle) Test Conditions DCVDD=1.8V, DBVDD=AVDD=HPVDD=3.3V, SPKVDD=5V, DGND=AGND=HPGND=SPKGND=0V, TA =+25oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK rising edge to CSB falling edge SCLK falling edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SDIN to SCLK hold time SDOUT propagation delay from SCLK rising edge Pulse width of spikes that will be suppressed SCLK falling edge to SDOUT transition tCSU tCHO tSCY tSCL tSCH tDSU tDHO tDL tps tDL 0 40 40 200 80 80 40 10 10 5 40 ns ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT w PP, May 2008, Rev 3.1 35 WM8991 INTERNAL POWER ON RESET CIRCUIT Pre-Production Figure 13 Internal Power on Reset Circuit Schematic The WM8991 includes an internal Power-On-Reset Circuit, as shown in Figure 13, which is used to reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and monitors DCVDD. It asserts PORB low if AVDD or DCVDD is below a minimum threshold. Figure 14 Typical Power up Sequence where AVDD is Powered before DCVDD Figure 14 shows a typical power-up sequence where AVDD comes up first. When AVDD goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Now AVDD is at full supply level. Next DCVDD rises to Vpord_on and PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the minimum threshold Vpora_off. w PP, May 2008, Rev 3.1 36 Pre-Production WM8991 Figure 15 Typical Power up Sequence where DCVDD is powered before AVDD Figure 15 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that DCVDD is already up to specified operating voltage. When AVDD goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD rises to Vpora_on, PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where DCVDD falls first, PORB is asserted low whenever DCVDD drops below the minimum threshold Vpord_off. SYMBOL Vpora Vpora_on Vpora_off Vpord_on Vpord_off MIN TYP 0.6 1.52 1.5 0.92 0.9 MAX UNIT V V V V V Table 1 Typical POR Operation (typical values, not tested) Notes: 1. If AVDD and DCVDD suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below Vpora_off or Vpord_off) then the chip will not reset and will resume normal operation when the voltage is back to the recommended level again. The chip will enter reset at power down when AVDD or DCVDD falls below Vpora_off or Vpord_off. This may be important if the supply is turned on and off frequently by a power management system. The minimum tpor period is maintained even if DCVDD and AVDD have zero rise time. This specification is guaranteed by design rather than test. 2. 3. w PP, May 2008, Rev 3.1 37 WM8991 DEVICE DESCRIPTION INTRODUCTION Pre-Production The WM8991 is a low power, high quality audio codec designed to interface with a wide range of processors and analogue components. A high level of mixed-signal integration in a small 5x5mm footprint makes it ideal for portable applications such as mobile phones. Eight highly flexible analogue inputs allow interfacing to up to four microphone inputs plus multiple stereo or mono line inputs (single-ended or differential). Connections to an external voice CODEC, FM radio, melody IC, line input, handset MIC and headset MIC are all fully supported. Signal routing to the output mixers and within the CODEC has been designed for maximum flexibility to support a wide variety of usage modes. Ten analogue output drivers are integrated, including a high power, high quality speaker driver, capable of providing 1W in class D mode or in class AB mode into 8 BTL. Four headphone drivers are provided, supporting ear speakers and stereo headsets. Fully differential headphone drive is supported for excellent crosstalk performance and removing the need for large and expensive headphone capacitors. Four line outputs are available for Tx voice output to a voice CODEC, interfacing to an additional speaker driver and single-ended or fully differential line output. All outputs have integrated pop and click suppression. The speaker supply has been designed with low leakage and high PSRR, to support direct connection to a Lithium battery. In addition to the speaker PGA, six AC and DC gain settings allow output signal level to be maximised for many commonly-used SPKVDD/AVDD combinations. Internal signal routing and amplifier configurations have been optimised to provide the lowest possible power consumption for a number of common usage scenarios such as voice calls and music playback. The stereo ADCs and DACs are of hi-fi quality using a 24-bit, low-order oversampling architecture to deliver optimum performance. A flexible clocking arrangement supports mixed ADC and DAC sample rates, while an integrated ultra-low power PLL provides additional flexibility. A high pass filter is available in the ADC path for removing DC offsets and suppressing low frequency noise such as mechanical vibration and wind noise. A digital mixing path from the ADC to the DAC provides a sidetone of enhanced quality during voice calls. DAC soft mute and un-mute is available for pop-free music playback. The WM8991 has a highly flexible digital audio interface, supporting a number of protocols, including I2S, DSP, MSB-First left/right justified, and can operate in master or slave modes. PCM operation is supported in the DSP mode. A-law and -law companding are also supported. Time division multiplexing (TDM) is available to allow multiple devices to stream data simultaneously on the same bus, saving space and power. Alternative DAC interface pins are provided to allow connection to an additional processor. The SYSCLK (system clock) provides clocking for the ADCs, DACs, DSP core, class D outputs and the digital audio interface. SYSCLK can be derived directly from the MCLK pin or via an integrated PLL, providing flexibility to support a wide range of clocking schemes. All MCLK frequencies typically used in portable systems are supported for sample rates between 8kHz and 48kHz. A flexible switching clock for the class D speaker drivers (synchronous with the audio DSP clocks for best performance) is also derived from SYSCLK. An additional master clock input pin is provided, to support operation on an alternative clock domain, selectable via a de-glitch circuit. To allow full software control over all its features, the WM8991 uses a standard 2-wire or 3/4-wire control interface with readback of key registers supported. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. Unused circuitry can be disabled via software to save power, while low leakage currents extend standby and off time in portable battery-powered applications. The device address can be selected using the CSB/ADDR pin. Versatile GPIO functionality is provided, with support for up to seven button/accessory detect inputs with interrupt and status readback and flexible de-bouncing options, clock output, alternative MCLK input, ADCLRC inversion for simultaneous streaming of ADC data to two separate processors and logic '1' / logic '0' for control of additional external circuitry. w PP, May 2008, Rev 3.1 38 Pre-Production WM8991 The WM8991 has eight highly flexible analogue input channels, configurable in many combinations of the following: 1. Up to four pseudo-differential or single-ended microphone inputs 2. Up to eight mono line inputs or 4 stereo line inputs 3. Mono input from external voice CODEC 4. Two fully balanced differential inputs These inputs may be mixed together or independently routed to different combinations of output drivers. An internal record path is provided at the input mixers to allow DAC output to be mixed with the input signal path (e.g. for karaoke or voice call recording). The WM8991 input signal paths and control registers are illustrated in Figure 16. INPUT SIGNAL PATH Figure 16 Control Registers for Input Signal Path w PP, May 2008, Rev 3.1 39 WM8991 MICROPHONE INPUTS Pre-Production Up to four microphones can be connected to the WM8991, either in single-ended or pseudodifferential mode. A low noise microphone bias is fully integrated to reduce the need for external components. In single-ended microphone input configuration, the microphone signal is connected to the inverting input of the PGA (LIN1, LIN3, RIN1 or RIN3). The non-inverting input of the PGAs should be internally connected to VMID in this configuration. This is enabled via the Input PGA configuration register settings. In this configuration, LIN2, LIN4, RIN2 or RIN4 may be free to be used as line inputs or ADC bypass inputs. In pseudo-differential microphone input configuration, the non-inverted microphone signal is connected to the non-inverting input of the PGA (LIN2, LIN4, RIN2 or RIN4) and the inverted (or noisy ground) signal is connected to the inverting input (LIN1, LIN3, RIN1 or RIN3). Any PGA input pin that is used in either microphone configuration should not be enabled as a line input path at the same time. The gain of the input PGAs is controlled via register settings. Note that the input impedance of LIN1, LIN3, RIN1 and RIN3 changes with the input PGA gain setting, as described under "Electrical Characteristics". (Note this does not apply to input paths which bypass the input PGA.) The input impedance of LIN2, LIN4, RIN2 and RIN4 does not change with input PGA gain. The inverting and non-inverting inputs are therefore not matched and the differential configuration is not fully differential. Figure 17 Single-Ended Microphone Input Figure 18 Differential Microphone Input w PP, May 2008, Rev 3.1 40 Pre-Production WM8991 LINE INPUTS All eight analogue input pins may be configured as line inputs. Various signal paths exist to provide flexibility, high performance and low power consumption for different usage modes. LIN1 and RIN1 can operate as line inputs to the Input PGAs LIN12 and RIN12 to provide high gain if required for small input signals. LIN2 and RIN2 can operate as line inputs directly to the input mixers or to the speaker output mixer. Direct routing to the speaker output minimises power consumption by reducing the number of active amplifiers in the signal path. LIN3 and RIN3 can operate as line inputs to the Input PGAs or as a line input directly to either of the output mixers LOMIX and ROMIX. LIN1+LIN3 and RIN1+RIN3 can also be used as fully balanced differential inputs via the Input PGAs to one of the input mixers. (Note that these inputs have matched input impedances.) LIN4/RXN and RIN4/RXP can operate as line inputs directly to the outputs OUT3 and OUT4, providing an ultra-low power stereo or mono differential signal path (e.g. from an external voice CODEC) to an ear speaker. LIN4/RXN and RIN4/RXP can also operate as a mono differential input to the ADC input signal path and output mixer stages. Figure 19 LIN1 or RIN1 as Line Inputs Figure 20 LIN2 or RIN2 as Line Inputs Figure 21 LIN3 or RIN3 as Line Inputs Figure 22 Fully Balanced Differential Input w PP, May 2008, Rev 3.1 41 WM8991 Pre-Production Figure 23 LIN4 and RIN4 as Rx Voice Inputs with Direct Low Power Path to Ear Speaker Figure 24 LIN4 or RIN4 as Line Inputs w PP, May 2008, Rev 3.1 42 Pre-Production WM8991 INPUT PGA ENABLE The Input PGAs are enabled using register bits LIN12_ENA, LIN34_ENA, RIN12_ENA and RIN34_ENA as described in Table 2. REGISTER ADDRESS R2 (02h) BIT LABEL DEFAULT DESCRIPTION 7 LIN34_ENA (rw) LIN12_ENA (rw) RIN34_ENA (rw) RIN12_ENA (rw) 0b LIN34 Input PGA Enable 0 = disabled 1 = enabled LIN12 Input PGA Enable 0 = disabled 1 = enabled RIN34 Input PGA Enable 0 = disabled 1 = enabled RIN12 Input PGA Enable 0 = disabled 1 = enabled 6 0b 5 0b 4 0b Table 2 Input PGA Enable To enable the input PGAs, the reference voltage VMID and the bias current must also be enabled. See "Power Management" for definitions of the associated controls VMID_MODE and VREF_ENA. MICROPHONE BIAS CONTROL The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones via an external resistor. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can be enabled or disabled using the MICBIAS_ENA control bit and the voltage can be selected using the MBSEL register bit as detailed in Table 3. REGISTER ADDRESS R1 (01h) BIT 4 LABEL MICBIAS_ENA (rw) MBSEL DEFAULT 0b DESCRIPTION Microphone Bias 0 = OFF (high impedance output) 1 = ON Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.65 * AVDD R58 (3Ah) 0 0b Table 3 Microphone Bias Control Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistance must be large enough to limit the MICBIAS current to 3mA. MICROPHONE CURRENT DETECT A MICBIAS current detect function allows detection of accessories such as headset microphones. When the MICBIAS load current exceeds one of two programmable thresholds, (e.g. short circuit current or normal operating current), an interrupt or GPIO output can be generated. The current detection circuit is enabled by the MCD bit; the current thresholds are selected by the MCDTHR and MCDSCTH register fields as described in Table 49- see "General Purpose Input/Output" for a full description of these fields. w PP, May 2008, Rev 3.1 43 WM8991 INPUT PGA CONFIGURATION Pre-Production Each of the four Input PGAs can be configured in single-ended or pseudo-differential mode. Single-ended microphone operation of an Input PGA is selected by connecting the input source to the inverting PGA input. The non-inverting PGA input must be connected to VMID by setting the appropriate register bits. For pseudo-differential microphone operation, the inverting and non-inverting PGA inputs are both connected to the input source and not to VMID. For any line input or other connection not using the Input PGA, the appropriate PGA input should be disconnected from the external pin and connected to VMID. Register bits LMN1, LMP2, LMN3, LMP4, RMN1, RMP2, RMN3 and RMP4 control connection of the PGA inputs to the device pins as shown in Table 4. The maximum available attenuation on any of these input paths is achieved using these bits to disable the input path to the applicable PGA. When not enabled as analogue inputs or as General Purpose inputs, the input pins can be biased to VREF via a 1k resistor by setting the BUFIOEN bit. See "Pop Suppression Control" for details. REGISTER ADDRESS R40 (28h) BIT 7 LABEL LMP4 DEFAULT 0b DESCRIPTION LIN34 PGA Non-Inverting Input Select 0 = LIN4 not connected to PGA 1 = LIN4 connected to PGA LIN34 PGA Inverting Input Select 0 = LIN3 not connected to PGA 1 = LIN3 connected to PGA LIN12 PGA Non-Inverting Input Select 0 = LIN2 not connected to PGA 1 = LIN2 connected to PGA LIN12 PGA Inverting Input Select 0 = LIN1 not connected to PGA 1 = LIN1 connected to PGA RIN34 PGA Non-Inverting Input Select 0 = RIN4 not connected to PGA 1 = RIN4 connected to PGA RIN34 PGA Inverting Input Select 0 = RIN3 not connected to PGA 1 = RIN3 connected to PGA RIN12 PGA Non-Inverting Input Select 0 = RIN2 not connected to PGA 1 = RIN2 connected to PGA RIN12 PGA Inverting Input Select 0 = RIN1 not connected to PGA 1 = RIN1 connected to PGA 6 LMN3 0b 5 LMP2 0b 4 LMN1 0b 3 RMP4 0b 2 RMN3 0b 1 RMP2 0b 0 RMN1 0b Table 4 Input PGA Configuration w PP, May 2008, Rev 3.1 44 Pre-Production WM8991 INPUT PGA VOLUME CONTROL Each of the four Input PGAs has an independently controlled gain range of -16.5dB to +30dB in 1.5dB steps. The gains on the inverting and non-inverting inputs to the PGAs are always equal. Each Input PGA can be independently muted using the PGA mute bits as described in Table 5, with specified mute attenuation achieved by simultaneously disconnecting the corresponding inputs described in Table 4. To prevent "zipper noise", a zero-cross function is provided, so that when enabled, volume updates will not take place until a zero-crossing is detected. In the event of a long period without zerocrossings, a timeout function is available. When this function is enabled (using the TOCLK_ENA register bit), the volume will update after the timeout period if no earlier zero-cross has occurred. The timeout period is set by TOCLK_RATE. See "Clocking and Sample Rates" for more information on these fields. The IPVU bit controls the loading of the input PGA volume data. When IPVU is set to 0, the PGA volume data will be loaded into the respective control register, but will not actually change the gain setting. The LIN12, RIN12, LIN34, RIN34 volume settings are all updated when a 1 is written to IPVU. This makes it possible to update the gain of all input paths simultaneously. The Input PGA Volume Control register fields are described in Table 5 and Table 6. REGISTER ADDRESS R24 (18h) BIT 8 LABEL IPVU[0] DEFAULT N/A DESCRIPTION Input PGA Volume Update Writing a 1 to this bit will cause all input PGA volumes to be updated simultaneously (LIN12, LIN34, RIN12 and RIN34) LIN12 PGA Mute 0 = Disable Mute 1 = Enable Mute LIN12 PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only LIN12 Volume (See Table 6 for volume range) Input PGA Volume Update Writing a 1 to this bit will cause all input PGA volumes to be updated simultaneously (LIN12, LIN34, RIN12 and RIN34) LIN34 PGA Mute 0 = Disable Mute 1 = Enable Mute LIN34 PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only LIN34 Volume (See Table 6 for volume range) Input PGA Volume Update Writing a 1 to this bit will cause all input PGA volumes to be updated simultaneously (LIN12, LIN34, RIN12 and RIN34) RIN12 PGA Mute 0 = Disable Mute 1 = Enable Mute RIN12 PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only 7 LI12MUTE 1b 6 LI12ZC 0b 4:0 R25 (19h) 8 LIN12VOL [4:0] IPVU[1] 01011b (0dB) N/A 7 LI34MUTE 1b 6 LI34ZC 0b 4:0 R26 (1Ah) 8 LIN34VOL [4:0] IPVU[2] 01011b (0dB) N/A 7 RI12MUTE 1b 6 RI12ZC 0b w PP, May 2008, Rev 3.1 45 WM8991 REGISTER ADDRESS BIT 4:0 R27 (1Bh) 8 LABEL RIN12VOL [4:0] IPVU[3] DEFAULT 01011b (0dB) N/A Pre-Production DESCRIPTION RIN12 Volume (See Table 6 for volume range) Input PGA Volume Update Writing a 1 to this bit will cause all input PGA volumes to be updated simultaneously (LIN12, LIN34, RIN12 and RIN34) RIN34 PGA Mute 0 = Disable Mute 1 = Enable Mute RIN34 PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only RIN34 Volume (See Table 6 for volume range) 7 RI34MUTE 1b 6 RI34ZC 0b 4:0 RIN34VOL [4:0] 01011b (0dB) Table 5 Input PGA Volume Control w PP, May 2008, Rev 3.1 46 Pre-Production WM8991 LIN12VOL[4:0], LIN34VOL[4:0], RIN12VOL[4:0], RIN34VOL[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Table 6 Input PGA Volume Range VOLUME (dB) -16.5 -15.0 -13.5 -12.0 -10.5 -9.0 -7.5 -6.0 -4.5 -3.0 -1.5 0 +1.5 +3.0 +4.5 +6.0 +7.5 +9.0 +10.5 +12.0 +13.5 +15.0 +16.5 +18.0 +19.5 +21.0 +22.5 +24.0 +25.5 +27.0 +28.5 +30.0 w PP, May 2008, Rev 3.1 47 WM8991 INPUT MIXER ENABLE Pre-Production The WM8991 has two analogue input mixers which allow the Input PGAs and Line Inputs to be combined in a number of ways and output to the ADCs or to the Output Mixers via bypass paths. The input mixers INMIXL and INMIXR are enabled by the AINL_ENA and AINR_ENA register bits, as described in Table 7. These control bits also enable the Input Multiplexers and Differential Input drivers, described in the following section. REGISTER ADDRESS R2 (02h) BIT 9 LABEL AINL_ENA (rw) DEFAULT 0b DESCRIPTION Left Input Path Enable (Enables AINLMUX, INMIXL, DIFFINL and RXVOICE input to AINLMUX) 0 = Input Path disabled 1 = Input Path enabled Right Input Path Enable (Enables AINRMUX, INMIXR, DIFFINR and RXVOICE input to AINRMUX) 0 = Input Path disabled 1 = Input Path enabled 8 AINR_ENA (rw) 0b Table 7 Input Mixer Enable INPUT MIXER CONFIGURATION The left and right channel input multiplexers AINLMUX and AINRMUX select one of three input sources for the Left and Right channels independently. The three input sources are as follows: 1. INMIXL or INMIXR output (a combination of Input PGAs, line inputs and the internal record path). 2. RXVOICE (a differential to single-ended conversion of RXP and RXN inputs). 3. DIFFINL or DIFFINR output (a differential to single-ended conversion of two Input PGAs). The input source for the multiplexers is controlled by register bits AINLMODE and AINRMODE as described in Table 8. REGISTER ADDRESS R39 (27h) BIT 3:2 LABEL AINLMODE [1:0] DEFAULT 00b DESCRIPTION AINLMUX Input Source 00 = INMIXL (Left Input Mixer) 01 = RXVOICE (RXP - RXN) 10 = DIFFINL (LIN12 PGA - LIN34 PGA) 11 = (Reserved) AINRMUX Input Source 00 = INMIXR (Right Input Mixer) 01 = RXVOICE (RXP - RXN) 10 = DIFFINR (RIN12 PGA - RIN34 PGA) 11 = (Reserved) 1:0 AINRMODE [1:0] 00b Table 8 Input Mixer Configuration The Input Mixer configuration is described for each of the three modes in the following sections. Note that the Left and Right multiplexer (mode) settings can be set independently. w PP, May 2008, Rev 3.1 48 Pre-Production WM8991 In Mixer Mode (AINLMODE=00, AINRMODE=00), adjustable gain control is available on the input mixers INMIXL and INMIXR for all available input signals (PGA outputs, line inputs and record paths). This configuration is illustrated in Figure 25. The applicable register settings are shown in Table 9. CONFIGURATION Left Channel Mixer Mode (INMIXL to AINLMUX) 1. Select Mixer Mode 2. Enable input paths as required (see Table 5 and Table 12 for full definitions of the applicable settings listed here) Right Channel Mixer Mode (INMIXR to AINRMUX) 1. Select Mixer Mode 2. Enable input paths as required (see Table 5 and Table 13 for full definitions of the applicable settings listed here) REGISTER SETTINGS AINLMODE = 00 L12MNB, L12MNBST LIN12VOL, LIN12MUTE L34MNB, L34MNBST LIN34VOL, LIN34MUTE LDBVOL LI2BVOL AINRMODE = 00 R12MNB, R12MNBST RIN12VOL, RIN12MUTE R34MNB, R34MNBST RIN34VOL, RIN34MUTE RDBVOL RI2BVOL Table 9 Mixer Mode Register Settings Figure 25 Mixer Mode Signal Paths w PP, May 2008, Rev 3.1 49 WM8991 Pre-Production In Rx Voice Mode (AINLMODE=01, AINRMODE=01), adjustable gain control is available for the RXVOICE output by use of the LR4BVOL[2:0] and LL4BVOL[2:0] register fields on the left channel and by RL4BVOL[2:0] and RR4BVOL[2:0] on the right channel. Both Volume fields for the desired channel(s) must be set to the same value for true Differential input characteristics. This configuration is illustrated in Figure 26. The applicable register settings are shown in Table 10. CONFIGURATION Left Channel Rx Voice Mode (RXVOICE to AINLMUX) REGISTER SETTINGS 1. Select Rx Voice Mode 2. Enable Rx Voice input as required Important: These two register fields must be set to the same value. See Table 12 for full definitions of these fields. 1. Select Rx Voice Mode 2. Enable Rx Voice input as required Important: These two register fields must be set to the same value. See Table 13 for full definitions of these fields. AINLMODE = 01 LL4BVOL LR4BVOL Right Channel Rx Voice Mode (RXVOICE to AINRMUX) AINRMODE = 01 RL4BVOL RR4BVOL Table 10 RxVoice Mode Register Settings Figure 26 RxVoice Mode Signal Paths w PP, May 2008, Rev 3.1 50 Pre-Production WM8991 In Differential Mode (AINLMODE=10, AINRMODE=10), no additional volume control is available in the input signal path, but the Input PGA volume control can be used to adjust the signal level as with other modes. Both PGAs on the desired channel(s) must be enabled, and the PGA volumes of each set to the same value for true Differential input characteristics. The PGA Output (LIN12 or RIN12) to Mixer (INMIXL or INMIXR) path must also be enabled on the desired channel(s) by use of register bit L12MNB or R12MNB. This configuration is illustrated in Figure 27. The applicable register settings are shown in Table 11. CONFIGURATION Left Channel Differential Mode (DIFFINL to AINLMUX) REGISTER SETTINGS 1. Select Differential Mode 2. Enable LIN12 input path 3. Set channel volume as required. Important: The LIN12 and LIN34 volume and mute settings must be set to the same value. See Table 5 for full definitions of these fields. 1. Select Differential Mode 2. Enable RIN12 input path 3. Set channel volume as required. Important: The RIN12 and RIN34 volume and mute settings must be set to the same value. See Table 5 for full definitions of these fields. AINLMODE = 10 L12MNB = 1 LIN12VOL, LIN12MUTE LIN34VOL, LIN34MUTE Right Channel Differential Mode (DIFFINR to AINRMUX) AINRMODE = 10 R12MNB = 1 RIN12VOL, RIN12MUTE RIN34VOL, RIN34MUTE Table 11 Differential Mode Register Settings Figure 27 Differential Mode Signal Paths INPUT MIXER VOLUME CONTROL The Input Mixer volume controls are described in Table 12 for the Left Channel and Table 13 for the Right Channel. The Input PGA levels may be set to Mute, 0dB or 30dB boost. The other gain controls provide adjustment from -12dB to +6dB in 3dB steps. To prevent pop noise it is recommended that gain and mute controls for the input mixers are not modified while the signal paths are active. If volume control is required on the input signal path it is recommended that the input PGA volume controls or the ADC volume controls are used instead of the input mixer gain registers. w PP, May 2008, Rev 3.1 51 WM8991 REGISTER ADDRESS R41 (29h) BIT 8 LABEL L34MNB DEFAULT 0b Pre-Production DESCRIPTION LIN34 PGA Output to INMIXL Mute 0 = Mute 1 = Un-Mute LIN34 PGA Output to INMIXL Gain 0 = 0dB 1 = +30dB LIN12 PGA Output to INMIXL Mute 0 = Mute 1 = Un-Mute LIN12 PGA Output to INMIXL Gain 0 = 0dB 1 = +30dB LOMIX to INMIXL Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB LIN2 Pin to INMIXL Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB RXVOICE to AINLMUX Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB RXVOICE to INMIXL Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Note - LR4BVOL must be set to the same value as LL4BVOL when AINLMODE=01. 7 L34MNBST 0b 5 L12MNB 0b 4 L12MNBST 0b 2:0 LDBVOL [2:0] 000b (Mute) R43 (2Bh) 8:6 LI2BVOL [2:0] 000b (Mute) 5:3 LR4BVOL [2:0] 000b (Mute) 2:0 LL4BVOL [2:0] 000b (Mute) Table 12 Left Input Mixer Volume Control w PP, May 2008, Rev 3.1 52 Pre-Production WM8991 REGISTER ADDRESS R42 (2A) BIT 8 LABEL R34MNB DEFAULT 0b DESCRIPTION RIN34 PGA Output to INMIXR Mute 0 = Mute 1 = Un-Mute RIN34 PGA Output to INMIXR Gain 0 = 0dB 1 = +30dB RIN12 PGA Output to INMIXR Mute 0 = Mute 1 = Un-Mute RIN12 PGA Output to INMIXR Gain 0 = 0dB 1 = +30dB ROMIX to INMIXR Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB RIN2 Pin to INMIXR Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB RXVOICE to AINRMUX Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB RXVOICE to INMIXR Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Note - RL4BVOL must be set to the same value as RR4BVOL when AINRMODE=01. 7 R34MNBST 0b 5 R12MNB 0b 4 R12MNBST 0b 2:0 RDBVOL [2:0] 000b (Mute) R44 (2Ch) 8:6 RI2BVOL [2:0] 000b (Mute) 5:3 RL4BVOL [2:0] 000b (Mute) 2:0 RR4BVOL [2:0] 000b (Mute) Table 13 Right Input Mixer Volume Control w PP, May 2008, Rev 3.1 53 WM8991 ANALOGUE TO DIGITAL CONVERTER (ADC) Pre-Production The WM8991 uses stereo 24-bit, 64x oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC full scale input level is proportional to AVDD. See "Electrical Characteristics" for further details. Any input signal greater than full scale may overload the ADC and cause distortion. The ADCs are enabled by the ADCL_ENA and ADCR_ENA register bits. REGISTER ADDRESS R2 (02h) BIT 1 LABEL ADCL_ENA (rw) ADCR_ENA (rw) DEFAULT 0b DESCRIPTION Left ADC Enable 0 = ADC disabled 1 = ADC enabled Right ADC Enable 0 = ADC disabled 1 = ADC enabled 0 0b Table 14 ADC Enable Control ADC DIGITAL VOLUME CONTROL The output of the ADCs can be digitally amplified or attenuated over a range from -71.625dB to +17.625dB in 0.375dB steps. The volume of each channel can be controlled separately. The gain for a given eight-bit code X is given by: 0.375 x (X-192) dB for 1 X 239; MUTE for X = 0 +17.625dB for 239 X 255 The ADC_VU bit controls the loading of digital volume control data. When ADC_VU is set to 0, the ADCL_VOL or ADCR_VOL control data will be loaded into the respective control register, but will not actually change the digital gain setting. Both left and right gain settings are updated when a 1 is written to ADC_VU. This makes it possible to update the gain of both channels simultaneously. REGISTER ADDRESS R15 (0Fh) BIT 8 LABEL ADC_VU DEFAULT N/A DESCRIPTION ADC Volume Update Writing a 1 to this bit will cause left and right ADC volume to be updated simultaneously Left ADC Digital Volume (See Table 16 for volume range) ADC Volume Update Writing a 1 to this bit will cause left and right ADC volume to be updated simultaneously Right ADC Digital Volume (See Table 16 for volume range) 7:0 R16 (10h) 8 ADCL_VOL [7:0] ADC_VU 1100_0000b (0dB) N/A 7:0 ADCR_VOL [7:0] 1100_0000b (0dB) Table 15 ADC Digital Volume Control w PP, May 2008, Rev 3.1 54 Pre-Production ADCL_VOL or ADCR_VOL 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh WM8991 Volume (dB) MUTE -71.625 -71.250 -70.875 -70.500 -70.125 -69.750 -69.375 -69.000 -68.625 -68.250 -67.875 -67.500 -67.125 -66.750 -66.375 -66.000 -65.625 -65.250 -64.875 -64.500 -64.125 -63.750 -63.375 -63.000 -62.625 -62.250 -61.875 -61.500 -61.125 -60.750 -60.375 -60.000 -59.625 -59.250 -58.875 -58.500 -58.125 -57.750 -57.375 -57.000 -56.625 -56.250 -55.875 -55.500 -55.125 -54.750 -54.375 -54.000 -53.625 -53.250 -52.875 -52.500 -52.125 -51.750 -51.375 -51.000 -50.625 -50.250 -49.875 -49.500 -49.125 -48.750 -48.375 ADCL_VOL or ADCR_VOL 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh Volume (dB) -48.000 -47.625 -47.250 -46.875 -46.500 -46.125 -45.750 -45.375 -45.000 -44.625 -44.250 -43.875 -43.500 -43.125 -42.750 -42.375 -42.000 -41.625 -41.250 -40.875 -40.500 -40.125 -39.750 -39.375 -39.000 -38.625 -38.250 -37.875 -37.500 -37.125 -36.750 -36.375 -36.000 -35.625 -35.250 -34.875 -34.500 -34.125 -33.750 -33.375 -33.000 -32.625 -32.250 -31.875 -31.500 -31.125 -30.750 -30.375 -30.000 -29.625 -29.250 -28.875 -28.500 -28.125 -27.750 -27.375 -27.000 -26.625 -26.250 -25.875 -25.500 -25.125 -24.750 -24.375 ADCL_VOL or ADCR_VOL 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh Volume (dB) -24.000 -23.625 -23.250 -22.875 -22.500 -22.125 -21.750 -21.375 -21.000 -20.625 -20.250 -19.875 -19.500 -19.125 -18.750 -18.375 -18.000 -17.625 -17.250 -16.875 -16.500 -16.125 -15.750 -15.375 -15.000 -14.625 -14.250 -13.875 -13.500 -13.125 -12.750 -12.375 -12.000 -11.625 -11.250 -10.875 -10.500 -10.125 -9.750 -9.375 -9.000 -8.625 -8.250 -7.875 -7.500 -7.125 -6.750 -6.375 -6.000 -5.625 -5.250 -4.875 -4.500 -4.125 -3.750 -3.375 -3.000 -2.625 -2.250 -1.875 -1.500 -1.125 -0.750 -0.375 ADCL_VOL or ADCR_VOL C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh Volume (dB) 0.000 0.375 0.750 1.125 1.500 1.875 2.250 2.625 3.000 3.375 3.750 4.125 4.500 4.875 5.250 5.625 6.000 6.375 6.750 7.125 7.500 7.875 8.250 8.625 9.000 9.375 9.750 10.125 10.500 10.875 11.250 11.625 12.000 12.375 12.750 13.125 13.500 13.875 14.250 14.625 15.000 15.375 15.750 16.125 16.500 16.875 17.250 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 Table 16 ADC Digital Volume Range w PP, May 2008, Rev 3.1 55 WM8991 HIGH PASS FILTER Pre-Production A digital high pass filter is applied by default to the ADC path to remove DC offsets. This filter can also be programmed to remove low frequency noise in voice applications (e.g. wind noise or mechanical vibration). This filter is controlled using the ADC_HPF_ENA and ADC_HPF_CUT register bits. In hi-fi mode the high pass filter is optimised for removing DC offsets without degrading the bass response and has a cut-off frequency of 3.7Hz at fs=44.1kHz. In voice mode the high pass filter is optimised for voice communication and it is recommended to program the cut-off frequency below 300Hz (e.g. ADC_HPF_CUT=11 at fs=8kHz or ADC_HPF_CUT=10 at fs=16kHz). REGISTER ADDRESS R14 (0Eh) 8 BIT LABEL ADC_HPF_ENA DEFAULT 1b DESCRIPTION ADC Digital High Pass Filter Enable 0 = disabled 1 = enabled ADC Digital High Pass Filter Cut-Off Frequency (fc) 00 = Hi-fi mode (fc=4Hz at fs=48kHz) 01 = Voice mode 1 (fc=127Hz at fs=16kHz) 10 = Voice mode 2 (fc=130Hz at fs=8kHz) 11 = Voice mode 3 (fc=267Hz at fs=8kHz) (Note: fc scales with sample rate. See Table 18 for cut-off frequencies at all supported sample rates) 6:5 ADC_HPF_CUT [1:0] 00b Table 17 ADC High Pass Filter Control Registers SAMPLE FREQUENCY (kHz) 8.000 11.025 16.000 22.050 24.000 32.000 44.100 48.000 CUT-OFF FREQUENCY (Hz) ADC_HPF_CUT =00 0.7 0.9 1.3 1.9 2.0 2.7 3.7 4.0 ADC_HPF_CUT ADC_HPF_CUT ADC_HPF_CUT =01 =10 =11 64 88 127 175 190 253 348 379 130 178 258 354 386 514 707 770 267 367 532 733 798 1063 1464 1594 Table 18 ADC High Pass Filter Cut-Off Frequencies The high pass filter characteristics are shown in the "Digital Filter Characteristics" section. w PP, May 2008, Rev 3.1 56 Pre-Production WM8991 DIGITAL MIXING The ADC and DAC data can be combined in various ways to support a range of different usage modes. Data from either of the two ADCs can be routed to either the left or the right channel of the digital audio interface. In addition, data from either of the digital audio interface channels can be routed to either the left or the right DAC. See "Digital Audio Interface" for more information on the audio interface. DIGITAL MIXING PATHS Figure 28 shows the digital mixing paths available in the WM8991 digital core. MAIN REGISTER BIT REFERENCE REGISTER BIT ALSO REFERENCED ELSEWHERE IN DIAGRAM READBACK AVAILABLE DIGITAL CORE DACL ADC en HIGH PASS FILTER (VOICE OR HI-FI) en ADCL_DAC_SVOL [7:0] en 0 ADC_TO_DACL [1:0] 00=0 01=ADCL 10=ADCR 11=Reserved ADC_TO_DACR [1:0] + DACL_VOL [7:0] MONO DAC ADCL_VOL [7:0] ADCL_ENA ADC_HPF_CUT [1:0] ADCR_ENA en ADC_HPF_ENA en + DAC_MONO ADC HIGH PASS FILTER (VOICE OR HI-FI) 0 + DACR_VOL [7:0] DAC_MUTE, DAC_MUTEMODE, DAC_MUTERATE, DAC_SB_FILT, DEEMP[1:0] DAC en DACR ADCR_VOL [7:0] ADCR_DAC_SVOL [7:0] DAC_BOOST [1:0] DAC_BOOST 00 = 0dB 01 = +6dB 10 = +12dB 11 = +18dB ADCR_DATINV ADCL_DATINV DACL_DATINV DACR_DATINV DACL_SRC DACR_SRC AIFADCR_SRC AIFADCL_SRC R L R L DIGITAL AUDIO INTERFACE A-law and u-law support TDM Support GPIO Alternative DAC Interface Alternative MCLK Button Control / Accessory Detect Clock Output Inverted ADCLRC GPIO6/ADCLRCB GPIO5/DACDAT2 GPIO4/DACLRC2 GPIO3/BCLK2 GPIO2/MCLK2 BCLK DACLRC DACDAT ADCDAT ADCLRC/GPIO1 Figure 28 Digital Mixing Paths w PP, May 2008, Rev 3.1 57 WM8991 Pre-Production The polarity of each ADC output signal can be changed under software control using the ADCL_DATINV and ADCR_DATINV register bits. The AIFADCL_SRC and AIFADCR_SRC register bits may be used to select which ADC is used for the left and right digital audio interface data. These register bits are described in Table 19. REGISTER ADDRESS R4 (04h) BIT 15 LABEL AIFADCL_SRC DEFAULT 0b DESCRIPTION Left Digital Audio channel source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel Right Digital Audio channel source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel Left ADC Invert 0 = Left ADC output not inverted 1 = Left ADC output inverted Right ADC Invert 0 = Right ADC output not inverted 1 = Right ADC output inverted 14 AIFADCR_SRC 1b R14 (0Eh) 1 ADCL_DATINV 0b 0 ADCR_DATINV 0b Table 19 ADC Routing and Control The input data source for each DAC can be changed under software control using register bits DACL_SRC and DACR_SRC. The polarity of each DAC input may also be modified using register bits DACL_DATINV and DACR_DATINV. These register bits are described in Table 20. REGISTER ADDRESS R5 (05h) BIT 15 LABEL DACL_SRC DEFAULT 0b DESCRIPTION Left DAC Data Source Select 0 = Left DAC outputs left channel data 1 = Left DAC outputs right channel data Right DAC Data Source Select 0 = Right DAC outputs left channel data 1 = Right DAC outputs right channel data Left DAC Invert 0 = Left DAC output not inverted 1 = Left DAC output inverted Right DAC Invert 0 = Right DAC output not inverted 1 = Right DAC output inverted 14 DACR_SRC 1b R10 (0Ah) 1 DACL_DATINV 0b 0 DACR_DATINV 0b Table 20 DAC Routing and Control w PP, May 2008, Rev 3.1 58 Pre-Production WM8991 DAC INTERFACE VOLUME BOOST A digital gain function is available at the audio interface to boost the DAC volume when a small signal is received on DACDAT. This is controlled using register bits DAC_BOOST[1:0]. To prevent clipping at the DAC input, this function should not be used when the boosted DAC data is expected to be greater than 0dBFS. REGISTER ADDRESS R5 (05h) BIT 11:10 LABEL DAC_BOOST [1:0] DEFAULT 00b DESCRIPTION DAC Input Volume Boost 00 = 0dB 01 = +6dB (Input data must not exceed -6dBFS) 10 = +12dB (Input data must not exceed -12dBFS) 11 = +18dB (Input data must not exceed -18dBFS) Table 21 DAC Interface Volume Boost DIGITAL SIDETONE A digital sidetone is available when ADCs and DACs are operating at the same sample rate. Digital data from either left or right ADC can be mixed with the audio interface data on the left and right DAC channels. Sidetone data is taken from the ADC high pass filter output, to reduce low frequency noise in the sidetone (e.g. wind noise or mechanical vibration). The digital sidetone will not function when ADCs and DACs are operating at different sample rates. When using the digital sidetone, it is recommended that the ADCs are enabled before un-muting the DACs to prevent pop noise. The DAC volumes and sidetone volumes should be set to an appropriate level to avoid clipping at the DAC input. The digital sidetone is controlled as shown in Table 22. REGISTER ADDRESS R13 (0Dh) BIT 12:9 8:5 3:2 LABEL ADCL_DAC_SVOL [3:0] ADCR_DAC_SVOL [3:0] ADC_TO_DACL [1:0] DEFAULT 0000b 0000b 00b DESCRIPTION Left Digital Sidetone Volume (See Table 23 for volume range) Right Digital Sidetone Volume (See Table 23 for volume range) Left DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = Reserved Right DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = Reserved 1:0 ADC_TO_DACR [1:0] 00b Table 22 Digital Sidetone Control w PP, May 2008, Rev 3.1 59 WM8991 ADCL_DAC_SVOL or ADCR_DAC_SVOL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SIDETONE VOLUME -36 -33 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 0 0 0 Pre-Production Table 23 Digital Sidetone Volume w PP, May 2008, Rev 3.1 60 Pre-Production WM8991 DIGITAL TO ANALOGUE CONVERTER (DAC) The WM8991 DACs receive digital input data from the DACDAT pin and via the digital sidetone path. The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to high quality analogue audio signals. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low distortion. The analogue outputs from the DACs can then be mixed with other analogue inputs using the output mixers LOMIX, ROMIX and the speaker output mixer SPKMIX. The DACs are enabled by the DACL_ENA and DACR_ENA register bits. REGISTER ADDRESS R3 (03h) BIT 1 LABEL DACL_ENA (rw) DACR_ENA (rw) DEFAULT 0b DESCRIPTION Left DAC Enable 0 = DAC disabled 1 = DAC enabled Right DAC Enable 0 = DAC disabled 1 = DAC enabled 0 0b Table 24 DAC Enable Control DAC DIGITAL VOLUME CONTROL The output level of each DAC can be controlled digitally over a range from -71.625dB to 0dB in 0.375dB steps. The level of attenuation for an eight-bit code X is given by: 0.375 x (X-192) dB for 1 X 192; MUTE for X = 0 0dB for 192 X 255 The DAC_VU bit controls the loading of digital volume control data. When DAC_VU is set to 0, the DACL_VOL or DACR_VOL control data will be loaded into the respective control register, but will not actually change the digital gain setting. Both left and right gain settings are updated when a 1 is written to DAC_VU. This makes it possible to update the gain of both channels simultaneously. REGISTER ADDRESS R11 (0Bh) BIT 8 LABEL DAC_VU DEFAULT N/A DESCRIPTION DAC Volume Update Writing a 1 to this bit will cause left and right DAC volume to be updated simultaneously Left DAC Digital Volume (See Table 26 for volume range) DAC Volume Update Writing a 1 to this bit will cause left and right DAC volume to be updated simultaneously Right DAC Digital Volume (See Table 26 for volume range) 7:0 R12 (0Ch) 8 DACL_VOL [7:0] DAC_VU 1100_0000b (0dB) N/A 7:0 DACR_VOL [7:0] 1100_0000b (0dB) Table 25 DAC Digital Volume Control w PP, May 2008, Rev 3.1 61 WM8991 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh MUTE -71.625 -71.250 -70.875 -70.500 -70.125 -69.750 -69.375 -69.000 -68.625 -68.250 -67.875 -67.500 -67.125 -66.750 -66.375 -66.000 -65.625 -65.250 -64.875 -64.500 -64.125 -63.750 -63.375 -63.000 -62.625 -62.250 -61.875 -61.500 -61.125 -60.750 -60.375 -60.000 -59.625 -59.250 -58.875 -58.500 -58.125 -57.750 -57.375 -57.000 -56.625 -56.250 -55.875 -55.500 -55.125 -54.750 -54.375 -54.000 -53.625 -53.250 -52.875 -52.500 -52.125 -51.750 -51.375 -51.000 -50.625 -50.250 -49.875 -49.500 -49.125 -48.750 -48.375 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh -48.000 -47.625 -47.250 -46.875 -46.500 -46.125 -45.750 -45.375 -45.000 -44.625 -44.250 -43.875 -43.500 -43.125 -42.750 -42.375 -42.000 -41.625 -41.250 -40.875 -40.500 -40.125 -39.750 -39.375 -39.000 -38.625 -38.250 -37.875 -37.500 -37.125 -36.750 -36.375 -36.000 -35.625 -35.250 -34.875 -34.500 -34.125 -33.750 -33.375 -33.000 -32.625 -32.250 -31.875 -31.500 -31.125 -30.750 -30.375 -30.000 -29.625 -29.250 -28.875 -28.500 -28.125 -27.750 -27.375 -27.000 -26.625 -26.250 -25.875 -25.500 -25.125 -24.750 -24.375 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh -24.000 -23.625 -23.250 -22.875 -22.500 -22.125 -21.750 -21.375 -21.000 -20.625 -20.250 -19.875 -19.500 -19.125 -18.750 -18.375 -18.000 -17.625 -17.250 -16.875 -16.500 -16.125 -15.750 -15.375 -15.000 -14.625 -14.250 -13.875 -13.500 -13.125 -12.750 -12.375 -12.000 -11.625 -11.250 -10.875 -10.500 -10.125 -9.750 -9.375 -9.000 -8.625 -8.250 -7.875 -7.500 -7.125 -6.750 -6.375 -6.000 -5.625 -5.250 -4.875 -4.500 -4.125 -3.750 -3.375 -3.000 -2.625 -2.250 -1.875 -1.500 -1.125 -0.750 -0.375 C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh Pre-Production DACL_VOL or DACL_VOL or DACL_VOL or DACL_VOL or DACR_VOL Volume (dB) DACR_VOL Volume (dB) DACR_VOL Volume (dB) DACR_VOL Volume (dB) 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 Table 26 DAC Digital Volume Range w PP, May 2008, Rev 3.1 62 Pre-Production WM8991 DAC SOFT MUTE AND SOFT UN-MUTE The WM8991 has a soft mute function which, when enabled, gradually attenuates the volume of the DAC output. When soft mute is disabled, the gain will either gradually ramp back up to the digital gain setting, or return instantly to the digital gain setting, depending on the DAC_MUTEMODE register bit. The DAC is soft-muted by default (DAC_MUTE = 1). To play back an audio signal, this function must first be disabled by setting DAC_MUTE to 0. Soft Mute Mode would typically be enabled (DAC_MUTEMODE = 1) when using DAC_MUTE during playback of audio data so that when DAC_MUTE is subsequently disabled, the sudden volume increase will not create pop noise by jumping immediately to the previous volume level (e.g. resuming playback after pausing during a track). Soft Mute Mode would typically be disabled (DAC_MUTEMODE = 0) when un-muting at the start of a music file, in order that the first part of the track is not attenuated (e.g. when starting playback of a new track, or resuming playback after pausing between tracks). DAC muting and un-muting using volume control bits DACL_VOL and DACR_VOL. DAC muting and un-muting using soft mute bit DAC_MUTE. Soft Mute Mode not enabled (DAC_MUTEMODE = 0). DAC muting and un-muting using soft mute bit DAC_MUTE. Soft Mute Mode enabled (DAC_MUTEMODE = 1). Figure 29 DAC Mute Control The volume ramp rate during soft mute and un-mute is controlled by the DAC_MUTERATE bit. Ramp rates of fs/32 and fs/2 are selectable as shown in Table 27. The ramp rate determines the rate at which the volume will be increased or decreased. The actual ramp time depends on the extent of the difference between the muted and un-muted volume settings. REGISTER ADDRESS R10 (0Ah) BIT 7 LABEL DAC_MUTERATE DEFAULT 0b DESCRIPTION DAC Soft Mute Ramp Rate 0 = Fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48k) 1 = Slow ramp (fs/32, maximum ramp time is 171ms at fs=48k) DAC Soft Mute Mode 0 = Disabling soft-mute (DAC_MUTE=0) will cause the DAC volume to change immediately to DACL_VOL and DACR_VOL settings 1 = Disabling soft-mute (DAC_MUTE=0) will cause the DAC volume to ramp up gradually to the DACL_VOL and DACR_VOL settings DAC Soft Mute Control 0 = DAC Un-mute 1 = DAC Mute 6 DAC_MUTEMODE 0b 2 DAC_MUTE 1b Table 27 DAC Soft-Mute Control PP, May 2008, Rev 3.1 63 w WM8991 DAC MONO MIX Pre-Production A DAC digital mono-mix mode can be enabled using the DAC_MONO register bit. This mono mix will be output on the enabled DACs. To prevent clipping, a -6dB attenuation is automatically applied to the mono mix. REGISTER ADDRESS R10 (0Ah) BIT 9 LABEL DAC_MONO DEFAULT 0b DESCRIPTION DAC Mono Mix 0 = Stereo 1 = Mono (Mono mix output on enabled DACs) Table 28 DAC Mono Mix DAC DE-EMPHASIS Digital de-emphasis can be applied to the DAC playback data (e.g. when the data comes from a CD with pre-emphasis used in the recording). De-emphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz. See "Digital Filter Characteristics" section for details of de-emphasis filter characteristics. REGISTER ADDRESS R10 (0Ah) ADC and DAC Control (1) BIT 5:4 LABEL DEEMP [1:0] DEFAULT 00b DESCRIPTION DAC De-Emphasis Control 00 = No de-emphasis 01 = 32kHz sample rate 10 = 44.1kHz sample rate 11 = 48kHz sample rate Table 29 DAC De-Emphasis Control DAC SLOPING STOPBAND FILTER Two DAC filter types are available, selected by the register bit DAC_SB_FILT. When operating at lower sample rates (e.g. during voice communication) it is recommended that the sloping stopband filter type is selected (DAC_SB_FILT=1) to reduce out-of-band noise which can be audible at low DAC sample rates. See "Digital Filter Characteristics" section for details of DAC filter characteristics. REGISTER ADDRESS R10 (0Ah) BIT 8 LABEL DAC_SB_FILT DEFAULT 0b DESCRIPTION Selects DAC filter characteristics 0 = Normal mode 1 = Sloping stopband mode Table 30 DAC Sloping Stopband Filter w PP, May 2008, Rev 3.1 64 Pre-Production WM8991 OUTPUT SIGNAL PATH The WM8991 output routing and mixers provide a high degree of flexibility, allowing operation of many simultaneous signal paths through the device to various analogue outputs. The outputs provide many combinations of headphone, loudspeaker and single-ended line drivers. See "Analogue Outputs" for further details of these outputs. The WM8991 output signal paths and control registers are illustrated in Figure 30. Figure 30 Control Registers for Output Signal Path w PP, May 2008, Rev 3.1 65 WM8991 OUTPUT SIGNAL PATHS ENABLE Pre-Production The output mixers and drivers can be independently enabled and disabled as described in Table 31. Note that the headphone outputs LOUT and ROUT have dedicated volume controls. As a result, the output PGAs LOPGA and ROPGA do not need to be enabled to provide volume control for the LOUT and ROUT outputs. REGISTER ADDRESS R3 (03h) BIT 13 LABEL LON_ENA (rw) LOP_ENA (rw) RON_ENA (rw) ROP_ENA (rw) SPKPGA_ENA (rw) DEFAULT 0b DESCRIPTION LON Line Out and LONMIX Enable 0 = disabled 1 = enabled LOP Line Out and LOPMIX Enable 0 = disabled 1 = enabled RON Line Out and RONMIX Enable 0 = disabled 1 = enabled ROP Line Out and ROPMIX Enable 0 = disabled 1 = enabled SPKMIX Mixer and Speaker PGA Enable 0 = disabled 1 = enabled Note that SPKMIX and SPKPGA are also enabled when SPK_ENA is set. LOPGA Left Volume Control Enable 0 = disabled 1 = enabled ROPGA Right Volume Control Enable 0 = disabled 1 = enabled LOMIX Left Output Mixer Enable 0 = disabled 1 = enabled ROMIX Right Output Mixer Enable 0 = disabled 1 = enabled SPKMIX Mixer, Speaker PGA and Speaker Output Enable 0 = disabled 1 = enabled OUT3 and OUT3MIX Enable 0 = disabled 1 = enabled OUT4 and OUT4MIX Enable 0 = disabled 1 = enabled LOUT (Left Headphone Output) Enable 0 = disabled 1 = enabled ROUT (Right Headphone Output) Enable 0 = disabled 1 = enabled 12 0b 11 0b 10 0b 8 0b 7 LOPGA_ENA (rw) ROPGA_ENA (rw) LOMIX_ENA (rw) ROMIX_ENA (rw) SPK_ENA (rw) 0b 6 0b 5 0b 4 0b R1 (01h) 12 0b 11 OUT3_ENA (rw) OUT4_ENA (rw) LOUT_ENA (rw) ROUT_ENA (rw) 0b 10 0b 9 0b 8 0b Table 31 Output Signal Paths Enable w PP, May 2008, Rev 3.1 66 Pre-Production WM8991 OUTPUT MIXER CONTROL The Output Mixer volume controls are described in Table 32 for the Left Channel and Table 33 for the Right Channel. The gain of each of analogue input paths may be controlled independently in the range described in Table 34. The DAC input levels may be controlled by the DAC digital volume control - see "Digital to Analogue Converter (DAC)" for further details of this control. REGISTER ADDRESS R45 (2Dh) BIT 5 LABEL LRI3LO DEFAULT 0b DESCRIPTION RIN3 to LOMIX Mute 0 = Mute 1 = Un-mute LIN3 to LOMIX Mute 0 = Mute 1 = Un-mute RIN3 to LOMIX Volume (See Table 34 for Volume Range) LIN3 to LOMIX Volume (See Table 34 for Volume Range) LIN12 PGA Output to LOMIX Mute 0 = Mute 1 = Un-mute LIN12 PGA Output to LOMIX Volume (See Table 34 for Volume Range) RIN12 PGA Output to LOMIX Mute 0 = Mute 1 = Un-mute RIN12 PGA Output to LOMIX Volume (See Table 34 for Volume Range) AINRMUX Output (Right ADC bypass) to LOMIX Mute 0 = Mute 1 = Un-mute AINRMUX Output (Right ADC bypass) to LOMIX Volume (See Table 34 for Volume Range) AINLMUX Output (Left ADC bypass) to LOMIX Mute 0 = Mute 1 = Un-mute AINLMUX Output (Left ADC bypass) to LOMIX Volume (See Table 34 for Volume Range) Left DAC to LOMIX Mute 0 = Mute 1 = Un-mute Note: LDLO must be muted when LDSPK=1 R45 (2Dh) 4 LLI3LO 0b R49 (31h) R47 (2Fh) R45 (2Dh) 8:6 8:6 2 LRI3LOVOL [2:0] LLI3LOVOL [2:0] LL12LO 000b 000b 0b R47 (2Fh) R45 (2Dh) 2:0 3 LL12LOVOL [2:0] LR12LO 000b 0 R47 (2Fh) R45 (2Dh) 5:3 7 LR12LOVOL [2:0] LRBLO 000b 0b R49 (31h) 5:3 LRBLOVOL [2:0] LLBLO 000b R45 (2Dh) 6 0b R49 (31h) 2:0 LLBLOVOL [2:0] LDLO 000b R45 (2Dh) 0 0b Table 32 Left Output Mixer (LOMIX) Volume Control w PP, May 2008, Rev 3.1 67 WM8991 REGISTER ADDRESS R46 (2Eh) BIT 5 LABEL RLI3RO DEFAULT 0b Pre-Production DESCRIPTION LIN3 to ROMIX Mute 0 = Mute 1 = Un-mute RIN3 to ROMIX Mute 0 = Mute 1 = Un-mute LIN3 to ROMIX Volume (See Table 34 for Volume Range) RIN3 to ROMIX Volume (See Table 34 for Volume Range) LIN12 PGA Output to ROMIX Mute 0 = Mute 1 = Un-mute LIN12 PGA Output to ROMIX Volume (See Table 34 for Volume Range) RIN12 PGA Output to ROMIX Mute 0 = Mute 1 = Un-mute RIN12 PGA Output to ROMIX Volume (See Table 34 for Volume Range) AINLMUX Output (Left ADC bypass) to ROMIX Mute 0 = Mute 1 = Un-mute AINLMUX Output (Left ADC bypass) to ROMIX Volume (See Table 34 for Volume Range) AINRMUX Output (Right ADC bypass) to ROMIX 0 = Mute 1 = Un-mute AINRMUX Output (Right ADC bypass) to ROMIX Volume (See Table 34 for Volume Range) Right DAC to ROMIX Mute 0 = Mute 1 = Un-mute Note: RDRO must be muted when RDSPK=1 R46 (2Eh) 4 RRI3RO 0b R50 (32h) R48 (30h) R46 (2Eh) 8:6 8:6 3 RLI3ROVOL [2:0] RRI3ROVOL [2:0] RL12RO 000b 000b 0b R48 (30h) R46 (2Eh) 5:3 2 RL12ROVOL [2:0] RR12RO 000b 0b R48 (30h) R46 (2Eh) 2:0 7 RR12ROVOL [2:0] RLBRO 000b 0b R50 (32h) 5:3 RLBROVOL [2:0] RRBRO 000b R46 (2Eh) 6 0b R50 (32h) 2:0 RRBROVOL [2:0] RDRO 000b R46 (2Eh) 0 0b Table 33 Right Output Mixer (ROMIX) Volume Control w PP, May 2008, Rev 3.1 68 Pre-Production WM8991 VOLUME SETTING 000 001 010 011 100 101 110 111 VOLUME (dB) 0 -3 -6 -9 -12 -15 -18 -21 Table 34 LOMIX and ROMIX Volume Range OUTPUT SIGNAL PATH VOLUME CONTROL The output drivers LOPGA, ROPGA, LOUT and ROUT can be independently controlled as shown in Table 35 and Table 36. To minimise pop noise it is recommended that only the LOPGAVOL, ROPGAVOL, LOUTVOL and ROUTVOL are modified while the output signal path is active. Other gain controls are provided in the output signal path to provide appropriate relative scaling of signals from different sources, and to prevent clipping when multiple signals are mixed. To prevent pop noise, only the gain controls noted above should be modified while playback is active. To prevent "zipper noise", a zero-cross function is provided on these output paths, so that when enabled, volume updates will not take place until a zero-crossing is detected. In the event of a long period without zero-crossings, a timeout function is available. When this function is enabled (using the TOCLK_ENA register bit), the volume will update after the timeout period if no earlier zero-cross has occurred. The timeout period is set by TOCLK_RATE. See "Clocking and Sample Rates" for more information on these fields. The OPVU bit controls the loading of the output driver volume data. When OPVU is set to 0, the volume control data will be loaded into the respective control register, but will not actually change the gain setting. The LOPGA, ROPGA, LOUT and ROUT volume settings are all updated when a 1 is written to OPVU. This makes it possible to update the gain of all output paths simultaneously. Note that the headphone outputs LOUT and ROUT have dedicated volume controls. As a result, the output PGAs LOPGA and ROPGA do not need to be enabled to provide volume control for the LOUT and ROUT outputs. w PP, May 2008, Rev 3.1 69 WM8991 REGISTER ADDRESS R32 (20h) BIT 8 LABEL OPVU[2] DEFAULT N/A Pre-Production DESCRIPTION Output PGA Volume Update Writing a 1 to this bit will update LOPGA, ROPGA, LOUTVOL and ROUTVOL volumes simultaneously. LOPGA Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled LOPGA Volume (See Table 36 for output PGA volume control range) Output PGA Volume Update Writing a 1 to this bit will update LOPGA, ROPGA, LOUTVOL and ROUTVOL volumes simultaneously. ROPGA Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled ROPGA Volume (See Table 36 for output PGA volume control range) Output PGA Volume Update Writing a 1 to this bit will update LOPGA, ROPGA, LOUTVOL and ROUTVOL volumes simultaneously. LOUT (Left Headphone Output) Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled LOUT (Left Headphone Output) Volume (See Table 36 for output PGA volume control range) Output PGA Volume Update Writing a 1 to this bit will update LOPGA, ROPGA, LOUTVOL and ROUTVOL volumes simultaneously. ROUT (Right Headphone Output) Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled ROUT (Right Headphone Output) Volume (See Table 36 for output PGA volume control range) 7 LOPGAZC 0b 6:0 LOPGAVOL [6:0] OPVU[3] 79h (0dB) N/A R33 (21h) 8 7 ROPGAZC 0b 6:0 ROPGAVOL [6:0] OPVU[0] 79h (0dB) N/A R28 (1Ch) 8 7 LOZC 0b 6:0 LOUTVOL [6:0] 00h (mute) R29 (1Dh) 8 OPVU[1] N/A 7 ROZC 0b 6:0 ROUTVOL [6:0] 00h (mute) Table 35 LOPGA, ROPGA, LOUT and ROUT Volume Control w PP, May 2008, Rev 3.1 70 Pre-Production LOPGAVOL, ROPGAVOL, LOUTVOL, ROUTVOL or SPKVOL 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh LOPGAVOL, ROPGAVOL, LOUTVOL, ROUTVOL or SPKVOL 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh WM8991 Volume (dB) MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE -73 -72 -71 -70 -69 -68 -67 -66 -65 -64 -63 -62 -61 -60 -59 -58 Volume (dB) -57 -56 -55 -54 -53 -52 -51 -50 -49 -48 -47 -46 -45 -44 -43 -42 -41 -40 -39 -38 -37 -36 -35 -34 -33 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 Table 36 LOPGA, ROPGA, LOUT, ROUT and SPKVOL Volume Range w PP, May 2008, Rev 3.1 71 WM8991 Pre-Production The speaker mixer SPKMIX, the speaker PGA SPKPGA and the outputs SPKN and SPKP are controlled as described in Table 37. Care should be taken to avoid clipping when enabling more than one path to the speaker mixer. Register bits SPKATTN control the speaker output attenuation and can be used to avoid clipping when more than one full scale signal is input to the mixer. Fine adjustment of the speaker output can be made using the SPKVOL register field. To prevent "zipper noise" when adjusting the SPKVOL, a zero-cross function is provided so that, when enabled, volume updates will not take place until a zero-crossing is detected. In the event of a long period without zero-crossings, a timeout function is available. When this function is enabled (using the TOCLK_ENA register bit), the volume will update after the timeout period if no earlier zerocross has occurred. The timeout period is set by TOCLK_RATE. See "Clocking and Sample Rates" for more information on these fields. REGISTER ADDRESS R54 (36h) BIT 7 LABEL LB2SPK DEFAULT 0b DESCRIPTION AINLMUX Output to SPKMIX 0 = Mute 1 = Un-mute AINRMUX Output to SPKMIX 0 = Mute 1 = Un-mute LIN2 to SPKMIX 0 = Mute 1 = Un-mute RIN2 to SPKMIX 0 = Mute 1 = Un-mute LOPGA to SPKMIX 0 = Mute 1 = Un-mute ROPGA to SPKMIX 0 = Mute 1 = Un-mute Left DAC to SPKMIX 0 = Mute 1 = Un-mute Note: LDSPK must be muted when LDLO=1 Right DAC to SPKMIX 0 = Mute 1 = Un-mute Note: RDSPK must be muted when RDRO=1 Speaker Output Attenuation (SPKN and SPKP) 00 = 0dB 01 = -6dB 10 = -12dB 11 = mute SPKPGA Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled SPKPGA Volume (see Table 36 for SPKPGA volume control range) 6 RB2SPK 0b 5 LI2SPK 0b 4 RI2SPK 0b 3 LOPGASPK 0b 2 ROPGASPK 0b 1 LDSPK 0b 0 RDSPK 0b R34 (22h) 1:0 SPKATTN [1:0] 11b R38 (26h) 7 SPKZC 0b 6:0 SPKVOL [6:0] 79h (0dB) Table 37 Speaker Output Volume Control w PP, May 2008, Rev 3.1 72 Pre-Production WM8991 The output mixers OUT3MIX and OUT4MIX and their outputs OUT3 and OUT4 are controlled as described in Table 38. Care should be taken to avoid clipping when enabling more than one path to OUT3 or OUT4. The OUT3ATTN and OUT4ATTN attenuation controls can be used to prevent clipping when more than one full scale signal is input to the mixers. REGISTER ADDRESS R31 (1Fh) BIT 5 LABEL OUT3MUTE DEFAULT 1b DESCRIPTION OUT3 Mute 0 = Un-mute 1 = Mute OUT3 Attenuation 0 = 0dB 1 = -6dB OUT4 Mute 0 = Un-mute 1 = Mute OUT4 Attenuation 0 = 0dB 1 = -6dB LIN4/RXN Pin to OUT3MIX 0 = Mute 1 = Un-mute LOPGA to OUT3MIX 0 = Mute 1 = Un-mute RIN4/RXP Pin to OUT4MIX 0 = Mute 1 = Un-mute ROPGA to OUT4MIX 0 = Mute 1 = Un-mute 4 OUT3ATTN 0b 1 OUT4MUTE 1b 0 OUT4ATTN 0b R51 (33h) 5 LI4O3 0b 4 LPGAO3 0b 1 RI4O4 0b 0 RPGAO4 0b Table 38 OUT3 and OUT4 Volume Control w PP, May 2008, Rev 3.1 73 WM8991 Pre-Production The output mixers LOPMIX and LONMIX and their outputs LOP and LON are controlled as described in Table 39. Care should be taken to avoid clipping when enabling more than one path to LOP or LON. The LOATTN attenuation control can be used to prevent clipping when more than one full scale signal is input to the LOP mixer. REGISTER ADDRESS R30 (1Eh) BIT 6 LABEL LONMUTE DEFAULT 1b DESCRIPTION LON Line Output Mute 0 = Un-mute 1 = Mute LOP Line Output Mute 0 = Un-mute 1 = Mute LOP Attenuation 0 = 0dB 1 = -6dB LOPGA to LONMIX 0 = Mute 1 = Un-mute ROPGA to LONMIX 0 = Mute 1 = Un-mute Inverted LOP Output to LONMIX 0 = Mute 1 = Un-mute RIN12 PGA Output to LOPMIX 0 = Mute 1 = Un-mute LIN12 PGA Output to LOPMIX 0 = Mute 1 = Un-mute LOPGA to LOPMIX 0 = Mute 1 = Un-mute 5 LOPMUTE 1b 4 LOATTN 0b R52 (34h) 6 LLOPGALON 0b 5 LROPGALON 0b 4 LOPLON 0b 2 LR12LOP 0b 1 LL12LOP 0b 0 LLOPGALOP 0b Table 39 LOP and LON Volume Control w PP, May 2008, Rev 3.1 74 Pre-Production WM8991 The output mixers ROPMIX and RONMIX and their outputs ROP and RON are controlled as described in Table 40. Care should be taken to avoid clipping when enabling more than one path to ROP or RON. The ROATTN attenuation control can be used to prevent clipping when more than one full scale signal is input to the ROP mixer. REGISTER ADDRESS R30 (1Eh) BIT 2 LABEL RONMUTE DEFAULT 1b DESCRIPTION RON Line Output Mute 0 = Un-mute 1 = Mute ROP Line Output Mute 0 = Un-mute 1 = Mute ROP Attenuation 0 = 0dB 1 = -6dB ROPGA to RONMIX 0 = Mute 1 = Un-mute LOPGA to RONMIX 0 = Mute 1 = Un-mute Inverted ROP Output to RONMIX 0 = Mute 1 = Un-mute LIN12 PGA Output to ROPMIX 0 = Mute 1 = Un-mute RIN12 PGA Output to ROPMIX 0 = Mute 1 = Un-mute ROPGA to ROPMIX 0 = Mute 1 = Un-mute 1 ROPMUTE 1b 0 ROATTN 0b R53 (35h) 6 RROPGARON 0b 5 RLOPGARON 0b 4 ROPRON 0b 2 RL12ROP 0b 1 RR12ROP 0b 0 RROPGAROP 0b Table 40 ROP and RON Volume Control w PP, May 2008, Rev 3.1 75 WM8991 ANALOGUE OUTPUTS Pre-Production The speaker, headphone and line outputs are highly configurable and may be used in many different ways. SPEAKER OUTPUT CONFIGURATIONS The speaker outputs SPKP and SPKN are driven by the speaker mixer SPKMIX, and speaker volume control SPKPGA, which can output a mix that is any combination of the following signals: * * * * Left DAC and Right DAC outputs LOMIX and ROMIX outputs via volume controls LOPGA and ROPGA Line inputs LIN2 and RIN2 Output from left and right input mixers (AINLMUX & AINRMUX) The speaker mixer is controlled as described under "Output Signal Path". The speaker mixer output can be attenuated to avoid clipping when mixing multiple signal inputs. Fine adjustment of the speaker output can be made by the speaker volume control SPKPGA. The speaker outputs SPKP and SPKN operate in a BTL configuration in Class AB and Class D amplifier modes. The mode is selected by register bit CDMODE. The outputs are capable of driving 1W into an 8 BTL load (or 500mW in class AB mode for thermal reasons) at room temperature. For performance at higher temperatures, see Figure 2 in the "Recommended Operating Conditions" section. Ultra-low leakage and high PSRR allow the speaker supply SPKVDD to be directly connected to a lithium battery. Six levels of AC and DC signal boost are provided in order to deliver maximum output power for many commonly-used SPKVDD/AVDD combinations. These boost options are available in both Class AB and Class D modes. The AC and DC gain levels from 1.0x to 1.8x are selected using register bits ACGAIN and DCGAIN. To prevent pop noise, DCGAIN and ACGAIN should not be modified while the speaker outputs are enabled. Note that an appropriate SPKVDD supply voltage must be provided to prevent waveform clipping when speaker boost is used. AVDD SPKVDD DCGAIN[2:0] SPKATTN[1:0] SPEAKER MIXER SPKVOL[6:0] ACGAIN[2:0] SPKP SPKN BTL Connection provides an additional 6dB gain AGND DCGAIN[2:0] or ACGAIN[2:0] 000 = 1.00x 001 = 1.27x 010 = 1.40x 011 = 1.52x 100 = 1.67x 101 = 1.80x SPKGND SPKVDD AVDD VMID x DCGAIN VMID AGND Signal x ACGAIN VMID x DCGAIN Figure 31 Speaker Boost Operation w PP, May 2008, Rev 3.1 76 Pre-Production WM8991 REGISTER ADDRESS R35 (23h) BIT 8 LABEL CDMODE DEFAULT 0b DESCRIPTION Speaker Class D Mode Enable 0 = Class D mode 1 = Class AB mode DC Speaker Boost 000 = 1.00x boost (+0dB) 001 = 1.27x boost (+2.1dB) 010 = 1.40x boost (+2.9dB) 011 = 1.52x boost (+3.6dB) 100 = 1.67x boost (+4.5dB) 101 = 1.80x boost (+5.1dB) 110 to 111 = Reserved AC Speaker Boost 000 = 1.00x boost (+0dB) 001 = 1.27x boost (+2.1dB) 010 = 1.40x boost (+2.9dB) 011 = 1.52x boost (+3.6dB) 100 = 1.67x boost (+4.5dB) 101 = 1.80x boost (+5.1dB) 110 to 111 = Reserved R37 (25h) 5:3 DCGAIN [2:0] 000b (1.0x) 2:0 ACGAIN [2:0] 000b (1.0x) Table 41 Speaker Boost Control HEADPHONE OUTPUT CONFIGURATIONS The headphone outputs LOUT, ROUT, OUT3 and OUT4 are each driven by different output mixers as described below. The LOUT and ROUT pins output the LOMIX and ROMIX outputs respectively. The output mixer OUT3MIX produces an output OUT3 that is a combination of: * * LIN4/RXN LOMIX output via volume control LOPGA The output mixer OUT4MIX produces an output OUT4 that is a combination of: * * RIN4/RXP ROMIX output via volume control ROPGA Full volume control is available on LOUT and ROUT. 0dB and -6dB attenuation is available on OUT3 and OUT4, with full volume control available using LOPGA and ROPGA for the LOMIX and ROMIX signals. The outputs LOUT, ROUT, OUT3 and OUT4 are capable of driving 40mW into 16 loads such as stereo headsets, headphones, and/or a handset ear speaker. AC-coupled, capless mode and fully differential headphone drive modes are available. AC-coupled output is possible on each of LOUT, ROUT, OUT3 and OUT4 simultaneously. Capless headphone output is possible on LOUT and ROUT by using either OUT3 or OUT4 as the common return path. (This is achieved by muting OUT3 or OUT4 as required.) If RXP and RXN are a mono differential input (e.g. a connection to an external voice CODEC), then OUT3 and OUT4 may be used as a differential output capable of driving a handset ear speaker. The signal paths from RXP to OUT4 and from RXN to OUT3 are direct, and do not pass through any additional amplifiers. This reduces standby and active power consumption and improves signal quality. w PP, May 2008, Rev 3.1 77 WM8991 Pre-Production When driving a handset ear speaker using OUT3 and OUT4 other than from RXP/RXN, the required phase difference can be provided by inverting one of the DAC outputs or alternatively by mixing Left and Right channels together using either LOMIX or ROMIX and muting the opposite channel. Note that a differential output will provide an additional 6dB gain at the output pins. Register bits OUT3ATTN and OUT4ATTN can be used to compensate for this gain if required. Fully differential headphone drive is possible between LOUT and OUT3 and between ROUT OUT4. Routing LOPGA to OUT3 and ROPGA to OUT4 results in a phase inversion at LOUT respect to OUT3 and at ROUT with respect to OUT4. This allows fully differential headset drive, greatly improved crosstalk performance, improved bass response, increased noise immunity removing the need for large and expensive DC-blocking capacitors. and with with and To ensure fully balanced differential operation, LOUT and OUT3 must be set to the same gain as each other, and ROUT and OUT4 must be set to the same gain as each other. This is best achieved by setting OUT3ATTN and OUT4ATTN to 0dB, whilst setting volume controls LOPGAVOL and LOUTVOL at matching levels and setting volume controls ROPGAVOL and ROUTVOL at matching levels. Some example headphone output configurations are shown below. Figure 32 AC-Coupled Headphone Drive Figure 33 Capless Mode Headphone Drive Figure 34 Headphone and Ear Speaker Drive Figure 35 Fully Differential Headphone Drive w PP, May 2008, Rev 3.1 78 Pre-Production WM8991 LINE OUTPUT CONFIGURATIONS The line outputs LON, LOP, RON and ROP are each driven by different output mixers as described below. The LOP and ROP pins output a mix of LIN12 input PGA, RIN12 input PGA and either LOMIX or ROMIX outputs. The LON output is a mix of ROMIX, LOMIX and a phase-inverted copy of LOP. The RON output is a mix of LOMIX, ROMIX and a phase-inverted copy of ROP. Volume control of LOMIX and ROMIX is available in all cases above via LOPGA and ROPGA. An additional -6dB attenuation option is provided on LOP and ROP outputs. The outputs LON, LOP, RON and ROP are capable of driving line loads only. Single ended output is possible on all these output simultaneously. Differential output is also possible between LOP and LON and between ROP and RON. Typical applications for the line outputs (single-ended or differential) are: * * * Handset or headset microphone output to external voice CODEC Stereo line output Output to external speaker driver(s) to support stereo loudspeakers Some example line output configurations are shown below. Figure 36 Stereo Line Out (A) -1 Figure 37 Differential Output of MIC PGA Figure 38 Stereo Line Out (B) Figure 39 Differential Output to Speaker Driver -1 -1 w PP, May 2008, Rev 3.1 79 WM8991 Pre-Production -1 Figure 40 Stereo Line Out (C) Figure 41 Stereo Differential Line Out w PP, May 2008, Rev 3.1 80 -1 -1 -1 Pre-Production WM8991 DISABLED OUTPUTS Whenever an analogue output is disabled, it can be connected to VREF through a resistor; this feature is enabled by setting the BUFIOEN bit - see "Pop Suppression Control". This helps to prevent pop noise when the output is re-enabled. The resistance between VREF and each output can be controlled using register bit VROI. By default, a high resistance is used - 20k for Headphone outputs (LOUT, ROUT, OUT3 and OUT4) and 10k for Line outputs (LON, LOP, RON and ROP). If a low impedance is desired for disabled outputs, VROI can then be set to 1, decreasing the resistance to about 500 in all cases. Note that a disabled output may be used as a common ground connection for a capless headphone output as described earlier. REGISTER ADDRESS R55 (37h) Additional Control BIT 0 LABEL VROI 0 DEFAULT DESCRIPTION VREF to Analogue Output Resistance (Disabled Outputs) 0 = 20k (Headphone) or 10k (Line Out) from buffered VMID to output 1 = 500 from buffered VMID to output Table 42 Disabled Outputs to VREF Resistance THERMAL SHUTDOWN The speaker and headphone outputs can drive very large currents. To protect the WM8991 from overheating a thermal shutdown circuit is included. If the device temperature reaches approximately 150C and the thermal shutdown circuit is enabled (TSHUT_ENA = 1; TSHUT_OPDIS = 1) the speaker and headphone amplifiers (LOUT, ROUT, SPKP, SPKN, OUT3 and OUT4) will be disabled. TSHUT_ENA must be set to 1 to enable the temperature sensor when using the TSHUT_OPDIS thermal shutdown function. The output of the temperature sensor can also be output to the GPIO pins. REGISTER ADDRESS R2 (02h) BIT 14 LABEL TSHUT_ENA (rw) TSHUT_OPDIS (rw) DEFAULT 1b DESCRIPTION Thermal Sensor Enable 0 = Thermal sensor disabled 1 = Thermal sensor enabled Thermal Shutdown Enable (Requires thermal sensor to be enabled) 0 = Thermal shutdown disabled 1 = Thermal shutdown enabled 13 1b Table 43 Thermal Shutdown When the speaker driver is operating in class AB mode the internal power dissipation of the WM8991 is likely to be significantly higher than when operating in class D mode. Note: To prevent potential pops and clicks THSUT_ENA and TSHUT_OPDIS need to be configured while the speaker and headphone outputs are off, i.e. LOUT_ENA, ROUT_ENA, OUT3_ENA, OUT4_ENA and SPK_ENA are 0 (see also Table 79). w PP, May 2008, Rev 3.1 81 WM8991 GENERAL PURPOSE INPUT/OUTPUT Pre-Production The WM8991 provides a number of versatile GPIO functions to enable features such as mobile TV support, Wi-Fi voice call recording, button and accessory detection and clock output. The WM8991 has eight multi-purpose pins for these functions. * * GPIO1 to GPIO6: Dedicated GPIO pins. LIN3/GPI7 and RIN3/GPI8: Analogue inputs or button/accessory detect inputs. The following functions are available on some or all of the GPIO pins. * * * * * * * * * * * Alternative DAC interface (DACDAT, DACLRC, BCLK) Button detect (latched with programmable de-bounce) MICBIAS / Accessory current or short circuit detect Alternative MCLK input Clock output Inverted ADCLRC output Temperature sensor output PLL lock output Logic '1' and logic '0' output Interrupt event output Serial data output (register readback) The functions available on each of the GPIO pins are identified in Table 44. GPIO Pin Function ADCLRC MCLK2 BCLK2 DACLRC2 DACDAT2 ADCLRCB Button/Accessory Detect Input Clock Output Temperature OK PLL Lock Logic 1 and Logic 0 Interrupt SDOUT (Readback Data) Pull-up & Pull-down Available GPIO PINS GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y GPI7 GPI8 Y Y Table 44 Functions Available on GPIO Pins The GPIO pins are configured by a combination of register settings described in Table 45 to Table 48 in the following section. The order of precedence for the control of the GPIO pins is as listed below. 1. Pin pull-up or pull-down (GPIOn_PU, GPIOn_PD) 2. Audio Interface and GPIO Tristate (AIF_TRIS) 3. Pin configuration (AIFSEL, MCLK_SRC, ALRCGPIO1, and ALRCBGPIO6) 4. GPIO functionality (GPIOn_SEL) w PP, May 2008, Rev 3.1 82 Pre-Production WM8991 GPIO CONTROL REGISTERS Table 45 shows how the dual-function GPIO pins are configured to operate in their different modes. Note that the order of precedence described earlier applies. Register field AIF_SEL selects the function of GPIO3, GPIO4 and GPIO5 between Audio Interface 2 and GPIO functions. Register field ALRCGPIO1 enables the GPIO functionality on GPIO1. Register field MCLK_SRC enables the GPIO functionality on GPIO2. Register field ALRCGPIO6 enables the inverted ADCLRC output on GPIO6. Register bit AIF_TRIS, when set, takes precedence over AIF_SEL, ALRCGPIO1, MCLK_SRC and ALRCBGPIO6 and tri-states all GPIO pins. REGISTER ADDRESS R7 (07h) BIT 15 LABEL MCLK_SRC DEFAULT 0b DESCRIPTION MCLK Source Select 0 = MCLK pin 1 = GPIO2/MCLK2 pin Audio Interface Select 0 = Audio interface 1 1 = Audio interface 2 (GPIO3/BCLK2, GPIO4/DACLRC2, GPIO5/DACDAT2) ADCLRC/GPIO1 Pin Function Select 0 = ADCLRC 1 = GPIO1 (ADCLRC connected to DACLRC internally) GPIO6/ADCLRCB Pin Function Select 0 = GPIO6 1 = Inverted ADCLRC clock output Audio Interface and GPIO Tristate 0 = Audio interface and GPIO pins operate normally 1 = Tristate all audio interface and GPIO pins R8 (08h) 13 AIF_SEL 0b R9 (09h) 15 ALRCGPIO1 0b 14 ALRCBGPIO6 0b 13 AIF_TRIS 0b Table 45 GPIO and GPI Pin Function Select The GPIO pins are also controlled by the register fields described in Table 46. Note the order of precedence described earlier applies. Pull-up and pull-down resistors may be enabled on any of GPIO1 to GPIO6. If enabled, these settings take precedence over all other GPIO selections for that pin. Note that, by default, the pulldown resistors on GPIO2, GPIO3, GPIO4, GPIO5 and GPIO6 are enabled. When the GPIO pins are used as inputs, de-bounce and interrupt masking may be controlled on all GPIO pins (including GPI7 and GPI8) using GPIOn_DEB_ENA and GPIOn_IRQ_ENA bits as shown in Table 47. For each of GPIO1 to GPIO6, the register field GPIOn_SEL is used to select the pin functions of the individual GPIO pins as shown in Table 47. Note that this control has the lowest precedence and is only effective when GPIOn_PU, GPIOn_PD, AIF_TRIS, AIFSEL, MCLK_SRC, ALRCGPIO1 and ALRCBGPIO6 are set to allow GPIO functionality on that GPIO pin. w PP, May 2008, Rev 3.1 83 WM8991 REGISTER ADDRESS R19 (13h) BIT 15 14 13 12 11:8 7 6 5 4 3:0 R20 (14h) 15 14 13 12 11:8 7 6 5 4 3:0 R21 (15h) 15 14 13 12 11:8 7 6 5 4 3:0 R22 (16h) 7 6 4 3 2 0 LABEL GPIO2_DEB_ENA GPIO2_IRQ_ENA GPIO2_PU GPIO2_PD GPIO2_SEL[3:0] GPIO1_DEB_ENA GPIO1_IRQ_ENA GPIO1_PU GPIO1_PD GPIO1_SEL[3:0] GPIO4_DEB_ENA GPIO4_IRQ_ENA GPIO4_PU GPIO4_PD GPIO4_SEL[3:0] GPIO3_DEB_ENA GPIO3_IRQ_ENA GPIO3_PU GPIO3_PD GPIO3_SEL[3:0] GPIO6_DEB_ENA GPIO6_IRQ_ENA GPIO6_PU GPIO6_PD GPIO6_SEL[3:0] GPIO5_DEB_ENA GPIO5_IRQ_ENA GPIO5_PU GPIO5_PD GPIO5_SEL[3:0] GPI8_DEB_ENA GPI8_IRQ_ENA GPI8_ENA GPI7_DEB_ENA GPI7_IRQ_ENA GPI7_ENA DEFAULT 0b 0b 0b 1b 0000b 0b 0b 0b 0b 0000b 0b 0b 0b 1b 0000b 0b 0b 0b 1b 0000b 0b 0b 0b 1b 0000b 0b 0b 0b 1b 0000b 0b 0b 0b 0b 0b 0b Pre-Production DESCRIPTION See Table 47 for GPIO2 control bit description See Table 47 for GPIO1 control bit description See Table 47 for GPIO4 control bit description See Table 47 for GPIO3 control bit description See Table 47 for GPIO6 control bit description See Table 47 for GPIO5 control bit description See Table 47 for GPIn control bit description See Table 47 for GPIn control bit description Table 46 GPIO and GPI Control w PP, May 2008, Rev 3.1 84 Pre-Production The following table describes the coding of the fields listed in Table 46. REGISTER ADDRESS Registers R19 (13h) to R21 (15h) (See Table 46) LABEL GPIOn_DEB_ENA (n = 1 to 8) DEFAULT 0b DESCRIPTION WM8991 De-Bounce 0 = disabled (Not de-bounced) 1 = enabled (Requires MCLK input and TOCLK_ENA = 1) IRQ Enable 0 = disabled 1 = enabled GPIO Pull-Up Resistor Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 150k) GPIO Pull-Down Resistor Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 150k) GPIOn Pin Function Select 0000 = Input pin 0001 = Clock output (SYSCLK/OPCLKDIV) 0010 = Logic '0' 0011 = Logic '1' 0100 = PLL Lock output 0101 = Temperature OK output 0110 = SDOUT data output 0111 = IRQ output 1000 = MIC Detect 1001 = MIC Short Circuit Detect 1010 to 1111 = Reserved GPIn Input Pin Enable 0 = pin disabled as GPIn input 1 = pin enabled as GPIn input GPIOn_IRQ_ENA (n = 1 to 8) GPIOn_PU (n = 1 to 6) GPIOn_PD (n = 1 to 6) GPIOn_SEL[3:0] (n = 1 to 6) 0b 0b See Table 46 0000b GPIn_ENA (n = 7 or 8) Table 47 GPIO Function Control Bits 0b The polarity of GPIO/GPI inputs may be configured using the GPIO_POL register bits. This is described in Table 48. REGISTER ADDRESS R23 (17h) BIT 7:0 LABEL GPIO_POL [7:0] (rw) DEFAULT 00h DESCRIPTION GPIOn Input Polarity 0 = Non-inverted 1 = Inverted GPIO_POL[7] = GPI8 polarity GPIO_POL[6] = GPI7 polarity GPIO_POL[5] = GPIO6 polarity GPIO_POL[4] = GPIO5 polarity GPIO_POL[3] = GPIO4 polarity GPIO_POL[2] = GPIO3 polarity GPIO_POL[1] = GPIO2 polarity GPIO_POL[0] = GPIO1 polarity Table 48 GPIO Polarity Each of the available GPIO functions is described in turn in the following sections. w PP, May 2008, Rev 3.1 85 WM8991 ALTERNATIVE DAC INTERFACE Pre-Production The WM8991 may be configured to select between two different audio interfaces, providing the capability to receive DAC input data via BCLK2, DACLRC2 and DACDAT2 instead of BCLK, DACLRC and DACDAT. This selection is made by register bit AIF_SEL, as described in Table 45. To use the alternative DAC interface, the following register settings are required: * * * * AIF_TRIS = 0 AIF_SEL = 1 GPIO3_PU = 0, GPIO4_PU = 0, GPIO5_PU = 0 GPIO3_PD = 0, GPIO4_PD = 0, GPIO5_PD = 0 Note that additional devices can also be connected to the main interface pins using the TDM mode. See "Digital Audio Interface" section for further details on controlling the audio interface pins. The alternative DAC interface connection is illustrated in Figure 42. DIGITAL AUDIO INTERFACE A-law and u-law support TDM Support GPIO Alternative DAC Interface Alternative MCLK Button Control / Accessory Detect Clock Output Inverted ADCLRC AIF_SEL Processor #1 Figure 42 Alternative DAC Interface Processor #2 w GPIO2/MCLK2 GPIO3/BCLK2 GPIO4/DACLRC2 GPIO5/DACDAT2 GPIO6/ADCLRCB PP, May 2008, Rev 3.1 86 BCLK DACDAT ADCDAT DACLRC ADCLRC/GPIO1 Pre-Production WM8991 BUTTON CONTROL The WM8991 GPIO supports button control detection with full status readback for up to seven inputs (and one IRQ output). All inputs are latched at the IRQ Register, with de-bounce available for normal operation. De-bouncing may be disabled in order to allow the device to respond to wake-up events while the processor is disabled and is unable to provide a clock for de-bouncing. To enable button control and accessory detection, the following register settings are required: * * * * * * * * ALRCGPIO1 = 1 (only required if using GPIO1) MCLK_SRC = 0 (only required if using GPIO2) AIF_SEL = 0 (only required if using GPIO3, GPIO4 or GPIO5) ALRCGPIO6 = 0 (only required if using GPIO6) LMN3 = 0, LLI3LO = 0 and RLI3LO = 0 (only required if using GPI7) RMN3 = 0, RRI3LO = 0 and LRI3RO = 0 (only required if using GPI8) AIF_TRIS = 0 GPIOn_SEL = 0000 for each required GPIO button input Programmable pull-up and pull-down resistors are available on GPIO1 to GPIO6. These should be set according to the external circuit configuration. Note that pull-up and pull-down resistors are not available on the GPI7 and GPI8 input pins. Note that the analogue input paths to GPI7 and GPI8 must be disabled as described above when using these as digital inputs. In this application, one or more of the GPIO pins may be configured as an Interrupt event if desired. This is controlled by the GPIOn_IRQ_ENA bits described in Table 46. The GPIO Pin status fields contained in the IRQ Register (R18) may be read at any time or else in response to an Interrupt event. See Table 55 for more details of the Interrupt function. An example configuration of the button control GPIO function is illustrated in Figure 43. Figure 43 Example of Button Control Using GPIO Pins Note: * * The GPIOs 1 to 6 are referenced to DBVDD The GPIs 7 and 8 are referenced to AVDD w PP, May 2008, Rev 3.1 87 WM8991 MICBIAS CURRENT AND ACCESSORY DETECT Pre-Production A MICBIAS current detect function is provided for accessory detection. When a microphone current is detected (e.g. when a headset is inserted), an interrupt event can be generated and the microphone status read back via the control interface. The MICBIAS current detect threshold is programmable. A short-circuit current detection is also available, with a programmable threshold. These functions are enabled by register bit MCD; the thresholds are programmable via register fields MCDTHR and MCDSCTR as shown in Table 49. The polarity of the current detect GPIO signals may be controlled by register bits MICDET_POL and MICSHRT_POL. Note that these polarity inversion bits apply to the Interrupt register behaviour only; they do not affect the direct GPIO output of the Current Detect functions. The respective interrupt events may be masked or enabled by register bits MICDET_IRQ_ENA and MICSHRT_IRQ_ENA. The MICBIAS current threshold status bits contained in the IRQ Register (R18) may be read at any time or else in response to an Interrupt event. See Table 55 for more details of the Interrupt function. If direct output of the MICBIAS current detect function is required to the external pins of the WM8991, the following register settings are required: * * * * * * * * * ALRCGPIO1 = 1 (only required if using GPIO1) MCLK_SRC = 0 (only required if using GPIO2) AIF_SEL = 0 (only required if using GPIO3, GPIO4 or GPIO5) ALRCGPIO6 = 0 (only required if using GPIO6) AIF_TRIS = 0 GPIOn_SEL = 1000 for the selected GPIO MICBIAS Current Detect output pin GPIOn_SEL = 1001 for the selected GPIO MICBIAS Short Circuit Detect output pin GPIOn_PU = 0 for the selected GPIO MICBIAS output pin or pins GPIOn_PD = 0 for the selected GPIO MICBIAS output pin or pins w PP, May 2008, Rev 3.1 88 Pre-Production WM8991 The register fields used to configure the MICBIAS Current Detect function are described in Table 49. REGISTER ADDRESS R58 (3Ah) BIT 7:6 LABEL MCDSCTH [1:0] DEFAULT 00b DESCRIPTION MICBIAS Short Circuit Detect Threshold 00 = 600uA 01 = 1200uA 10 = 1800uA 11 = 2400uA These values are for AVDD=3.3V and scale proportionally with AVDD. MICBIAS Current Detect Threshold 000 = 200uA 001 = 350uA 010 = 500uA 011 = 650uA 100 = 800uA 101 = 950uA 110 = 1100uA 111 = 1250uA These values are for AVDD=3.3V and scale proportionally with AVDD. MICBIAS Current and Short Circuit Detect Enable 0 = disabled 1 = enabled MICBIAS short circuit detect polarity 0 = Non-inverted 1 = Inverted MICBIAS current detect polarity 0 = Non-inverted 1 = Inverted MICBIAS short circuit detect IRQ Enable 0 = disabled 1 = enabled MICBIAS current detect IRQ Enable 0 = disabled 1 = enabled 5:3 MCDTHR [2:0] 000b 2 MCD 0b R23 (17h) 10 MICSHRT_POL (rw) MICDET_POL (rw) MICSHRT_IRQ_ENA 0b 9 0b R22 (16h) 10 0b 9 MICDET_IRQ_ENA 0b Table 49 MICBIAS Current Detect Control The current detect function operates according to the following the truth table: LABEL Mic Short Circuit Detect Mic Short Circuit Detect Mic Current Detect Mic Current Detect VALUE 0 1 0 1 DESCRIPTION MCDSCTH current threshold not exceeded MCDSCTH current threshold exceeded MCDTHR current threshold not exceeded MCDTHR current threshold exceeded Table 50 Truth Table for GPIO Output of MICBIAS Current Detect Function w PP, May 2008, Rev 3.1 89 WM8991 ALTERNATIVE MCLK INPUT Pre-Production An alternative MCLK source can be input via the MCLK2/GPIO2 pin. This provides additional flexibility for systems where the CODEC is required to interface with more than one processor. See "Clocking and Sample Rates" for more information on selecting MCLK source. To enable the alternative MCLK input on GPIO2, the following register settings are required: * * * * * MCLK_SRC = 1 AIF_TRIS = 0 GPIO2_PU = 0 GPIO2_PD = 0 GPIO2_SEL = 0000 The above register fields are described in Table 45 and Table 46. CLOCK OUTPUT A clock output (OPCLK) derived from SYSCLK may be output via GPIO1 to GPIO6. SYSCLK is derived from MCLK (either directly, or in conjunction with the PLL), and is used to provide all internal clocking for the WM8991 (see "Clocking and Sample Rates" section for more information). A programmable clock divider OPCLKDIV controls the frequency of the OPCLK output. This clock is enabled by register bit OPCLK_ENA. See "Clocking and Sample Rates" for a definition of this register field. To enable clock output via one or more GPIO pins, the following register settings are required: * * * * * * * * ALRCGPIO1 = 1 (only required if using GPIO1) MCLK_SRC = 0 (only required if using GPIO2) AIF_SEL = 0 (only required if using GPIO3, GPIO4 or GPIO5) ALRCGPIO6 = 0 (only required if using GPIO6) AIF_TRIS = 0 GPIOn_SEL = 0001 for the selected GPIO clock output pin GPIOn_PU = 0 for the selected GPIO clock output pin GPIOn_PD = 0 for the selected GPIO clock output pin INVERTED ADCLRC OUTPUT An inverted ADCLRC signal can be output via the GPIO6/ADCLRCB pin. To enable the Inverted ADCLRC output, the following register settings are required: * * * * ALRCGPIO6 = 1 AIF_TRIS = 0 GPIO6_PU = 0 GPIO6_PD = 0 w PP, May 2008, Rev 3.1 90 Pre-Production WM8991 TEMPERATURE SENSOR OUTPUT The WM8991 output drivers can generate a large amount of heat. To protect the device from overheating a thermal shutdown function is provided (see "Thermal Shutdown" section for more information). The polarity of the Thermal Shutdown sensor may be controlled by register bit TEMPOK_POL. Note that this polarity inversion bit applies to the Interrupt register behaviour only; it does not affect the direct GPIO output of the Temperature Sensor function. The associated interrupt event may be masked or enabled by register bit TEMPOK_IRQ_ENA. The Temperature status bit contained in the IRQ Register (R18) may be read at any time or else in response to an Interrupt event. See Table 55 for more details of the Interrupt function. If direct output of the Temperature status bit is required to the external pins of the WM8991, the following register settings are required: * * * * * * * * ALRCGPIO1 = 1 (only required if using GPIO1) MCLK_SRC = 0 (only required if using GPIO2) AIF_SEL = 0 (only required if using GPIO3, GPIO4 or GPIO5) ALRCGPIO6 = 0 (only required if using GPIO6) AIF_TRIS = 0 GPIOn_SEL = 0101 for the selected GPIO Temperature status output pin GPIOn_PU = 0 for the selected GPIO Temperature status output pin GPIOn_PD = 0 for the selected GPIO Temperature status output pin The register fields used to configure the Temperature Sensor GPIO function are described in Table 51. REGISTER ADDRESS R23 (17h) BIT 11 LABEL TEMPOK_POL (rw) TEMPOK_IRQ_ ENA DEFAULT 1b DESCRIPTION Temperature Sensor polarity 0 = Non-inverted 1 = Inverted Temperature Sensor IRQ Enable 0 = disabled 1 = enabled R22 (16h) 11 0b Table 51 Temperature Sensor GPIO Control The temperature sensor function operates according to the following truth table: LABEL Temperature Sensor output Temperature Sensor output VALUE 0 1 DESCRIPTION Overheat temperature exceeded Overheat temperature not exceeded Table 52 Truth table for GPIO Output of Temperature Sensor Function w PP, May 2008, Rev 3.1 91 WM8991 PLL LOCK OUTPUT Pre-Production An internal signal used to indicate the lock status of the PLL can be output to a GPIO pin or used to trigger an Interrupt event. The polarity of the PLL Lock indication may be controlled by register bit PLL_LCK_POL. Note that this polarity inversion bit applies to the Interrupt register behaviour only; it does not affect the direct GPIO output of the PLL Lock function. The associated interrupt event may be masked or enabled by register bit PLL_LCK_IRQ_ENA. The PLL Lock status bit in the IRQ Register (R18) may be read at any time or else in response to an Interrupt event. See Table 55 for more details of the Interrupt function. If direct output of the PLL Lock status bit is required to the external pins of the WM8991, the following register settings are required: * * * * * * * * ALRCGPIO1 = 1 (only required if using GPIO1) MCLK_SRC = 0 (only required if using GPIO2) AIF_SEL = 0 (only required if using GPIO3, GPIO4 or GPIO5) ALRCGPIO6 = 0 (only required if using GPIO6) AIF_TRIS = 0 GPIOn_SEL = 0100 for the selected PLL Lock status output pin GPIOn_PU = 0 for the selected PLL Lock status output pin GPIOn_PD = 0 for the selected PLL Lock status output pin The register fields used to configure the PLL Lock GPIO function are described in Table 53. REGISTER ADDRESS R23 (17h) BIT 8 LABEL PLL_LCK_POL (rw) PLL_LCK_IRQ_ ENA DEFAULT 0b DESCRIPTION PLL Lock polarity 0 = Non-inverted 1 = Inverted PLL Lock IRQ Enable 0 = disabled 1 = enabled R22 (16h) 8 0b Table 53 PLL Lock GPIO Control The PLL Lock function operates according to the following truth table: LABEL PLL Lock output PLL Lock output VALUE 0 1 PLL Locked DESCRIPTION PLL not Locked Table 54 Truth Table for GPIO Output of PLL Lock Function w PP, May 2008, Rev 3.1 92 Pre-Production WM8991 LOGIC '1' AND LOGIC '0' OUTPUT The GPIO pins can be programmed to drive a logic high or logic low signal. The following register settings are required: * * * * * * * * * ALRCGPIO1 = 1 (only required if using GPIO1) MCLK_SRC = 0 (only required if using GPIO2) AIF_SEL = 0 (only required if using GPIO3, GPIO4 or GPIO5) ALRCGPIO6 = 0 (only required if using GPIO6) AIF_TRIS = 0 GPIOn_SEL = 0010 for each Logic `0' output pin GPIOn_SEL = 0011 for each Logic `1' output pin GPIOn_PU = 0 for each Logic `0' or Logic `1' GPIO pin GPIOn_PD = 0 for each Logic `0' or Logic `1' GPIO pin w PP, May 2008, Rev 3.1 93 WM8991 INTERRUPT EVENT OUTPUT An interrupt can be generated by any of the following events described earlier: * * * * Button Control input (on GPIO1 to GPIO6, GPI7 and GPI8) MICBIAS current / short circuit / accessory detect PLL Lock Temperature Sensor Pre-Production The interrupt status flag IRQ is asserted when any un-masked Interrupt input is asserted. It is the OR'd combination of all the un-masked Interrupt inputs. If required, this flag may be inverted using the IRQ_INV register bit. The GPIO pins can be configured to output the IRQ signal. The interrupt behaviour is driven by level detection (not edge detection) of the un-masked inputs. Therefore, if an input remains asserted after the interrupt register has been reset, then the interrupt status flag IRQ will be triggered again even though no transition has occurred. If edge detection is required (eg. confirming that the input has been de-asserted), then the polarity inversion may be used after each event in order to detect each rising and falling edge separately. This is described further in the "GPIO Summary" section. The status of the IRQ flag may be read back via the control interface. The status of each GPIO pin and the internal signals PLL_LCK, TEMPOK, MICSHRT and MICDET may also be read back in the same way. The IRQ register (R18) is described in Table 55. The status of the GPIO pins or other Interrupt inputs can be read back via the read/write bits R18[11:0]. The Interrupt inputs are latched once set. Each input may be reset by writing a 1 to the appropriate bit. The IRQ bit cannot be reset; it is the OR'd combination of all other registers and will reset only if R18[11:0] are all 0. If direct output of the Interrupt signal is required to external pins of the WM8991, the following register settings are required: * * * * * * * * ALRCGPIO1 = 1 (only required if using GPIO1) MCLK_SRC = 0 (only required if using GPIO2) AIF_SEL = 0 (only required if using GPIO3, GPIO4 or GPIO5) ALRCGPIO6 = 0 (only required if using GPIO6) AIF_TRIS = 0 GPIOn_SEL = 0111 for the selected Interrupt (IRQ) output pin GPIOn_PU = 0 for the selected Interrupt (IRQ) output pin GPIOn_PD = 0 for the selected Interrupt (IRQ) output pin w PP, May 2008, Rev 3.1 94 Pre-Production The IRQ register (R18) is described in Table 55. REGISTER ADDRESS R18 (12h) BIT 12 11 IRQ (ro) TEMPOK (rr) LABEL DEFAULT Read Only Read or Reset DESCRIPTION WM8991 IRQ Readback (Allows polling of IRQ status) Temperature OK status Read0 = Device temperature NOT ok 1 = Device temperature ok Write 1 = Reset TEMPOK latch MICBIAS short status Read0 = MICBIAS ok 1 = MICBIAS shorted Write1 = Reset MICSHRT latch MICBIAS detect status MICBIAS microphone detect Readback Read0 = No Microphone detected 1 = Microphone detected Write1 = Reset MICDET latch PLL Lock status Read0 = PLL NOT locked 1 = PLL locked Write1 = Reset PLL_LCK latch GPIO and GPI Input Pin Status GPIO_STATUS[7] = GPI8 pin status GPIO_STATUS[6] = GPI7 pin status GPIO_STATUS[5] = GPIO6 status GPIO_STATUS[4] = GPIO5 status GPIO_STATUS[3] = GPIO4 status GPIO_STATUS[2] = GPIO3 status GPIO_STATUS[1] = GPIO2 status GPIO_STATUS[0] = GPIO1 status IRQ Invert 0 = IRQ output active high 1 = IRQ output active low 10 MICSHRT (rr) Read or Reset 9 MICDET (rr) Read or Reset 8 PLL_LCK (rr) Read or Reset 7:0 GPIO_STATUS [7:0] (rr) Read or Reset R23 (17h) GPIO Control (2) 12 IRQ_INV (rw) 0b Table 55 GPIO Interrupt and Status Readback w PP, May 2008, Rev 3.1 95 WM8991 SERIAL DATA OUTPUT (REGISTER READBACK) Pre-Production The GPIO pins can be configured to output serial data during register readback in 3-wire (open-drain) or 4-wire mode. The readback mode is configured using the register bits RD_3W_ENA and MODE_3W4W as described in Table 56. Setting the RD_3W_ENA bit to 1 enables 3-wire readback using the SDIN pin in open-drain mode. Setting the RD_3W_ENA bit to 0 requires the use of a GPIO pin as SDOUT. To enable SDOUT on a GPIO pin, the following register settings are required: * * * * * * * * ALRCGPIO1 = 1 (only required if using GPIO1) MCLK_SRC = 0 (only required if using GPIO2) AIF_SEL = 0 (only required if using GPIO3, GPIO4 or GPIO5) ALRCGPIO6 = 0 (only required if using GPIO6) AIF_TRIS = 0 GPIOn_SEL = 0110 for the selected SDOUT output pin GPIOn_PU = 0 for the selected SDOUT output pin GPIOn_PD = 0 for the selected SDOUT output pin The register fields used to configure SDOUT on the GPIO pins are described in Table 56. Refer to "Control Interface" for more details of 3-wire and 4-wire interfacing. REGISTER ADDRESS R22 (16h) BIT 15 LABEL RD_3W_ENA DEFAULT 1b DESCRIPTION 3- / 4-wire readback configuration 1 = 3-wire mode 0 = 4-wire mode, using GPIO pin 3-wire mode 0 = push 0/1 1 = open-drain 4-wire mode 0 = push 0/1 1 = wired-OR 14 MODE_3W4W 0b Table 56 GPIO 3-Wire Readback Enable w PP, May 2008, Rev 3.1 96 Pre-Production WM8991 GPIO SUMMARY The GPIO functions are summarised in Figure 44. Figure 44 GPIO Control Diagram w PP, May 2008, Rev 3.1 97 WM8991 Pre-Production Details of the GPIO implementation are shown below. In order to avoid GPIO loops if a GPIO is configured as an output the corresponding input is disabled, as shown in Figure 45 below. Figure 45 GPIO Pad The GPIO register, i.e. latch structure, is shown in Figure 46 below. The de-bounce Control fields GPIOn_DEB_ENA determine whether the signal is de-bounced or not. (Note that TOCLK (via SYSCLK) needs to be present in order for the debounce circuit to work.) The polarity bits GPIO_POL[7:0] control whether an interrupt is triggered by a logic 1 level (for GPIO_POL[n] = 0) or a logic 0 level (for GPIO_POL[n] = 1). The latch will cause the interrupt to be stored until it is reset by writing to the Interrupt Register. The latched signal is processed by the IRQ circuit, shown in Figure 44 above. The interrupt status bits can be read at any time from Register R18 (see Table 55) and are reset by writing a "1" to the applicable bit in Register R18. Note that the interrupt behaviour is driven by level detection (not edge detection). Therefore, if an input remains asserted after the interrupt register has been reset, then the interrupt event will be triggered again even though no transition has occurred. If edge detection is required, this may be implemented as described in the following paragraphs. Figure 46 GPIO Function Three typical scenarios are presented in the following Figure 47, Figure 48 and Figure 49. The examples are: * * * Latch a GPIO input (Figure 47) Debounce and latch a GPIO input (Figure 48) Use the GPIOn_POL bit to implement an IRQ edge detect function (Figure 49) w PP, May 2008, Rev 3.1 98 Pre-Production WM8991 The GPIO input or internal Interrupt event (eg. MICBIAS current detect) is latched as illustrated below: Figure 47 GPIO Latch The de-bounce function on the GPIO input pins enables transient behaviour to be filtered as illustrated below: Figure 48 GPIO De-bounce To implement an edge detect function on a GPIO input, the GPIOn_POL bits may be used to alternate the GPIO polarity after each edge transition. For example, after a logic 1 has caused an Interrupt event, the polarity may be inverted prior to resetting the Interrupt register bit. In this way, the next interrupt event generated by this GPIO will occur when it returns to the logic 0 state. The GPIOn_POL bit must be reversed after every GPIO edge transition, as illustrated below: Figure 49 GPIO Edge Detect w PP, May 2008, Rev 3.1 99 WM8991 GPIO IRQ HANDLING In the following diagram Figure 50 a typical IRQ scenario is illustrated. Pre-Production Figure 50 GPIO IRQ Handling w PP, May 2008, Rev 3.1 100 Pre-Production WM8991 DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting DAC data to the WM8991 and outputting ADC data from it. It uses five pins: * * * * * ADCDAT: ADC data output ADCLRC: ADC data alignment clock (An inverted ADCLRC is also available via GPIO) DACDAT: DAC data input (An alternative DACDAT is also available via GPIO) DACLRC: DAC data alignment clock (An alternative DACLRC is also available via GPIO) BCLK: Bit clock, for synchronisation (An alternative BCLK is also available via GPIO) The clock signals BCLK, ADCLRC and DACLRC can be outputs when the WM8991 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). ADCLRC can also be configured as a GPIO pin. In this case, the ADC will use DACLRC as a frame clock. The ADCLRC/GPIO1 pin function should not be modified while the ADC is enabled. DACDAT, DACLRC and BCLK functions can also be supported using GPIO pins. An inverted ADCLRC can also be output via GPIO pins. Four different audio data formats are supported: * * * * Left justified Right justified I 2S DSP mode All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the "Electrical Characteristics" section for timing information. Time Division Multiplexing (TDM) is available in all four data format modes. The WM8991 can be programmed to send and receive data in one of two time slots. PCM operation is supported using the DSP mode. MASTER AND SLAVE MODE OPERATION The WM8991 digital audio interface can operate as a master or slave as shown in Figure 51 and Figure 52. Figure 51 Master Mode Figure 52 Slave Mode OPERATION WITH ADCLRC AS GPIO When the ADCLRC/GPIO1 pin is configured as a GPIO pin (ALRCGPIO=1), the DACLRC pin is used as a frame clock for ADCs and DACs as shown in Figure 53 and Figure 54. The ADCs and DACs must operate at the same sample rate in this configuration. w PP, May 2008, Rev 3.1 101 WM8991 Pre-Production Figure 53 Master Mode with ADCLRC as GPIO Figure 54 Slave Mode with ADCLRC as GPIO OPERATION WITH ALTERNATIVE DAC INTERFACE To allow data to be input to the WM8991 DACs from two separate sources, the GPIO[5:3] pins can be configured as an alternative DAC interface (BCLK2, DACLRC2, DACDAT2) as shown in Figure 57 to Figure 60. Figure 55 Interface 2 = Master Figure 56 Interface 2 = Slave BCLK AIF_MSTR1=1 AIF_MSTR2=0 ADCLRC DACLRC ADCDAT DACDAT WM8991 Processor #1 BCLK2 DACLRC2 /N DACDAT2 Processor #2 /N Figure 57 Interface 1 = Master, Interface 2 = Master Figure 58 Interface 1 = Master, Interface 2 = Slave w PP, May 2008, Rev 3.1 102 Pre-Production WM8991 Figure 59 Interface 1 = Slave, Interface 2 = Master Figure 60 Interface 1 = Slave, Interface 2 = Slave The dual Audio Interface approach of the WM8991 has been implemented in such a way that it gives the user and application as much flexibility as possible, without any restrictions built into the WM8991. This means that the application has to be carefully analysed and the WM8991 configured accordingly. In the following Figure 61 and Figure 62 the Audio Interface input flow and the output controlling are illustrated. w PP, May 2008, Rev 3.1 103 WM8991 Pre-Production BCLK ALRCGPIO1 0 ADCLRC 1 ADC_BCLK ADC_LRCLK ADCDAT AIF_SEL 0 ADC_DATA DACLRC 1 Audio Interface DACDAT 0 1 DAC_BCLK DAC_LRCLK DAC_DATA BCLK2 DACLRC2 0 DACDAT2 1 Figure 61 Audio Interface Input Flow The Audio Interface input flow illustrated above is controlled by only two signals. These are ALRCGPIO1 and AIF_SEL. REGISTER ADDRESS R8 (08h) BIT 13 LABEL AIF_SEL DEFAULT 0b DESCRIPTION Audio Interface Select 0 = Audio interface 1 1 = Audio interface 2 (GPIO3/BCLK2, GPIO4/DACLRC2, GPIO5/DACDAT2) ADCLRC/GPIO1 Pin Function Select 0 = ADCLRC pin 1 = GPIO1 pin (ADCLRC connected to DACLRC internally) R9 (09h) 15 ALRCGPIO1 0b Table 57 Audio Interface Pin Function Select w PP, May 2008, Rev 3.1 104 Pre-Production SYSCLK enable WM8991 AIF_SEL & !(ADCENL+ADCENR) 0 0 AIF_MSTR1 1 BCLK Generator BCLK AIF_MSTR1 ADCLRC_DIR ADCLRC >1 0 1 ALRCGPIO1 enable DACENL+DACENR AIF_SEL & !(ALRCGPIO1 & (ADCENL+ADCENR)) 0 0 1 0 1 ADCDAT ADCLRC Generator AIF_MSTR1 DACLRC_DIR DACLRC >1 DACDAT enable 0 AIF_SEL 0 1 AIF_MSTR2 AIF_SEL BCLK2 DACLRC Generator 0 0 1 DACLRC2 AIF_MSTR2 DACLRC_DIR AIF_SEL >1 DACDAT2 & Figure 62 Audio Interface Output Control The Audio Interface output control is illustrated above. The master mode control registers AIF_MSTR1 and AIF_MSTR2 as well as the left-right clock control registers ADCLRC_DIR and DACLRC_DIR determine whether the WM8991 generates the according clocks and AIF_SEL and ALRCGPIO1 control registers define the pins these clocks are provided from. w PP, May 2008, Rev 3.1 105 WM8991 These registers are described in Table 58 below. REGISTER ADDRESS R8 (08h) BIT 15 LABEL AIF_MSTR1 DEFAULT 0b Pre-Production DESCRIPTION Audio Interface 1 Master Mode Select 0 = Slave mode 1 = Master mode Audio Interface 2 Master Mode Select 0 = Slave mode 1 = Master mode Audio Interface Select 0 = Audio interface 1 1 = Audio interface 2 (GPIO3/BCLK2, GPIO4/DACLRC2, GPIO5/DACDAT2) ADCLRC Direction (Forces ADCLRC clock to be output in slave mode) 0 = ADCLRC normal operation 1 = ADCLRC clock output enabled ADCLRC/GPIO1 Pin Function Select 0 = ADCLRC pin 1 = GPIO1 pin (ADCLRC connected to DACLRC internally) GPIO6/ADCLRCB Pin Function Select 0 = GPIO6 pin 1 = Inverted ADCLRC clock output DACLRC Direction (Forces DACLRC clock to be output in slave mode) 0 = DACLRC normal operation 1 = DACLRC clock output enabled 14 AIF_MSTR2 0b 13 AIF_SEL 0b 11 ADCLRC_DIR 0b R9 (09h) 15 ALRCGPIO1 0b 14 ALRCBGPIO6 0b 11 DACLRC_DIR 0b Table 58 Audio Interface Output Function Control OPERATION WITH TDM Time division multiplexing (TDM) allows multiple devices to transfer data simultaneously on the same bus. The WM8991 ADCs and DACs support TDM in master and slave modes, on both interfaces, and for all data formats and word lengths. TDM is enabled using register bits AIFADC_TDM and AIFDAC_TDM. The TDM data slot is programmed using register bits AIFADC_TDM_CHAN and AIFDAC_TDM_CHAN. w PP, May 2008, Rev 3.1 106 Pre-Production WM8991 BCLK ADCLRC WM8991 DACLRC ADCDAT DACDAT Processor WM8991 BCLK ADCLRC DACLRC ADCDAT DACDAT Processor BCLK ADCLRC WM8991 or Similar CODEC DACLRC ADCDAT DACDAT WM8991 or Similar CODEC BCLK ADCLRC DACLRC ADCDAT DACDAT Figure 63 TDM with WM8991 as Master Figure 64 TDM with Other CODEC as Master Figure 65 TDM with Processor as Master Note: The WM8991 is a 24-bit device. If the user operates the WM8991 in 32-bit mode then the 8 LSBs will be ignored on the receiving side and not driven on the transmitting side. It is therefore recommended to add a pull-down resistor if necessary to the DACDAT line and the ADCDAT line in TDM mode. BCLK DIVIDE The BCLK frequency is controlled by BCLK_DIV. When the ADCs and DACs are operating at different sample rates, BCLK_DIV must be set appropriately to support the data rate of whichever is the faster. w PP, May 2008, Rev 3.1 107 WM8991 Pre-Production Internal clock divide and phase control mechanisms ensure that the BCLK, ADCLRC and DACLRC edges will occur in a predictable and repeatable position relative to each other and to the data for a given combination of DAC sample rate, ADC sample rate and BCLK_DIV settings. See "Clocking and Sample Rates" section for more information. AUDIO DATA FORMATS (NORMAL MODE) In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition. Figure 66 Right Justified Audio Interface (assuming n-bit word length) In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition. Figure 67 Left Justified Audio Interface (assuming n-bit word length) In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. w PP, May 2008, Rev 3.1 108 Pre-Production WM8991 Figure 68 I2S Justified Audio Interface (assuming n-bit word length) In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRC output will resemble the frame pulse shown in Figure 69 and Figure 70. In device slave mode, Figure 71 and Figure 72, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse. Figure 69 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master) Figure 70 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master) w PP, May 2008, Rev 3.1 109 WM8991 1/fs 1 BCLK 1 BCLK falling edge can occur anywhere in this area Pre-Production LRCLK BCLK LEFT CHANNEL DACDAT / ADCDAT 1 2 3 n-2 n-1 n 1 2 RIGHT CHANNEL 3 n-2 n-1 n MSB Input Word Length (WL) LSB Figure 71 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave) 1/fs 1 BCLK 1 BCLK falling edge can occur anywhere in this area LRC BCLK LEFT CHANNEL DACDAT / ADCDAT 1 2 3 n-2 n-1 n 1 2 RIGHT CHANNEL 3 n-2 n-1 n MSB Input Word Length (WL) LSB Figure 72 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Slave) PCM operation is supported in DSP interface mode. WM8991 ADC data that is output on the Left Channel will be read as mono PCM data by the receiving equipment. Mono PCM data received by the WM8991 will be treated as Left Channel data. This data may be routed to the Left/Right DACs as described in the "Digital Input Path" section. AUDIO DATA FORMATS (TDM MODE) TDM is supported in master and slave mode and is enabled by register bits AIF_ADC_TDM and AIF_DAC_TDM. All audio interface data formats support time division multiplexing (TDM) for ADC and DAC data. Two time slots are available (Slot 0 and Slot 1), selected by register bits AIFADC_TDM_CHAN and AIFDAC_TDM_CHAN which control time slots for the ADC data and the DAC data. When TDM is enabled, the ADCDAT pin will be tri-stated immediately before and immediately after data transmission, to allow another ADC device to drive this signal line for the remainder of the sample period. Note that it is important that two ADC devices do not attempt to drive the data pin simultaneously. A short circuit may occur if the transmission time of the two ADC devices overlap with each other. See "Audio Interface Timing - TDM Mode" for details of the ADCDAT output relative to BCLK signal. Note that it is possible to ensure a gap exists between transmissions by setting the transmitted word length to a value higher than the actual length of the data. For example, if 32-bit word length is selected where only 24-bit data is available, then the WM8991 interface will tri-state after transmission of the 24-bit data, ensuring a gap after the WM8991's TDM slot. When TDM is enabled, BCLK frequency must be high enough to allow data from both time slots to be transferred. The relative timing of Slot 0 and Slot 1 depends upon the selected data format as shown in Figure 74 to Figure 77. w PP, May 2008, Rev 3.1 110 Pre-Production WM8991 Figure 73 TDM in Right-Justified Mode Figure 74 TDM in Left-Justified Mode Figure 75 TDM in I2S Mode w PP, May 2008, Rev 3.1 111 WM8991 Pre-Production Figure 76 TDM in DSP Mode A Figure 77 TDM in DSP Mode B w PP, May 2008, Rev 3.1 112 Pre-Production WM8991 DIGITAL AUDIO INTERFACE CONTROL The register bits controlling audio data format, word length, left/right channel data source and TDM are summarised in Table 59. REGISTER ADDRESS R4 (04h) BIT 15 LABEL AIFADCL_SRC DEFAULT 0b DESCRIPTION Left ADC Data Source Select 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel Right ADC Data Source Select 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel ADC TDM Enable 0 = Normal ADCDAT operation 1 = TDM enabled on ADCDAT ADCDAT TDM Channel Select 0 = ADCDAT outputs data on slot 0 1 = ADCDAT output data on slot 1 BCLK Invert 0 = BCLK not inverted 1 = BCLK inverted Right, left and I2S modes - LRCLK polarity 0 = normal LRCLK polarity 1 = invert LRCLK polarity DSP Mode - mode A/B select 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) 6:5 AIF_WL [1:0] 10b Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits Note - see "Companding" for the selection of 8-bit mode Digital Audio Interface Format 00 = Right justified 01 = Left justified 10 = I2S Format 11 = DSP Mode Left DAC Data Source Select 0 = Left DAC outputs left channel data 1 = Left DAC outputs right channel data Right DAC Data Source Select 0 = Right DAC outputs left channel data 1 = Right DAC outputs right channel data DAC TDM Enable 0 = Normal DACDAT operation 1 = TDM enabled on DACDAT DACDAT TDM Channel Select 0 = DACDAT data input on slot 0 1 = DACDAT data input on slot 1 14 AIFADCR_SRC 1b 13 AIFADC_TDM 0b 12 AIFADC_TDM_ CHAN AIF_BCLK_INV 0b 8 0b 7 AIF_LRCLK_IN V 0b 4:3 AIF_FMT [1:0] 10b R5 (05h) 15 DACL_SRC 0b 14 DACR_SRC 1b 12 AIFDAC_TDM 0b 13 AIFDAC_TDM_ CHAN 0b Table 59 Audio Data Format Control w PP, May 2008, Rev 3.1 113 WM8991 AUDIO INTERFACE OUTPUT AND GPIO TRISTATE Pre-Production Register bit AIF_TRIS can be used to tristate the audio interface and GPIO pins as described in Table 60. All GPIO[6:1] pins and digital audio interface pins will be tristated by this function, regardless of the state of other registers which control these pin configurations. REGISTER ADDRESS R9 (09h) BIT 13 LABEL AIF_TRIS DEFAULT 0 DESCRIPTION Audio Interface and GPIO Tristate 0 = Audio interface and GPIO pins operate normally 1 = Tristate all audio interface and GPIO pins Table 60 Tri-stating the Audio Interface and GPIO Pins MASTER MODE BCLK, ADCLRC AND DACLRC ENABLE The main audio interface pins (BCLK, ADCLRC, ADCDAT, DACLRC and DACDAT) and the alternative DAC interface pins (BCLK2, DACLRC2, DACDAT2) can be independently programmed to operate in master mode or slave mode using register bits AIF_MSTR1 and AIF_MSTR2. When the main audio interface is operating in slave mode, the BCLK, ADCLRC and DACLRC clock outputs to these pins are by default disabled to allow the digital audio source to drive these pins. Similarly, when the alternative audio interface is operating in slave mode, the BCLK2 and DACLRC2 clock outputs to these pins are by default disabled. It is also possible to force the ADCLRC, DACLRC or DACLRC2 to be output using register bits ADCLRC_DIR and DACLRC_DIR, allowing mixed master and slave modes for the ADCs or the active DAC audio interface. The active audio interface is selected by register bit AIF_SEL. Enabled clock outputs on the de-selected audio interface will output logic 0. When ADCLRC is configured as a GPIO pin (ALRCGPIO1=1), the DACLRC pin is used for the ADCs and the DACs and will only be disabled in master mode when both ADCs and both DACs are disabled. The clock generators for the audio interface are enabled according to the control signals shown in Figure 78. Figure 78 Clock Output Control w PP, May 2008, Rev 3.1 114 Pre-Production REGISTER ADDRESS R8 (08h) BIT 15 LABEL AIF_MSTR1 DEFAULT 0b WM8991 DESCRIPTION Audio Interface 1 Master Mode Select 0 = Slave mode 1 = Master mode Audio Interface 2 Master Mode Select 0 = Slave mode 1 = Master mode Audio Interface Select 0 = Audio interface 1 1 = Audio interface 2 (GPIO3/BCLK2, GPIO4/DACLRC2, GPIO5/DACDAT2) ADCLRC Direction (Forces ADCLRC clock to be output in slave mode) 0 = ADCLRC normal operation 1 = ADCLRC clock output enabled ADCLRC Rate ADCLRC clock output = BCLK / ADCLRC_RATE Integer (LSB = 1) Valid from 8..2047 R9 (09h) 15 ALRCGPIO1 0b ADCLRC/GPIO1 Pin Function Select 0 = ADCLRC pin 1 = GPIO1 pin (ADCLRC connected to DACLRC internally) DACLRC Direction (Forces DACLRC clock to be output in slave mode) 0 = DACLRC normal operation 1 = DACLRC clock output enabled DACLRC Rate DACLRC clock output = BCLK / DACLRC_RATE Integer (LSB = 1) Valid from 8..2047 Table 61 Digital Audio Interface Clock Output Control 14 AIF_MSTR2 0b 13 AIF_SEL 0b 11 ADCLRC_DIR 0b 10:0 ADCLRC_RATE [10:0] 040h 11 DACLRC_DIR 0b 10:0 DACLRC_RATE [10:0] 040h w PP, May 2008, Rev 3.1 115 WM8991 COMPANDING Pre-Production The WM8991 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides as shown in Table 62. REGISTER ADDRESS R5 (05h) BIT 4 LABEL DAC_COMP DEFAULT 0b DESCRIPTION DAC Companding Enable 0 = disabled 1 = enabled DAC Companding Type 0 = -law 1 = A-law ADC Companding Enable 0 = disabled 1 = enabled ADC Companding Type 0 = -law 1 = A-law 3 DAC_COMPMODE 0b 2 ADC_COMP 0b 1 ADC_COMPMODE 0b Table 62 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: -law (where =255 for the U.S. and Japan): F(x) = ln( 1 + |x|) / ln( 1 + ) A-law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA) F(x) = ( 1 + lnA|x|) / (1 + lnA) } for x 1/A } for 1/A x 1 -1 x 1 The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSBs of data. Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. This provides greater precision for low amplitude signals than for high amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quantization. The companded signal is an 8-bit word comprising sign (1 bit), exponent (3 bits) and mantissa (4 bits). 8-bit mode is selected whenever DAC_COMP=1 or ADC_COMP=1. The use of 8-bit data allows samples to be passed using as few as 8 BCLK cycles per LRC frame. When using DSP mode B, 8bit data words may be transferred consecutively every 8 BCLK cycles. 8-bit mode (without Companding) may be enabled by setting DAC_COMPMODE=1 or ADC_COMPMODE=1, when DAC_COMP=0 and ADC_COMP=0. BIT7 SIGN BIT[6:4] EXPONENT BIT[3:0] MANTISSA Table 63 8-bit Companded Word Composition w PP, May 2008, Rev 3.1 116 Pre-Production WM8991 u-law Companding 1 120 100 Companded Output 80 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output Figure 79 -Law Companding A-law Companding 1 120 100 Companded Output 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output Figure 80 A-Law Companding w PP, May 2008, Rev 3.1 117 WM8991 LOOPBACK Pre-Production Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data from the ADC audio interface is fed directly into the DAC data input. REGISTER ADDRESS R5 (05h) BIT 0 LABEL LOOPBACK DEFAULT 0b DESCRIPTION Digital Loopback Function 0 = No loopback 1 = Loopback enabled (ADC data output is directly input to DAC data input). Table 64 Loopback Control Note: 1. 2. 3. Master Mode: ADC and DAC left/right clocks must be set to the same pin when using LOOPBACK function (ALRCGPIO1=1) Slave Mode: It is recommended to set ALRCGPIO1=1 as well, otherwise ADCLRC and DACLRC must be running at the same BCLK rate and in phase. When the digital sidetone is enabled, ADC data will continue to be added to DAC data when LOOPBACK is enabled w PP, May 2008, Rev 3.1 118 Pre-Production WM8991 CLOCKING AND SAMPLE RATES The internal clocks for the ADCs, DACs, DSP core functions, digital audio interface and Class D switching amplifier are all derived from a common internal clock source, SYSCLK. SYSCLK can either be derived directly from MCLK, or may be generated from a PLL using MCLK as an external reference. Many commonly-used audio sample rates can be derived directly from typical MCLK frequencies; the PLL provides additional flexibility for a wide range of MCLK frequencies. An alternative MCLK input may be selected via the GPIO2/MCLK2 pin. All clock configurations must be set up before enabling playback to avoid glitches. The ADC and DAC sample rates are independently selectable, relative to SYSCLK, using ADC_CLKDIV and DAC_CLKDIV. These fields must be set according to the required sampling frequency and depending on the selected clocking mode (AIF_LRCLKRATE). In master mode, BCLK is also derived from SYSCLK via a programmable division set by BCLK_DIV. In the case where the ADCs and DACs are operating at different sample rates, BCLK must be set according to whichever is the faster rate. The ADCLRC and DACLRC signals do not automatically match the ADC and DAC sample rates; these must be configured using ADCLRC_RATE and DACLRC_RATE as described under "Digital Audio Interface Control". A clock (OPCLK) derived from SYSCLK can be output on the GPIO pins to provide clocking for other parts of the system. This clock is enabled by OPCLK_ENA and its frequency is set by OPCLKDIV. A slow clock (TOCLK) derived from SYSCLK can be used to de-bounce the button/accessory detect inputs, and to set the timeout period for volume updates when zero-cross detect is used. This clock is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE. The Class D switching amplifier requires a clock; this is derived from SYSCLK via a programmable divider DCLKDIV. Table 65 to Table 71 show the clocking and sample rate controls for MCLK input, BCLK output (in master mode), ADCs, DACs, class D outputs and GPIO clock output. The overall clocking scheme for the WM8991 is illustrated in Figure 81. Figure 81 Clocking Scheme w PP, May 2008, Rev 3.1 119 WM8991 SYSCLK CONTROL Pre-Production The MCLK_SRC bit is used to select the MCLK source. The source may be either MCLK or GPIO2/MCLK2. The selected source may also be inverted by setting register bit MCLK_INV. Note that it is not recommended to change the control bit MCLK_INV while the WM8991 is processing data as this may lead to clock glitches and signal pop and clicks. The SYSCLK_SRC bit is used to select the source for SYSCLK. The source may be either the selected MCLK source or the PLL output. The selected source is divided by the SYSCLK pre-divider MCLK_DIV to generate SYSCLK. The selected source may also be adjusted by the MCLK_DIV divider. These register fields are described in Table 65. See "PLL" for more details of the Phase Locked Loop clock generator. The WM8991 supports glitch-free MCLK and SYSCLK source selection. When both clock sources are running and MCLK_SRC or SYSCLK_SRC is modified to select one of these clocks, a glitch-free clock transition will take place. The de-glitching circuit will ensure that the minimum pulse width will be no less than the pulse width of the faster of the two clock sources. When the initial clock source is to be disabled before changing to the new clock source, the CLK_FORCE bit must also be used to force the clock source transition to take place. In this case, glitch-free operation cannot be guaranteed. REGISTER ADDRESS R7 (07h) BIT 15 LABEL MCLK_SRC DEFAULT 0b DESCRIPTION MCLK Source Select 0 = MCLK pin 1 = GPIO2/MCLK2 pin SYSCLK Source Select 0 = MCLK (or MCLK2 if MCLK_SRC=1) 1 = PLL output Forces Clock Source Selection 0 = Existing SYSCLK source (MCLK, MCLK2 or PLL output) must be active when changing to a new clock source. 1 = Allows existing MCLK source to be disabled before changing to a new clock source. SYSCLK Pre-divider. Clock source (MCLK, MCLK2 or PLL output) will be divided by this value to generate SYSCLK. 00 = Divide SYSCLK by 1 01 = Reserved 10 = Divide SYSCLK by 2 11 = Reserved MCLK Invert 0 = Master clock (MCLK or MCLK2) not inverted 1 = Master clock (MCLK or MCLK2) inverted 14 SYSCLK_SRC 0b 13 CLK_FORCE 0b 12:11 MCLK_DIV [1:0] 00b 10 MCLK_INV 0b Table 65 MCLK and SYSCLK Control ADC / DAC SAMPLE RATES The ADC and DAC sample rates are independently selectable, relative to SYSCLK, by setting the register fields ADC_CLKDIV and DAC_CLKDIV. These fields must be set according to the SYSCLK frequency, and according to the selected clocking mode. Two clocking modes are provided - Normal Mode (AIF_LRCLKRATE = 0) allows selection of the commonly used sample rates from typical audio system clocking frequencies (eg. 12.288MHz); USB Mode (AIF_LRCLKRATE = 1) allows many of these sample rates to be generated from a 12MHz USB clock. Depending on the available clock sources, the USB mode may be used to save power by supporting 44.1kHz operation without requiring the PLL. w PP, May 2008, Rev 3.1 120 Pre-Production WM8991 The AIF_LRCLKRATE field must be set as described in Table 66 to ensure correct operation of internal functions according to the SYSCLK / Fs ratio. Table 67 describes the available sample rates using four different common MCLK frequencies. In Normal mode, the programmable division set by ADC_CLKDIV must ensure that a 256 * ADC Fs clock is generated for the ADC DSP. DAC_CLKDIV must ensure that a 256 * DAC Fs clock is generated for the DAC DSP. In USB mode, the programmable division set by ADC_CLKDIV must ensure that a 272 * ADC Fs clock is generated for the ADC DSP. DAC_CLKDIV must ensure that a 272 * DAC Fs clock is generated for the DAC DSP. Note that in USB mode, the ADC / DAC sample rates do not match exactly with the commonly used sample rates (e.g. 44.118 kHz instead of 44.100 kHz). At most, the difference is less than 0.5%. Data recorded at 44.100 kHz sample rate and replayed at 44.118 kHz will experience a slight (sub 0.5%) pitch shift as a result of this difference. Note also that the USB mode cannot be used to generate a 48kHz samples rate from a 12MHz MCLK; the PLL should be used in this case. In low sample rate modes (eg. 8kHz voice), the SNR is liable to be degraded if the typical 64fs DAC clocking rate is used (see Figure 81). In this case, it may be possible to improve the SNR by raising the DAC clocking rate by setting the DAC_SDMCLK_RATE register field, causing the DAC clocking rate to be set equal to SYSCLK/4. The DAC_CLKDIV field must still be set as described above to derive the correct clock for the DAC DSP. In 8kHz voice applications, in systems where SYSCLK > 256fs (or 272fs when applicable), setting DAC_SDMCLK_RATE will result in the SNR performance being improved. Note that setting DAC_SDMCLK_RATE will result in an increase in power consumption. REGISTER ADDRESS R7 (07h) BIT 7:5 LABEL ADC_CLKDIV [2:0] DEFAULT 000b DESCRIPTION ADC Sample Rate Divider 000 = SYSCLK / 1.0 001 = SYSCLK / 1.5 010 = SYSCLK / 2.0 011 = SYSCLK / 3.0 100 = SYSCLK / 4.0 101 = SYSCLK / 5.5 110 = SYSCLK / 6.0 111= Reserved DAC Sample Rate Divider 000 = SYSCLK / 1.0 001 = SYSCLK / 1.5 010 = SYSCLK / 2.0 011 = SYSCLK / 3.0 100 = SYSCLK / 4.0 101 = SYSCLK / 5.5 110 = SYSCLK / 6.0 111= Reserved DAC clocking rate 0 = Normal operation (64fs) 1 = SYSCLK/4 LRCLK Rate 0 = Normal mode (256 * fs) 1 = USB mode (272 * fs) 4:2 DAC_CLKDIV [2:0] 000b R10 (0Ah) 12 DAC_SDMCLK_R ATE AIF_LRCLKRATE 0b 10 0b Table 66 ADC / DAC Sample Rate Control w PP, May 2008, Rev 3.1 121 WM8991 SYSCLK ADC / DAC SAMPLE RATE DIVIDER 000 = SYSCLK / 1 001 = SYSCLK / 1.5 010 = SYSCLK / 2 12.288 MHz 011 = SYSCLK / 3 100 = SYSCLK / 4 101 = SYSCLK / 5.5 110 = SYSCLK / 6 111 = Reserved 000 = SYSCLK / 1 001 = SYSCLK / 1.5 010 = SYSCLK / 2 11.2896 MHz 011 = SYSCLK / 3 100 = SYSCLK / 4 101 = SYSCLK / 5.5 110 = SYSCLK / 6 111 = Reserved 000 = SYSCLK / 1 001 = SYSCLK / 1.5 010 = SYSCLK / 2 12 MHz 011 = SYSCLK / 3 100 = SYSCLK / 4 101 = SYSCLK / 5.5 110 = SYSCLK / 6 111 = Reserved 000 = SYSCLK / 1 001 = SYSCLK / 1.5 010 = SYSCLK / 2 2.048 MHz 011 = SYSCLK / 3 100 = SYSCLK / 4 101 = SYSCLK / 5.5 110 = SYSCLK / 6 111 = Reserved Table 67 ADC and DAC Sample Rates Normal (256 * Fs) USB Mode (272 * Fs) Normal (256 * Fs) Normal (256 * Fs) CLOCKING MODE Pre-Production ADC / DAC SAMPLE RATE 48 kHz 32 kHz 24 kHz 16 kHz 12 kHz Not used 8 kHz Reserved 44.1 kHz Not used 22.05 kHz Not used 11.025 kHz 8.018 kHz Not used Reserved 44.118 kHz Not used 22.059 kHz Not used 11.029 kHz 8.021 kHz Not used Reserved 8 kHz Not used Not used Not used Not used Not used Not used Reserved w PP, May 2008, Rev 3.1 122 Pre-Production WM8991 BCLK CONTROL In Master Mode, BCLK is derived from SYSCLK via a programmable division set by BCLK_DIV, as described in Table 68. BCLK_DIV must be set to an appropriate value to ensure that there are sufficient BCLK cycles to transfer the complete data words from the ADCs and to the DACs. In Slave Mode, BCLK is generated externally and appears as an input to the CODEC. The host device must provide sufficient BCLK cycles to transfer complete data words to the ADCs and DACs. Note that, although the ADC and DAC can run at different sample rates, they share the same bit clock pin BCLK. In the case where different ADC / DAC sample rates are used, the BCLK frequency should be set according to the higher of the ADC / DAC bit rates. REGISTER ADDRESS R6 (06h) BIT 4:1 LABEL BCLK_DIV [3:0] DEFAULT 0100b DESCRIPTION BCLK Frequency (Master Mode) 0000 = SYSCLK 0001 = SYSCLK / 1.5 0010 = SYSCLK / 2 0011 = SYSCLK / 3 0100 = SYSCLK / 4 0101 = SYSCLK / 5.5 0110 = SYSCLK / 6 0111 = SYSCLK / 8 1000 = SYSCLK / 11 1001 = SYSCLK / 12 1010 = SYSCLK / 16 1011 = SYSCLK / 22 1100 = SYSCLK / 24 1101 = SYSCLK / 32 1110 = SYSCLK / 44 1111 = SYSCL:K / 48 Table 68 BCLK Control OPCLK CONTROL A clock output (OPCLK) derived from SYSCLK may be output via GPIO1 to GPIO6. This clock is enabled by register bit OPCLK_ENA, and its frequency is controlled by OPCLKDIV. This output of this clock is also dependent upon the GPIO register settings described under "General Purpose Input/Output". REGISTER ADDRESS R6 (06h) BIT 12:9 LABEL OPCLKDIV [3:0] DEFAULT 0000b DESCRIPTION GPIO Output Clock Divider 0000 = SYSCLK 0001 = SYSCLK / 2 0010 = SYSCLK / 3 0011 = SYSCLK / 4 0100 = SYSCLK / 5.5 0101 = SYSCLK / 6 0110 = SYSCLK / 8 0111 = SYSCLK / 12 1000 = SYSCLK / 16 1001 to 1111 = Reserved GPIO Clock Output Enable 0 = disabled 1 = enabled R2 (02h) 11 OPCLK_ENA (rw) 0b Table 69 OPCLK Control w PP, May 2008, Rev 3.1 123 WM8991 CLASS D SWITCHING CLOCK Pre-Production The Class D switching clock is derived from SYSCLK as determined by register field DCLKDIV as described in Table 70. This clock should be set to between 700kHz and 800kHz for optimum performance. The class D switching clock should not be disabled when the speaker output is active, as this will prevent the speaker outputs from functioning. The class D switching clock frequency should not be altered while the speaker output is active as this may generate an audible click. REGISTER ADDRESS R6 (06h) BIT 8:6 LABEL DCLKDIV [2:0] DEFAULT 111b DESCRIPTION Class D Clock Divider 000 = SYSCLK 001 = SYSCLK / 2 010 = SYSCLK / 3 011 = SYSCLK / 4 100 = SYSCLK / 6 101 = SYSCLK / 8 110 = SYSCLK / 12 111 = SYSCLK / 16 Table 70 DCLK Control TOCLK CONTROL A slow clock (TOCLK) is derived from SYSCLK to enable input de-bouncing and volume update timeout functions. This clock is enabled by register bit TOCLK_ENA, and its frequency is controlled by TOCLK_RATE, as described in Table 71. REGISTER ADDRESS R6 (06h) BIT 15 LABEL TOCLK_RATE DEFAULT 0b DESCRIPTION Timeout Clock Rate (Selects clock to be used for volume update timeout and GPIO input debounce) 0 = SYSCLK / 221 (Slower Response) 1 = SYSCLK / 219 (Faster Response) Timeout Clock Enable (This clock is required for volume update timeout and GPIO input de-bounce) 0 = disabled 1 = enabled 14 TOCLK_ENA 0b Table 71 TOCLK Control USB MODE It is possible to reduce power consumption by disabling the PLL in some applications. One such application is when SYSCLK is generated from a 12MHz USB clock source. Setting the AIF_LRCLKRATE bit as described earlier (see "ADC / DAC Sample Rates") allows a sample rate close to 44.1kHz to be generated with no additional PLL power consumption. In this configuration, SYSCLK must be driven directly from MCLK (or MCLK2) and by disabling the PLL. This is achieved by setting SYSCLK_SRC=0, PLL_ENA=0. REGISTER ADDRESS R10 (0Ah) BIT 10 LABEL AIF_LRCLKRATE DEFAULT 0b DESCRIPTION LRCLK Rate 0 = Normal mode (256 * fs) 1 = USB mode (272 * fs) Table 72 USB Mode Control w PP, May 2008, Rev 3.1 124 Pre-Production WM8991 PLL The integrated PLL can be used to generate SYSCLK for the WM8991 from a wide range of MCLK reference frequencies. The PLL is enabled by the PLL_ENA register bit. If required, the input reference clock can be divided by 2 by setting the register bit PRESCALE. The PLL frequency ratio R is equal to f2/f1 (see Figure 81). This ratio is the real number represented by register fields PLLN and PLLK, where PLLN is an integer (LSB = 1) and PLLK is the fractional portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by the field SDM. De-selection of fractional mode results in lower power consumption. For PLL stability, input frequencies and divisions must be chosen so that 5 PLLN 13. Best performance is achieved for 7 N 9. Also, the PLL performs best when f2 is set between 90MHz and 100MHz. If PLLK is regarded as a 16-bit integer (instead of a fractional quantity), then PLLN and PLLK may be determined as follows: * * PLLN = int R PLLK = int (216 (R - PLLN)) The PLL Control register settings are described in Table 73. REGISTER ADDRESS R2 (02h) BIT 15 LABEL PLL_ENA (rw) SDM DEFAULT 0 PLL Enable 0 = disabled 1 = enabled Enable PLL Integer Mode 0 = Integer mode 1 = Fractional mode Divide MCLK by 2 at PLL input 0 = Divide by 1 1 = Divide by 2 Integer (N) part of PLL frequency ratio. Fractional (K) part of PLL frequency ratio. (Most significant bits) Fractional (K) part of PLL frequency ratio. (Least significant bits) DESCRIPTION R60 (3Ch) 7 0 6 PRESCALE 0b 3:0 R61 (3Dh) R62 (3Eh) 7:0 7:0 PLLN [3:0] PLLK [15:8] PLLK [7:0] 8h 31h 26h Table 73 PLL Control w PP, May 2008, Rev 3.1 125 WM8991 EXAMPLE PLL CALCULATION To generate 12.288MHz SYSCLK from a 12MHz reference clock: Pre-Production There is a fixed divide by 4 at the PLL output (see Figure 81) followed by a selectable divide by 2 in the same path. PLL output f2 should be set in the range 90MHz - 100MHz. Enabling the divide by 2 (MCLK_DIV = 10b) sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz. There is a selectable pre-scale (divide MCLK by 2) at the PLL input (f1 - see Figure 75). The PLL frequency ratio f2/f1 must be set in the range 5 - 13. Disabling the MCLK pre-scale (PRESCALE = 0b) sets the required ratio f2/f1 = 8.192. The required settings for this example are: * * * * * * MCLK_DIV = 10b PRESCALE = 0b PLL_ENA = 1 SDM = 1 PLLN = 8 = 8h PLLK = 0.192 = 3126h EXAMPLE PLL SETTINGS Table 74 provides example PLL settings for generating common SYSCLK frequencies from a variety of MCLK reference frequencies. MCLK (MHZ) 12 12 13 13 14.4 14.4 19.2 19.2 19.68 19.68 19.8 19.8 24 24 26 26 27 27 SYSCLK (MHZ) 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 MCLKDIV F2 = SYSCLK * 4 * MCLKDIV 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 PRESCALE F1 = MCLK/ PRESCALE 12 12 13 13 14.4 14.4 9.6 9.6 9.84 9.84 9.9 9.9 12 12 13 13 13.5 13.5 R = F2/F1 7.5264 8.192 6.947446 7.561846 6.272 6.826667 9.408 10.24 9.178537 9.990243 9.122909 9.929697 7.5264 8.192 6.947446 7.561846 6.690133 7.281778 7h 8h 6h 7h 6h 6h 9h Ah 9h 9h 9h 9h 7h 8h 6h 7h 6h 7h N K 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 86C2h 3126h F28Bh 8FD5h 45A1h D3A0h 6872h 3D70h 2DB4h FD80h 1F76h EE00h 86C2h 3126h F28Bh 8FD5h B0ACh 4822h Table 74 PLL Frequency Examples w PP, May 2008, Rev 3.1 126 Pre-Production WM8991 CONTROL INTERFACE The WM8991 is controlled by writing to its control registers. Readback is available for certain registers, including device ID, power management registers and some GPIO status bits. The control interface can operate as either a 2-, 3- or 4-wire control interface, with additional variants as detailed below: 1. 2. 2-wire - open-drain 3-wire - push 0/1 - open drain 4-wire - push 0/1 - wired-OR 3. Readback is provided on the bi-directional pin SDIN in 2-/3-wire modes and on a GPIO pin in 4-wire mode. SELECTION OF CONTROL MODE The MODE pin determines the 2- or 3-/4-wire mode as shown in Table 75. MODE Low High INTERFACE FORMAT 2 wire 3- or 4- wire Table 75 Control Interface Mode Selection 2-WIRE SERIAL CONTROL MODE The WM8991 is controlled by writing to registers through a 2-wire serial control interface. A control word consists of 24 bits. The first 8 bits (B23 to B16) are address bits that select which control register is accessed. The remaining 16 bits (B15 to B0) are data bits, corresponding to the 16 bits in each control register. Many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 8-bit address of each register in the WM8991). The default device address is 0011010 (0x34h). The WM8991 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8991, then the WM8991 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is `1' when operating in write only mode, the WM8991 returns to the idle condition and wait for a new start condition and valid address. The WM8991 supports a multitude of read and write operations, which are: * * * * Single write Single read Multiple write using auto-increment Multiple read using auto-increment w PP, May 2008, Rev 3.1 127 WM8991 TERMINOLOGY S Sr A P RW Table 76 Terminology ReadNotWrite DESCRIPTION Start Condition Repeated start Acknowledge Stop Condition 0 = Write 1 = Read Pre-Production These modes are shown in the section below. Terminology used in the following figures: Figure 82 2-Wire Serial Control Interface (single write) S Device ID RW A Index A Sr Device ID RW A MSByte Data A LSByte Data A P (0) (1) Figure 83 2-Wire Serial Control Interface (single read) Figure 84 2-Wire Serial Control Interface (multiple write using auto-increment) Figure 85 2-Wire Serial Control Interface (multiple read using auto-increment) In 2-wire mode, the WM8991 has two possible device addresses, which can be selected using the CSB/ADDR pin. CSB/ADDR STATE Low High DEVICE ADDRESS 0011010 (0 x 34h) 0011011 (0 x 36h) Table 77 2-Wire Control Interface Address Selection w PP, May 2008, Rev 3.1 128 Pre-Production WM8991 3-WIRE / 4-WIRE SERIAL CONTROL MODES The WM8991 is controlled by writing to registers through a 3- or 4-wire serial control interface. A control word consists of 24 bits. The first bit is the read/write bit (R/W), which is followed by 7 address bits (A6 to A0) that determine which control register is accessed. The remaining 16 bits (B15 to B0) are data bits, corresponding to the 16 bits in each control register. The 3- or 4-wire modes are selected by the RD_3W_ENA register bit. Additionally the MODE_3W4W control bit can be used to select between push 0/1 and open-drain or wired-OR modes, as described in Table 78 below. REGISTER ADDRESS R22 (16h) BIT 15 LABEL RD_3W_ENA DEFAULT 1b DESCRIPTION 3- / 4-wire readback configuration 1 = 3-wire mode 0 = 4-wire mode, using GPIO pin 3-wire mode 0 = push 0/1 1 = open-drain 4-wire mode 0 = push 0/1 1 = wired-OR 14 MODE_3W4W 0b Table 78 3-Wire / 4-Wire Control Interface Selection 3-wire control mode is selected by setting RD_3W_ENA = 1. In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB/ADDR latches in a complete control word consisting of the last 24 bits. In Write operations (R/W=0), all SDIN bits are driven by the controlling device. In Read operations (R/W=1), the SDIN pin is driven by the controlling device to clock in the register address, after which the WM8991 drives the SDIN pin to output the applicable data bits. The 3-wire control mode timing is illustrated in Figure 86. Figure 86 3-Wire Serial Control Interface 4-wire control mode is selected by setting RD_3W_ENA = 0. In Write operations (R/W=0), this mode is the same as 3-wire mode described above. In Read operations (R/W=1), a GPIO pin must be selected to output SDOUT by setting GPIOn_SEL=0110b (n= 1 to 6). In this mode, the SDIN pin is ignored following receipt of the valid register address. SDOUT is driven by the WM8991. In 4-wire Push 0/1 mode, SDOUT is driven low when not outputting register data bits. In Wired-OR mode, SDOUT is undriven when not outputting register data bits. The 4-wire control mode timing is illustrated in Figure 87 and Figure 88. w PP, May 2008, Rev 3.1 129 WM8991 CSB SCLK SDIN SDOUT R/W A6 A5 A4 A3 A2 A1 A0 B15 B15 B14 B14 B13 B13 B12 B12 B11 B11 B10 B10 B9 B9 B8 B8 B7 B7 B6 B6 B5 B5 B4 B4 B3 B3 B2 B2 Pre-Production B1 B1 B0 B0 control register address control register data bits (READ/WRITE) Figure 87 4-Wire Readback (Push 0/1) CSB SCLK SDIN SDOUT R/W A6 A5 A4 A3 A2 A1 A0 B15 B15 B14 B14 B13 B13 B12 B12 B11 B11 B10 B10 B9 B9 B8 B8 B7 B7 B6 B6 B5 B5 B4 B4 B3 B3 B2 B2 B1 B1 B0 B0 undriven control register address ud control register data bits (READ/WRITE) Figure 88 4-Wire Readback (wired-OR) w PP, May 2008, Rev 3.1 130 Pre-Production WM8991 POWER MANAGEMENT POWER MANAGEMENT REGISTERS The WM8991 has three control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled. To minimise pop or click noise, it is important to enable or disable functions in the correct order. See "Pop Suppression Control" for further details of recommended control sequences. REGISTER ADDRESS R1 (1h) BIT 12 LABEL SPK_ENA (rw) DEFAULT 0b DESCRIPTION SPKMIX Mixer, Speaker PGA and Speaker Output Enable 0 = disabled 1 = enabled OUT3 and OUT3MIX Enable 0 = disabled 1 = enabled OUT4 and OUT4MIX Enable 0 = disabled 1 = enabled LOUT (Left Headphone Output) Enable 0 = disabled 1 = enabled ROUT (Right Headphone Output) Enable 0 = disabled 1 = enabled MICBIAS Enable 0 = OFF (high impedance output) 1 = ON Vmid Divider Enable and Select 00 = Vmid disabled (for OFF mode) 01 = 2 x 50k divider (Normal mode) 10 = 2 x 250k divider (Standby mode) 11 = 2 x 5k divider (for fast start-up) VREF Enable (Bias for all analogue functions) 0 = VREF bias disabled 1 = VREF bias enabled PLL Enable 0 = disabled 1 = enabled Thermal Sensor Enable 0 = Thermal sensor disabled 1 = Thermal sensor enabled Thermal Shutdown Enable (Requires thermal sensor to be enabled) 0 = Thermal shutdown disabled 1 = Thermal shutdown enabled GPIO Clock Output Enable 0 = disabled 1 = enabled Left Input Path Enable (Enables AINLMUX, INMIXL, DIFFINL and RXVOICE input to AINLMUX) 0 = disabled 1 = enabled 11 OUT3_ENA (rw) OUT4_ENA (rw) LOUT_ENA (rw) ROUT_ENA (rw) MICBIAS_ENA (rw) VMID_MODE [1:0] (rw) 0b 10 0b 9 0b 8 0b 4 0b 2:1 00b 0 VREF_ENA (rw) 0b R2 (02h) 15 PLL_ENA (rw) TSHUT_ENA (rw) TSHUT_OPDIS (rw) 0b 14 0b 13 1b 11 OPCLK_ENA (rw) AINL_ENA (rw) 0b 9 0b w PP, May 2008, Rev 3.1 131 WM8991 REGISTER ADDRESS BIT 8 LABEL AINR_ENA (rw) DEFAULT 0b DESCRIPTION Pre-Production Left Input Path Enable (Enables AINRMUX, INMIXR, DIFFINR and RXVOICE input to AINRMUX) 0 = disabled 1 = enabled LIN34 Input PGA Enable 0 = disabled 1 = enabled LIN12 Input PGA Enable 0 = disabled 1 = enabled RIN34 Input PGA Enable 0 = disabled 1 = enabled RIN12 Input PGA Enable 0 = disabled 1 = enabled Left ADC Enable 0 = disabled 1 = enabled Right ADC Enable 0 = disabled 1 = enabled LON Line Out and LONMIX Enable 0 = disabled 1 = enabled LOP Line Out and LOPMIX Enable 0 = disabled 1 = enabled RON Line Out and RONMIX Enable 0 = disabled 1 = enabled ROP Line Out and ROPMIX Enable 0 = disabled 1 = enabled SPKMIX Mixer and Speaker PGA Enable 0 = disabled 1 = enabled Note that SPKMIX and SPKPGA are also enabled when SPK_ENA is set. LOPGA Left Volume Control Enable 0 = disabled 1 = enabled ROPGA Right Volume Control Enable 0 = disabled 1 = enabled LOMIX Left Output Mixer Enable 0 = disabled 1 = enabled ROMIX Right Output Mixer Enable 0 = disabled 1 = enabled Left DAC Enable 0 = disabled 1 = enabled PP, May 2008, Rev 3.1 132 7 LIN34_ENA (rw) LIN12_ENA (rw) RIN34_ENA (rw) RIN12_ENA (rw) ADCL_ENA (rw) ADCR_ENA (rw) LON_ENA (rw) LOP_ENA (rw) RON_ENA (rw) ROP_ENA (rw) SPKPGA_ENA (rw) 0b 6 0b 5 0b 4 0b 1 0b 0 0b R3 (03h) 13 0b 12 0b 11 0b 10 0b 8 0b 7 LOPGA_ENA (rw) ROPGA_ENA (rw) LOMIX_ENA (rw) ROMIX_ENA (rw) DACL_ENA (rw) 0b 6 0b 5 0b 4 0b 1 0b w Pre-Production REGISTER ADDRESS BIT 0 LABEL DACR_ENA (rw) DEFAULT 0b DESCRIPTION Right DAC Enable 0 = disabled 1 = enabled WM8991 Table 79 Power Management CHIP RESET AND ID The device ID can be read back from register 0. Writing to this register will reset the device. REGISTER ADDRESS R0 (00h) Reset / ID BIT 15:0 LABEL SW_RESET_ CHIP_ID [15:0] (rr) DEFAULT 8990h DESCRIPTION Writing to this register resets all registers to their default state. Reading from this register will indicate device family ID 8990h. Table 80 Chip Reset and ID SAVING POWER AT HIGHER SUPPLY VOLTAGE The AVDD supply of the WM8991 can operate between 2.7V and 3.6V. By default, all analogue circuitry on the device is optimized to run at 3.3V. This set-up is also good for all other supply voltages down to 2.7V. At lower voltages, performance can be improved by increasing the bias current. If low power operation is preferred the bias current can be left at the default setting. This is controlled as shown in Table 81. REGISTER ADDRESS R51 (33h) BIT 8:7 LABEL VSEL [1:0] DEFAULT 11 DESCRIPTION Analogue Bias Optimisation 00 = Reserved 01 = Bias current optimized for AVDD=2.7V 1X = Bias current optimized for AVDD=3.3V Table 81 Bias Optimisation w PP, May 2008, Rev 3.1 133 WM8991 POP SUPPRESSION CONTROL Pre-Production In normal operation, the analogue circuits in the WM8991 are referenced to VMID (AVDD/2). When this reference voltage is first enabled, it will ramp quickly from AGND to AVDD/2 and, if connected to an active output, will result in an audible pop being heard. Enabling or disabling the output stage after the internal reference has settled can also result in an audible pop as the output rises rapidly from AGND. The WM8991 provides a number of features which enable these pops to be suppressed. The associated control bits are described in this section. Careful attention is required to the sequence and timing of these controls in order to get maximum benefit. An outline of some generic control sequences is provided in order to assist users in the definition of application-specific sequences. REFERENCE VOLTAGES VMID is generated from AVDD via a programmable resistor chain as shown in the audio signal paths diagram on page 28. Together with the external decoupling capacitor on VMID, the programmable resistor chain results in a slow, normal or fast charging characteristic on VMID. The VMID reference is controlled by VMID_MODE[1:0]. The analogue circuits in the WM8991 require a bias current. The default bias current is enabled by setting VREF_ENA. Note that the default bias current source requires VMID to be enabled also. REGISTER ADDRESS R1 (01h) BIT 2:1 LABEL VMID_MODE [1:0] (rw) DEFAULT 00b DESCRIPTION VMID Divider Enable and Select 00 = VMID disabled (for OFF mode) 01 = 2 x 50k divider (Normal mode) 10 = 2 x 250k divider (Standby mode) 11 = 2 x 5k divider (for fast start-up) VREF Enable (Bias for all analogue functions) 0 = VREF bias disabled 1 = VREF bias enabled 0 VREF_ENA (rw) 0b Table 82 Reference Voltages SOFT START CONTROL A pop-suppressed start-up requires VMID to be enabled smoothly, without the step change normally associated with the initial stage of the VMID capacitor charging. A pop-suppressed start-up also requires the analogue bias current to be enabled throughout the signal path prior to the VMID reference voltage being applied. The WM8991 incorporates pop-suppression circuits which address these requirements. The WM8991 provides an alternative start-up bias circuit which can be used in place of the default bias current during start-up. The start-up bias current source is enabled by BUFDCOPEN. The startup bias source is selected (in place of the default bias source) by POBCTRL. It is recommended that the start-up bias is used during start-up, before switching back to the higher quality, VREF-enabled bias. A soft-start circuit is provided in order to control the switch-on of the VMID reference. The soft-start control circuit is enabled by setting SOFTST. When the soft-start circuit is enabled prior to enabling VMID_MODE, the reference voltage rises smoothly, without the step change that would otherwise occur. It is recommended that the soft-start circuit and the output signal path be enabled before VMID is enabled by VMID_MODE. Soft shut-down of VMID is also provided by the soft-start control circuit and the start-up bias current generator. The soft shut-down of VMID is achieved by setting SOFTST = 1, BUFCOPEN = 1 and POBCTRL = 1 prior to setting VMID_MODE = 00. w PP, May 2008, Rev 3.1 134 Pre-Production The register fields associated with soft start control are described in Table 83. REGISTER ADDRESS R57 (39h) Anti-Pop (2) BIT 6 LABEL SOFTST DEFAULT 0b DESCRIPTION Enables VMID soft start 0 = Disabled 1 = Enabled WM8991 2 BUFDCOPEN 0b Enables the Start-Up bias current generator 0 = Disabled 1 = Enabled Selects the bias current source for output amplifiers and VMID buffer 0 = Default bias 1 = Start-Up bias 1 POBCTRL 0b Table 83 Soft Start Control DISABLED INPUT/OUTPUT CONTROL After start-up, it may be desirable to disable an output stage, in order to reduce power consumption on an unused output. In order to avoid audible pops caused by a disabled output dropping to AGND, the WM8991 can maintain the output at VMID even when the output driver is disabled. This is achieved by connecting a buffered VMID reference to the output. The buffered VMID is enabled by setting BUFIOEN. When BUFIOEN is enabled, it will be connected to any disabled output driver. It is recommended that BUFIOEN is enabled prior to disabling the output driver. The buffered VMID, enabled by BUFIOEN, also maintains the charge on the input capacitors connected to any disabled input amplifier. Buffered VMID is connected to each input through 1k resistors. This suppresses the audible artefacts that would otherwise arise when an input amplifier is disabled or enabled. In some applications, a pop generated at an input stage can be entirely suppressed by correctly managing the output stages. However, it may be desirable to use the buffered VMID feature in order to eliminate the input PGA start-up delay (the input capacitor charging time) in addition to suppressing any mute/un-mute pops. In applications where frequent enabling and configuration of signal paths is used, it is recommended to enable BUFIOEN at all times. REGISTER ADDRESS R57 (39h) Anti-Pop (2) BIT 3 LABEL BUFIOEN DEFAULT 0b DESCRIPTION Enables the Buffered VMID reference at disabled inputs/outputs 0 = Disabled 1 = Enabled Table 84 Disabled Input/Output Control OUTPUT DISCHARGE CONTROL The output paths may also be actively discharged to AGND through internal resistors if desired. This is desirable at start-up in order to achieve a known output stage condition prior to enabling the softstart VMID reference voltage. This is also desirable in shut-down in order to eliminate pops arising from memory effects in the output capacitors on completion of the controlled shut-down of the VMID reference. Note that, for any signal paths that do not use output capacitors (eg. capless headphone drive), the discharge control is not normally required. It is recommended that the output paths should be actively discharged prior to commencing a startup sequence. The active discharging should then be disabled prior to enabling the output drivers. In shut-down, it is recommended that the output paths should be actively discharged after the VMID reference has settled to AGND and the output drivers have been disabled. The line and headphone output pins are discharged by setting DIS_LLINE, DIS_RLINE, DIS_OUT3, DIS_OUT4, DIS_LOUT and DIS_ROUT, as described in Table 85. Note that the buffered VMID reference is not applied to an actively discharged output, regardless of BUFIOEN. w PP, May 2008, Rev 3.1 135 WM8991 REGISTER ADDRESS R56 (38h) Anti-Pop (1) BIT 5 LABEL DIS_LLINE DEFAULT 0b DESCRIPTION Pre-Production Discharges LOP and LON outputs via approx 500 resistor 0 = Not active 1 = Actively discharging LOP and LON Discharges ROP and RON outputs via approx 500 resistor 0 = Not active 1 = Actively discharging ROP and RON Discharges OUT3 output via approx 500 resistor 0 = Not active 1 = Actively discharging OUT3 Discharges OUT4 output via approx 500 resistor 0 = Not active 1 = Actively discharging OUT4 Discharges LOUT output via approx 500 resistor 0 = Not active 1 = Actively discharging LOUT Discharges ROUT output via approx 500 resistor 0 = Not active 1 = Actively discharging ROUT 4 DIS_RLINE 0b 3 DIS_OUT3 0b 2 DIS_OUT4 0b 1 DIS_LOUT 0b 0 DIS_ROUT 0b Table 85 Output Discharge Control VMID REFERENCE DISCHARGE CONTROL The VMID reference can be discharged to AGND through internal resistors. Discharging VMID ensures that a subsequent start-up procedure commences with a known voltage condition; this is necessary in order to ensure maximum suppression of audible pops associated with start-up. VMID is discharged by setting VMIDTOG, as described in Table 86. REGISTER ADDRESS R57 (39h) Anti-Pop (2) BIT 0 LABEL VMIDTOG DEFAULT 0b DESCRIPTION Connects VMID to ground 0 = Disabled 1 = Enabled Table 86 VMID Reference Discharge Control w PP, May 2008, Rev 3.1 136 Pre-Production WM8991 EXAMPLE CONTROL SEQUENCES Pop-suppression control sequences are described below for typical WM8991 operations involving start-up, muting and disabling of signal paths. Note that these descriptions are intended for guidance only. Application software should be verified and tailored to ensure optimum performance. Start-up sequence The following sequence describes the register settings required to enable the headphone outputs LOUT and ROUT. It assumes that VMID and VREF are initially disabled and actively discharged to AGND. STEP 1 2 3 DESCRIPTION Discharge output drivers. Time delay for output capacitors to discharge. Enable soft start control and start-up bias source. Select start-up bias. Disable active discharging of VMID and Output drivers. Enable Output drivers. Enable VMID and VREF. Time delay for soft-start to execute Select default bias source. Disable soft start control and soft start voltage. POBCTRL = 0 SOFTST = 0 BUFCOPEN = 0 SOFTST = 1 BUFCOPEN = 1 POBCTRL = 1 VMIDTOG = 0 DIS_LOUT = 0 DIS_ROUT = 0 LOUT_ENA = 1 ROUT_ENA = 1 VMID_MODE = 01 VREF_ENA = 1 REGISTER SETTING DIS_LOUT = 1 DIS_ROUT = 1 4 5 6 7 8 9 Table 87 Example Start-Up Control Sequence Output Mute sequence The following sequence describes the register settings required to mute and disable the headphone outputs LOUT and ROUT. It assumes that the soft start bias voltage is initially disabled. STEP 1 2 DESCRIPTION Enable buffered VMID at all input and output circuits. Disable output drivers BUFIOEN = 1 LOUT_ENA = 0 ROUT_ENA = 0 REGISTER SETTING Table 88 Example Mute Control Sequence Output Un-Mute sequence The following sequence describes the register settings required to enable and un-mute the headphone outputs LOUT and ROUT. STEP 1 2 DESCRIPTION Enable Output drivers. Disable buffered VMID at all input and output circuits. REGISTER SETTING LOUT_ENA = 1 ROUT_ENA = 1 BUFIOEN = 0 Table 89 Example Un-Mute Control Sequence w PP, May 2008, Rev 3.1 137 WM8991 Shut-down and discharge sequence Pre-Production The following sequence describes the register settings required to mute, disable and discharge the headphone outputs LOUT and ROUT. It assumes that the soft start control and voltage source is already disabled. STEP 1 DESCRIPTION Enable soft start control and start-up bias source. Select start-up bias. Disable VMID Time delay for soft-shutdown to execute Disable Output drivers. Discharge output drivers. Select default bias source. Disable soft start control and soft start voltage. LOUT_ENA = 0 ROUT_ENA = 0 DIS_LOUT = 1 DIS_ROUT = 1 POBCTRL = 0 SOFTST = 0 BUFCOPEN = 0 REGISTER SETTING SOFTST = 1 BUFCOPEN = 1 POBCTRL = 1 VMID_MODE = 00 2 3 4 5 6 7 Table 90 Example Shut-down and Discharge Control Sequence w PP, May 2008, Rev 3.1 138 Pre-Production WM8991 POWER DOMAINS Figure 89 WM8991 Power Domains w PP, May 2008, Rev 3.1 139 Dec Addr SW_RESET_CHIP_ID[15:0] 1000_1001_1001_0000 0 LIN12_ENA ROMIX_ENA AIF_FMT[1:0] 0 0 0 0 0 DAC_CLKDIV[2:0] 0 0 BCLK_DIV[3:0] 0 DAC_COMPM ADC_COMPM DAC_COMP ADC_COMP LOOPBACK ODE ODE 0100_0000_0101_0000 0100_0000_0000_0000 0000_0001_1100_1000 00p0_0000_0000_0000 0000_0000_0100_0000 0000_0000_0100_0000 0 DACL_VOL[7:0] DACR_VOL[7:0] ADCR_DAC_SVOL[3:0] 0 0 ADCL_VOL[7:0] ADCR_VOL[7:0] 0 0 0 0 0 GPIO_STATUS[7:0] GPIO1_DEB_ GPIO1_IRQ_E ENA NA GPIO3_DEB_ GPIO3_IRQ_E ENA NA GPIO5_DEB_ GPIO5_IRQ_E ENA NA GPIO1_PU GPIO3_PU GPIO5_PU 0 GPIO1_PD GPIO3_PD GPIO5_PD GPI8_ENA GPIO1_SEL[3:0] GPIO3_SEL[3:0] GPIO5_SEL[3:0] GPI7_DEB_E GPI7_IRQ_EN NA A GPIO_POL[7:0] LI12MUTE LI34MUTE RI12MUTE IPVU[3] OPVU[0] 0 0 0 0 OPVU[1] 0 0 RI34MUTE LOZC ROZC 0 0 LONMUTE 0 LOPMUTE OUT3MUTE LOATTN OUT3ATTN LI12ZC LI34ZC RI12ZC RI34ZC 0 0 0 0 LOUTVOL[6:0] 0 ROUTVOL[6:0] 0 0 RONMUTE 0 ROPMUTE OUT4MUTE ROATTN OUT4ATTN LIN12VOL[4:0] LIN34VOL[4:0] RIN12VOL[4:0] IPVU[2] RIN34VOL[4:0] 0 GPI7_ENA 0 0 0 0 0 0 0 0 MICDET PLL_LCK 0 ADC_VU ADC_VU ADC_HPF_EN A 0 ADC_HPF_CUT[1:0] ADC_TO_DACL[1:0] 0 ADC_TO_DACR[1:0] ADCL_DATIN ADCR_DATIN V V DAC_MUTE DACL_DATIN DACR_DATIN V V 0000_0000_0000_0100 0000_000p_1100_0000 0000_000p_1100_0000 0000_0000_0000_0000 0000_0001_0000_0000 0000_000p_1100_0000 0000_000p_1100_0000 0000_0000_0000_0000 0000_pppp_pppp_pppp 0001_0000_0000_0000 0001_0000_0001_0000 0001_0000_0001_0000 1000_0000_0000_0000 0000_1000_0000_0000 0000_000p_1000_1011 0000_000p_1000_1011 0000_000p_1000_1011 0000_000p_1000_1011 0000_000p_0000_0000 0000_000p_0000_0000 0000_0000_0110_0110 0000_0000_0010_0010 0 0 DACL_ENA DACR_ENA 0000_0000_0000_0000 RIN34_ENA RIN12_ENA 0 0 ADCL_ENA ADCR_ENA 0110_0000_0000_0000 0 MICBIAS_EN A 0 VMID_MODE[1:0] VREF_ENA 0000_0000_0000_0000 0 TSHUT_ENA 0 0 DAC_BOOST[1:0] 0 DCLKDIV[2:0] 0 ADCLRC_RATE[10:0] DACLRC_RATE[10:0] AIF_LRCLKR ATE DEEMP[1:0] 0 0 0 DAC_VU 0 DAC_VU DAC_MUTER DAC_MUTEM DAC_MONO DAC_SB_FILT ATE ODE 0 ADC_CLKDIV[2:0] 0 0 0 OPCLKDIV[3:0] MCLK_DIV[1:0] MCLK_INV 0 0 DAC_SDMCL K_RATE 0 0 0 ADCL_DAC_SVOL[3:0] 0 0 0 0 IRQ GPIO2_PD GPIO4_PD GPIO6_PD 0 IRQ_INV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVU[1] 0 0 0 IPVU[0] PLL_LCK_PO TEMPOK_PO MICSHRT_PO MICDET_POL L L L GPIO6_SEL[3:0] GPIO4_SEL[3:0] GPIO2_SEL[3:0] TEMPOK MICSHRT 0 0 0 0 0 0 0 0 0 0 DACLRC_DIR ADCLRC_DIR 0 0 AIF_BCLK_IN AIF_LRCLK_I V NV AIF_WL[1:0] LON_ENA LOP_ENA RON_ENA ROP_ENA 0 SPKPGA LOPGA_ENA ROPGA_ENA LOMIX_ENA TSHUT_OPDI S 0 OPCLK_ENA 0 AINL_ENA AINR_ENA LIN34_ENA 0 SPK_ENA OUT3_ENA OUT4_ENA LOUT_ENA ROUT_ENA 0 Hex Addr Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bin Default 0 0 Reset WM8991 1 1 Power Management (1) 0 2 2 Power Management (2) PLL_ENA 3 3 Power Management (3) 0 4 DACR_SRC 0 AIFDAC_TDM_C AIFDAC_TDM HAN 4 Audio Interface (1) AIFADC_TDM_C AIFADCL_SR AIFADCR_SR AIFADC_TDM C C HAN REGISTER MAP w AIF_MSTR2 AIF_TRIS 0 0 0 0 0 0 0 0 0 GPIO2_PU GPIO4_PU GPIO6_PU 0 0 0 0 0 0 0 0 0 0 AIF_SEL 0 0 0 0 0 0 0 0 0 TEMPOK_IRQ MICSHRT_IR MICDET_IRQ PLL_LCK_IRQ GPI8_DEB_E GPI8_IRQ_EN _ENA Q_ENA _ENA _ENA NA A 0 0 0 0 0 0 0 0 0 5 5 Audio Interface (2) DACL_SRC 6 6 Clocking (1) TOCLK_RATE TOCLK_ENA 7 7 Clocking (2) MCLK_SRC SYSCLK_SRC CLK_FORCE 8 8 Audio Interface (3) AIF_MSTR1 9 9 Audio Interface (4) ALRCGPIO1 ALRCBGPIO6 10 A DAC CTRL 0 11 B Left DAC Digital Volume 0 12 C Right DAC Digital Volume 0 13 D Digital Side Tone 0 14 E ADC CTRL 0 15 F Left ADC Digital Volume 0 16 10 Right ADC Digital Volume 0 17 11 Reserved 0 18 12 GPIO CTRL 1 0 19 13 GPIO1 & GPIO2 GPIO2_DEB_ GPIO2_IRQ_E ENA NA 20 14 GPIO3 & GPIO4 GPIO4_DEB_ GPIO4_IRQ_E ENA NA 21 15 GPIO5 & GPIO6 GPIO6_DEB_ GPIO6_IRQ_E ENA NA 22 16 GPIOCTRL 2 RD_3W_ENA MODE_3W4W 23 17 GPIO_POL 0 24 18 Left Line Input 1&2 Volume 0 25 19 Left Line Input 3&4 Volume 0 26 1A Right Line Input 1&2 Volume 0 27 1B Right Line Input 3&4 Volume 0 28 1C Left Output Volume 0 29 1D Right Output Volume 0 30 1E Line Outputs Volume 0 31 1F Out3/4 Volume 0 PP, May 2008, Rev 3.1 Pre-Production 140 Note: 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LB2SPK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSEL[1:0] 0 0 0 0 0 0 0 RLI3ROVOL[2:0] LI4O3 0 0 0 0 0 0 LRI3LOVOL[2:0] 0 0 0 0 0 0 RRI3ROVOL[2:0] 0 0 0 0 0 0 LLI3LOVOL[2:0] 0 0 0 0 0 0 0 RLBRO RRBRO RLI3RO RRI3RO LR12LOVOL[2:0] RL12ROVOL[2:0] LRBLOVOL[2:0] RLBROVOL[2:0] LPGAO3 LOPLON RROPGARON RLOPGARON RB2SPK 0 0 SOFTST MCDSCTH[1:0] 0 SDM 0 PRESCALE 0 0 LI2SPK 0 DIS_LLINE 0 ROPRON RI2SPK 0 DIS_RLINE 0 MCDTHR[2:0] 0 0 PLLK[15:8] PLLK[7:0] 0 0 0 0 0 0 0 0 LOPGASPK 0 DIS_OUT3 BUFIOEN 0 LR12LOP RL12ROP ROPGASPK 0 DIS_OUT4 BUFDCOPEN MCD 0 PLLN[3:0] 0 0 0 0 0 0 0 LRBLO LLBLO LRI3LO LLI3LO LR12LO RL12RO 0 0 0 0 0 0 RI2BVOL[2:0] RL4BVOL[2:0] LL12LO RR12RO 0 0 0 0 0 0 LI2BVOL[2:0] LR4BVOL[2:0] 0 0 0 0 0 0 R34MNB R34MNBST 0 R12MNB R12MNBST 0 0 0 0 0 0 0 L34MNB L34MNBST 0 L12MNB L12MNBST 0 0 0 0 0 0 0 0 LMP4 LMN3 LMP2 LMN1 RMP4 RMN3 RMP2 LDBVOL[2:0] RDBVOL[2:0] LL4BVOL[2:0] RR4BVOL[2:0] 0 0 LL12LOVOL[2:0] RR12ROVOL[2:0] LLBLOVOL[2:0] RRBROVOL[2:0] RI4O4 LL12LOP RR12ROP LDSPK 0 DIS_LOUT POBCTRL 0 0 RPGAO4 LLOPGALOP RROPGAROP RDSPK VROI DIS_ROUT VMIDTOG MBSEL 0 LDLO RDRO 0 0 0 0 0 0 0 0 0 0 0 AINLMODE[1:0] AINRMODE[1:0] RMN1 0 0 0 0 0 0 0 SPKZC SPKVOL[6:0] 0 0 0 0 0 0 1 0 0 DCGAIN[2:0] ACGAIN[2:0] 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 CDMODE 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 SPKATTN[1:0] 0000_0000_0000_0011 0000_0000_0000_0011 0000_0000_0101_0101 0000_0001_0000_0000 0000_0000_0111_1001 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0001_1000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_1000 0000_0000_0011_0001 0000_0000_0010_0110 0000_0000_0000_0000 0 0 0 0 0 0 OPVU[3] ROPGAZC ROPGAVOL[6:0] 0000_000p_0111_1001 0 0 0 0 0 0 OPVU[2] LOPGAZC LOPGAVOL[6:0] 0000_000p_0111_1001 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bin Default Dec Addr Hex Addr Name 32 20 Left OPGA Volume 33 21 Right OPGA Volume Pre-Production 34 22 Speaker Volume 35 23 ClassD1 36 24 ClassD2 w LLOPGALON LROPGALON 37 25 ClassD3 38 26 ClassD4 39 27 Input Mixer1 40 28 Input Mixer2 41 29 Input Mixer3 42 2A Input Mixer4 43 2B Input Mixer5 44 2C Input Mixer6 45 2D Output Mixer1 46 2E Output Mixer2 47 2F Output Mixer3 48 30 Output Mixer4 49 31 Output Mixer5 50 32 Output Mixer6 51 33 Out3/4 Mixer 52 34 Line Mixer1 53 35 Line Mixer2 54 36 Speaker Mixer 55 37 Additional Control 56 38 AntiPOP1 57 39 AntiPOP2 58 3A MICBIAS 59 3B Reserved A bin default value of `p' indicates a register field where a default value is not applicable e.g. a volume update bit. 60 3C PLL1 61 3D PLL2 62 3E PLL3 63 3F Reserved PP, May 2008, Rev 3.1 WM8991 141 WM8991 REGISTER BITS BY ADDRESS REGISTER ADDRESS R0 (00h) Reset / ID BIT 15:0 LABEL SW_RESET_CHIP_ ID [15:0] (rr) SPK_ENA (rw) OUT3_ENA (rw) OUT4_ENA (rw) LOUT_ENA (rw) ROUT_ENA (rw) DEFAULT 8990h DESCRIPTION Pre-Production Writing to this register resets all registers to their default state. Reading from this register will indicate device family ID 8990h. R1 (01h) Power Management (1) 15:13 12 000b 0b Reserved - Do Not Change SPKMIX Mixer, Speaker PGA and Speaker Output Enable 0 = disabled 1 = enabled OUT3 and OUT3MIX Enable 0 = disabled 1 = enabled OUT4 and OUT4MIX Enable 0 = disabled 1 = enabled LOUT (Left Headphone Output) Enable 0 = disabled 1 = enabled ROUT (Right Headphone Output) Enable 0 = disabled 1 = enabled Reserved - Do Not Change MICBIAS Enable 0 = OFF (high impedance output) 1 = ON Reserved - Do Not Change Vmid Divider Enable and Select 00 = Vmid disabled (for OFF mode) 01 = 2 x 50k divider (Normal mode) 10 = 2 x 250k divider (Standby mode) 11 = 2 x 5k divider (for fast start-up) VREF Enable (Bias for all analogue functions) 0 = VREF bias disabled 1 = VREF bias enabled PLL Enable 0 = disabled 1 = enabled Thermal Sensor Enable 0 = Thermal sensor disabled 1 = Thermal sensor enabled Thermal Shutdown Enable (Requires thermal sensor to be enabled) 0 = Thermal shutdown disabled 1 = Thermal shutdown enabled Reserved - Do Not Change GPIO Clock Output Enable 0 = disabled 1 = enabled Reserved - Do Not Change 11 0b 10 0b 9 0b 8 0b 7:5 4 MICBIAS_ENA (rw) 000b 0b 3 2:1 VMID_MODE [1:0] (rw) 0b 00b 0 VREF_ENA (rw) PLL_ENA (rw) TSHUT_ENA (rw) TSHUT_OPDIS (rw) 0b R02 (02h) Power Management (2) 15 0b 14 1b 13 1b 12 11 OPCLK_ENA (rw) 0b 0b 10 0b w PP, May 2008, Rev 3.1 142 Pre-Production REGISTER ADDRESS 9 BIT LABEL AINL_ENA (rw) DEFAULT 0b DESCRIPTION WM8991 Left Input Path Enable (Enables AINLMUX, INMIXL, DIFFINL and RXVOICE input to AINLMUX) 0 = disabled 1 = enabled Right Input Path Enable (Enables AINRMUX, INMIXR, DIFFINR and RXVOICE input to AINRMUX) 0 = disabled 1 = enabled LIN34 Input PGA Enable 0 = disabled 1 = enabled LIN12 Input PGA Enable 0 = disabled 1 = enabled RIN34 Input PGA Enable 0 = disabled 1 = enabled RIN12 Input PGA Enable 0 = disabled 1 = enabled Reserved - Do Not Change Left ADC Enable 0 = disabled 1 = enabled Right ADC Enable 0 = disabled 1 = enabled Reserved - Do Not Change LON Line Out and LONMIX Enable 0 = disabled 1 = enabled LOP Line Out and LOPMIX Enable 0 = disabled 1 = enabled RON Line Out and RONMIX Enable 0 = disabled 1 = enabled ROP Line Out and ROPMIX Enable 0 = disabled 1 = enabled Reserved - Do Not Change SPKMIX Mixer and Speaker PGA Enable 0 = disabled 1 = enabled Note that SPKMIX and SPKPGA are also enabled when SPK_ENA is set. LOPGA Left Volume Control Enable 0 = disabled 1 = enabled ROPGA Right Volume Control Enable 0 = disabled 1 = enabled PP, May 2008, Rev 3.1 143 8 AINR_ENA (rw) 0b 7 LIN34_ENA (rw) LIN12_ENA (rw) RIN34_ENA (rw) RIN12_ENA (rw) 0b 6 0b 5 0b 4 0b 3:2 1 ADCL_ENA (rw) ADCR_ENA (rw) 00b 0b 0 0b R03 (03h) Power Management (3) 15:14 13 LON_ENA (rw) LOP_ENA (rw) RON_ENA (rw) ROP_ENA (rw) 00b 0b 12 0b 11 0b 10 0b 9 8 SPKPGA_ENA (rw) 0b 0b 7 LOPGA_ENA (rw) ROPGA_ENA (rw) 0b 6 0b w WM8991 REGISTER ADDRESS 5 BIT LABEL LOMIX_ENA (rw) ROMIX_ENA (rw) DEFAULT 0b DESCRIPTION LOMIX Left Output Mixer Enable 0 = disabled 1 = enabled ROMIX Right Output Mixer Enable 0 = disabled 1 = enabled Reserved - Do Not Change Left DAC Enable 0 = disabled 1 = enabled Right DAC Enable 0 = disabled 1 = enabled Left Digital Audio channel source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel Right Digital Audio channel source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel ADC TDM Enable 0 = Normal ADCDAT operation 1 = TDM enabled on ADCDAT ADCDAT TDM Channel Select 0 = ADCDAT outputs data on slot 0 1 = ADCDAT output data on slot 1 Reserved - Do Not Change BCLK Invert 0 = BCLK not inverted 1 = BCLK inverted Right, left and I2S modes - LRCLK polarity 0 = normal LRCLK polarity 1 = invert LRCLK polarity Pre-Production 4 0b 3:2 1 DACL_ENA (rw) DACR_ENA (rw) AIFADCL_SRC 00b 0b 0 0b R04 (04h) Audio Interface (1) 15 0b 14 AIFADCR_SRC 1b 13 AIFADC_TDM 0b 12 AIFADC_TDM_ CHAN 0b 11:9 8 AIF_BCLK_INV 0b 0b 7 AIF_LRCLK_INV 0b DSP Mode - mode A/B select 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) 6:5 AIF_WL [1:0] 10b Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits Digital Audio Interface Format 00 = Right justified 01 = Left justified 10 = I2S Format 11 = DSP Mode Reserved - Do Not Change Left DAC Data Source Select 0 = Left DAC outputs left channel data 1 = Left DAC outputs right channel data Right DAC Data Source Select 0 = Right DAC outputs left channel data 1 = Right DAC outputs right channel data PP, May 2008, Rev 3.1 144 4:3 AIF_FMT [1:0] 10b 2:0 R05 (05h) Audio Interface (2) 15 DACL_SRC 0b 0b 14 DACR_SRC 1b w Pre-Production REGISTER ADDRESS BIT 13 LABEL AIFDAC_TDM DEFAULT 0b DESCRIPTION DAC TDM Enable 0 = Normal DACDAT operation 1 = TDM enabled on DACDAT DACDAT TDM Channel Select 0 = DACDAT data input on slot 0 1 = DACDAT data input on slot 1 DAC Input Volume Boost 00 = 0dB 01 = +6dB (Input data must not exceed -6dBFS) 10 = +12dB (Input data must not exceed -12dBFS) 11 = +18dB (Input data must not exceed -18dBFS) Reserved - Do Not Change DAC_COMP 0b DAC Companding Enable 0 = disabled 1 = enabled DAC Companding Type 0 = -law 1 = A-law ADC Companding Enable 0 = disabled 1 = enabled ADC Companding Type 0 = -law 1 = A-law WM8991 12 AIFDAC_TDM_ CHAN DAC_BOOST [1:0] 0b 11:10 00b 9:5 4 3 DAC_COMPMODE 0b 2 ADC_COMP 0b 1 ADC_COMPMODE 0b 0 LOOPBACK 0b Digital Loopback Function 0 = No loopback 1 = Loopback enabled (ADC data output is directly input to DAC data input). Note: ADC and DAC left/right clocks must be set to the same pin when using LOOPBACK function (ALRCGPIO1=1) Timeout Clock Rate (Selects clock to be used for volume update timeout and GPIO input de-bounce) 0 = SYSCLK / 221 (Slower Response) 19 1 = SYSCLK / 2 (Faster Response) Timeout Clock Enable (This clock is required for volume update timeout and GPIO input de-bounce) 0 = disabled 1 = enabled Reserved - Do Not Change GPIO Output Clock Divider 0000 = SYSCLK 0001 = SYSCLK / 2 0010 = SYSCLK / 3 0011 = SYSCLK / 4 0100 = SYSCLK / 5.5 0101 = SYSCLK / 6 0110 = SYSCLK / 8 0111 = SYSCLK / 12 1000 = SYSCLK / 16 1001 to 1111 = Reserved R06 (06h) Clocking (1) 15 TOCLK_RATE 0b 14 TOCLK_ENA 0b 13 12:9 OPCLKDIV [3:0] 0000b w PP, May 2008, Rev 3.1 145 WM8991 REGISTER ADDRESS BIT 8:6 LABEL DCLKDIV [2:0] DEFAULT 111b Class D Clock Divider 000 = SYSCLK 001 = SYSCLK / 2 010 = SYSCLK / 3 011 = SYSCLK / 4 100 = SYSCLK / 6 101 = SYSCLK / 8 110 = SYSCLK / 12 111 = SYSCLK / 16 Reserved - Do Not Change BCLK Frequency (Master Mode) 0000 = SYSCLK 0001 = SYSCLK / 1.5 0010 = SYSCLK / 2 0011 = SYSCLK / 3 0100 = SYSCLK / 4 0101 = SYSCLK / 5.5 0110 = SYSCLK / 6 0111 = SYSCLK / 8 1000 = SYSCLK / 11 1001 = SYSCLK / 12 1010 = SYSCLK / 16 1011 = SYSCLK / 22 1100 = SYSCLK / 24 1101 = SYSCLK / 32 1110 = SYSCLK / 44 1111 = SYSCL:K / 48 Reserved - Do Not Change MCLK Source Select 0 = MCLK pin 1 = GPIO2/MCLK2 pin SYSCLK Source Select 0 = MCLK (or MCLK2 if MCLK_SRC=1) 1 = PLL output DESCRIPTION Pre-Production 5 4:1 BCLK_DIV [3:0] 0b 0100b 0 R07 (07h) Clocking (2) 15 MCLK_SRC 0b 0b 14 SYSCLK_SRC 0b 13 CLK_FORCE 0b Forces Clock Source Selection 0 = Existing SYSCLK source (MCLK, MCLK2 or PLL output) must be active when changing to a new clock source. 1 = Allows existing MCLK source to be disabled before changing to a new clock source. SYSCLK Pre-divider. Clock source (MCLK, MCLK2 or PLL output) will be divided by this value to generate SYSCLK. 00 = Divide SYSCLK by 1 01 = Reserved 10 = Divide SYSCLK by 2 11 = Reserved MCLK Invert 0 = Master clock (MCLK or MCLK2) not inverted 1 = Master clock (MCLK or MCLK2) inverted Reserved - Do Not Change 12:11 MCLK_DIV [1:0] 00b 10 MCLK_INV 0b 9:8 00b w PP, May 2008, Rev 3.1 146 Pre-Production REGISTER ADDRESS BIT 7:5 LABEL ADC_CLKDIV [2:0] DEFAULT 000b DESCRIPTION ADC Sample Rate Divider 000 = SYSCLK / 1.0 001 = SYSCLK / 1.5 010 = SYSCLK / 2.0 011 = SYSCLK / 3.0 100 = SYSCLK / 4.0 101 = SYSCLK / 5.5 110 = SYSCLK / 6.0 111= Reserved DAC Sample Rate Divider 000 = SYSCLK / 1.0 001 = SYSCLK / 1.5 010 = SYSCLK / 2.0 011 = SYSCLK / 3.0 100 = SYSCLK / 4.0 101 = SYSCLK / 5.5 110 = SYSCLK / 6.0 111= Reserved Reserved - Do Not Change Audio Interface 1 Master Mode Select 0 = Slave mode 1 = Master mode Audio Interface 2 Master Mode Select 0 = Slave mode 1 = Master mode WM8991 4:2 DAC_CLKDIV [2:0] 000b 1:0 R08 (08h) Audio Interface (3) 15 AIF_MSTR1 00b 0b 14 AIF_MSTR2 0b 13 AIF_SEL 0b Audio Interface Select 0 = Audio interface 1 1 = Audio interface 2 (GPIO3/BCLK2, GPIO4/DACLRC2, GPIO5/DACDAT2) Reserved - Do Not Change ADCLRC Direction (Forces ADCLRC clock to be output in slave mode) 0 = ADCLRC normal operation 1 = ADCLRC clock output enabled ADCLRC Rate ADCLRC clock output = BCLK / ADCLRC_RATE Integer (LSB = 1) Valid from 8..2047 12 11 ADCLRC_DIR 0b 0b 10:0 ADCLRC_RATE [10:0] 040h R09 (09h) Audio Interface (4) 15 ALRCGPIO1 0b ADCLRC/GPIO1 Pin Function Select 0 = ADCLRC pin 1 = GPIO1 pin (ADCLRC connected to DACLRC internally) GPIO6/ADCLRCB Pin Function Select 0 = GPIO6 pin 1 = Inverted ADCLRC clock output Audio Interface and GPIO Tristate 0 = Audio interface and GPIO pins operate normally 1 = Tristate all audio interface and GPIO pins Reserved - Do Not Change DACLRC Direction (Forces DACLRC clock to be output in slave mode) 0 = DACLRC normal operation 1 = DACLRC clock output enabled 14 ALRCBGPIO6 0b 13 AIF_TRIS 0b 12 11 DACLRC_DIR 0b 0b w PP, May 2008, Rev 3.1 147 WM8991 REGISTER ADDRESS BIT 10:0 LABEL DACLRC_RATE [10:0] DEFAULT 040h DESCRIPTION DACLRC Rate DACLRC clock output = BCLK / DACLRC_RATE Integer (LSB = 1) Valid from 8..2047 R10 (0Ah) DAC Control 15:13 12 DAC_SDMCLK_ RATE 000b 0b Reserved - Do Not Change DAC clocking rate 0 = Normal operation (64fs) 1 = SYSCLK/4 Reserved - Do Not Change LRCLK Rate 0 = Normal mode (256 * fs) 1 = USB mode (272 * fs) DAC Mono Mix 0 = Stereo 1 = Mono (Mono mix output on enabled DACs) Selects DAC filter characteristics 0 = Normal mode 1 = Sloping stopband mode Pre-Production 11 10 AIF_LRCLKRATE 0b 0b 9 DAC_MONO 0b 8 DAC_SB_FILT 0b 7 DAC_MUTERATE 0b DAC Soft Mute Ramp Rate 0 = Fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48k) 1 = Slow ramp (fs/32, maximum ramp time is 171ms at fs=48k) DAC Soft Mute Mode 0 = Disabling soft-mute (DAC_MUTE=0) will cause the DAC volume to change immediately to DACL_VOL and DACR_VOL settings 1 = Disabling soft-mute (DAC_MUTE=0) will cause the DAC volume to ramp up gradually to the DACL_VOL and DACR_VOL settings DAC De-Emphasis Control 00 = De-emphasis disabled 01 = De-emphasis enabled (Optimised for fs=32kHz) 10 = De-emphasis enabled (Optimised for fs=44.1kHz) 11 = De-emphasis enabled (Optimised for fs=48kHz) Reserved - Do Not Change DAC Soft Mute Control 0 = DAC Un-mute 1 = DAC Mute Left DAC Invert 0 = Left DAC output not inverted 1 = Left DAC output inverted Right DAC Invert 0 = Right DAC output not inverted 1 = Right DAC output inverted Reserved - Do Not Change DAC Volume Update Writing a 1 to this bit will cause left and right DAC volume to be updated simultaneously Left DAC Digital Volume (See Table 26 for volume settings) Reserved - Do Not Change 6 DAC_MUTEMODE 0b 5:4 DEEMP 00b 3 2 DAC_MUTE 0b 1b 1 DACL_DATINV 0b 0 DACR_DATINV 0b R11 (0Bh) Left DAC Digital Volume 15:9 8 DAC_VU 00h N/A 7:0 DACL_VOL [7:0] 1100_000 0b (0dB) 00h R12 (0Ch) 15:9 w PP, May 2008, Rev 3.1 148 Pre-Production REGISTER ADDRESS Right DAC Digital Volume 8 BIT LABEL DAC_VU DEFAULT N/A DESCRIPTION WM8991 DAC Volume Update Writing a 1 to this bit will cause left and right DAC volume to be updated simultaneously Right DAC Digital Volume (See Table 26 for volume settings) Reserved - Do Not Change Left Channel Digital Sidetone Volume (See Table 23 for volume range) Right Channel Digital Sidetone Volume (See Table 23 for volume range) Reserved - Do Not Change Left DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = Reserved Right DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = Reserved Reserved - Do Not Change ADC Digital High Pass Filter Enable 0 = disabled 1 = enabled Reserved - Do Not Change ADC Digital High Pass Filter Cut-Off Frequency (fc) 00 = Hi-fi mode (fc=4Hz at fs=48kHz) 01 = Voice mode 1 (fc=127Hz at fs=16kHz) 10 = Voice mode 2 (fc=130Hz at fs=8kHz) 11 = Voice mode 3 (fc=267Hz at fs=8kHz) (Note: fc scales with sample rate. See Table 18 for cut-off frequencies at all supported sample rates) Reserved - Do Not Change Left ADC Invert 0 = Left ADC output not inverted 1 = Left ADC output inverted Right ADC Invert 0 = Right ADC output not inverted 1 = Right ADC output inverted Reserved - Do Not Change ADC Volume Update Writing a 1 to this bit will cause left and right ADC volume to be updated simultaneously Left ADC Digital Volume (See Table 16 for volume range) Reserved - Do Not Change ADC Volume Update Writing a 1 to this bit will cause left and right ADC volume to be updated simultaneously 7:0 DACR_VOL [7:0] 1100_ 0000b (0dB) 000b 0000b 0000b 0b R13 (0Dh) Digital Sidetone 15:13 12:9 8:5 4 3:2 ADC_TO_DACL [1:0] ADCL_DAC_SVOL [3:0] ADCR_DAC_SVOL [3:0] 00b 1:0 ADC_TO_DACR [1:0] 00b R14 (0Eh) ADC Control 15:9 8 ADC_HPF_ENA 00h 1b 7 6:5 ADC_HPF_CUT [1:0] 0b 00b 4:2 1 ADCL_DATINV 000b 0b 0 ADCR_DATINV 0b R15 (0Fh) Left ADC Digital Volume 15:9 8 ADC_VU 00h N/A 7:0 ADCL_VOL [7:0] 1100_ 0000b (0dB) 00h N/A R16 (10h) Right ADC Digital Volume 15:9 8 ADC_VU w PP, May 2008, Rev 3.1 149 WM8991 REGISTER ADDRESS BIT 7:0 LABEL ADCR_VOL [7:0] DEFAULT 1100_ 0000b (0dB) 0000h 0dB IRQ (ro) TEMPOK (rr) Read Only Read or Reset DESCRIPTION Right ADC Digital Volume (See Table 16 for volume range) Reserved - Do Not Change Reserved - Do Not Change IRQ Readback (Allows polling of IRQ status) Temperature OK status Read0 = Device temperature NOT ok 1 = Device temperature ok Write 1 = Reset TEMPOK latch MICBIAS short status Read0 = MICBIAS ok 1 = MICBIAS shorted Write1 = Reset MICSHRT latch MICBIAS detect status MICBIAS microphone detect Readback Read0 = No Microphone detected 1 = Microphone detected Write1 = Reset MICDET latch PLL Lock status Read0 = PLL NOT locked 1 = PLL locked Write1 = Reset PLL_LCK latch GPIO and GPI Input Pin Status GPIO_STATUS[7] = GPI8 pin status GPIO_STATUS[6] = GPI7 pin status GPIO_STATUS[5] = GPIO6 pin status GPIO_STATUS[4] = GPIO5 pin status GPIO_STATUS[3] = GPIO4 pin status GPIO_STATUS[2] = GPIO3 pin status GPIO_STATUS[1] = GPIO2 pin status GPIO_STATUS[0] = GPIO1 pin status Pre-Production R17 (11h) R18 (12h) GPIO Control (1) 15:0 15:13 12 11 10 MICSHRT (rr) Read or Reset 9 MICDET (rr) Read or Reset 8 PLL_LCK (rr) Read or Reset 7:0 GPIO_STATUS [7:0] (rr) Read or Reset R19 (13h) GPIO1 and GPIO2 15 GPIO2_DEB_ENA 0b GPIO2 Input De-Bounce 0 = disabled (Not de-bounced) 1 = enabled (Requires MCLK input and TOCLK_ENA=1) GPIO2 IRQ Enable 0 = disabled 1 = enabled (GPIO2 input will generate IRQ) GPIO2 Pull-Up Resistor Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 150k) GPIO2 Pull-Down Resistor Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 150k) 14 GPIO2_IRQ_ENA 0b 13 GPIO2_PU 0b 12 GPIO2_PD 1b w PP, May 2008, Rev 3.1 150 Pre-Production REGISTER ADDRESS BIT 11:8 LABEL GPIO2_SEL [3:0] DEFAULT 0000b DESCRIPTION GPIO2 Function Select 0000 = Input pin 0001 = Clock output (f=SYSCLK/OPCLKDIV) 0010 = Logic '0' 0011 = Logic '1' 0100 = PLL Lock output 0101 = Temperature OK output 0110 = SDOUT data output 0111 = IRQ output 1000 = MIC Detect 1001 = MIC Short Circuit Detect 1010 to 1111 = Reserved WM8991 7 GPIO1_DEB_ENA 0b GPIO1 Input De-Bounce 0 = disabled (Not de-bounced) 1 = enabled (Requires MCLK input and TOCLK_ENA=1) GPIO1 IRQ Enable 0 = disabled 1 = enabled (GPIO1 input will generate IRQ) GPIO1 Pull-Up Resistor Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 150k) GPIO1 Pull-Down Resistor Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 150k) GPIO1 Function Select 0000 = Input pin 0001 = Clock output (f=SYSCLK/OPCLKDIV) 0010 = Logic '0' 0011 = Logic '1' 0100 = PLL Lock output 0101 = Temperature OK output 0110 = SDOUT data output 0111 = IRQ output 1000 = MIC Detect 1001 = MIC Short Circuit Detect 1010 to 1111 = Reserved GPIO4 Input De-Bounce 0 = disabled (Not de-bounced) 1 = enabled (Requires MCLK input and TOCLK_ENA=1) GPIO4 IRQ Enable 0 = disabled 1 = enabled (GPIO4 input will generate IRQ) GPIO4 Pull-Up Resistor Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 150k) GPIO4 Pull-Down Resistor Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 150k) 6 GPIO1_IRQ_ENA 0b 5 GPIO1_PU 0b 4 GPIO1_PD 0b 3:0 GPIO1_SEL [3:0] 0000b R20 (14h) GPIO3 and GPIO4 15 GPIO4_DEB_ENA 0b 14 GPIO4_IRQ_ENA 0b 13 GPIO4_PU 0b 12 GPIO4_PD 1b w PP, May 2008, Rev 3.1 151 WM8991 REGISTER ADDRESS BIT 11:8 LABEL GPIO4_SEL [3:0] DEFAULT 0000b DESCRIPTION GPIO4 Function Select 0000 = Input pin 0001 = Clock output (f=SYSCLK/OPCLKDIV) 0010 = Logic '0' 0011 = Logic '1' 0100 = PLL Lock output 0101 = Temperature OK output 0110 = SDOUT data output 0111 = IRQ output 1000 = MIC Detect 1001 = MIC Short Circuit Detect 1010 to 1111 = Reserved Pre-Production 7 GPIO3_DEB_ENA 0b GPIO3 Input De-Bounce 0 = disabled (Not de-bounced) 1 = enabled (Requires MCLK input and TOCLK_ENA=1) GPIO3 IRQ Enable 0 = disabled 1 = enabled (GPIO3 input will generate IRQ) GPIO3 Pull-Up Resistor Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 150k) GPIO3 Pull-Down Resistor Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 150k) GPIO3 Function Select 0000 = Input pin 0001 = Clock output (f=SYSCLK/OPCLKDIV) 0010 = Logic '0' 0011 = Logic '1' 0100 = PLL Lock output 0101 = Temperature OK output 0110 = SDOUT data output 0111 = IRQ output 1000 = MIC Detect 1001 = MIC Short Circuit Detect 1010 to 1111 = Reserved GPIO6 Input De-Bounce 0 = disabled (Not de-bounced) 1 = enabled (Requires MCLK input and TOCLK_ENA=1) GPIO6 IRQ Enable 0 = disabled 1 = enabled (GPIO6 input will generate IRQ) GPIO6 Pull-Up Resistor Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 150k) GPIO6 Pull-Down Resistor Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 150k) 6 GPIO3_IRQ_ENA 0b 5 GPIO3_PU 0b 4 GPIO3_PD 1b 3:0 GPIO3_SEL [3:0] 0000b R21 (15h) GPIO5 and GPIO6 15 GPIO6_DEB_ENA 0b 14 GPIO6_IRQ_ENA 0b 13 GPIO6_PU 0b 12 GPIO6_PD 1b w PP, May 2008, Rev 3.1 152 Pre-Production REGISTER ADDRESS BIT 11:8 LABEL GPIO6_SEL [3:0] DEFAULT 0000b DESCRIPTION GPIO6 Function Select 0000 = Input pin 0001 = Clock output (f=SYSCLK/OPCLKDIV) 0010 = Logic '0' 0011 = Logic '1' 0100 = PLL Lock output 0101 = Temperature OK output 0110 = SDOUT data output 0111 = IRQ output 1000 = MIC Detect 1001 = MIC Short Circuit Detect 1010 to 1111 = Reserved WM8991 7 GPIO5_DEB_ENA 0b GPIO5 Input De-Bounce 0 = disabled (Not de-bounced) 1 = enabled (Requires MCLK input and TOCLK_ENA=1) GPIO5 IRQ Enable 0 = disabled 1 = enabled (GPIO5 input will generate IRQ) GPIO5 Pull-Up Resistor Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 150k) GPIO5 Pull-Down Resistor Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 150k) GPIO5 Function Select 0000 = Input pin 0001 = Clock output (f=SYSCLK/OPCLKDIV) 0010 = Logic '0' 0011 = Logic '1' 0100 = PLL Lock output 0101 = Temperature OK output 0110 = SDOUT data output 0111 = IRQ output 1000 = MIC Detect 1001 = MIC Short Circuit Detect 1010 to 1111 = Reserved 3- / 4-wire readback configuration 1 = 3-wire mode 0 = 4-wire mode, using GPIO pin 3-wire mode 0 = push 0/1 1 = open-drain 4-wire mode 0 = push 0/1 1 = wired-OR Reserved - Do Not Change Temperature Sensor IRQ Enable 0 = disabled 1 = enabled MICBIAS short circuit detect IRQ Enable 0 = disabled 1 = enabled 6 GPIO5_IRQ_ENA 0b 5 GPIO5_PU 0b 4 GPIO5_PD 1b 3:0 GPIO5_SEL [3:0] 0000b R22 (16h) GPI7 and GPI8 15 RD_3W_ENA 1b 14 MODE_3W4W 0b 13:12 11 TEMPOK_IRQ_ENA 00b 0b 10 MICSHRT_IRQ_ ENA 0b w PP, May 2008, Rev 3.1 153 WM8991 REGISTER ADDRESS 9 BIT LABEL MICDET_IRQ_ENA DEFAULT 0b DESCRIPTION MICBIAS current detect IRQ Enable 0 = disabled 1 = enabled PLL Lock IRQ Enable 0 = disabled 1 = enabled Pre-Production 8 PLL_LCK_IRQ_ENA 0b 7 GPI8_DEB_ENA 0b GPI8 Input De-Bounce 0 = disabled (Not de-bounced) 1 = enabled (Requires MCLK input and TOCLK_ENA=1) GPI8 IRQ Enable 0 = disabled 1 = enabled (GPI8 input will generate IRQ) Reserved - Do Not Change GPI8 Input Pin Enable 0 = RIN3/GPI8 pin disabled as GPI8 input 1 = RIN3/GPI8 pin enabled as GPI8 input GPI7 Input De-Bounce 0 = disabled (Not de-bounced) 1 = enabled (Requires MCLK input and TOCLK_ENA=1) GPI7 IRQ Enable 0 = disabled 1 = enabled (GPI7 input will generate IRQ) Reserved - Do Not Change GPI7 Input Pin Enable 0 = LIN3/GPI7 pin disabled as GPI7 input 1 = LIN3/GPI7 pin enabled as GPI7 input Reserved - Do Not Change IRQ Invert 0 = IRQ output active high 1 = IRQ output active low Temperature Sensor polarity 0 = Non-inverted 1 = Inverted MICBIAS short circuit detect polarity 0 = Non-inverted 1 = Inverted MICBIAS current detect polarity 0 = Non-inverted 1 = Inverted PLL Lock Polarity 0 = Non-inverted 1 = Inverted GPIOn Input Polarity 0 = Non-inverted 1 = Inverted GPIO_POL[7]: GPI8 polarity GPIO_POL[6]: GPI7 polarity GPIO_POL[5]: GPIO6 polarity GPIO_POL[4]: GPIO5 polarity GPIO_POL[3]: GPIO4 polarity GPIO_POL[2]: GPIO3 polarity GPIO_POL[1]: GPIO2 polarity GPIO_POL[0]: GPIO1 polarity Reserved - Do Not Change PP, May 2008, Rev 3.1 154 6 GPI8_IRQ_ENA 0b 5 4 GPI8_ENA 0b 0b 3 GPI7_DEB_ENA 0b 2 GPI7_IRQ_ENA 0b 1 0 GPI7_ENA 0b 0b R23 (17h) GPIO Control (2) 15:13 12 IRQ_INV (rw) TEMPOK_POL (rw) MICSHRT_POL (rw) MICDET_POL (rw) PLL_LCK_POL (rw) GPIO_POL[7:0] (rw) 0000b 0b 11 1b 10 0b 9 0b 8 0b 7:0 00h R24 (18h) 15:9 00h w Pre-Production REGISTER ADDRESS LIN12 Input PGA Volume 8 BIT LABEL IPVU[0] DEFAULT N/A DESCRIPTION WM8991 Input PGA Volume Update Writing a 1 to this bit will cause all input PGA volumes to be updated simultaneously (LIN12, LIN34, RIN12 and RIN34) LIN12 PGA Mute 0 = Disable Mute 1 = Enable Mute LIN12 PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only Reserved - Do Not Change LIN12 Volume (See Table 6 for PGA volume range) Reserved - Do Not Change Input PGA Volume Update Writing a 1 to this bit will cause all input PGA volumes to be updated simultaneously (LIN12, LIN34, RIN12 and RIN34) LIN34 PGA Mute 0 = Disable Mute 1 = Enable Mute LIN34 PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only Reserved - Do Not Change LIN34 Volume (See Table 6 for PGA volume range) Reserved - Do Not Change Input PGA Volume Update Writing a 1 to this bit will cause all input PGA volumes to be updated simultaneously (LIN12, LIN34, RIN12 and RIN34) RIN12 PGA Mute 0 = Disable Mute 1 = Enable Mute RIN12 PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only Reserved - Do Not Change RIN12 Volume (See Table 6 for PGA volume range) Reserved - Do Not Change Input PGA Volume Update Writing a 1 to this bit will cause all input PGA volumes to be updated simultaneously (LIN12, LIN34, RIN12 and RIN34) RIN34 PGA Mute 0 = Disable Mute 1 = Enable Mute RIN34 PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only Reserved - Do Not Change RIN34 Volume (See Table 6 for PGA volume range) 7 LI12MUTE 1b 6 LI12ZC 0b 5 4:0 R25 (19h) LIN34 Input PGA Volume 15:9 8 IPVU[1] LIN12VOL [4:0] 0b 01011b 00h N/A 7 LI34MUTE 1b 6 LI34ZC 0b 5 4:0 R26 (1Ah) RIN12 Input PGA Volume 15:9 8 IPVU[2] LIN34VOL [4:0] 0b 01011b 00h N/A 7 RI12MUTE 1b 6 RI12ZC 0b 5 4:0 R27 (1Bh) RIN34 Input PGA Volume 15:9 8 IPVU[3] RIN12VOL [4:0] 0b 01011b 00h N/A 7 RI34MUTE 1b 6 RI34ZC 0b 5 4:0 RIN34VOL [4:0] 0b 01011b w PP, May 2008, Rev 3.1 155 WM8991 REGISTER ADDRESS R28 (1Ch) Left Headphone Output Volume 8 BIT 15:9 OPVU[0] LABEL DEFAULT 00h N/A DESCRIPTION Reserved - Do Not Change Pre-Production Output PGA Volume Update Writing a 1 to this bit will update LOPGA, ROPGA, LOUTVOL and ROUTVOL volumes simultaneously. Left Headphone Output Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled Left Headphone Output Volume (See Table 36 for output PGA volume control range) Reserved - Do Not Change Output PGA Volume Update Writing a 1 to this bit will update LOPGA, ROPGA, LOUTVOL and ROUTVOL volumes simultaneously. Right Headphone Output Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled Right Headphone Output Volume (See Table 36 for output PGA volume control range) Reserved - Do Not Change LON Line Output Mute 0 = Un-mute 1 = Mute LOP Line Output Mute 0 = Un-mute 1 = Mute LOP Attenuation 0 = 0dB 1 = -6dB Reserved - Do Not Change RON Line Output Mute 0 = Un-mute 1 = Mute ROP Line Output Mute 0 = Un-mute 1 = Mute ROP Attenuation 0 = 0dB 1 = -6dB Reserved - Do Not Change OUT3 Mute 0 = Un-mute 1 = Mute OUT3 Attenuation 0 = 0dB 1 = -6dB Reserved - Do Not Change OUT4 Mute 0 = Un-mute 1 = Mute OUT4 Attenuation 0 = 0dB 1 = -6dB Reserved - Do Not Change PP, May 2008, Rev 3.1 156 7 LOZC 0b 6:0 R29 (1Dh) Right Headphone Output Volume 15:9 8 LOUTVOL [6:0] OPVU[1] 00h (mute) 00h N/A 7 ROZC 0b 6:0 R30 (1Eh) Line Output Volume 15:7 6 ROUTVOL [6:0] LONMUTE 00h (mute) 000h 1b 5 LOPMUTE 1b 4 LOATTN 0b 3 2 RONMUTE 0b 1b 1 ROPMUTE 1b 0 ROATTN 0b R31 (1Fh) OUT3 and OUT4 Volume 15:6 5 OUT3MUTE 00000000 00b 1b 4 OUT3ATTN 0b 3:2 1 OUT4MUTE 00b 1b 0 OUT4ATTN 0b R32 (20h) 15:9 00h w Pre-Production REGISTER ADDRESS LOPGA Volume 8 BIT LABEL OPVU[2] DEFAULT N/A DESCRIPTION WM8991 Output PGA Volume Update Writing a 1 to this bit will update LOPGA, ROPGA, LOUTVOL and ROUTVOL volumes simultaneously. LOPGA Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled LOPGA Volume (See Table 36 for output PGA volume control range) Reserved - Do Not Change Output PGA Volume Update Writing a 1 to this bit will update LOPGA, ROPGA, LOUTVOL and ROUTVOL volumes simultaneously. ROPGA Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled ROPGA Volume (See Table 36 for output PGA volume control range) Reserved - Do Not Change Speaker Output Attenuation (SPKN and SPKP) 00 = 0dB 01 = -6dB 10 = -12dB 11 = mute Reserved - Do Not Change Speaker Class D Mode Enable 0 = Class D mode 1 = Class AB mode Reserved - Do Not Change Reserved - Do Not Change Reserved - Do Not Change DC Speaker Boost 000 = 1.00x boost (+0dB) 001 = 1.27x boost (+2.1dB) 010 = 1.40x boost (+2.9dB) 011 = 1.52x boost (+3.6dB) 100 = 1.67x boost (+4.5dB) 101 = 1.8x boost (+5.1dB) 110 to 111 = Reserved AC Speaker Boost 000 = 1.00x boost (+0dB) 001 = 1.27x boost (+2.1dB) 010 = 1.40x boost (+2.9dB) 011 = 1.52x boost (+3.6dB) 100 = 1.67x boost (+4.5dB) 101 = 1.8x boost (+5.1dB) 110 to 111 = Reserved Reserved - Do Not Change SPKPGA Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled 7 LOPGAZC 0b 6:0 R33 (21h) ROPGA Volume 15:9 8 LOPGAVOL [6:0] OPVU[3] 79h (0dB) 00h N/A 7 ROPGAZC 0b 6:0 R34 (22h) Speaker Volume 15:2 1:0 ROPGAVOL [6:0] SPKATTN [1:0] 79h (0dB) 0000h 11b R35 (23h) Class D (1) 15:9 8 CDMODE 00h 0b 7:0 R36 (24h) Class D (2) R37 (25h) Class D (3) 15:0 15:6 5:3 DCGAIN [2:0] 00000011 b 0055h 00000001 00b 000b 2:0 ACGAIN [2:0] 000b R38 (26h) Class D (4) 15:8 7 SPKZC 00h 0b w PP, May 2008, Rev 3.1 157 WM8991 REGISTER ADDRESS BIT 6:0 R39 (27h) Input Mixers (1) 15:4 3:2 AINLMODE [1:0] LABEL SPKVOL [6:0] DEFAULT 79h (0dB) 000h 00b DESCRIPTION Pre-Production SPKPGA Volume (see Table 36 for SPKPGA volume control range) Reserved - Do Not Change AINLMUX Input Source 00 = INMIXL (Left Input Mixer) 01 = RXVOICE (RXP - RXN) 10 = DIFFINL (LIN12 PGA - LIN34 PGA) 11 = (Reserved) AINRMUX Input Source 00 = INMIXR (Right Input Mixer) 01 = RXVOICE (RXP - RXN) 10 = DIFFINR (RIN12 PGA - RIN34 PGA) 11 = (Reserved) Reserved - Do Not Change LIN34 PGA Non-Inverting Input Select 0 = LIN4 not connected to PGA 1 = LIN4 connected to PGA LIN34 PGA Inverting Input Select 0 = LIN3 not connected to PGA 1 = LIN3 connected to PGA LIN12 PGA Non-Inverting Input Select 0 = LIN2 not connected to PGA 1 = LIN2 connected to PGA LIN12 PGA Inverting Input Select 0 = LIN1 not connected to PGA 1 = LIN1 connected to PGA RIN34 PGA Non-Inverting Input Select 0 = RIN4 not connected to PGA 1 = RIN4 connected to PGA RIN34 PGA Inverting Input Select 0 = RIN3 not connected to PGA 1 = RIN3 connected to PGA RIN12 PGA Non-Inverting Input Select 0 = RIN2 not connected to PGA 1 = RIN2 connected to PGA RIN12 PGA Inverting Input Select 0 = RIN1 not connected to PGA 1 = RIN1 connected to PGA Reserved - Do Not Change LIN34 PGA Output to INMIXL Mute 0 = Mute 1 = Un-Mute LIN34 PGA Output to INMIXL Gain 0 = 0dB 1 = +30dB Reserved - Do Not Change LIN12 PGA Output to INMIXL Mute 0 = Mute 1 = Un-Mute LIN12 PGA Output to INMIXL Gain 0 = 0dB 1 = +30dB Reserved - Do Not Change PP, May 2008, Rev 3.1 158 1:0 AINRMODE [1:0] 00b R40 (28h) Input Mixers (2) 15:8 7 LMP4 00h 0b 6 LMN3 0b 5 LMP2 0b 4 LMN1 0b 3 RMP4 0b 2 RMN3 0b 1 RMP2 0b 0 RMN1 0b R41 (29h) Input Mixers (3) 15:9 8 L34MNB 00h 0b 7 L34MNBST 0b 6 5 L12MNB 0b 0b 4 L12MNBST 0b 3 0b w Pre-Production REGISTER ADDRESS BIT 2:0 LABEL LDBVOL [2:0] DEFAULT 000b DESCRIPTION LOMIX to INMIXL Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Reserved - Do Not Change RIN34 PGA Output to INMIXR Mute 0 = Mute 1 = Un-Mute RIN34 PGA Output to INMIXR Gain 0 = 0dB 1 = +30dB Reserved - Do Not Change RIN12 PGA Output to INMIXR Mute 0 = Mute 1 = Un-Mute RIN12 PGA Output to INMIXR Gain 0 = 0dB 1 = +30dB Reserved - Do Not Change ROMIX to INMIXR Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Reserved - Do Not Change LIN2 Pin to INMIXL Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB RXVOICE to AINLMUX Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB WM8991 R42 (2Ah) Input Mixers (4) 15:9 8 R34MNB 00h 0b 7 R34MNBST 0b 6 5 R12MNB 0b 0b 4 R12MNBST 0b 3 2:0 RDBVOL [2:0] 0b 000b R43 (2Bh) Input Mixers (5) 15:9 8:6 LI2BVOL [2:0] 00h 000b 5:3 LR4BVOL [2:0] 000b w PP, May 2008, Rev 3.1 159 WM8991 REGISTER ADDRESS BIT 2:0 LABEL LL4BVOL [2:0] DEFAULT 000b DESCRIPTION LIN4/RXN Pin to INMIXL Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Reserved - Do Not Change RIN2 Pin to INMIXR Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB RXVOICE to AINRMUX Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB RIN4/RXP Pin to INMIXR Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Reserved - Do Not Change Pre-Production R44 (2Ch) Input Mixers (6) 15:9 8:6 RI2BVOL [2:0] 00h 000b 5:3 RL4BVOL [2:0] 000b 2:0 RR4BVOL [2:0] 000b R45 (2Dh) Output Mixers (1) 15:8 7 LRBLO 00h 0b AINRMUX Output (Right ADC bypass) to LOMIX Mute 0 = Mute 1 = Un-mute AINLMUX Output (Left ADC bypass) to LOMIX Mute 0 = Mute 1 = Un-mute RIN3 to LOMIX Mute 0 = Mute 1 = Un-mute LIN3 to LOMIX Mute 0 = Mute 1 = Un-mute RIN12 PGA Output to LOMIX Mute 0 = Mute 1 = Un-mute 6 LLBLO 0b 5 LRI3LO 0b 4 LLI3LO 0b 3 LR12LO 0b w PP, May 2008, Rev 3.1 160 Pre-Production REGISTER ADDRESS 2 BIT LABEL LL12LO DEFAULT 0b DESCRIPTION LIN12 PGA Output to LOMIX Mute 0 = Mute 1 = Un-mute Reserved - Do Not Change Left DAC to LOMIX Mute 0 = Mute 1 = Un-mute Note: LDLO must be muted when LDSPK=1 Reserved - Do Not Change WM8991 1 0 LDLO 0b 0b R46 (2Eh) Output Mixers (2) 15:8 7 RLBRO 00h 0b AINLMUX Output (Left ADC bypass) to ROMIX Mute 0 = Mute 1 = Un-mute AINRMUX Output (Right ADC bypass) to ROMIX 0 = Mute 1 = Un-mute LIN3 to ROMIX Mute 0 = Mute 1 = Un-mute RIN3 to ROMIX Mute 0 = Mute 1 = Un-mute LIN12 PGA Output to ROMIX Mute 0 = Mute 1 = Un-mute RIN12 PGA Output to ROMIX Mute 0 = Mute 1 = Un-mute Reserved - Do Not Change Right DAC to ROMIX Mute 0 = Mute 1 = Un-mute Note: RDRO must be muted when RDSPK=1 Reserved - Do Not Change LIN3 Pin to LOMIX Volume (See Table 34 for Volume Range) RIN12 PGA Output to LOMIX Volume (See Table 34 for Volume Range) LIN12 PGA Output to LOMIX Volume (See Table 34 for Volume Range) Reserved - Do Not Change RIN3 to ROMIX Volume (See Table 34 for Volume Range) LIN12 PGA Output to ROMIX Volume (See Table 34 for Volume Range) RIN12 PGA Output to ROMIX Volume (See Table 34 for Volume Range) Reserved - Do Not Change RIN3 to LOMIX Volume (See Table 34 for Volume Range) AINRMUX Output (Right ADC bypass) to LOMIX Volume (See Table 34 for Volume Range) AINLMUX Output (Left ADC bypass) to LOMIX Volume (See Table 34 for Volume Range) PP, May 2008, Rev 3.1 161 6 RRBRO 0b 5 RLI3RO 0b 4 RRI3RO 0b 3 RL12RO 0b 2 RR12RO 0b 1 0 RDRO 0b 0b R47 (2Fh) Output Mixers (3) 15:9 8:6 5:3 2:0 LLI3LOVOL [2:0] LR12LOVOL [2:0] LL12LOVOL [2:0] RRI3ROVOL [2:0] RL12ROVOL [2:0] RR12ROVOL [2:0] LRI3LOVOL [2:0] LRBLOVOL [2:0] LLBLOVOL [2:0] 00h 000b 000b 000b 00h 000b 000b 000b 000h 000b 000b 000b R48 (30h) Output Mixers (4) 15:9 8:6 5:3 2:0 R49 (31h) Output Mixers (5) 15:9 8:6 5:3 2:0 w WM8991 REGISTER ADDRESS R50 (32h) Output Mixers (6) BIT 15:9 8:6 5:3 2:0 R51 (33h) OUT3 and OUT4 Mixers 15:9 8:7 VSEL [1:0] RLI3ROVOL [2:0] RLBROVOL [2:0] RRBROVOL [2:0] LABEL DEFAULT 00h 000b 000b 000b 00h 11b DESCRIPTION Reserved - Do Not Change LIN3 to ROMIX Volume (See Table 34 for Volume Range) Pre-Production AINLMUX Output (Left ADC bypass) to ROMIX Volume (See Table 34 for Volume Range) AINRMUX Output (Right ADC bypass) to ROMIX Volume (See Table 34 for Volume Range) Reserved - Do Not Change Analogue Bias Optimisation 00 = Reserved 01 = Bias current optimized for AVDD=2.7V 1X = Lowest bias current, optimized for AVDD=3.3V Reserved - Do Not Change LIN4/RXN Pin to OUT3MIX 0 = Mute 1 = Un-mute LOPGA to OUT3MIX 0 = Mute 1 = Un-mute Reserved - Do Not Change RIN4/RXP Pin to OUT4MIX 0 = Mute 1 = Un-mute ROPGA to OUT4MIX 0 = Mute 1 = Un-mute Reserved - Do Not Change LOPGA to LONMIX 0 = Mute 1 = Un-mute ROPGA to LONMIX 0 = Mute 1 = Un-mute Inverted LOP Output to LONMIX 0 = Mute 1 = Un-mute Reserved - Do Not Change RIN12 PGA Output to LOPMIX 0 = Mute 1 = Un-mute LIN12 PGA Output to LOPMIX 0 = Mute 1 = Un-mute LOPGA to LOPMIX 0 = Mute 1 = Un-mute Reserved - Do Not Change ROPGA to RONMIX 0 = Mute 1 = Un-mute LOPGA to RONMIX 0 = Mute 1 = Un-mute PP, May 2008, Rev 3.1 162 6 5 LI4O3 0b 0b 4 LPGAO3 0b 3:2 1 RI4O4 00b 0b 0 RPGAO4 0b R52 (34h) Line Output Mixers (1) 15:7 6 LLOPGALON 000h 0b 5 LROPGALON 0b 4 LOPLON 0b 3 2 LR12LOP 0b 0b 1 LL12LOP 0b 0 LLOPGALOP 0b R53 (35h) Line Output Mixers (2) 15:7 6 RROPGARON 000h 0b 5 RLOPGARON 0b w Pre-Production REGISTER ADDRESS 4 BIT LABEL ROPRON DEFAULT 0b DESCRIPTION Inverted ROP Output to RONMIX 0 = Mute 1 = Un-mute Reserved - Do Not Change LIN12 PGA Output to ROPMIX 0 = Mute 1 = Un-mute RIN12 PGA Output to ROPMIX 0 = Mute 1 = Un-mute ROPGA to ROPMIX 0 = Mute 1 = Un-mute Reserved - Do Not Change AINLMUX Output to SPKMIX 0 = Mute 1 = Un-mute AINRMUX Output to SPKMIX 0 = Mute 1 = Un-mute LIN2 to SPKMIX 0 = Mute 1 = Un-mute RIN2 to SPKMIX 0 = Mute 1 = Un-mute LOPGA to SPKMIX 0 = Mute 1 = Un-mute ROPGA to SPKMIX 0 = Mute 1 = Un-mute Left DAC to SPKMIX 0 = Mute 1 = Un-mute Note: LDSPK must be muted when LDLO=1 Right DAC to SPKMIX 0 = Mute 1 = Un-mute Note: RDSPK must be muted when RDRO=1 Reserved - Do Not Change WM8991 3 2 RL12ROP 0b 0b 1 RR12ROP 0b 0 RROPGAROP 0b R54 (36h) Speaker Output Mixer 15:8 7 LB2SPK 000h 0b 6 RB2SPK 0b 5 LI2SPK 0b 4 RI2SPK 0b 3 LOPGASPK 0b 2 ROPGASPK 0b 1 LDSPK 0b 0 RDSPK 0b R55 (37h) Additional Control 15:1 0 VROI 0000h 0b VREF to Analogue Output Resistance (Disabled Outputs) 0 = 20k (Headphone) or 10k (Line Out) from buffered VMID to output 1 = 500 from buffered VMID to output Reserved - Do Not Change Discharges LOP and LON outputs via approx 500 resistor 0 = Not active 1 = Actively discharging LOP and LON Discharges ROP and RON outputs via approx 500 resistor 0 = Not active 1 = Actively discharging ROP and RON R56 (38h) Anti-Pop (1) 15:6 5 DIS_LLINE 000h 0b 4 DIS_RLINE 0b w PP, May 2008, Rev 3.1 163 WM8991 REGISTER ADDRESS 3 BIT LABEL DIS_OUT3 DEFAULT 0b DESCRIPTION Pre-Production Discharges OUT3 output via approx 500 resistor 0 = Not active 1 = Actively discharging OUT3 Discharges OUT4 output via approx 500 resistor 0 = Not active 1 = Actively discharging OUT4 Discharges LOUT output via approx 500 resistor 0 = Not active 1 = Actively discharging LOUT Discharges ROUT output via approx 500 resistor 0 = Not active 1 = Actively discharging ROUT Reserved - Do Not Change Enables VMID soft start 0 = Disabled 1 = Enabled Reserved - Do Not Change Enables the VGS / R current generator and the analogue input and output bias 0 = Disabled 1 = Enabled Enables the VGS / R current generator 0 = Disabled 1 = Enabled Selects the bias current source for output amplifiers and VMID buffer 0 = VMID / R bias 1 = VGS / R bias Connects VMID to ground 0 = Disabled 1 = Enabled Reserved - Do Not Change MICBIAS Short Circuit Current Detect Threshold 00 = 600uA 01 = 120uA 10 = 1800uA 11 = 2400uA These values are for AVDD=3.3V and scale proportionally with AVDD. MICBIAS Current Detect Threshold 000 = 200uA 001 = 350uA 010 = 500uA 011 = 650uA 100 = 800uA 101 = 950uA 110 = 1100uA 111 = 1200uA These values are for AVDD=3.3V and scale proportionally with AVDD. MICBIAS Current and Short Circuit Detect Enable 0 = disabled 1 = enabled PP, May 2008, Rev 3.1 164 2 DIS_OUT4 0b 1 DIS_LOUT 0b 0 DIS_ROUT 0b R57 (39h) Anti-Pop (2) 15:7 6 SOFTST 0000_000 0_0b 0b 5:4 3 BUFIOEN 00b 0b 2 BUFDCOPEN 0b 1 POBCTRL 0b 0 VMIDTOG 0b R58 (3Ah) Microphone Bias 15:8 7:6 MCDSCTH [1:0] 0000_000 0b 00b 5:3 MDCTHR [2:0] 000b 2 MCD 0b w Pre-Production REGISTER ADDRESS 1 0 MBSEL BIT LABEL DEFAULT 0b 0b DESCRIPTION Reserved - Do Not Change Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.65 * AVDD Reserved - Do Not Change Reserved - Do Not Change Enable PLL Integer Mode 0 = Integer mode 1 = Fractional mode Divide MCLK by 2 at PLL input 0 = Divide by 1 1 = Divide by 2 Reserved - Do Not Change Reserved - Do Not Change Integer (N) part of PLL frequency ratio. Use values greater than 5 and less than 13. Reserved - Do Not Change Fractional (K) part of PLL frequency ratio (Most significant bits) Reserved - Do Not Change Fractional (K) part of PLL frequency ratio (Least significant bits) WM8991 R59 (3Bh) R60 (3Ch) PLL (1) 15:0 15:8 7 SDM 0000h 00h 0b 6 PRESCALE 0b 5 4 3:0 R61 (3Dh) PLL (2) R62 (3Eh) PLL (3) R63 (3Fh) to R127 (7Fh) 15:8 7:0 15:8 7:0 Reserved PLLK [7:0] PLLK [15:8] PLLN [3:0] 0b 0b 8h 00h 31h 00h 26h w PP, May 2008, Rev 3.1 165 WM8991 DIGITAL FILTER CHARACTERISTICS PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation DAC Normal Filter Passband Passband Ripple Stopband Stopband Attenuation DAC Sloping Stopband Filter Passband +/- 0.03dB +/- 1dB -6dB Passband Ripple Stopband 1 Stopband 1 Attenuation Stopband 2 Stopband 2 Attenuation Stopband 3 Stopband 3 Attenuation F > 1.4 fs f > 0.7 fs f > 0.546 fs 0.25 fs 0.546 fs -60 0.7 fs -85 1.4 fs -55 dB 1.4 fs dB 0 0.25 fs 0.5 fs +/- 0.03 0.7 fs dB dB 0.25 fs 0.454 fs F > 0.546 fs +/- 0.03dB -6dB 0.454 fs 0.546 fs -50 dB 0 0.5 fs +/- 0.03 dB 0.454 fs f > 0.546 fs 0.546s -60 dB +/- 0.05dB -6dB 0 0.5fs +/- 0.05 dB 0.454 fs TEST CONDITIONS MIN TYP MAX Pre-Production UNIT DAC FILTERS Mode Normal Sloping Stopband Group Delay 18 / fs 18 / fs Mode Normal ADC FILTERS Group Delay 18 / fs w PP, May 2008, Rev 3.1 166 Pre-Production WM8991 ADC FILTER RESPONSES 20 0 -20 -40 -60 -80 -100 -120 -140 0.00 0.1 0.08 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.1 0.00 0.25 0.50 Frequency (fs) 0.75 0.25 Frequency (fs) Figure 90 ADC Digital Filter Frequency Response Figure 91 ADC Digital Filter Ripple ADC HIGH PASS FILTER RESPONSES 2.1246m -2.3338m -1.1717 -8.3373 -2.3455 -16.672 -3.5193 -25.007 -4.6931 -33.342 -5.8669 -41.677 -7.0407 -50.012 -8.2145 -58.347 -9.3883 -66.682 -10.562 -75.017 -11.736 1 2.6923 7.2484 19.515 52.54 141.45 380.83 1.0253k 2.7605k 7.432k 20.009k -83.352 2 5.0248 12.624 31.716 79.683 200.19 502.96 1.2636k 3.1747k 7.9761k 20.039k MAGNITUDE(dB) hpf_response.res MAGNITUDE(dB) hpf_response2.res#1 MAGNITUDE(dB) hpf_response2.res MAGNITUDE(dB) Figure 92 ADC Digital High Pass Filter Frequency Response (48kHz, Hi-Fi Mode, ADC_HPF_CUT[1:0]=00) Figure 93 ADC Digital High Pass Filter Ripple (48kHz, Voice Mode, ADC_HPF_CUT=01, 10 and 11) w PP, May 2008, Rev 3.1 167 WM8991 DAC FILTER RESPONSES DAC STOPBAND ATTENUATION Pre-Production The DAC digital filter type is selected by the DAC_SB_FILT register bit as shown in Table 91. REGISTER ADDRESS R10 (0Ah) BIT 8 LABEL DAC_SB_FI LT DEFAULT 0b DESCRIPTION Selects DAC filter characteristics 0 = Normal mode 1 = Sloping stopband mode Table 91 DAC Filter Selection MAGNITUDE(dB) 10 -10 0 -30 -50 0.02 0.04 MAGNITUDE(dB) 0.5 1 1.5 2 2.5 3 0.035 0.03 0.025 -70 -90 -110 -130 -150 Frequency (fs) 0.015 0.01 0.005 0 -0.005 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (fs) Figure 94 DAC Digital Filter Frequency Response (Normal Mode) MAGNITUDE(dB) 10 -10 0 -30 -50 -70 -90 -110 -130 -150 Frequency (fs) 0.5 1 1.5 2 2.5 3 Figure 95 DAC Digital Filter Ripple (Normal Mode) MAGNITUDE(dB) 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 -0.45 -0.5 Frequency (fs) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Figure 96 DAC Digital Filter Frequency Response (Sloping Stopband Mode) Figure 97 DAC Digital Filter Ripple (Sloping Stopband Mode) w PP, May 2008, Rev 3.1 168 Pre-Production WM8991 DE-EMPHASIS FILTER RESPONSES MAGNITUDE(dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 Frequency (Hz) -0.1 -0.15 Frequency (Hz) 0.3 MAGNITUDE(dB) 0 5000 10000 15000 20000 0.25 0.2 0.15 0.1 0.05 0 -0.05 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 Figure 98 De-Emphasis Digital Filter Response (32kHz) Figure 99 De-Emphasis Error (32kHz) MAGNITUDE(dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 Frequency (Hz) 0 5000 10000 15000 20000 25000 MAGNITUDE(dB) 0.2 0.15 0.1 0.05 0 0 -0.05 -0.1 Frequency (Hz) 5000 10000 15000 20000 25000 Figure 100 De-Emphasis Digital Filter Response (44.1kHz) Figure 101 De-Emphasis Error (44.1kHz) MAGNITUDE(dB) 0 0 -2 -4 -6 -8 -10 -12 Frequency (Hz) 5000 10000 15000 20000 25000 30000 0.1 0.15 MAGNITUDE(dB) 0.05 0 0 -0.05 5000 10000 15000 20000 25000 30000 -0.1 -0.15 Frequency (Hz) Figure 102 De-Emphasis Digital Filter Response (48kHz) Figure 103 De-Emphasis Error (48kHz) w PP, May 2008, Rev 3.1 169 WM8991 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Pre-Production DVDD Vbatt AVDD 0.1 F 0.1 F 4.7 F 4.7 F 4.7 F WM8991 AVDD HPVDD SPKVDD DCVDD DBVDD MODE CSB/ADDR SCLK SDIN MCLK GPIO2/MCLK2 BCLK DACLRC DACDAT ADCLRC/GPIO1 ADCDAT GPIO3/BCLK2 GPIO4/DACLRC2 GPIO5/DACDAT2 GPIO6/ADCLRCB LIN1 ROP LIN2 RON LIN3/GPI7 LOP LIN4/RXN LON RIN1 RIN2 RIN3/GPI8 RIN4/RXP 1F 1F 1F 1F AGND HPGND SPKGND DGND MICBIAS CONTROL INTERFACE (2, 3 or 4-wire via GPIO) MICBIAS VMID 4.7 F 4.7 F AGND LOUT ROUT OUT3 OUT4 220 F 220 F 16 or 32 OHM HEADPHONES 16 or 32 OHM EAR SPEAKER 8 OHM LOUDSPEAKER LINE OUTPUTS AUDIO INTERFACE MICBIAS 2k2 2k2 GPIO SPKP SPKN HEADSET MIC HANDSET MIC 1F 1F 1F 1F 1F 1F LINE INPUT (FM Radio) LINE INPUT (Melody Chip) 1F 1F BB (Voice CODEC) Notes: 1. Wolfson recommend using a single, common ground reference. Where this is not possible care should be taken to optimise split ground configuration for audio performance. 2. Supply decoupling capacitors on DCVDD, DBVDD, SPKVDD, HPVDD and AVDD should be positioned as close to the WM8991 as possible. Values indicated are minimum requirements. 3. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum performance. 4. The loudspeaker should be connected as close as possible to the WM8991. When this is not possible, filtering should be placed on the speaker outputs close to the WM8991. 5. The 2k2 MICBIAS resistors on each of the MIC inputs are typical values and will be suitable for many electret type microphones. However, it is recommended that engineers refer to individual microphone specifications prior to finalising the value of this component. w PP, May 2008, Rev 3.1 170 Pre-Production WM8991 SPEAKER SELECTION For filterless operation, it is important to select a speaker with appropriate internal inductance. The internal inductance and the speaker's load resistance create a low-pass filter with a cut-off frequency of: fc = RL / 2L e.g. for an 8 speaker and required cut-off frequency of 20kHz, the speaker should be chosen to have an inductance of: L = RL / 2fc = 8 / 2 * 20kHz = 64H 8 speakers typically have an inductance in the range 20H to 100H. Care should be taken to ensure that the cut-off frequency of the speaker's internal filtering is low enough to prevent speaker damage. The class D outputs of the WM8991 operate at much higher frequencies than is recommended for most speakers, and the cut-off frequency of the filter should be low enough to protect the speaker. Figure 104 Speaker Equivalent Circuit PCB LAYOUT CONSIDERATIONS The efficiency of the speaker drivers is affected by the series resistance between the WM8991 and the speaker (e.g. inductor ESR) as shown in Figure 105. This resistance should be as low as possible to maximise efficiency. Figure 105 Speaker Connection Losses w PP, May 2008, Rev 3.1 171 WM8991 Pre-Production The distance between the WM8991 and the speakers should be kept to a minimum to reduce series resistance, and also to reduce EMI. Further reductions in EMI can be achieved by additional passive filtering and/or shielding as shown in Figure 106. When additional passive filtering is used, low ESR components should be chosen to minimise series resistance between the WM8991 and the speaker, maximising efficiency. LC passive filtering will usually be effective at reducing EMI at frequencies up to around 30MHz. To reduce emissions at higher frequencies, ferrite beads placed as close to the device as possible will be more effective. Figure 106 EMI Reduction Techniques w PP, May 2008, Rev 3.1 172 Pre-Production WM8991 PACKAGE DIMENSIONS w PP, May 2008, Rev 3.1 173 WM8991 IMPORTANT NOTICE Pre-Production Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w PP, May 2008, Rev 3.1 174 |
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