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M36L0T7050T2 M36L0T7050B2
128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package
Preliminary Data
Feature summary
Multi-Chip Package - 1 die of 128 Mbit (8Mb x16, Multiple Bank, Multi-level, Burst) Flash Memory - 1 die of 32 Mbit (2Mb x16) Pseudo SRAM Supply voltage - VDDF = 1.7 to 1.95V - VCCP = VDDQ = 2.7 to 3.1V - VPPF = 9V for fast program Electronic signature - Manufacturer Code: 20h - Device Code (Top Flash Configuration) M36L0T7050T2: 88C4h - Device Code (Bottom Flash Configuration) M36L0T7050B2: 88C5h ECOPACK(R) packages available

FBGA
TFBGA88 (ZAQ) 8 x 10mm
Block locking - All blocks locked at power-up - Any combination of blocks can be locked with zero latency - WP for Block Lock-Down - Absolute Write Protection with VPP = VSS Security - 64 bit unique device number - 2112 bit user programmable OTP Cells Common Flash Interface (CFI) 100,000 program/erase cycles per block
Flash memory
Synchronous / Asynchronous Read - Synchronous Burst Read mode: 52MHz - Random Access: 85ns Synchronous Burst Read Suspend Programming time - 2.5s typical Word program time using Buffer Enhanced Factory Program command Memory organization - Multiple Bank Memory Array: 8 Mbit Banks - Parameter Blocks (Top or Bottom location) Dual operations - program/erase in one Bank while read in others - No delay between read and write operations

PSRAM

Access time: 65ns 8-Word Page Access capability: 18ns Low standby current: 100A Deep power down current: 10A Compatible with standard LPSRAM Power-down modes - Deep Power-Down - 4 Mbit Partial Array Refresh - 8 Mbit Partial Array Refresh
November 2007
Rev 0.2
1/22
www.numonyx.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
M36L0T7050T2, M36L0T7050B2
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 Address Inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data Input/Output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Chip Enable (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Latch Enable (LF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Clock (KF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Wait (WAITF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PSRAM Chip Enable Input (E1P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PSRAM Chip Enable Input (E2P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VDDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VCCP Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VPPF Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 4 5 6
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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M36L0T7050T2, M36L0T7050B2
Contents
7 8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22
List of tables
M36L0T7050T2, M36L0T7050B2
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data . . . . . . 19 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4/22
M36L0T7050T2, M36L0T7050B2
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Bottom View Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5/22
Summary description
M36L0T7050T2, M36L0T7050B2
1
Summary description
The M36L0T7050T2 and M36L0T7050B2 combine two memory devices in a Multi-Chip Package:

a 128-Mbit, Multiple Bank, Multi-Level, Burst, Flash memory, the M58LT128HT or M58LT128HB a 32-Mbit PseudoSRAM, the M69KW048BD.
The purpose of this document is to describe how the two memory components operate with respect to each other. It should be read in conjunction with the M58LT128HTB and M69KW048BD datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. These datasheets are available from your local Numonyx distributor. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8 x 10mm, 8x10 ball array, 0.8mm pitch) package. The devices are supplied with all the bits erased (set to `1'). Figure 1. Logic diagram
VDDQ VDDF 23 A0-A22 EF GF WF RPF WPF LF KF E1P GP WP E2P UBP LBP VSS M36L0T7050T2 M36L0T7050B2 WAITF DQ0-DQ15 VPPF VCCP 16
AI12878
6/22
M36L0T7050T2, M36L0T7050B2 Table 1.
A0-A22
(1)
Summary description
Signal names
Address Inputs Common Data Input/Output Power Supply for Flash Memory Flash Memory Power Supply for I/O Buffers Flash Optional Supply Voltage for Fast Program and Erase Ground PSRAM Power Supply Not Connected Internally Do Not Use as Internally Connected
DQ0-DQ15 VDDF VDDQ VPPF VSS VCCP NC DU
Flash memory signals LF EF GF WF RPF WPF KF WAITF PSRAM signals E1P GP WP E2P UBP LBP Chip Enable Input Output Enable Input Write Enable Input Power-down Input Upper Byte Enable Input Lower Byte Enable Input Latch Enable Input Chip Enable Input Output Enable Input Write Enable Input Reset Input Write Protect Input Burst Clock Wait Data in Burst Mode
1. A22-A21 are not connected to the PSRAM component.
7/22
Summary description Figure 2.
M36L0T7050T2, M36L0T7050B2 TFBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
DU
DU
DU
DU
B
A4
A18
A19
VSS
VDDF
NC
A21
A11
C
A5
LBP
NC
VSS
NC
KF
A22
A12
D
A3
A17
NC
VPPF
WP
EP
A9
A13
E
A2
A7
NC
WPF
LF
A20
A10
A15
F
A1
A6
UBP
RPF
WF
A8
A14
A16
G
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAITF
NC
H
GP
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
NC
J
NC
GF
DQ9
DQ11
DQ4
DQ6
DQ15
VDDQ
K
EF
DU
DU
NC
VCCP
NC
VDDQ
E2P
L
VSS
VSS
VDDQ
VDDF
VSS
VSS
VSS
VSS
M
DU
DU
DU
DU
AI08735b
8/22
M36L0T7050T2, M36L0T7050B2
Signal descriptions
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.
2.1
Address Inputs (A0-A22)
Addresses A0-A20 are common inputs for the Flash memory and the PSRAM components. The other lines (A21-A22) are inputs for the Flash memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller in the Flash memory, and they select the cells to be accessed in the PSRAM.
2.2
Data Input/Output (DQ0-DQ15)
In the Flash memory, the Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation. In the PSRAM DQ0-DQ7 and/or DQ8-DQ15 carry the data to or from the upper and/or lower part(s) of the selected address during a Write or Read operation, when Upper Byte Enable (UBP) and/or Lower Byte Enable (LBP) is/are driven Low.
2.3
Flash Chip Enable (EF)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. It is not allowed to set EF at VIL, E1P at VIL and E2P at VIH at the same time.
2.4
Flash Output Enable (GF)
The Output Enable input controls data output during Flash memory Bus Read operations.
2.5
Flash Write Enable (WF)
The Write Enable controls the Bus Write operation of the Flash memories' Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.
9/22
Signal descriptions
M36L0T7050T2, M36L0T7050B2
2.6
Flash Write Protect (WPF)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the LockedDown blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M58LT128HTB datasheet).
2.7
Flash Reset (RPF)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to M58LT128HTB datasheet for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to M58LT128HTB datasheet).
2.8
Flash Latch Enable (LF)
Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is Low, VIL, and it is inhibited when Latch Enable is High, VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported.
2.9
Flash Clock (KF)
The Clock input synchronizes the Flash memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is don't care during Asynchronous Read and in write operations.
2.10
Flash Wait (WAITF)
WAIT is a Flash output signal used during Synchronous Read to indicate whether the data on the output bus are valid. This output is high impedance when Flash Chip Enable is at VIH or Flash Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAITF signal is not gated by Output Enable.
2.11
PSRAM Chip Enable Input (E1P)
When asserted (Low), the Chip Enable, E1P, activates the memory state machine, address buffers and decoders, allowing Read and Write operations to be performed. When deasserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode. It is not allowed to set EF at VIL, E1P at VIL and E2P at VIH at the same time.
10/22
M36L0T7050T2, M36L0T7050B2
Signal descriptions
2.12
PSRAM Chip Enable Input (E2P)
The Chip Enable, E2P, puts the device in Deep Power-down mode when it is driven Low. This is the lowest power mode.
2.13
PSRAM Write Enable (WP)
The Write Enable, WP, controls the Bus Write operation of the memory.
2.14
PSRAM Output Enable (GP)
The Output Enable, GP, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus.
2.15
PSRAM Upper Byte Enable (UBP)
The Upper Byte Enable, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8DQ15) to or from the upper part of the selected address during a Write or Read operation.
2.16
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0DQ7) to or from the lower part of the selected address during a Write or Read operation.
2.17
VDDF Supply Voltage
VDDF provides the power supply to the internal cores of the Flash memory component. It is the main power supply for all Flash operations (Read, Program and Erase).
2.18
VCCP Supply Voltage
The VCCP Supply Voltage supplies the power for all operations (Read or Write) and for driving the refresh logic, even when the device is not being accessed.
2.19
VDDQ Supply Voltage
VDDQ provides the power supply for the Flash memory I/O pins. This allows all Outputs to be powered independently of the Flash Memory core power supply, VDDF.
11/22
Signal descriptions
M36L0T7050T2, M36L0T7050B2
2.20
VPPF Program Supply Voltage
VPPF is both a Flash control input and a Flash power supply pin. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQ) VPPF is seen as a control input. In this case a voltage lower than VPPLKF gives an absolute protection against Program or Erase, while VPPF > VPP1 enables these functions (see the M58LT128HTB datasheet for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If VPPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed.
2.21
VSS Ground
VSS is the common ground reference for all voltage measurements in the Flash (core and I/O Buffers) and PSRAM chips.
Note:
The Flash memory device in a system should have their supply voltage (VDDF) and the program supply voltage VPPF decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 5: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents.
12/22
M36L0T7050T2, M36L0T7050B2
Functional description
3
Functional description
The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by three Chip Enable inputs: EF for the Flash memory and E1P and E2P for the PSRAM. Recommended operating conditions do not allow more than one device to be active at a time. The most common example is simultaneous read operations in the Flash memory and the PSRAM which would result in a data bus contention. Therefore it is recommended to put the other device in the high impedance state when reading the selected device. Figure 3. Functional block diagram
VDDF VPPF VDDQ
EF A20-A22 A0-A19 GF WF RPF WPF LF KF VCCP 128 Mbit Flash Memory DQ0-DQ15 WAITF
E1P GP WP E2P UBP LBP 16 Mbit PSRAM
VSS
AI10965
13/22
Functional description Table 2. Operating modes(1)
EF GF WF LF RPF WAITF(2) E1P E2P VIH VIH VIH VIH VIH VIL Hi-Z Hi-Z Hi-Z VIL PSRAM Read(5) Flash Memory must be disabled PSRAM Write(5) VIL VIL VIL VIL VIL PSRAM Output Disabled(5) PSRAM Standby (Deselected) PSRAM PowerDown(7)
1. X = Don't care.
M36L0T7050T2, M36L0T7050B2
Operation Flash Read Flash Write Flash Address Latch Flash Output Disable Flash Standby Flash Reset
GP
WP LBP, UBP
DQ0DQ7
DQ8DQ15
VIL VIL VIH VIL(3) VIL VIH VIL VIL X VIH VIL(3) VIL X X X
Data Out PSRAM must be disabled Data In Data Out or Hi-Z(4) Hi-Z Any PSRAM mode is allowed Hi-Z Hi-Z VIH VIH VIH VIH VIH VIL VIL VIL VIH VIH VIH VIH VIH VIL VIL VIL VIL VIH X X VIL VIH VIL VIL VIH VIL VIH X X VIH VIL VIL VIH VIL VIL VIH data out Hi-Z Hi-Z data out
VIL VIH VIH VIH X X X X X
data out data in Hi-Z Hi-Z data in data in Hi-Z
VIH VIH(6) VIH VIH VIL VIH VIL X X
VIL Any Flash mode is allowed VIH X
Hi-Z Hi-Z
2. WAIT signal polarity is configured using the Set Configuration Register command. See the M58LT128HTB datasheet for details. 3. LF can be tied to VIH if the valid address has been previously latched. 4. Depends on GF. 5. Should not be kept in this logic condition for a period longer than 1s. 6. GP can be VIL during the Write operation if the following conditions are satisfied: a. Write pulse is initiated by E1P (E1P Controlled Write timing), or cycle time of the previous operation cycle is satisfied; b. GP stays VIL during the entire Write cycle. 7. Power-Down mode can be entered from Standby state and all Data outputs are in High-Z. The Power-Down current and data retention depend on the selection of Power-Down programming.
14/22
M36L0T7050T2, M36L0T7050B2
Maximum rating
4
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 3.
Symbol TA TBIAS TSTG VIO VDDF VDDQ, VCCP VPPF IO tVPPFH
Absolute maximum ratings
Value Parameter Min Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltage Flash Memory Core Supply Voltage PSRAM and Input/Output Supply Voltages Flash Program Voltage Output Short Circuit Current Time for VPPF at VPPFH -25 -25 -55 -0.5 -0.2 -0.2 -0.2 - Max 85 85 125 3.6 2.5 3.6 10 100 100 C C C V V V V mA hours Unit
15/22
DC and AC parameters
M36L0T7050T2, M36L0T7050B2
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4. Operating and AC measurement conditions
Flash Memories Parameter Min VDDF Supply Voltage VCCP Supply Voltage VDDQ Supply Voltage
VPPF Supply Voltage (Factory environment) VPPF Supply Voltage (Application
PSRAM Unit Min - 2.7 - - - -30 50 22 Max - 3.1 - - - 85 V V V V V C pF k ns 0 to VDDQ VDDQ/2 V V
Max 1.95 - 3.1 9.5 VDDQ +0.4 85 30 22 5
1.7 - 2.7 8.5 -0.4 -25
environment) Ambient Operating Temperature Load Capacitance (CL) Output Circuit Resistors (R1, R2) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
5
0 to VDDQ VDDQ/2
Figure 4.
AC Measurement I/O Waveform
VDDQ VDDQ/2 0V
AI06161
16/22
M36L0T7050T2, M36L0T7050B2 Figure 5. AC measurement load circuit
VDDQ
DC and AC parameters
VDDF
VDDQ R1 DEVICE UNDER TEST
0.1F 0.1F
CL
R2
CL includes JIG capacitance
AI08364B
Table 5.
Symbol CIN COUT
Device Capacitance(1)
Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 12 15 Unit pF pF
1. Sampled only, not 100% tested.
Please refer to the M58LT128HTB and M69KW048BD datasheets for further DC and AC characteristic values and illustrations.
17/22
Package mechanical
M36L0T7050T2, M36L0T7050B2
6
Package mechanical
In order to meet environmental requirements, Numonyx offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 6. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Bottom View Outline
D D1
e SE E E2 E1 b BALL "A1"
ddd FE FE1 A A1 FD SD A2
BGA-Z42
1. Drawing is not to scale.
18/22
M36L0T7050T2, M36L0T7050B2
Table 6.
Package mechanical
Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 E2 e FD FE FE1 SD SE 10.000 7.200 8.800 0.800 1.200 1.400 0.600 0.400 0.400 - - 9.900 0.850 0.350 8.000 5.600 0.100 10.100 0.3937 0.2835 0.3465 0.0315 0.0472 0.0551 0.0236 0.0157 0.0157 0.300 7.900 0.400 8.100 0.200 0.0335 0.0138 0.3150 0.2205 Min Max 1.200 Typ
inches Min Max 0.0472 0.0079
0.0118 0.3110
0.0157 0.3189
0.0039 0.3898 0.3976
-
-
19/22
Part numbering
M36L0T7050T2, M36L0T7050B2
7
Part numbering
Table 7.
Example: Device Type M36 = Multi-Chip Package (Flash + RAM) Flash 1 Architecture L = Multilevel, Multiple Bank, Burst mode Flash 2 Architecture 0 = No Die Operating Voltage T = VDDF = 1.7 to 1.95V; VDDQ = VCCP = 2.7 to 3.1V Flash 1 Density 7 = 128 Mbit Flash 2 Density 0 = No Die RAM 1 Density 5 = 32 Mbit RAM 0 Density 0 = No Die Parameter Blocks Location T = Top Boot Block Flash B = Bottom Boot Block Flash Product Version 2 = 90nm Flash technology and Multi-Level design, 85ns speed; 0.13m RAM, 65ns speed Package ZAQ = Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch Option Blank = Standard Packing T = Tape & Reel Packing E = ECOPACK(R) package, standard packing F = ECOPACK(R) package, tape and reel packing
Ordering information scheme
M36 L 0T 7 05 0 T2 ZAQ F
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you.
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M36L0T7050T2, M36L0T7050B2
Revision history
8
Revision history
Table 8.
Date 04-May-2006 13-Nov-2007
Document revision history
Revision 01 02 Initial release. Applied Numonyx branding. Changes
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M36L0T7050T2, M36L0T7050B2
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