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K9F1G08U0B
FLASH MEMORY
K9XXG08UXB
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* Samsung Electronics reserves the right to change products or specification without notice.
1
K9F1G08U0B
FLASH MEMORY
Document Title 128M x 8 Bit NAND Flash Memory Revision History
Revision No
0.0 1.0
History
1. Initial issue 1. 1.8V device is eliminated
Draft Date
May 26. 2006 Sep. 27. 2006
Remark
Advance Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.
2
K9F1G08U0B
FLASH MEMORY
128M x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number K9F1G08U0B-P Vcc Range 2.70 ~ 3.60V Organization x8 PKG Type TSOP1
FEATURES
* Voltage Supply - 3.3V Device(K9F1G08U0B) : 2.70V ~ 3.60V * Organization - Memory Cell Array : (128M + 4M) x 8bit - Data Register : (2K + 64) x 8bit * Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte * Page Read Operation - Page Size : (2K + 64)Byte - Random Read : 25s(Max.) - Serial Access : 25ns(Min.) * Fast Write Cycle Time - Page Program time : 200s(Typ.) - Block Erase Time : 1.5ms(Typ.) * Command/Address/Data Multiplexed I/O Port * Hardware Data Protection - Program/Erase Lockout During Power Transitions * Reliable CMOS Floating-Gate Technology -Endurance : 100K Program/Erase Cycles with 1bit/512Byte ECC) - Data Retention : 10 Years * Command Driven Operation * Intelligent Copy-Back with internal 1bit/528Byte EDC * Unique ID for Copyright Protection * Package : - K9F1G08U0B-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
GENERAL DESCRIPTION
Offered in 128Mx8bit, the K9F1G08U0B is a 1G-bit NAND Flash Memory with spare 32M-bit. Its NAND cell provides the most costeffective solution for the solid state application market. A program operation can be performed in typical 200s on the (2K+64)Byte page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F1G08U0Bs extended reliability of 100K program/ erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F1G08U0B is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
3
K9F1G08U0B
PIN CONFIGURATION (TSOP1)
K9F1G08U0B-PCB0/PIB0
N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C
FLASH MEMORY
48-pin TSOP1 Standard Type 12mm x 20mm
PACKAGE DIMENSIONS
48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220F
Unit :mm/Inch
0.10 MAX 0.004 #48 ( 0.25 ) 0.010 12.40 0.488 MAX 0.50 0.0197 #24 #25 1.000.05 0.0390.002 0.25 0.010 TYP 18.400.10 0.7240.004
+0.075
20.000.20 0.7870.008
0.008-0.001
+0.07
+0.003
0.20 -0.03
#1
12.00 0.472
0.05 0.002 MIN
0.125 0.035
0~8
0.45~0.75 0.018~0.030
( 0.50 ) 0.020
4
+0.003 0.005-0.001
1.20 0.047MAX
K9F1G08U0B
PIN DESCRIPTION
Pin Name I/O0 ~ I/O7 Pin Function
FLASH MEMORY
DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CHIP ENABLE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation. READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WRITE PROTECT The WP pin provides inadvertent program/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. READY/BUSY OUTPUT The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. POWER VCC is the power supply for device. GROUND NO CONNECTION Lead is not internally connected.
CLE
ALE
CE
RE
WE
WP
R/B
Vcc Vss N.C
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.
5
K9F1G08U0B
Figure 1. K9F1G08U0B Functional Block Diagram
VCC VSS A12 - A27 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders 1,024M + 32M Bit NAND Flash ARRAY
FLASH MEMORY
A0 - A11
(2,048 + 64)Byte x 65,536 Data Register & S/A Y-Gating
Command Command Register I/O Buffers & Latches VCC VSS I/0 0
CE RE WE
Control Logic & High Voltage Generator
Global Buffers
Output Driver
I/0 7 CLE ALE WP
Figure 2. K9F1G08U0B Array Organization
1 Block = 64 Pages (128K + 4k) Byte
64K Pages (=1,024 Blocks) 8 bit 2K Bytes 64 Bytes
1 Page = (2K + 64)Bytes 1 Block = (2K + 64)B x 64 Pages = (128K + 4K) Bytes 1 Device = (2K+64)B x 64Pages x 1,024 Blocks = 1,056 Mbits
Page Register
2K Bytes I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle A0 A8 A12 A20 I/O 1 A1 A9 A13 A21 I/O 2 A2 A10 A14 A22 64 Bytes I/O 3 A3 A11 A15 A23
I/O 0 ~ I/O 7
I/O 4 A4 *L A16 A24
I/O 5 A5 *L A17 A25
I/O 6 A6 *L A18 A26
I/O 7 A7 *L A19 A27 Column Address Column Address Row Address Row Address
NOTE : Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than required.
6
K9F1G08U0B
Product Introduction
FLASH MEMORY
The K9F1G08U0B is a 1,056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2,112x8 columns. Spare 64x8 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 1,024 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1G08U0B. The K9F1G08U0B has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 132M byte physical space requires 28 addresses, thereby requiring four cycles for addressing : 2 cycles of column address, 2 cycles of row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F1G08U0B. In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
Function Read Read for Copy Back Read ID Reset Page Program Copy-Back Program Block Erase Random Data Input(1) Random Data Output Read Status Read EDC Status
(2) (1)
1st Cycle 00h 00h 90h FFh 80h 85h 60h 85h 05h 70h 7Bh
2nd Cycle 30h 35h 10h 10h D0h E0h
Acceptable Command during Busy
O
O O
NOTE : 1. Random Data Input/Output can be executed in a page. 2. Read EDC Status is only available on Copy Back operation.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
7
K9F1G08U0B
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol VCC Voltage on any pin relative to VSS VIN VI/O Temperature Under Bias Storage Temperature Short Circuit Current K9XXG08XXB-XCB0 K9XXG08XXB-XIB0 K9XXG08XXB-XCB0 K9XXG08XXB-XIB0
IOS 5
FLASH MEMORY
Rating 3.3V Device -0.6 to + 4.6 -0.6 to + 4.6 -0.6 to Vcc + 0.3 (< 4.6V) -10 to +125 -40 to +125 TSTG -65 to +150 C
mA
Unit
V
TBIAS
C
NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F1G08U0B-XCB0 :TA=0 to 70C, K9F1G0808B-XIB0:TA=-40 to 85C) Parameter Supply Voltage Supply Voltage Symbol VCC VSS K9F1G08U0B(3.3V) Min 2.7 0 Typ. 3.3 0 Max 3.6 0 V V Unit
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter Page Read Serial Access Program Erase Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level Output Low Current(R/B) with Symbol ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO VIH(1) VIL(1) VOH VOL Test Conditions tRC=25ns CE=VIL, IOUT=0mA CE=VIH, WP=0V/VCC CE=VCC-0.2, WP=0V/VCC VIN=0 to Vcc(max) VOUT=0 to Vcc(max) K9F1G08U0A :IOH=-400A K9F1G08U0A :IOL=2.1mA 0.8xVcc -0.3 2.4 8 10 10 1 50 10 10 VCC +0.3 0.2xVcc 0.4 mA V A 15 30 mA K9F1G08U0B(3.3V) Min Typ Max Unit
Operating Current
IOL(R/B) K9F1G08U0A :VOL=0.4V
NOTE : 1. VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less. 2. Typical value is measured at Vcc=3.3V, TA=25C. Not 100% tested.
8
K9F1G08U0B
VALID BLOCK
Parameter K9F1G08U0B Symbol NVB Min 1,004 Typ. -
FLASH MEMORY
Max 1,024 Unit Blocks
NOTE : 1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.
AC TEST CONDITION
(K9F1G08U0B-XCB0 :TA=0 to 70C, K9F1G08U0B-XIB0:TA=-40 to 85C, K9F1G08U0B : Vcc=2.7V~3.6V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load K9F1G08U0B 0V to Vcc 5ns Vcc/2 1 TTL GATE and CL=50pF
CAPACITANCE(TA=25C, VCC=3.3V, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Condition VIL=0V VIN=0V Min Max 10 10 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE H L H L L L X X X X X ALE L H L H L L X X X X(1) X CE L L L L L L X X X X H H X X X X X H X X X X WE RE H H H H H WP X X H H H X X H H L 0V/VCC(2) Data Input Data Output During Read(Busy) During Program(Busy) During Erase(Busy) Write Protect Stand-by Write Mode Read Mode Mode Command Input Address Input(4clock) Command Input Address Input(4clock)
NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby.
9
K9F1G08U0B
Program / Erase Characteristics
Parameter Program Time Dummy Busy Time for Two-Plane Page Program Number of Partial Program Cycles Block Erase Time Symbol tPROG tDBSY Nop tBERS Min Typ 200 0.5 1.5
FLASH MEMORY
Max 700 1 4 2
Unit s s cycles ms
NOTE : 1. Typical value is measured at Vcc=3.3V, TA=25C. Not 100% tested. 2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25C temperature.
AC Timing Characteristics for Command / Address / Data Input
Parameter CLE Setup Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time Address to Data Loading Time Symbol tCLS
(1)
Min 12 5 20 5 12 12 5 12 5 25 10 100
Max -
Unit ns ns ns ns ns ns ns ns ns ns ns ns
tCLH tCS
(1)
tCH tWP tALS(1) tALH tDS
(1)
tDH tWC tWH tADL
(2)
NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low 2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle
10
K9F1G08U0B
AC Characteristics for Operation
Parameter Data Transfer from Cell to Register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time CE Access Time RE High to Output Hi-Z CE High to Output Hi-Z CE High to ALE or CLE Don't Care RE High to Output Hold RE Low to Output Hold CE High to Output Hold RE High Hold Time Output Hi-Z to RE Low RE High to WE Low WE High to RE Low Device Resetting Time(Read/Program/Erase) Symbol tR tAR tCLR tRR tRP tWB tRC tREA tCEA tRHZ tCHZ tCSD tRHOH tRLOH tCOH tREH tIR tRHW tWHR tRST Min 10 10 20 12 25 10 15 5 15 10 0 100 60
-
FLASH MEMORY
Max 25 100 20 25 100 30 5/10/500
(1)
Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5s.
11
K9F1G08U0B
NAND Flash Technical Notes
Initial Invalid Block(s)
FLASH MEMORY
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.
Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
*
Create (or update) Initial Invalid Block(s) Table No Check "FFh"
Check "FFh" at the column address 2048 of the 1st and 2nd page in the block
Yes No
Last Block ?
Yes
End
Figure 3. Flow chart to create initial invalid block table
12
K9F1G08U0B
NAND Flash Technical Notes (Continued)
Error in write or read operation
FLASH MEMORY
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode Write Read Erase Failure Program Failure Single Bit Failure
Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Verify ECC -> ECC Correction
ECC
: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ?
No
*
Program Error
Yes Program Completed
*
: If program operation results in an error, map out the block including the page in error and copy the target data to another block.
13
K9F1G08U0B
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Start Write 60h Write Block Address Write D0h Read Status Register
FLASH MEMORY
Read Flow Chart
Start Write 00h Write Address Write 30h Read Data ECC Generation I/O 6 = 1 ? or R/B = 1 ? Yes No No Reclaim the Error
Verify ECC Yes Page Read Completed
*
Erase Error
No
I/O 0 = 0 ? Yes Erase Completed
*
: If erase operation results in an error, map out the failing block and replace it with another block.
Block Replacement
1st (n-1)th nth (page)
{ {
Block A
1st (n-1)th nth (page)
* Step1 When an error happens in the nth page of the Block 'A' during erase or program operation. * Step2 Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block 'B') * Step3 Then, copy the nth page data of the Block 'A' in the buffer memory to the nth page of the Block 'B'. * Step4 Do not erase or program to Block 'A' by creating an 'invalid block' table or other appropriate scheme.

1 an error occurs. Buffer memory of the controller. Block B 2
14
K9F1G08U0B
NAND Flash Technical Notes (Continued)
Copy-Back Operation with EDC & Sector Definition for EDC
FLASH MEMORY
Generally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate bit errors. K9F1G08U0B supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation should be performed on either whole page(2112byte) or sector(528byte). Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes. A 2,112-byte page is composed of 4 sectors of 528-byte and each 528-byte sector is composed of 512-byte main area and 16-byte spare area.
Main Field (2,048 Byte)
Spare Field (64 Byte)
"A" area (1'st sector)
"B" area (2'nd sector)
"C" area (3'rd sector)
"D" area (4'th sector)
"E" area "F" area "G" area "H" area (1'st sector) (2'nd sector) (3'rd sector) (4'th sector)
512 Byte
512 Byte
512 Byte
512 Byte
16 Byte
16 Byte
16 Byte
16 Byte
Table 2. Definition of the 528-Byte Sector
Sector 1'st 528-Byte Sector 2'nd 528-Byte Sector 3'rd 528-Byte Sector 4'th 528-Byte Sector Main Field (Column 0~2,047) Area Name "A" "B" "C" "D" Column Address 0 ~ 511 512 ~ 1,023 1,024 ~ 1,535 1,536 ~ 2,047 Spare Field (Column 2,048~2,111) Area Name "E" "F" "G" "H" Column Address 2,048 ~ 2,063 2,064 ~ 2,079 2,080 ~ 2,095 2,096 ~ 2,111
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn't need to be page 0.
Page 63
(64)
:
Page 63
(64)
:
Page 31
(32)
:
Page 31
(1)
:
Page 2 Page 1 Page 0
(3) (2) (1)
Page 2 Page 1 Page 0
(3) (32) (2)
Data register
Data register
From the LSB page to MSB page DATA IN: Data (1) Data (64)
Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (64)
15
K9F1G08U0B
System Interface Using CE don't-care.
FLASH MEMORY
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of -seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption.
Figure 4. Program Operation with CE don't-care.
CE don't-care
I/Ox
80h
Address(4Cycles)
Data Input
Data Input
ALE
WE
CE
CLE
10h
tCS CE
tCH CE
tCEA
tREA tWP WE I/O0~7 out RE
Figure 5. Read Operation with CE don't-care.
CE don't-care
CE
RE ALE R/B

tR
I/Ox
WE
00h
Address(4Cycle)
30h
Data Output(serial access)
16

CLE
K9F1G08U0B
NOTE
FLASH MEMORY
I/O I/Ox I/O 0 ~ I/O 7 DATA Data In/Out ~2112byte Col. Add1 A0~A7 ADDRESS Col. Add2 A8~A11 Row Add1 A12~A19 Row Add2 A20~A27
Device K9F1G08U0B
Command Latch Cycle
CLE tCLS tCS CE tCLH tCH
tWP WE
tALS ALE tDS I/Ox
tALH
tDH
Command
Address Latch Cycle
tCLS CLE
tCS CE tWC tWC tWC
tWP WE tALS ALE tDS I/Ox tDH tWH tALH
tWP tALS tWH tALH
tWP tALS tWH tALH
tWP tALS tALH
tDS
tDH
tDS
tDH
tDS
tDH
Col. Add1
Col. Add2
Row Add1
Row Add2
17
K9F1G08U0B
Input Data Latch Cycle
tCLH
FLASH MEMORY
CLE
tCH CE
tWC ALE tALS tWP WE tDS I/Ox tWH tDH tDS tDH tDS tDH tWP

tWP DIN 0 DIN 1 DIN final
* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
CE
tRC tREH tCHZ tREA tCOH
RE tRHZ tRHZ tRHOH I/Ox tRR R/B
NOTES : Transition is measured at 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. tRLOH is valid when frequency is higher than 33MHz. tRHOH starts to be valid when frequency is lower than 33MHz.
Dout
tREA
tREA
Dout
Dout
18
K9F1G08U0B
FLASH MEMORY
Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L)
tRC tRP RE tREA tCEA I/Ox tRR tREA tRLOH Dout tREH
CE
tCHZ tCOH
tRHZ tRHOH
Dout
R/B
NOTES : Transition is measured at 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. tRLOH is valid when frequency is higher than 33MHz. tRHOH starts to be valid when frequency is lower than 33MHz.
Status Read Cycle & EDC Status Read Cycle
tCLR CLE tCLS tCS CE tCH tWP WE tWHR RE tDS I/Ox tDH tIR tREA tRHZ
tRHOH
tCLH
tCEA
tCHZ tCOH
70h or 7Bh
Status Output
19
K9F1G08U0B
Read Operation
tCLR CLE
FLASH MEMORY
CE tWC WE tWB tAR ALE tR RE tRR I/Ox
00h
Col. Add1 Col. Add2 Row Add1 Row Add2
tCSD
tRC
tRHZ
30h
tCOH tCHZ
Dout N+2
Dout N Dout N+1 Dout M
Column Address
Row Address Busy
R/B
Read Operation(Intercepted by CE)
CLE
CE
WE tWB tAR ALE tR RE tRR I/Ox
00h Col. Add1 Col. Add2 Row Add1 Row Add2 30h
tCSD
tRC
Dout N
Dout N+1
Column Address
Row Address
R/B
Busy
20
K9F1G08U0B
Random Data Output In a Page
CLE tCLR
CE
WE tWB tAR tWHR
21 tR tRC tRR
Col. Add2 Row Add1 Row Add2
ALE tREA
RE
I/Ox
Row Address
00h Dout N
Col. Add1
30h
Dout N+1
05h
Col Add1
Col Add2
E0h
Dout M
Dout M+1
Column Address
Column Address
FLASH MEMORY
R/B
Busy
K9F1G08U0B
Page Program Operation
FLASH MEMORY
CLE
CE
WE tADL ALE tWB tPROG tWHR
RE
Din Din N M 1 up to m Byte Serial Input
I/Ox
80h SerialData Input Command
Co.l Add1
Col. Add2
Row Add1
Row Add2
tWC
tWC
tWC
10h Program Command
70h Read Status Command
I/O0
Column Address
Row Address
R/B
m = 2112byte
I/O0=0 Successful Program I/O0=1 Error in Program
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
22
K9F1G08U0B
Page Program Operation with Random Data Input
CLE
CE
tWC tWC
tWC
WE tADL tADL tWB tPROG tWHR
ALE
RE
Serial Data Column Address Input Command Row Address Serial Input
Random Data Column Address Input Command
Serial Input
Col. Add2
I/Ox
80h 85h
Col. Add1
Col. Add2
Row Add1
Row Add2
Din N
Col. Add1
FLASH MEMORY
NOTES : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 2. For EDC operation, only one time random data input is possible at the same address.
23
Din M Din J
Din K
10h Program Command
70h Read Status Command
I/O0
R/B
K9F1G08U0B
Copy-Back Program Operation with Random Data Input
CLE
CE
tWC
WE tWB tADL
tPROG tWB
Column Address Row Address
Column Address Row Address
Busy
Copy-Back Data Input Command
I/O0=0 Successful Program I/O0=1 Error in Program I/O1 ~ I/O2 : EDC Status (7Bh only)
FLASH MEMORY
NOTES : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 2. For EDC operation, only one time random data input is possible at the same address.
Busy
24 tR
Row Add1 Row Add2
ALE
RE
I/Ox
35h
Col Add1 Col Add2
00h
Col Add1
Col Add2
85h
Row Add1 Row Add2
Data 1
Data N
10h
7Bh/70h I/O Read EDC Status or Read Status Command
R/B
K9F1G08U0B
Block Erase Operation
FLASH MEMORY
CLE
CE tWC WE tWB ALE tBERS tWHR
RE
I/Ox
60h
Row Add1
Row Add2
D0h
70h
I/O 0
Row Address
Auto Block Erase Setup Command
Erase Command
R/B
Busy
Read Status Command
I/O0=0 Successful Erase I/O0=1 Error in Erase
25
K9F1G08U0B
Read ID Operation
FLASH MEMORY
CLE
CE
WE tAR
ALE
RE tREA I/Ox
90h Read ID Command 00h Address 1cycle ECh Device Code 3rd cyc. 4th cyc. 5th cyc.
Maker Code Device Code
Device K9F1G08U0B
Device Code (2nd Cycle) F1h
3rd Cycle 00h
4th Cycle 95h
5th Cycle 40h
26
K9F1G08U0B
ID Definition Table 90 ID : Access command = 90H
Description 1 Byte 2nd Byte 3rd Byte 4th Byte 5th Byte
st
FLASH MEMORY
Maker Code Device Code Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum Plane Number, Plane Size
3rd ID Data
Description 1 2 4 8 2 Level Cell 4 Level Cell 8 Level Cell 16 Level Cell 1 2 4 8 Not Support Support Not Support Support 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 0 0 1 1 0 1 0 1
Internal Chip Number
Cell Type
Number of Simultaneously Programmed Pages Interleave Program Between multiple chips Cache Program
4th ID Data
Description Page Size (w/o redundant area ) 1KB 2KB 4KB 8KB 64KB 128KB 256KB 512KB 8 16 x8 x16 50ns/30ns 25ns Reserved Reserved 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 0 0 1 1 0 1 0 1
Block Size (w/o redundant area ) Redundant Area Size ( byte/512byte) Organization
Serial Access Minimum
27
K9F1G08U0B
5th ID Data
Description 1 2 4 8 64Mb 128Mb 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 I/O7 I/O6 I/O5 I/O4
FLASH MEMORY
I/O3 I/O2 0 0 1 1 0 1 0 1
I/O1
I/O0
Plane Number
Plane Size (w/o redundant Area)
Reserved
0
0
28
K9F1G08U0B
Device Operation
PAGE READ
FLASH MEMORY
Page read is initiated by writing 00h-30h to the command register along with four address cycles. After initial power up, 00h command is latched. Therefore only four address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data within the selected page are transferred to the data registers in less than 20s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 25ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page.
Figure 6. Read Operation
ALE
WE
CE
CLE
R/B RE I/Ox
00h
tR
Address(4Cycle) Col. Add.1,2 & Row Add.1,2
30h
Data Output(Serial Access)
Data Field
Spare Field
29
K9F1G08U0B
Figure 7. Random Data Output In a Page
tR
FLASH MEMORY
R/B RE I/Ox
00h Address 4Cycles 30h
Data Output
05h
Address 2Cycles Col. Add.1,2
E0h
Data Output
Col. Add.1,2 & Row Add.1,2
Data Field
Spare Field
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive bytes up to 2,112, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address inputs and then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes. The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.
Figure 8. Program & Read Status Operation
tPROG R/B
"0"
I/Ox
80h
Address & Data Input Col. Add.1,2 & Row Add.1,2 Data
10h
70h
I/O0 "1" Fail
Pass
30
K9F1G08U0B
Figure 9. Random Data Input In a Page
tPROG R/B
FLASH MEMORY
"0"
I/Ox
80h
Address & Data Input Col. Add.1,2 & Row Add1,2 Data
85h
Address & Data Input Col. Add.1,2 Data
10h
70h
I/O0 "1" Fail
Pass
Note: 1. For EDC operation, only one time random data input is possible at the same address.
Copy-Back Program
The Copy-Back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copying-program with the address of destination page. A read operation with "35h" command and the address of the source page moves the whole 2,112-byte data into the internal data buffer. As soon as the device returns to Ready state, Page-Copy Data-input command (85h) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to actually begin the programming operation. During tPROG, the device executes EDC of itself. Once the program process starts, the Read Status Register command (70h) or Read EDC Status command (7Bh) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When the Copy-Back Program is complete, the Write Status Bit(I/O 0) and EDC Status Bits (I/O 1 ~ I/O 2) may be checked(Figure 10 & Figure 11& Figure 12). The internal write verification detects only errors for "1"s that are not successfully programmed to "0"s and the internal EDC checks whether there is only 1-bit error for each 528-byte sector of the source page. More than 2-bit error detection is not available for each 528-byte sector. The command register remains in Read Status command mode or Read EDC Status command mode until another valid command is written to the command register. During copy-back program, data modification is possible using random data input command (85h) as shown in Figure11. But EDC status bits are not available during copy back for some bits or bytes modified by Random Data Input operation. However, in case of the 528 byte sector unit modification, EDC status bits are available.
Figure 10. Page Copy-Back Program Operation
tR R/B I/Ox
"0"
tPROG
00h
Add.(4Cycles)
35h
85h
Add.(4Cycles)
10h
70h/7Bh
I/O0 "1" Fail
Pass
Col. Add.1,2 & Row Add.1,2 Source Address
Col. Add.1,2 & Row Add.1,2 Destination Address
Note: 1. Copy-Back Program operation is allowed only within the same memory plane. 2. On the same plane, It's prohibited to operate copy-back program from an odd address page(source page) to an even address page(target page) or from an even address page(source page) to an odd address page(target page). Therefore, the copy-back program is permitted just between odd address pages or even address pages.
Figure 11. Page Copy-Back Program Operation with Random Data Input
tR R/B I/Ox
Add.(4Cycles) Add.(2Cycles) Col. Add.1,2
tPROG
00h
35h
85h
Add.(4Cycles)
Data
85h
Data
10h
70h
Col. Add.1,2 & Row Add.1,2 Source Address
Col. Add.1,2 & Row Add.1,2 Destination Address
There is no limitation for the number of repetition.
Note: 1. For EDC operation, only one time random data input is possible at the same address.
31
K9F1G08U0B
EDC OPERATION
FLASH MEMORY
Note that for the user who use Copy-Back with EDC mode, only one time random data input is possible at the same address during Copy-Back program or page program mode. For the user who use Copy-Back without EDC, there is no limitation for the random data input at the same address.
Figure 12. Page Copy-Back Program Operation with EDC & Read EDC Status
tR R/B I/Ox tPROG
00h
Add.(4Cycles)
35h
85h
Add.(4Cycles)
10h
7Bh
EDC Status Output
Col. Add.1,2 & Row Add.1,2 Source Address
Col. Add.1,2 & Row Add.1,2 Destination Address
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60h). Only address A18 to A27 is valid while A12 to A17 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
Figure 13. Block Erase Operation
R/B tBERS
"0"
I/Ox
60h
Address Input(2Cycle) Row Add 1,2
D0h
70h
I/O0 "1" Fail
Pass
32
K9F1G08U0B
READ STATUS
FLASH MEMORY
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 3 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles.
Table 3. Status Register Definition for 70h Command
I/O I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Page Program Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Block Erase Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Read Not use Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Pass : "0" Don't -cared Don't -cared Don't -cared Don't -cared Don't -cared Busy : "0" Protected : "0" Ready : "1" Not Protected : "1" Definition Fail : "1"
NOTE : 1. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed.
READ EDC STATUS
Read EDC status operation is only available on 'Copy Back Program'. The device contains an EDC Status Register which may be read to find out whether there is error during 'Read for Copy Back'. After writing 7Bh command to the command register, a read cycle outputs the content of the EDC Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 4 for specific Status Register definitions. The command register remains in EDC Status Read mode until further commands are issued to it.
Table 4. Status Register Definition for 7Bh Command
I/O I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 Copy Back Program Pass/Fail of Copy Back Program EDC Status Validity of EDC Status Not Use Not Use Not Use Ready/Busy of Copy Back Program Page Program Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Block Erase Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Read Not use Not use Not use Not Use Not Use Not Use Ready/Busy Definition Pass : "0", Fail : "1" No Error : "0", Error : "1" Valid : "1", Invalid : "0" Don't -cared Don't -cared Don't -cared Busy : "0", Ready : "1"
I/O 7 Write Protect of Copy Back Program
Write Protect Protected : "0", Not Protected :"1"
NOTE : 1. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed.
2. More than 2-bit error detection isn't available for each 528 Byte sector. That is to say, only 1-bit error detection is avaliable for each 528 Byte sector.
33
K9F1G08U0B
Read ID
FLASH MEMORY
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 18 shows the operation sequence.
Figure 18. Read ID Operation
CLE CE WE tAR ALE tWHR RE I/OX tREA
90h 00h Address. 1cycle Device Code Device code
tCLR tCEA
ECh
3rd Cyc.
4th Cyc.
5th Cyc.
Maker code
Device K9F1G08U0B
Device Code (2nd Cycle) F1h
3rd Cycle 00h
4th Cycle 95h
5th Cycle 40h
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 19 below.
Figure 19. RESET Operation
tRST R/B I/OX
FFh
Table 5. Device Status
After Power-up Operation mode 00h Command is latched After Reset Waiting for next command
34
K9F1G08U0B
READY/BUSY
FLASH MEMORY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig.20). Its value can be determined by the following guidance.
Rp VCC
ibusy 3.3V device - VOL : 0.4V, VOH : 2.4V Ready Vcc
R/B open drain output
VOH
CL
VOL Busy tf tr
GND Device
Figure 20. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25C , CL = 50pF
2.4
200n
tr,tf [s]
Ibusy
150 1.2
200
2m
Ibusy [A]
100n tr
50 3.6
100
0.8 0.6
1m
tf
3.6
3.6
3.6
1K
2K 3K Rp(ohm)
4K
Rp value guidance
VCC(Max.) - VOL(Max.) IOL + IL = 3.2V 8mA + IL
Rp(min, 3.3V part) =
where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr
35
K9F1G08U0B
Data Protection & Power up sequence
FLASH MEMORY
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 100s is required before internal circuit gets ready for any command sequences as shown in Figure 21. The two step command sequence for program/erase provides additional software protection.
Figure 21. AC Waveforms for Power Transition
3.3V device : ~ 2.5V VCC High
3.3V device : ~ 2.5V
WP
WE
36
100s

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