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| EM77F900 USB HUB+BB Controller Product Specification DOC. VERSION 1.0 ELAN MICROELECTRONICS CORP. July 2007 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright (c) 2007 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Flat A, 19F., World Tech Centre 95 How Ming Street, Kwun Tong Kowloon, HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. 3F, SSMEC Bldg., Gaoxin S. Ave. I Shenzhen Hi-tech Industrial Park (South Area), Shenzhen CHINA 518057 Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group (USA) 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8225 Fax: +1 408 366-8220 Shanghai: Elan Microelectronics Shanghai, Ltd. #23, Zone 115, Lane 572, Bibo Rd. Zhangjiang Hi-Tech Park Shanghai, CHINA 201203 Tel: +86 21 5080-3866 Fax: +86 21 5080-4600 Contents Contents 1 2 General Description ................................................................................................ 1 Features ................................................................................................................... 1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Core ................................................................................................................. 1 Oscillators/System Clocks ................................................................................ 2 Input and Output (I/O) Pins ............................................................................... 2 Timers and Counters ........................................................................................ 2 Interrupt Sources and Features ........................................................................ 2 Baseband ......................................................................................................... 4 Universal Serial Bus HUB (USB HUB) .............................................................. 4 Serial Peripheral Interface (SPI) ....................................................................... 4 2.9 Pulse Width Modulation (PWM) ........................................................................ 4 2.10 Analog-to-Digital Converter (ADC) ................................................................... 4 3 4 5 6 2.11 Built-in Voltage Regulator ................................................................................ 4 Pin Assignment ....................................................................................................... 5 Pin Description........................................................................................................ 6 Block Diagram ......................................................................................................... 9 Memory .................................................................................................................. 10 6.1 Program Memory............................................................................................ 10 6.2 RAM-Register ................................................................................................ 11 Function Description ............................................................................................ 33 7.1 Special Purpose Registers.............................................................................. 33 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9 7.1.10 7.1.11 7.1.12 7.1.13 7.1.14 7.1.15 7.1.16 7.1.17 7.1.18 Accumulator - ACC .......................................................................................... 33 Indirect Addressing Contents - IAC0 and IAC1 ............................................... 33 High byte Program Counter HPC and Low byte Program Counter LPC.......... 33 Status Register - SR ........................................................................................ 34 RAM Bank Selector - RAMBS0 and RAMBS1 ................................................ 34 ROM Page Selector - ROMPS ........................................................................ 35 Indirect Addressing Pointers - IAP0 and IAP1 ................................................. 35 Indirect Address Pointer Direction Control Register - IAPDR ........................ 35 Pointer of Table Look-up - LTBL (0x0B), and HTBL ........................................ 35 Stack Pointer - STKPTR .................................................................................. 35 Repeat Counter - RPTC .................................................................................. 35 Prescaler Counter - PRC ................................................................................. 36 Real Time Clock Counter - RTCC.................................................................... 36 Interrupt Flag Register - INTF.......................................................................... 36 Key Wake-up Flag Register - KWUAIF and KWUBIF ..................................... 36 I/O Port Registers - PTA ~ PTF........................................................................ 36 16-bit Free Run Counter (FRC) - LFRC, HFRC and LFRCB .......................... 37 Serial Peripheral Interface Read Register - SPIRB ......................................... 37 * iii 7 Product Specification (V1.0) 07.31.2007 Contents 7.1.19 7.1.20 7.1.21 7.1.22 7.1.23 7.1.24 7.1.25 7.1.26 7.1.27 Serial Peripheral Interface Write Register - SPIWB ........................................ 37 Converting Value of ADC - ADDATAH and ADDATAL ..................................... 37 PWM Duty - DT0L/DT0H and DT1L/DT1H...................................................... 37 PWM Period - PRD0L/PRD0H and PRD1L/PRD1H........................................ 37 PWM Duty Latch - DL0L/DL0H and DL1L/DL1H............................................. 37 BB Address Register - RFAAR ........................................................................ 37 BB Data Buffer Register - RFDB ..................................................................... 37 BB Data Read/Write Control Register - RFACR .............................................. 38 BB Interrupt Flag Register - RFINTF ............................................................... 38 7.2 7.3 Dual Port Register (0x40 ~ 0x7F) ................................................................... 38 System Status, Control and Configuration Registers....................................... 38 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 7.3.13 7.3.14 7.3.15 Peripherals Enable Control - PRIE .................................................................. 38 Interrupts Enable Control - INTE ..................................................................... 39 Key Wake-up Enable Control - KWUAIE and KWUBIE................................... 39 External Interrupts Edge Control - EINTED ..................................................... 40 Serial Peripheral Serial (SPI) Enable Control Register - SPIC........................ 40 I/O Control Registers - IOCA~IOCF ................................................................ 41 Pull-up Resistance Control Registers for Ports A~F - PUCA~PUCF .............. 41 Open Drain Control Registers of Port B - ODCB............................................. 41 Timer Clock Counter Controller - TCCC .......................................................... 41 Free Run Counter Controller - FRCC .............................................................. 42 Watchdog Timer Controller - WDTC ................................................................ 42 ADC analog Input Pin Select - ADCAIS........................................................... 43 ADC Configuration Register - ADCCR ............................................................ 43 PWM Control Register - PWMCR.................................................................... 43 BB Interrupt Control Register - RFINTE .......................................................... 44 7.4 8 USB Status, Control and Configuration Registers ........................................... 44 7.5 Code Option (ROM-0x3FFF) .......................................................................... 44 Base Band (BB) ..................................................................................................... 45 8.1 BB: Standard Interface to the RFW102 Series ................................................ 45 8.1.1 8.1.2 8.1.3 8.1.4 Features............................................................................................................ 45 Description........................................................................................................ 46 I/O and Package Description............................................................................ 47 BB Architecture ................................................................................................. 48 Reset ................................................................................................................ 49 Power Saving Modes........................................................................................ 49 8.2.2.1 Power-Down Mode ............................................................................ 49 8.2.2.2 Idle Mode ........................................................................................... 49 Preamble Correlation........................................................................................ 50 Refresh Bit ........................................................................................................ 50 Bit Structure ...................................................................................................... 51 CRC .................................................................................................................. 52 Product Specification (V1.0) 07.31.2007 8.2 BB Description................................................................................................ 49 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 iv * Contents 8.2.7 8.2.8 8.2.9 8.2.10 8.2.11 8.2.12 RX FIFO............................................................................................................ 53 TX FIFO ............................................................................................................ 54 Interrupt Driver.................................................................................................. 54 Packet Size....................................................................................................... 55 NET_ID and NODE_ID Filters .......................................................................... 56 Carrier-sense .................................................................................................... 56 8.2.12.1 RFWaves Carrier-Sense Algorithm ................................................... 57 8.2.13 Receiver Reference Capacitor Discharge ........................................................ 58 8.2.14 Changing BB Configuration .............................................................................. 58 8.2.15 Input Synchronizer............................................................................................ 59 8.3 Register Description ....................................................................................... 59 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.3.10 8.3.11 8.3.12 8.3.13 8.3.14 8.3.15 8.3.16 Bit Length Register (BLR)................................................................................. 59 Preamble Low Register (PRE-L) ...................................................................... 59 Preamble High Register (PRE-H)..................................................................... 59 Packet Parameter Register (PPR).................................................................... 60 System Control Register 1 (SCR1)................................................................... 61 System Control Register 2 (SCR2)................................................................... 61 System Control Register 3 (SCR3)................................................................... 63 System Control Register 4 (SCR4)................................................................... 64 Transmit FIFO Status Register (TFSR) ............................................................ 65 Receive FIFO Status Register (RFSR)............................................................. 65 Location Control Register (LCR) ...................................................................... 65 Node Identity Register (BIR)............................................................................. 66 Net Identity Register (NIR) ............................................................................... 66 System Status Register (SSR) ......................................................................... 67 Packet Size Register (PSR) ............................................................................. 68 Carrier Sense Register (CSR) .......................................................................... 68 Interrupt Enable Register (IER) ........................................................................ 69 Interrupt Identification Register (IIR)................................................................. 70 8.4 Interrupt Registers .......................................................................................... 69 8.4.1 8.4.2 8.5 8.6 List of BB Register Mapping ........................................................................... 71 MCU BB Control Registers ............................................................................. 71 8.6.1 8.6.2 Control Registers List ....................................................................................... 71 BB Control Example ......................................................................................... 72 9 Universal Serial Bus Hub (USB Hub) ................................................................... 74 9.1 9.2 9.3 9.4 9.5 9.6 Instruction....................................................................................................... 74 Block Diagram ................................................................................................ 74 USB Embedded Function FIFO Allocation ...................................................... 74 Pin Description ............................................................................................... 75 Timing Diagram of MCU Interface................................................................... 76 USB Hub and Function Register Summary..................................................... 77 9.6.1 USB General Control Register - GCNTR ........................................................ 78 Product Specification (V1.0) 07.31.2007 *v Contents 9.6.2 9.6.3 9.6.4 9.6.5 9.6.6 9.6.7 9.6.8 9.6.9 9.6.10 9.6.11 9.6.12 9.6.13 9.6.14 9.6.15 9.6.16 9.6.17 9.6.18 9.6.19 9.6.20 9.6.21 9.6.22 9.6.23 9.6.24 9.6.25 9.6.26 9.6.27 9.6.28 9.6.29 9.6.30 9.6.31 9.6.32 9.6.33 9.6.34 9.6.35 9.6.36 9.6.37 Endpoint X Control Register - EP1/2/3CNTR .................................................. 80 Endpoint Interrupt Event Status Register - EPINTR ........................................ 80 Endpoint Interrupt Event Enable Control Register - EPINTE .......................... 82 State Interrupt Event Flag Register - STAINTR ............................................... 82 State interrupt event Enable Control Register - STAINTE ............................... 83 Function Address Register - FAR .................................................................... 83 Endpoint 0 RX Token Register - EP0RXTR..................................................... 83 Endpoint 0 RX Command/Status Register - EP0RXCSR............................... 84 Endpoint 0 TX Command/Status Register - EP0TXCSR................................. 85 Endpoint X Command/Status Register - EP1/2/3CSR .................................... 86 Endpoint 0 RX Count Register - EP0RXCTR .................................................. 87 Endpoint 0 TX Count Register - EP0TXCTR ................................................... 88 Endpoint X Count Register - EP1/2/3CTR....................................................... 88 Endpoint 0 RX Data Register - EP0RXDAR .................................................... 88 Endpoint 0 TX Data Register - EP0TXDAR..................................................... 88 Endpoint X Data Register - EP1/2/3DAR......................................................... 89 Hub Global State Register - HGSR.................................................................. 89 Hub Interrupt Event Register - HINTR ............................................................. 90 Hub Interrupt Event Enable Control Register - HINTE .................................... 91 Hub Address Register - HAR ........................................................................... 91 HUB Endpoint 0 RX Token Register - HEP0RXTR ......................................... 91 HUB Endpoint 0 Rx Command/Status Register - HEP0RXCSR ..................... 92 HUB Endpoint 0 TX Command/Status Register - HEP0TXCSR ..................... 93 HUB Endpoint 1 TX Command/Status Register - HEP1TXCSR ..................... 94 HUB Endpoint 0 RX Count Register - HEP0RXCTR....................................... 95 HUB Endpoint 0 TX count Register - HEP0TXCTR ........................................ 95 HUB Endpoint 0 RX Data Register - HEP0RXDAR......................................... 95 HUB Endpoint 0 TX Data Register - HEP0TXDAR.......................................... 95 HUB Endpoint 1 TX Data Register - HEP1TXDAR.......................................... 95 HUB Port Control Register - HPCONR............................................................ 96 HUB Port State Register - HPSTAR ................................................................ 97 Hub Status Register - HSR .............................................................................. 97 Hub Port X Status Register - HPSR1/2/3/4 ..................................................... 98 Hub PortX Status Change Register - HPSCR1/2/3/4 ...................................... 99 Frame Number Low-Byte Register - FNLR ..................................................... 99 Frame Number High-Byte Register - FNHR .................................................... 99 10 Direction Serial Peripheral Interface (SPI) ......................................................... 100 10.1 Introduction................................................................................................... 100 10.2 Features ....................................................................................................... 100 10.3 Block Diagram .............................................................................................. 100 10.4 Transceiver Timing ....................................................................................... 101 10.5 SPI Related Registers .................................................................................. 101 10.6 Function Description ..................................................................................... 102 vi * Product Specification (V1.0) 07.31.2007 Contents 10.6.1 Block Diagram Description ............................................................................. 102 10.6.2 Signal & Pin Description ................................................................................. 102 11 Analog-to-Digital Converter (ADC) ..................................................................... 103 11.1 ADC Control Registers ................................................................................. 104 11.2 Programming Steps/Considerations.............................................................. 106 Dual Pulse Width Modulations (PWM0 and PWM1)........................................... 107 12.1 Overview ...................................................................................................... 107 12.2 PWM Control Registers ................................................................................ 108 12.3 PWM Programming Procedures/Steps.......................................................... 110 Interrupts ..............................................................................................................110 13.1 Introduction................................................................................................... 110 Circuitry of Input and Output Pins ......................................................................113 14.1 Introduction................................................................................................... 113 Timer/Counter System .........................................................................................113 15.1 Introduction................................................................................................... 113 15.2 Time Clock Counter (TCC) ........................................................................... 113 15.2.1 Block Diagram of TCC .....................................................................................114 15.2.2 TCC Control Registers ....................................................................................114 15.2.3 TCC Programming Procedures/Steps .............................................................115 12 13 14 15 15.3 Free Run Counter......................................................................................... 115 15.3.1 Block Diagram of FRC.....................................................................................115 15.3.2 FRC Control Registers ....................................................................................116 15.3.3 FRC Programming Procedures/Steps .............................................................116 16 Reset and Wake Up ..............................................................................................117 16.1 Reset ............................................................................................................ 117 16.2 The Status of RST, T, and P of the STATUS Register.................................... 117 16.3 System Set-up (SSU) Time........................................................................... 118 16.4 Wake-up Procedure on Power-on Reset....................................................... 118 Oscillators.............................................................................................................119 17.1 Introduction................................................................................................... 119 17.2 Clock Signal Distribution............................................................................... 119 17.3 PLL Oscillator ............................................................................................... 119 Low-Power Mode................................................................................................. 120 18.1 Introduction................................................................................................... 120 18.2 Green Mode ................................................................................................. 120 18.3 Sleep Mode .................................................................................................. 121 Instruction Description ....................................................................................... 121 19.1 Instruction Set Summary .............................................................................. 121 Electrical Characteristics.................................................................................... 124 20.1 Absolute Maximum Ratings .......................................................................... 124 17 18 19 20 Product Specification (V1.0) 07.31.2007 * vii Contents 20.2 DC Electrical Characteristic .......................................................................... 124 20.3 Voltage Detector Electrical Characteristic ..................................................... 125 20.4 AC Electrical Characteristic .......................................................................... 125 20.4.1 MCU................................................................................................................ 125 20.4.2 BB ................................................................................................................... 126 21 Application Circuit .............................................................................................. 127 APPENDIX A B Package Type ...................................................................................................... 128 Package Information ........................................................................................... 128 Specification Revision History Doc. Version 1.0 Revision Description Initial new released version Date 2007/07/31 viii * Product Specification (V1.0) 07.31.2007 EM77F900 USB HUB+BB Controller 1 General Description The EM77F900 from ELAN Technology is a low-cost and high performance 8-bit CMOS advance RISC architecture microcontroller device. It has an on-chip 1-Mbps RF driver Baseband (BB), Universal Serial Bus Hub (USB Hub), Serial Peripheral Interface (SPI), dual Pulse Width Modulation (PWM) with 16-bit resolution, an 8-bit Timer Clock Counter (TCC) and a 16-bit Free Run Timer, multi-channel Analog to Digital Converter (ADC) with 10-bit resolution, Key Wake-up function (KWU), Power-on Reset (POR), Watchdog Timer (WDT), security Protection Bit, and power saving Sleep Mode. All these features combine to ensure applications require the least external components, hence, not only reduce system cost, but also have the advantage of low power consumption and enhanced device reliability. The 100-pin EM77F900 is available in a very cost-effective flash version. It is also suitable and flexible for any quantities of volume production. 2 Features 2.1 Core Operating Voltage Range: 2.2V ~ 3.6V DC (ADC reference volt 3V) Operating Temperature Range: 0 C ~ 70 C Operating Frequency Range: DC ~ 48MHz (1 clock/cycle) 6 MHz external clock source 6/12/24 MHz Core & WM clock 48 MHz internal USB HUB clock 16K x 16 bits on-chip Program ROM 1.3K x 8 bits on-chip Register (SRAM) plus USB indirect addressing RAM Watchdog Timer (WDT) 16-level stacks for both CALL and interrupt subroutine Internal Power-on Reset (POR) function Code protection function available All single cycle (1 clock) instruction except for conditional branches which are two or three cycles Direct, indirect and relative addressing modes Low power, high speed CMOS technology Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) *1 EM77F900 USB HUB+BB Controller Power consumption: < 4 mA @ 3.3V, 6 MHz < 1 A standby current 2.2 Oscillators/System Clocks Three oscillator options: * * * High frequency Crystal oscillator/Resonator PLL oscillator: 6MHz, 12 MHz, 24 MHz, and 48 MHz (External crystal should be 6 MHz). External RC oscillator Three modes of system clocks: * * * Sleep mode Green mode Normal mode External RC oscillator for Power-on Reset (POR) and Watchdog Timer (WDT) 2.3 Input and Output (I/O) Pins Max. of 42 I/O pins Pull-up resistor options Key Wake-up function Open drain output options 2.4 Timers and Counters Programmable 8-bit real Time Clock/Counter (TCC) with prescaler and overflow interrupt 16-bit Free Run Counter (FRC) with overflow interrupt 2.5 Interrupt Sources and Features Hardware priority check Different interrupt vectors Interrupts * * * Key Wake up External pin interrupt 16-bit Free Run Counter Overflow 2* Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller * * * * * TCC (time-base) overflow Read Buffer Full Interrupt in Serial Peripheral Interface (SPI); Complete Analog-to-digital conversion (ADC) One complete period of Pulse Width Modulation (PWM) Baseband (BB) function interrupts: CSD: carrier sense detection TX_AE: TX_FIFO almost full RX_AF: RX_FIFO almost full TX_ EMPTY: finish transmitting a package RX_OF: RX_FIFO overflow LINK_DIS: zero counter capacitor discharge mechanism LOCK_OUT: finish receiving a package LOCK_IN: start receiving a package * USB Hub function interrupts: Endpoint 0 Interrupt Event: INT0RX: EP0 USB RX Event INT0TX: EP0 USB TX Event INT0IN: EP0 USB IN Token Event Endpoint X Interrupt Event: INT1: EP1 Interrupt INT2: EP2 Interrupt INT3: EP3 Interrupt Device State Interrupt Event: RSTINT: USB Bus Reset Event Detect IDLEINT: USB Bus Suspend Detect RUEINT: Enable USB Bus Resume Detect FRWPINT: Function Remote Wake-up Interrupt Hub Interrupt Event: HINT0RX: Hub EP0 USB RX Event HINT0TX: Hub EP0 USB TX Event HINT0IN: Hub EP0 USB IN Token Event HINT1: Hub EP1 Interrupt Hub State Interrupt Event: EOF1INT: EOF1 Interrupt EOF2INT: EOF2 Interrupt SOFINT: Start of Frame Interrupt HPSTSCINT: Hub and Port Status Change Interrupt Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) *3 EM77F900 USB HUB+BB Controller 2.6 Baseband Serial to Parallel conversion of RFW102 interface Input FIFO (RX_FIFO) Output FIFO (TX_FIFO) Preamble Correlation Packet Address Filter (unique Network) CRC calculation Inter-RFWAVES networks Carrier-sense Discharge of RFW-102 reference capacitor Compensate for clock drifts between the transmitting EM77F900 and the receiving EM77F900 up to 1000ppm. Hence, the EM77F900 requires low performance crystal Interrupt Driver 2.7 Universal Serial Bus HUB (USB HUB) One-to-Three Built-in USB HUB with embedded function * * * One upstream port capable of full speed (12 Mbps, 2 lines D+/D-) Up to three downstream ports capable of full speed (12Mbps) 5V supplied from PC USB interface USB Specification Compliance * * Conforms to USB specification, version 1.1. Conforms to USB Human Interface Device (HID) Specification, version 1.1 2.8 Serial Peripheral Interface (SPI) Either MSB or LBS can be remitted/received first Both Master and Slave modes available 2.9 Pulse Width Modulation (PWM) Dual Pulse Width Modulation (PWM) with 16-bit resolution 2.10 Analog-to-Digital Converter (ADC) 16 multi-channel Analog-to-Digital Converter with 10-bit resolution 2.11 Built-in Voltage Regulator Internal 3.3V regulator is used to be the power source of the MCU and the regulated output pin to provide a pull-up source for the external USB resistor on the downstream D- pin. 4* Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 3 Pin Assignment AVDD1 RF_ACT TXRX RFIO AVSS1 PTC0/SDI PTC1/SDO PTC2/SCK PTC3/EINT0 PTC4/EINT1 PTC5/PWM1 PLLC DVSS1 OSCO OSCI DVDD1 /PRST PGCLK PGDATA RCI NC NC NC NC NC DVSS3 AVSS2 PTD0/ADC0 PTD1/ADC1 PTD2/ADC2 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 PTB7/KWU7 PTB6/KWU6 PTB5/KWU5 PTB4/KWU4 PTB3/KWU3 PTB2/KWU2 PTB1/KWU1 PTB0/KWU0 TEST_C2 TEST_C1 TEST_C0 TEST_D7 TEST_D6 TEST_D5 TEST_D4 TEST_D3 TEST_D2 TEST_D1 TEST_D0 REG_C DVSS0 PTA0/KWU8 PTA1/KWU9 PTA2/KWUA PTA3/KWUB /RST DVDD0 PTA4 PTA5 PTA6 PTA7/PWM0 DVSS2 TUSB_CLK UPRT_D+ UPRT_DDPRT2_D+ DPRT2_DDPRT3_D+ DPRT3_DDPRT4_D+ DPRT4_DDVDD2 DPRT2_OVCUR_DET DPRT3_OVCUR_DET DPRT4_OVCUR_DET DPRT2_PWR_EN DPRT3_PWR_EN DPRT4_PWR_EN VUSB_3.3V AVDD0_5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PTD3/ADC3 PTD4/ADC4 PTD5/ADC5 PTD6/ADC6 PTD7/ADC7 VREF_ADC PTE0/ADC8 PTE1/ADC9 PTE2/ADCA PTE3/ADCB PTE4/ADCC PTE5/ADCD PTE6/ADCE PTE7/ADCF AVDD2 DVDD3 PTF0 PTF1 PTF2 PTF3 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 EM77F900 100 QFP Fig. 3-1 Pad and Pin Configuration of EM77F900 Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) *5 EM77F900 USB HUB+BB Controller 4 Pin Description Table 3.2-2: Corresponding relationship between the pad and pins of EM77F900 Pin No. 1 2~5 6 Symbol DVSS KWU8~B, PTA0~3 /RST Type - I/O - Smith Pull High Open Trigger /50K Drain - - - - - - - Function Description Ground Pin Pins 0~3 of Port A (default) Key Wake up 8~B Reset Power supply for digital circuit. The value of power source should be within the range of operating voltage. 5V direct power input is not allowed. Pins 4~6 of Port A Pin 7 of Port A PWM0 output Ground Pin USB test clock input USB Hub upstream differential data plus USB Hub upstream differential data minus USB Hub downstream differential data plus USB Hub downstream differential data minus USB Hub downstream differential data plus USB Hub downstream differential data minus USB Hub downstream differential data plus USB Hub downstream differential data minus Power supply for digital circuit. The value of power source should be within the range of operating voltage. 5V direct power input is not allowed. USB Hub external power switch port USB Hub external power switch port USB Hub external power switch port USB Hub external power switch enable port USB Hub external power switch enable port 7 DVDD0 - - - - 8~10 11 12 13 14 15 16 17 18 19 20 21 PTA4~6 PWM0/PTA7 DVSS2 TUSB_CLK UPRT_D+ UPRT_DDPRT2_D+ DPRT2_DDPRT3_D+ DPRT3_DDPRT4_D+ DPRT4_D- I/O I/O -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 22 DVDD2 - - - - 23 24 25 26 27 DPRT2_OVC UR_DET DPRT3_OVC UR_DET DPRT4_OVC UR_DET DPRT2_PWR _EN DPRT3_PWR _EN - - - - - - - - - - - - - - - - - - - - 6* Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Pin No. 28 29 Symbol DPRT4_PWR _EN VUSB_3.3V Type - - Schmitt Pull-high Open Trigger /50K Drain - - - - - - Function Description USB Hub external power switch enable port 3.3V stable output 5V USB Power source input pin. If REG_C pin is connected to GND: enable regulator function. USB 5V power will be regulated down to 3.3V as whole chip operating power source. If connected to VDD: disable regulator function. VDD_5V pin has to be connected with 3.3V power source. 5V power source is not allowed. 30 AVDD0_5V - - - - 31 REG_C I I/O I I/O - - - - - - - - - - USB 5V-to-3.3V internal regulator enable/disable control pin. Test data pin Test command pin Pin 0~7 of Port B (default) Key Wake up 0~7 Power supply for WM circuit. The value of the power source should be within the range of the operating voltage. 5V direct power input is not allowed. WM/RF Active Transceiver modes control Transceiver to/from RF modem Ground Pin for WM circuit Data in of SPI Pin 0 of Port C Data out of SPI Pin 1 of Port C Clock of SPI Pin 2 of Port C External interrupt Pin 0 Pin 3 of Port C External interrupt Pin 1 Pin 4 of Port C Pin 5 of Port C PWM1 output 32~39 TEST_D0~7 40~42 TEST_C0~2 43~50 KWU0~7, PTB0~7 51 AVDD1 - - - - 52 53 54 55 56 57 58 59 60 61 RF_ACT TXRX RFIO AVSS1 SDI/PTC0 SDO/PTC1 SCK/PTC2 EINT0/ PTC3 EINT1/ PTC4 PWM1/PTC5 O O I/O I/O I/O I/O I/O I/O I/O - - - - - - - - - - - - - - - - - - - - Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) *7 EM77F900 USB HUB+BB Controller Pin No. 62 63 64 65 Symbol PLLC DVSS1 OSCO OSCI Type - - O I Schmitt Pull-high Open Trigger /50K Drain - - - - - - - - - - - - Function Description External capacitor for PLL circuit Ground Pin Output of crystal oscillator Input of crystal oscillator Power supply for digital circuit. The value of power source should be within the range of operating voltage. 5V direct power input is not allowed. Programming reset pin Programming clock input pin Programming data pin Input of RC oscillator No use Ground pin Ground Pin for ADC Pins 0~7 of Port D Input 0~7 of ADC Reference voltage for ADC Pins 0~7 of Port E Input 8~F of ADC Power supply for ADC circuit. The value of the power source should be within the range of the operating voltage. 5V direct power input is not allowed. Power supply for digital circuit. The value of power source should be within the range of operating voltage. 5V direct power input is not allowed. Pins 0~3 of Port F 66 DVDD1 - - - - 67 68 69 70 71~75 76 77 78~85 86 87~94 /PRST PGCLK PGDATA RCI NC DVSS3 AVSS2 PTD0~7, ADC0~7 VREF_ADC PTE0~7, ADC8~F - - - I - - - I/O I I/O - - - - - - - - - - - - - - - - - - - - - - - - - - - 95 AVDD2 - - - - 96 DVDD3 - - - - 97~100 PTF0~3 I/O - - 8* Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 5 Block Diagram ROM MCU RAM DOWNSTREAM Port 3 UPSTREAM Port I/O Port USB HUB+ Embedded Port SPI ADC RF Module WM PWM PLL Timer Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) *9 EM77F900 USB HUB+BB Controller 6 Memory 6.1 Program Memory The EM77F900 has a 14-bit program counter (PC). The program memory space, which is partitioned into two pages can address up to 16K. Each page has 8K in length. Fig. 6-1 depicts the profile of the program memory and stack. The initial address is 0x0000. The table of the interrupt-vectors starts from 0x10 to 0xA8 with every other eight-address space. HP C+LP C IN T CA LL PC8 PC7~PC 0 PC13 PC 12 PC 11 P C 10 PC9 S TA CK 0 RET RETL RETI S TA CK 1 S TA CK 2 S TA CK 3 S TA CK 4 S TA CK 5 S TA CK 6 S TA CK 7 S TA CK 8 ROMPS 0 1 A d d re s s 0 00 0~ 1F F F 2 00 0~ 3F F F Page 0 1 16K RO M A d d re s s 0000 0010 0018 0020 0028 0030 0038 0040 0048 0050 0058 0060 0068 0070 0078 0080 0088 0090 0098 00A0 00A8 V e c to r RESET K W U A ,B E IN T 0 ,1 FRC TCC R B F (S P I) ADC P W M 0 ,1 CSD TX_AE RX_A F TX_E M PTY R X_O F L IN K _ D IS LO CK _O UT L O C K _ IN IN T 0 R X ,T X,IN IN T 1 ,2 ,3 R S T IN T ,ID L E IN T , R U E IN T , F R W P IN T H IN T 0 R X , T X , IN , H IN T 1 E O F1, E O F2, SOF, HPSTSC S TA CK 9 STACKA STACKB STACKC STACKD STACKE STACKF ACCD ACCE ACCF RAMBS0D RAMBS0E R AM B S0F ROMPSD ROMPSE RO MPSF SRD SRE SRF 1 6 -le ve l S ta c k s In te rru p t V e c to rs Fig. 6-1 Configuration of Program Memory (ROM) for EM77F900 10 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 6.2 RAM-Register A total of 1368 accessible bytes of data memory are available for the EM77F900. By function, they are classified into general purpose registers, system control / configuration registers, specification purpose registers, USB control/status registers, baseband (BB) control/status registers, SPI control/status registers, timer/counter registers, and I/O port status/control registers. All of the above registers except I/O ports and their related control registers are implemented as static RAM. The RAM configurations are shown in Fig. 6-2. S y s te m , C o n fig u ra tio n , C lo c k , I/O P o rt 3 0 R e g is te rs 31 00 G e n e ra l P u rp o s e R e g is te rs 3F 40 D u a l P o rt R e g is te rs 7F 001 80 P e rip h e ra ls & In te rru p tC o n tro l R e g is te rs 9A 9B 180 00 3F 00 EP0 RX B u ffe r EP0 TX B u ffe r EP1 B u ffe r EP2 B u ffe r EP3 B u ffe r 010 280 110 680 G e n e ra l P u rp o s e R e g is te rs Bank1 3F 00 3F 00 3F G e n e ra l P u rp o s e R e g is te rs Bank 2 .... G e n e ra l P u rp o s e R e g is te rs Bank 6 G e n e ra l P u rp o s e R e g is te rs Bank 0 FF 1CB 1CC USB HUB S ta tu s /In te r ru p t C o n tro l R e g is te rs 1FF 00 3F 00 07 00 07 00 07 HUB EP0 R X B u ffe r HUB EP0 T X B u ffe r HUB EP1 T X B u ffe r 2FF 6FF Fig. 6-2 Data Memory Configuration (RAM) of EM77F900 Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 11 EM77F900 USB HUB+BB Controller The table is a summary of all registers except general purpose registers. Addr Name Reset Type Full Name Bit Name 0x00 IAC0 Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name 0x01 HPC Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name 0x02 LPC Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name 0x03 SR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name 0x04 RAMBS0 Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name 0x05 ROMPS Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int RST R/W 0 P P PCF R/W 0 0 PCE R/W 0 0 PC7 R 0 0 PC6 R 0 0 IAC07 R/W 0 0 P IAC06 R/W 0 0 P Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indirect Addressing Register contents IAC05 R/W 0 0 P IAC04 R/W 0 0 P IAC03 R/W 0 0 P IAC02 R/W 0 0 P IAC01 R/W 0 0 P IAC00 R/W 0 0 P Most Significant Byte of Programming Counter PC5 R 0 0 PC4 R 0 0 PC3 R 0 0 PC2 R 0 0 PC1 R 0 0 PC0 R 0 0 Jump to the corresponding interrupt vector or continue to execute next instruction Least Significant Byte of Programming Counter PCD R/W 0 0 PCC R/W 0 0 PCB R/W 0 0 PCA R/W 0 0 PC9 R/W 0 0 PC8 R/W 0 0 Jump to the corresponding interrupt vector or continue to execute next instruction Status Register T R/W 1 T T P R/W 1 T T Z R/W U P P DC R/W U P P C R/W U P P RAM Bank Select 0 RBS02 R/W 0 0 P RBS01 R/W 0 0 P RBS00 R/W 0 0 P ROM Page Select RPS0 R/W 0 0 P 12 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indirect Addressing Pointer 0 IAP07 R/W 0 0 P IAP06 R/W 0 0 P IAP05 R/W 0 0 P IAP04 R/W 0 0 P IAP03 R/W 0 0 P IAP02 R/W 0 0 P IAP01 R/W 0 0 P IAP00 R/W 0 0 P 0x06 IAP0 Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name RAM Bank Select 1 RBS12 R/W 0 0 P RBS11 R/W 0 0 P RBS10 R/W 0 0 P 0x07 RAMBS1 Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Indirect Addressing Pointer 1 IAP17 R/W 0 0 P IAP16 R/W 0 0 P IAP15 R/W 0 0 P IAP14 R/W 0 0 P IAP13 R/W 0 0 P IAP12 R/W 0 0 P IAP11 R/W 0 0 P IAP10 R/W 0 0 P 0x08 IAP1 Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Indirect Addressing Contents 1 IAC17 R/W 0 0 P IAC16 R/W 0 0 P IAC15 R/W 0 0 P IAC14 R/W 0 0 P IAC13 R/W 0 0 P IAC12 R/W 0 0 P IAC11 R/W 0 0 P IAC10 R/W 0 0 P 0x09 IAC1 Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Indirect Address Pointer Direction Control Register IAP1_D IAP0_D IAP1_D_E IAP0_D_E R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x0A IAPDR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name R/W 0 0 P Least Significant Byte of Table Lookup TBL7 R/W 0 0 P TBL6 R/W 0 0 P TBL5 R/W 0 0 P TBL4 R/W 0 0 P TBL3 R/W 0 0 P TBL2 R/W 0 0 P TBL1 R/W 0 0 P TBL0 R/W 0 0 P 0x0B LTBL Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 13 EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Most Significant Byte of Table Lookup TBLF R/W 0 0 P TBLE R/W 0 0 P TBLD R/W 0 0 P TBLC R/W 0 0 P TBLB R/W 0 0 P TBLA R/W 0 0 P TBL9 R/W 0 0 P TBL8 R/W 0 0 P 0x0C HTBL Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Stack Pointer STKPT7 STKPT6 STKPT5 STKPT4 STKPT3 STKPT2 STKPT1 STKPT0 R 1 1 P R 1 1 P R 1 1 P R 1 1 P R 1 1 P R 1 1 P R 1 1 P R 1 1 P 0x0D STKPTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Repeat Pointer RPTC7 R/W 0 0 P RPTC6 R/W 0 0 P RPTC5 R/W 0 0 P RPTC4 R/W 0 0 P RPTC3 R/W 0 0 P RPTC2 R/W 0 0 P RPTC1 R/W 0 0 P RPTC0 R/W 0 0 P 0x0E RPTC Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Prescale Counter PRC7 R/W 0 0 0 PRC6 R/W 0 0 0 PRC5 R/W 0 0 0 PRC4 R/W 0 0 0 PRC3 R/W 0 0 0 PRC2 R/W 0 0 0 PRC1 R/W 0 0 0 PRC0 R/W 0 0 0 0x0F PRC Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Time Clock/Counter TCC7 R/W 0 0 0 TCC6 R/W 0 0 0 TCC5 R/W 0 0 0 TCC4 R/W 0 0 0 TCC3 R/W 0 0 0 TCC2 R/W 0 0 0 TCC1 R/W 0 0 0 TCC0 R/W 0 0 0 0x10 TCC Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Interrupt Flag ADIF R/W 0 0 P RBFIF R/W 0 0 P PWM1IF PWM0IF R/W 0 0 P R/W 0 0 P EINT1F R/W 0 0 P EINT0F R/W 0 0 P TCCOF R/W 0 0 P FRCOF R/W 0 0 P 0x11 INTF Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int 14 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port A Key Wake-up Interrupt Flag KWUBIF KWUAIF KWU9IF KWU8IF R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x12 KWUAIF Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Port B Key Wake-up Interrupt Flag KWU7IF KWU6IF KWU5IF KWU4IF KWU3IF KWU2IF KWU1IF KWU0IF R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x13 KWUBIF Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name General Purpose I/O port, Port A PTA7 R/W U U P PTA6 R/W U U P PTA5 R/W U U P PTA4 R/W U U P PTA3 R/W U U P PTA2 R/W U U P PTA1 R/W U U P PTA0 R/W U U P 0x14 PTA Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name General Purpose I/O port, Port B PTB7 R/W U U P PTB6 R/W U U P PTB5 R/W U U P PTB4 R/W U U P PTB3 R/W U U P PTB2 R/W U U P PTB1 R/W U U P PTB0 R/W U U P 0x15 PTB Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name General Purpose I/O port, Port C PTC5 R/W U U P PTC4 R/W U U P PTC3 R/W U U P PTC2 R/W U U P PTC1 R/W U U P PTC0 R/W U U P 0x16 PTC Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name General Purpose I/O port, Port D PTD7 R/W U U P PTD6 R/W U U P PTD5 R/W U U P PTD4 R/W U U P PTD3 R/W U U P PTD2 R/W U U P PTD1 R/W U U P PTD0 R/W U U P 0x17 PTD Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 15 EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 General Purpose I/O port, Port E PTE7 R/W U U P PTE6 R/W U U P PTE5 R/W U U P PTE4 R/W U U P PTE3 R/W U U P PTE2 R/W U U P PTE1 R/W U U P PTE0 R/W U U P 0x18 PTE Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name General Purpose I/O port, Port F PTF3 R/W U U P PTF2 R/W U U P PTF1 R/W U U P PTF0 R/W U U P 0x19 PTF Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Least significant Byte of the 16-bit Free Run Counter FRC7 R 0 0 0 FRC6 R 0 0 0 FRC5 R 0 0 0 FRC4 R 0 0 0 FRC3 R 0 0 0 FRC2 R 0 0 0 FRC1 R 0 0 0 FRC0 R 0 0 0 0x1A LFRC Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Most significant Byte of 16-bit Free Run Counter FRCF R/W 0 0 0 FRCE R/W 0 0 0 FRCD R/W 0 0 0 FRCC R/W 0 0 0 FRCB R/W 0 0 0 FRCA R/W 0 0 0 FRC9 R/W 0 0 0 FRC8 R/W 0 0 0 0x1B HFRC Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Least significant Byte Buffer of the 16-bit Free Run Counter FRCB7 R/W 0 0 0 FRCB6 R/W 0 0 0 FRCB5 R/W 0 0 0 FRCB4 R/W 0 0 0 FRCB3 R/W 0 0 0 FRCB2 R/W 0 0 0 FRCB1 R/W 0 0 0 FRCB0 R/W 0 0 0 0x1C LFRCB Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Serial Peripheral Interface Read Register SPIR7 R/W 0 0 P SPIR6 R/W 0 0 P SPIR5 R/W 0 0 P SPIR4 R/W 0 0 P SPIR3 R/W 0 0 P SPIR2 R/W 0 0 P SPIR1 R/W 0 0 P SPIR0 R/W 0 0 P 0x1D SPIRB Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int 16 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Serial Peripheral Interface Write Register SPIW7 R/W 0 0 P SPIW6 R/W 0 0 P SPIW5 R/W 0 0 P SPIW4 R/W 0 0 P SPIW3 R/W 0 0 P SPIW2 R/W 0 0 P SPIW1 R/W 0 0 P SPIW0 R/W 0 0 P 0x1E SPIWB Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name MSB Converting Value of ADC ADD9 R/W 0 0 P ADD8 R/W 0 0 P ADD7 R/W 0 0 P ADD6 R/W 0 0 P ADD5 R/W 0 0 P ADD4 R/W 0 0 P ADD3 R/W 0 0 P ADD2 R/W 0 0 P 0x1F ADDATAH Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name LSB Converting Value of ADC ADD1 R/W 0 0 P ADD0 R/W 0 0 P - 0x20 ADDATAL Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Duty of PWM0-Low Byte DT07 R 0 0 P DT06 R 0 0 P DT05 R 0 0 P DT04 R 0 0 P DT03 R 0 0 P DT02 R 0 0 P DT01 R 0 0 P DT00 R 0 0 P 0x21 DT0L Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Duty of PWM0-High Byte DT0F R 0 0 P DT0E R 0 0 P DT0D R 0 0 P DT0C R 0 0 P DT0B R 0 0 P DT0A R 0 0 P DT09 R 0 0 P DT08 R 0 0 P 0x22 DT0H Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Period of PWM0- Low Byte PRD07 R/W 0 0 P PRD06 R/W 0 0 P PRD05 R/W 0 0 P PRD04 R/W 0 0 P PRD03 R/W 0 0 P PRD02 R/W 0 0 P PRD01 R/W 0 0 P PRD00 R/W 0 0 P 0x23 PRD0L Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 17 EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Period of PWM0- High Byte PRD0F R/W 0 0 P PRD0E R/W 0 0 P PRD0D R/W 0 0 P PRD0C R/W 0 0 P PRD0B R/W 0 0 P PRD0A R/W 0 0 P PRD09 R/W 0 0 P PRD08 R/W 0 0 P 0x24 PRD0H Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Duty Latch of PWM0-Low Byte DL07 R/W 0 0 P DL06 R/W 0 0 P DL05 R/W 0 0 P DL04 R/W 0 0 P DL03 R/W 0 0 P DL02 R/W 0 0 P DL01 R/W 0 0 P DL00 R/W 0 0 P 0x25 DL0L Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Duty Latch of PWM0-High Byte DL0F R/W 0 0 P DL0E R/W 0 0 P DL0D R/W 0 0 P DL0C R/W 0 0 P DL0B R/W 0 0 P DL0A R/W 0 0 P DL019 R/W 0 0 P DL08 R/W 0 0 P 0x26 DL0H Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Duty of PWM1-Low Byte DT17 R 0 0 P DT16 R 0 0 P DT15 R 0 0 P DT14 R 0 0 P DT13 R 0 0 P DT12 R 0 0 P DT11 R 0 0 P DT10 R 0 0 P 0x27 DT1L Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Duty of PWM1-High Byte DT1F R 0 0 P DT1E R/ 0 0 P DT1D R 0 0 P DT1C R 0 0 P DT1B R 0 0 P DT1A R 0 0 P DT19 R 0 0 P DT18 R 0 0 P 0x28 DT1H Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Period of PWM1- Low Byte PRD17 R/W 0 0 P PRD16 R/W 0 0 P PRD15 R/W 0 0 P PRD14 R/W 0 0 P PRD13 R/W 0 0 P PRD12 R/W 0 0 P PRD1 R/W 0 0 P PRD10 R/W 0 0 P 0x29 PRD1L Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int 18 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Period of PWM1- High Byte PRD1F R/W 0 0 P PRD1E R/W 0 0 P PRD1D R/W 0 0 P PRD1C R/W 0 0 P PRD1B R/W 0 0 P PRD1A R/W 0 0 P PRD19 R/W 0 0 P PRD18 R/W 0 0 P 0x2A PRD1H Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Duty Latch of PWM1-Low Byte DL17 R/W 0 0 P DL16 R/W 0 0 P DL15 R/W 0 0 P DL14 R/W 0 0 P DL13 R/W 0 0 P DL12 R/W 0 0 P DL11 R/W 0 0 P DL10 R/W 0 0 P 0x2B DL1L Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Duty Latch of PWM1-High Byte DL1F R/W 0 0 P DL1E R/W 0 0 P DL1D R/W 0 0 P DL1C R/W 0 0 P DL1B R/W 0 0 P DL1A R/W 0 0 P DL19 R/W 0 0 P DL18 R/W 0 0 P 0x2C DL1H Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name WM Address Register AAR4 R/W 0 0 P AAR3 R/W 0 0 P AAAR2 R/W 0 0 P AAR1 R/W 0 0 P AAR0 R/W 0 0 P 0x2D RFAAR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name BB Data Buffer RFDB7 R/W 0 0 P RFDB6 R/W 0 0 P RFDB5 R/W 0 0 P RFDB4 R/W 0 0 P RFDB3 R/W 0 0 P RFDB2 R/W 0 0 P RFDB1 R/W 0 0 P RFDB0 R/W 0 0 P 0x2E RFDB Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name BB Data Read/Write Control Register RRST R/W 0 0 P RFRD R/W 1 1 P RFWR R/W 1 1 P 0x2F RFACR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 19 EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BB Interrupt Flag Register CSDF R/W 0 0 P TX_AEF RX_AFF TX_EMPTYF RX_OFF LINK_ DISF LOCK_OUTF LOCK_ INF R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x30 RFINTF Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Dual Port Registers (64 in total) DPR7 R/W X X P DPR6 R/W X X P DPR5 R/W X X P DPR4 R/W X X P DPR3 R/W X X P DPR2 R/W X X P DPR1 R/W X X P DPR0 R/W X X P 0x40 ~ 0x7F DPR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Peripheral Function Enable SPIE R/W 0 0 P USBE R/W 0 0 P WME R/W 0 0 P ADE R/W 0 0 P PWM1E R/W 0 0 P PWM0E R/W 0 0 P TCCE R/W 0 0 P FRCE R/W 0 0 P 0x80 PRIE Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Interrupt Enable Control Register GIE R/W 0 0 P RBFIE R/W 0 0 P PWM1IE PWM0IE R/W 0 0 P R/W 0 0 P EINT1E R/W 0 0 P EINT0E R/W 0 0 P TCCOE R/W 0 0 P FRCOE R/W 0 0 P 0x81 INTE Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Port A Key Wake-up Interrupt Enable Control Register KWUBE R/W 0 0 P KWUAE R/W 0 0 P KWU9E R/W 0 0 P KWU8E R/W 0 0 P 0x82 KWUAIE Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Port B Key Wake-up Interrupt Enable Control Register KWU7E R/W 0 0 P KWU6E R/W 0 0 P KWU5E R/W 0 0 P KWU4E R/W 0 0 P KWU3E R/W 0 0 P KWU2E R/W 0 0 P KWU1E R/W 0 0 P KWU0E R/W 0 0 P 0x83 KWUBIE Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int 20 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 External Interrupt Edge Control EINT1ED EINT0ED R/W 0 0 P R/W 0 0 P 0x84 EINTED Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name SPI_RBF R/W 0 0 P Serial Peripheral Serial (SPI) Enable Control Register CES R/W 0 0 P SBR2 R/W 0 0 P SBR1 R/W 0 0 0 SBR0 R/W 0 0 0 SDID R/W 0 0 0 SDOD R/W 0 0 0 SPIS R/W 0 0 0 0x85 SPIC Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name I/O Control of Port A IOCA7 R/W 1 1 P IOCA6 R/W 1 1 P IOCA5 R/W 1 1 P IOCA4 R/W 1 1 P IOCA3 R/W 1 1 P IOCA2 R/W 1 1 P IOCA1 R/W 1 1 P IOCA0 R/W 1 1 P 0x86 IOCA Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name I/O Control of Port B IOCB7 R/W 1 1 P IOCB5 R/W 1 1 P IOCB5 R/W 1 1 P IOCB4 R/W 1 1 P IOCB3 R/W 1 1 P IOCB2 R/W 1 1 P IOCB1 R/W 1 1 P IOCB0 R/W 1 1 P 0x87 IOCB Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name I/O Control of Port C IOCC5 R/W 1 1 P IOCC4 R/W 1 1 P IOCC3 R/W 1 1 P IOCC2 R/W 1 1 P IOCC1 R/W 1 1 P IOCC0 R/W 1 1 P 0x88 IOCC Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name I/O Control of Port D IOCD7 R/W 1 1 P IOCD6 R/W 1 1 P IOCD5 R/W 1 1 P IOCD4 R/W 1 1 P IOCD3 R/W 1 1 P IOCD2 R/W 1 1 P IOCD1 R/W 1 1 P IOCD0 R/W 1 1 P 0x89 IOCD Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 21 EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I/O Control of Port E IOCE7 R/W 1 1 P IOCE6 R/W 1 1 P IOCE5 R/W 1 1 P IOCE4 R/W 1 1 P IOCE3 R/W 1 1 P IOCE2 R/W 1 1 P IOCE1 R/W 1 1 P IOCE0 R/W 1 1 P 0x8A IOCE Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name I/O Control of Port F IOCF3 R/W 1 1 P IOCF2 R/W 1 1 P IOCF1 R/W 1 1 P IOCF0 R/W 1 1 P 0x8B IOCF Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Pull Up control of Port A PUCA7 R/W 0 0 P PUCA6 R/W 0 0 P PUCA5 R/W 0 0 P PUCA4 R/W 0 0 P PUCA3 R/W 0 0 P PUCA2 R/W 0 0 P PUCA1 R/W 0 0 P PUCA0 R/W 0 0 P 0x8C PUCA Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Pull Up control of Port B PUCB7 R/W 0 0 P PUCB6 R/W 0 0 P PUCB5 R/W 0 0 P PUCB4 R/W 0 0 P PUCB3 R/W 0 0 P PUCB2 R/W 0 0 P PUCB1 R/W 0 0 P PUCB0 R/W 0 0 P 0x8D PUCB Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Pull Up control of Port C PUCC5 R/W 0 0 P PUCC4 R/W 0 0 P PUCC3 R/W 0 0 P PUCC2 R/W 0 0 P PUCC1 R/W 0 0 P PUCC0 R/W 0 0 P 0x8E PUCC Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Pull Up control of Port D PUCD7 R/W 0 0 P PUCD6 R/W 0 0 P PUCD5 R/W 0 0 P PUCD4 R/W 0 0 P PUCD3 R/W 0 0 P PUCD2 R/W 0 0 P PUCD1 R/W 0 0 P PUCD0 R/W 0 0 P 0x8F PUCD Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int 22 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pull Up control of Port E PUCE7 R/W 0 0 P PUCE6 R/W 0 0 P PUCE5 R/W 0 0 P PUCE2 R/W 0 0 P PUCE3 R/W 0 0 P PUCE2 R/W 0 0 P PUCE1 R/W 0 0 P PUCE0 R/W 0 0 P 0x90 PUCE Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Pull Up control of Port F PUCF3 R/W 0 0 P PUCF2 R/W 0 0 P PUCF1 R/W 0 0 P PUCF0 R/W 0 0 P 0x91 PUCF Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Open Drain control of Port B OPCB7 R/W 0 0 P OPCB6 R/W 0 0 P OPCB5 R/W 0 0 P OPCB4 R/W 0 0 P OPCB3 R/W 0 0 P OPCB2 R/W 0 0 0 OPCB1 R/W 0 0 0 OPCB0 R/W 0 0 0 0x92 ODCB Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Time Clock/Counter Control TCCS0 R/W 0 0 P PS2 R/W 0 0 P PS1 R/W 0 0 P PS0 R/W 0 0 P 0x93 TCCC Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Free Run Counter Control FRCCS R/W 0 0 P 0x94 FRCC Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Watchdog Timer Control GREEN R/W 0 0 0 WDTCE R/W 0 0 P RAT2 R/W 0 0 P RAT1 R/W 0 0 P RAT0 R/W 0 0 P 0x95 WDTC Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 23 EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADC Analog Input Pin Select IMS2 R/W 0 0 P IMS1 R/W 0 0 P IMS0 R/W 0 0 P CKR2 R/W 0 0 P CKR1 R/W 0 0 P CKR0 R/W 0 0 P 0x96 ADCAIS Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name ADC Configuration Register ADRUN R/W 0 0 P ADIE R/W 0 0 P AIPS3 R/W 0 0 P AIPS2 R/W 0 0 P AIPS1 R/W 0 0 P AIPS0 R/W 0 0 P 0x97 ADCCR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name PWM Control Register S_PWM1 S_PWM0 R/W 0 0 P R/W 0 0 P - 0x98 PWMCR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name BB Interrupt Enable Control Register CSDE R/W 0 0 P TX_AEE RX_AFE TX_EMPTYE RX_OFE LINK_DISE LOCK_OUTE LOCK_INE R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x99 RFINTE Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name USB Test Register USBT7 R/W P P P USBT6 R/W P P P USBT5 R/W P P P USBT4 R/W P P P USBT3 R/W P P P USBT2 R/W P P P USBT1 R/W P P P USBT0 R/W P P P 0x1CC USBTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name USB General Control Register FUNEN FUNRST RESUME SUSPEND R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P PLUG R/W 0 0 P URST R/W 0 0 P 0x1CD GCNTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int 24 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 End Point 1 Control Register EP1EN R/W 0 0 P EP1DIR R/W 1 1 P EP1TP1 R/W 0 0 P EP1TP0 R/W 0 0 P 0x1CE EP1CNTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name End Point 2 Control Register EP2EN R/W 0 0 P EP2DIR R/W 1 1 P EP2TP1 R/W 0 0 P EP2TP0 R/W 0 0 P 0x1CF EP2CNTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name End Point 3 Control Register EP3EN R/W 0 0 P EP3DIR R/W 1 1 P EP3TP1 R/W 0 0 P EP3TP0 R/W 0 0 P 0x1D0 EP3CNTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Endpoint Interrupt Event Status Register INT3 R/W 0 0 P INT2 R/W 0 0 P INT1 R/W 0 0 P INT0IN R/W 1 1 P INT0TX R/W 0 0 P INT0RX R 0 0 P 0x1D1 EPINTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Endpoint Interrupt Event Enable Control Register INT3E R/W 0 0 P INT2E R/W 0 0 P INT1E R/W 0 0 P INT0INE INT0TXE INT0RXE R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x1D2 EPINTE Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name State Interrupt Event Flag Register FRWPINT RUEINT IDLEINT R/W 0 0 P R/W 0 0 P R/W 0 0 P RSTINT R/W 0 0 P 0x1D3 STAINTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 25 EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 State Interrupt Event Enable Control Register FRWPINTE RUEINTE IDLEINTE RSTINTE R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x1D4 STAINTE Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Function Address FADDR6 FADDR5 FADDR4 FADDR3 FADDR2 FADDR1 FADDR0 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x1D5 FAR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Endpoint 0 RX Token USETUPO W USETUP UOUT R/W 0 0 P 0x1D6 EP0RXTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name R/W 0 0 P R/W 0 0 P Endpoint 0 RX Command/Status CDTOG0RX ERRSTS0RX STALLSTS0RX ACKSTS0RX D G R 0 X DTOG0RX SESTALL0RX RXEN0RX TO E R R 0x1D7 EP0RXCSR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name W 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R/W 1 1 P R/W 1 1 P Endpoint 0 TX Command/Status CDTOG0TX ERRSTS0TX STALLSTS0TX ACKSTS0TX - DTOG0TX SESTALL0TX TXEN0TX 0x1D8 EP0TXCSR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name W 0 0 P R 0 0 P R 0 0 P R 0 0 P R 1 1 P R/W 1 1 P R/W 0 0 P Endpoint 1 Command/Status CDTOG1 ERRSTS1 STALLSTS1 ACKSTS1 DTOGERR1 DTOG1 SESTALL1 RXTXEN1 W 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R/W 1 1 P R/W 0 0 P 0x1D9 EP1CSR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int 26 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Endpoint 2 Command/Status CDTOG2 ERRSTS2 STALLSTS2 ACKSTS2 DTOGERR2 DTOG2 W 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P SESTALL2 RXTXEN2 R/W 1 1 P R/W 0 0 P 0x1DA EP2CSR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Endpoint 3 Command/Status CDTOG3 ERRSTS3 STALLSTS3 ACKSTS3 DTOGERR3 DTOG3 W 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P SESTALL3 RXTXEN3 R/W 1 1 P R/W 0 0 P 0x1DB EP3CSR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Endpoint 0 RX Count EP0RXCT6 EP0RXCT5 EP0RXCT4 EP0RXCT3 EP0RXCT2 EP0RXCT1 EP0RXCT0 R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P 0x1DC EP0RXCTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Endpoint 0 TX Count EP0TXCT6 EP0TXCT5 EP0TXCT4 EP0TXCT3 EP0TXCT2 EP0TXCT1 EP0TXCT0 R 0 0 P R 0 0 P R 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x1DD EP0TXCTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Endpoint 1 Count EP1CT6 EP1CT5 EP1CT4 EP1CT3 EP1CT2 EP1CT1 EP1CT0 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x1DE EP1CTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Endpoint 2 Count EP2CT6 EP2CT5 EP2CT4 EP2CT3 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P EPCT2 R/W 0 0 P EP2CT1 EP2CT0 R/W 0 0 P R/W 0 0 P 0x1DF EP2CTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 27 EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Endpoint 3 count EP3CT6 EP3CT5 EP3CT4 EP3CT3 EP3CT2 EP3CT1 EP3CT0 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x1E0 EP3CTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Endpoint 0 RX data EP0RX7 EP0RX6 EP0RX5 EP0RX4 EP0RX3 EP0RX2 EP0RX1 EP0RX0 R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P 0x1E1 EP0RXD AR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Endpoint 0 TX data EP0TX7 W 0 0 P EP0TX6 W 0 0 P EP0TX5 W 0 0 P EP0TX4 W 0 0 P EP0TX3 W 0 0 P EP0TX2 W 0 0 P EP0TX1 W 0 0 P EP0TX0 W 0 0 P 0x1E2 EP0TXD AR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Endpoint 1 data EP1D7 R/W 0 0 P EP1D6 R/W 0 0 P EP1D5 R/W 0 0 P EP1D4 R/W 0 0 P EP1D3 R/W 0 0 P EP1D2 R/W 0 0 P EP1D1 R/W 0 0 P EP1D0 R/W 0 0 P 0x1E3 EP1DAR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Endpoint 2 data EP2D7 R/W 0 0 P EP2D6 R/W 0 0 P EP2D5 R/W 0 0 P EP2D4 R/W 0 0 P EP2D3 R/W 0 0 P EP2D2 R/W 0 0 P EP2D1 R/W 0 0 P EP2D0 R/W 0 0 P 0x1E4 EP2DAR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Endpoint 3 data EP3D7 R/W 0 0 P EP3D6 R/W 0 0 P EP3D5 R/W 0 0 P EP3D4 R/W 0 0 P EP3D3 R/W 0 0 P EP3D2 R/W 0 0 P EP3D1 R/W 0 0 P EP3D0 R/W 0 0 P 0x1E5 EP3DAR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int 28 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hub Global State Register CONFG RM WUPEN PWRM PWRS/ M W PWRS/W OVCM 0x1E6 HGSR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name R/W 0 0 P R/W 1 1 P R/W 1 1 P R/W 1 1 P R/W 1 1 P R/W 1 1 P Hub Interrupt Event Flag Register HPSTSCINT SOFINT EOF2INT EOF1INT HINT1 HINT0IN HINT0TX HINT0RX 0x1E7 HINTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R 0 0 P Hub Interrupt Event Enable Control Register HPSTSCINTE SOFINTE EOF2INTE EOF1INTE HINT1E HINT0INE HINT0TX E HINT0RX E 0x1E8 HINTE Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P Hub Address Register HADDR6 HADDR5 HADDR4 HADDR3 HADDR2 HADDR1 HADDR0 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x1E9 HAR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Hub Endpoint0 RX Token Register H EU O STP W HSETUP HOUT 0x1EA HEP0RXTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name R/W 0 0 P R/W 0 0 P R/W 0 0 P Hub Endpoint0 RX Command/Status Register HCDTOG0RX HERRSTS0RX H T L S S R HACKSTS0RX H T G R 0 X HDTOG0RX H E T L 0 X HRX S AL T 0 X D O E RR S S ALR EN0RX 0x1EB HEP0RXC SR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int W 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R/W 1 1 P R/W 1 1 P Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 29 EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hub Endpoint0 TX Command/Status Register HCDTOG0TX HERRSTS0TX H TA L T 0 HACKSTS0TX S L S S TX - H TO 0 D G TX H E T L0 S S A L TX H E0 TX N TX 0x1EC HEP0TX CSR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name W 0 0 P R 0 0 P R 0 0 P R 0 0 P R 1 1 P R/W 1 1 P R/W 0 0 P Hub Endpoint1 TX Command/Status Register H D G TX H R S S TX H TA L T 1 H C S S TX C TO 1 ERT1 S L S S TX A K T 1 - H TO 1 D G TX H E T L1 S S A L TX H E1 TX N TX 0x1ED HEP1TX CSR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name W 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R/W 1 1 P R/W 0 0 P Hub Endpoint0 RX Count register HEP0RX C3 HEP0RX C2 HEP0RX C1 HEP0RX C0 0x1EE HEP0RXCTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P Hub Endpoint0 TX Count register H P TX 3 E0 C H P TX 2 E0 C H P TX 1 E0 C H P TX 0 E0 C 0x1EF HEP0TXCTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P Hub Endpoint0 RX Data Register H PR D E0X7 H PR D E0X6 H PR D E0X5 H PR D E0X4 H PR D E0X3 H PR D E0X2 H PR D E0X1 H PR D E0X 0 0x1F0 HEP0RXDAR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P Hub Endpoint0 TX Data Register H P TX 7 E0 D H P TX 6 E0 D H P TX 5 E0 D H P TX 4 E0 D H P TX 3 E0 D H P TX 2 E0 D H P TX 1 E0 D H P TXD E0 0 0x1F1 HEP0TXDAR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int W 0 0 P W 0 0 P W 0 0 P W 0 0 P W 0 0 P W 0 0 P W 0 0 P W 0 0 P 30 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hub Endpoint1 TX Data Register HSTSCP4 HSTSCP3 HSTSCP2 HSTSCP1 W 0 0 P W 0 0 P W 0 0 P W 0 0 P HSTSC W 0 0 P 0x1F2 H P T D R E1X A Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Hub Port Control Register CMDVLD W 0 0 P HPCON5 HPCON4 HPCON3 HPADDR2 HPADDR1 HPADDR0 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x1F3 HPCONR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Hub Port State Register DPSTATE4 DMSTATE4 DPSTATE3 DMSTATE3 DPSTATE2 DMSTATE2 DPSTATE1 DMSTATE1 R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P 0x1F4 HPSTAR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Hub status Register OVIC R/W 0 0 P LPSC R/W 0 0 P OVI R 0 0 P LPS R 0 0 P 0x1F5 HSR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Hub Port 1 Status Register LSDA1 PPWRSTA1 PRTSTS1 R 0 0 P R 0 0 P R 0 0 P POCI1 R 0 0 P PSUSSTS1 PENSTS1 PCSTS1 R 0 0 P R 0 0 P R 0 0 P 0x1F6 HPSR1 Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Hub Port 2 Status Register LSDA2 PPWRSTA2 PRTSTS2 R 0 0 P R 0 0 P R 0 0 P POCI2 R 0 0 P PSUSSTS2 PENSTS2 PCSTS2 R 0 0 P R 0 0 P R 0 0 P 0x1F7 HPSR2 Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 31 EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hub Port 3 Status Register LSDA3 PPWRSTA3 PRTSTS3 R 0 0 P R 0 0 P R 0 0 P POCI3 R 0 0 P PSUSSTS3 PENSTS3 PCSTS3 R 0 0 P R 0 0 P R 0 0 P 0x1F8 HPSR3 Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Hub Port 4 Status Register LSDA4 PPWRSTA4 PRTSTS4 R 0 0 P R 0 0 P R 0 0 P POCI4 R 0 0 P PSUSSTS4 PENSTS4 PCSTS4 R 0 0 P R 0 0 P R 0 0 P 0x1F9 HPSR4 Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Hub Port 1 Status Change Register PRTSTSC1 POCIC1 PSU SSTSC1 PENSTSC1 PCSTSC1 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x1FA HPSCR1 Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Hub Port 2 Status Change Register PRTSTSC2 POCIC2 PSU SSTSC2 PENSTSC2 PCSTSC2 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x1FB HPSCR2 Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Hub Port 3 Status change Register PRTSTSC3 POCIC3 PSU SSTSC3 PENSTSC3 PCSTSC3 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x1FC HPSCR3 Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Hub Port 4 Status change Register PRTSTSC4 R/W 0 0 P POCIC4 R/W 0 0 P PSU SSTSC4 PENSTSC4 PCSTSC4 R/W 0 0 P R/W 0 0 P R/W 0 0 P 0x1FD HPSCR4 Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int 32 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Addr Name Reset Type Full Name Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Least Significant Byte of Frame Number FN7 R 0 0 P FN6 R 0 0 P FN5 R 0 0 P FN4 R 0 0 P FN3 R 0 0 P FN2 R 0 0 P FN1 R 0 0 P FN0 R 0 0 P 0x1FE FNLR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Most Significant Byte of Frame Number FNA R 0 0 P FN9 R 0 0 P FN8 R 0 0 P 0x1FF FNHR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int 7 Function Description 7.1 Special Purpose Registers The special purpose registers are function-oriented registers used by the CPU to access memory, record execution results, and carry out the desired operation. The functions of the registers related to the core are described in the following subsections. 7.1.1 Accumulator - ACC Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register. 7.1.2 Indirect Addressing Contents - IAC0 (0x00), and IAC1 (0x09) The contents of R0 and R9 are implemented as indirect addressing pointers if any instruction uses R6 and R8 as registers. 7.1.3 High byte Program Counter HPC (0x01) and Low byte Program Counter LPC (0x02) The Program Counter (PC) is composed of registers HPC and LPC. The PC and the hardware stacks are 14 bits wide. The structure is depicted in Fig. 5-1 Generates 16Kx16 on-chip ROM addresses to the corresponding program memory (ROM). All the bits of the PC are set to "0"s as a reset condition occurs. "RET" ("RETL k", "RETI") instruction loads the program counter with the contents at the top of the stack. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 33 EM77F900 USB HUB+BB Controller "MOV R2, A" allows the loading of an address from the "A" register to the lower 8 bits of the PC, and the high byte (A8~A14) of the PC remain unchanged. "ADD R2, A" & "TBL" allows a corresponding address/offset be added to the current PC. 7.1.4 Status Register - SR (0x03) Bit 7 Bit 6 Bit 5 RST Bit 4 T Bit 3 P Bit 2 Z Bit 1 DC Bit 0 C Bit 0 (C): Carry flag. This bit indicates that a carry out of ALU occurred during the last arithmetic operation. This bit is also affected during bit test, branch instruction and during bit shifts. Bit 1 (DC): Auxiliary carry flag. This bit is set during ADD and ADC operations to indicate that a carry occurred between Bit 3 and Bit 4. Bit 2 (Z): Zero flag. Set to "1" if the result of the last arithmetic, data or logic operation is zero. Bit 3 (P): Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 4 (T): Time-out bit. Set to 1 by the "SLEP" command and the "WDTC" command, or during power up and reset to 0 by WDT timeout. Bit 5 (RST): Set if the CPU wakes up by keying on the wake-up pins. Reset if the chip wakes up through other ways. Bits 6 and 7 are reserved. 7.1.5 RAM Bank Selector - RAMBS0 (0x04), and RAMBS1 (0x07) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RAMBSX2 RAMBSX1 RAMBSX0 As depicted in Fig. 5-2, there are seven available banks in the MCU. Each of them has 128 registers and can be accessed by defining the bits, RAMBSX0 ~ RAMBSX2, as shown below. RAMBSX (0x04/0x07) 000 001 010 011 100 101 110 34 * Bank 0 1 2 3 4 5 6 Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 7.1.6 ROM Page Selector - ROMPS (0x05) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RPS0 As depicted in Fig. 6-1, there are two available pages in the MCU. Each of them has 8Kx16 ROM size and can be accessed by defining the bits, RPS0, as shown below. RPS0 0 1 Page (Address) 0 (0x0000~0x1FFF) 1 (0x2000~0x3FFF) 7.1.7 Indirect Addressing Pointers - IAP0 (0x06), and IAP1 (0x08) Both R6 and R8 are not physically implemented registers. They are useful as indirect addressing pointers. Any instruction using R6/R4 and R8/R7 as registers actually access data pointed by R0 and R9 individually. 7.1.8 Indirect Address Pointer Direction Control Register - IAPDR (0x0A) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 IAP1_D Bit 2 IAP0_D Bit 1 Bit 0 IAP1_D_E IAP0_D_E Bit 0/1 (IAP0_D_E/IAP1_D_E) Indirect addressing Pointer 0/1 direction function enable bit. 0: Disable 1: Enable Bit 2/3 (IAP0_D/IAP1_D) Indirect addressing Pointer 0/1 direction control bit. 0: Minus direction 1: Plus direction 7.1.9 Pointer of Table Look-up - LTBL (0x0B), and HTBL (0x0C) The maximum length of a table is 64K, and can be accessed through registers LTBL and HTBL. HTBL is the high byte of the pointer, whereas LTBL is the low byte. 7.1.10 Stack Pointer - STKPTR (0x0D) Register RD indicates how many stacks the current free run program uses. It is a read only register. 7.1.11 Repeat Counter - RPTC (0x0E) RE register is used to set how many times that the "RPT" instruction is going to read the table. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 35 EM77F900 USB HUB+BB Controller 7.1.12 Prescaler Counter - PRC (0x0F) Prescaler counter for TCC. 7.1.13 Real Time Clock Counter - RTCC (0x10) TCC counter. 7.1.14 Interrupt Flag Register - INTF (0x11) Bit 7 ADIF Bit 6 RBFIF Bit 5 PWM1IF Bit 4 PWM0IF Bit 3 EINT1F Bit 2 EINT0F Bit 1 TCCOF Bit 0 FRCOF Bit 0 (FRCOF): FRC Overflow interrupt. Set as the contents of the FRC counter change from 0xFFFF to 0x0000, reset by software. Bit 1 (TCCOF): TCC Overflow interrupt. Set as the contents of the TCC counter change from 0xFF to 0x00, reset by software. Bits 2 ~ 3 (EINT0F & EINTIF): External input pin interrupt flag. Interrupt occurs at the defined edge of the external input pin, reset by software. Bits 4 ~ 5 (PWM0IF & PWM1IF): PWM interrupt flag. Interrupt occurs when TMRX is equal to PRDX, reset by software. Bit 6 (RBFIF): SPI receiving buffer full Interrupt flag. Interrupt occurs when an 8-bit data received, reset by software. Bit 7 (ADIF): ADC conversion complete interrupt flag. Each bit can function independently regardless whether its related interrupt mask bit is enabled or not. 7.1.15 Key Wake-up Flag Register - KWUAIF (0x12) & KWUBIF (0x13) KWUAIF: Port A Key Wake-up Interrupt Flag Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 KWUBIF Bit 2 KWUAIF Bit 1 KWU9IF Bit 0 KWU8IF KWUBIF: Port B Key Wake-up Interrupt Flag Bit 7 KWU7IF Bit 6 KWU6IF Bit 5 KWU5IF Bit 4 KWU4IF Bit 3 KWU3IF Bit 2 KWU2IF Bit 1 KWU1IF Bit 0 KWU0IF 7.1.16 I/O Port Registers - PTA ~ PTF (0x14 ~ 0x19) PTX can be operated as any other general purpose registers by related instructions. That is, PTX is an 8-bit, bidirectional, general purpose port. Its corresponding I/O control bit determines the data direction of a PTX pin. 36 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 7.1.17 16-bit Free Run Counter (FRC) - LFRC (0x1A), HFRC (0x1B) & LFRCB (0x1C) R1A is a 16-bit FRC low byte; R1B is high byte; R1C is a low byte buffer. 7.1.18 Serial Peripheral Interface Read Register - SPIRB (0x1D) Register R1D indicates an SPI receive data. 7.1.19 Serial Peripheral Interface Write Register - SPIWB (0x1E) Register R1E indicates an SPI transmit data. 7.1.20 Converting Value of ADC - ADDATAH (0x1F) & ADDATAL (0x20) ADDATAH: MSB Converting Value of ADC. Bit 7 ADD9 Bit 6 ADD8 Bit 5 ADD7 Bit 4 ADD6 Bit 3 ADD5 Bit 2 ADD4 Bit 1 ADD3 Bit 0 ADD2 ADDATAL: LSB Converting Value of ADC. Bit 7 ADD1 Bit 6 ADD0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - 7.1.21 PWM Duty - DT0L (0x21)/DT0H (0x22) & DT1L (0x27)/DT1H (0x28) R22:R21 16-bit PWM0 output duty cycle. R28:R27 16-bit PWM1 output duty cycle. 7.1.22 PWM Period - PRD0L (0x23)/PRD0H (0x24) & PRD1L (0x29)/PRD1H (0x2A) R24:R23 16-bit PWM0 output period cycle. R2A:R29 16-bit PWM1 output period cycle. 7.1.23 PWM Duty Latch - DL0L (0x25)/DL0H (0x26) & DL1L (0x2B)/DL1H (0x2C) R26:R25 16-bit PWM0 output duty cycle buffer. R2C:R2B 16-bit PWM1 output duty cycle buffer. 7.1.24 BB Address Register - RFAAR (0x2D) Register R2D indicates WM indirect RAM address. 7.1.25 BB Data Buffer Register - RFDB (0x2E) Register R2E indicates WM indirect RAM data. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 37 EM77F900 USB HUB+BB Controller 7.1.26 BB Data Read/Write Control Register - RFACR (0x2F) Register R2F indicates WM RAM access control. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 RRST Bit 1 RFRD Bit 0 RFWR Bit 0 (RFWR): Write BB register Bit 1 (RFRD): Read BB register Bit 2 (RRST): BB S/W reset Bit 3 ~ Bit 7 reserved 7.1.27 BB Interrupt Flag Register - RFINTF (0x30) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CSDF TX_AEF RX_AFF TX_ EMPTYF RX_OFF LINK_ DISF LOCK_OUTF LOCK_ INF Bit 0 (LOCK_INF): This bit reflects the LOCK IN flag interrupt. Bit 1 (LOCK_OUTF): This bit reflects the LOCK OUT flag interrupt. Bit 2 (LINK_DISF): This interrupt is invoked by the zero counter capacitor discharge mechanism. Bit 3 (RX_OFF): This bit reflects the RX FIFO full flag interrupt. Bit 4 (TX_EMPTYF): This bit reflects the TX EMPTY flag interrupt. Bit 5 (RX_AFF): This bit reflects the RX FIFO almost full flag interrupt. Bit 6 (TX_AEF): This bit reflects the TX FIFO almost empty flag interrupt. Bit 7 (CSDF): This flag indicates that a carrier-sense interrupt has occurred. 7.2 Dual Port Register (0x40 ~ 0x7F) R 40 ~ R7F are dual port registers. 7.3 System Status, Control and Configuration Registers These registers are function-oriented registers used by the CPU to record, enable or disable the peripheral modules, interrupts, and the operation clock modes. 7.3.1 Peripherals Enable Control - PRIE (0x80) Bit 7 SPIE Bit 6 USBE Bit 5 BBE Bit 4 ADE Bit 3 PWM1E Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE Bit 0 (FRCE): Free Run Counter 0 (FRC0) Enable bit. 38 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Bit 1 (TCCE): Timer Clock/Counter (TCC) Enable bit. Bit 2 (PWM0E): PWM0 function enable bit. Bit 3 (PWM1E): PWM1 function Enable bit. Bit 4 (ADE): ADC Enable bit. Bit 5 (BBE): Base band (BB) Enable bit. Bit 6 (USBE): Universal Serial Bus (USB) Enable bit. Bit 7 (SPIE): Serial Peripheral Interface Enable bit. 0: disable function 1: enable function 7.3.2 Interrupts Enable Control - INTE (0x81) Bit 7 GIE Bit 6 RBFIE Bit 5 PWM1IE Bit 4 PWM0IE Bit 3 EINT1E Bit 2 EINT0E Bit 1 TCCOE Bit 0 FRCOE Bit 0 (FRC0OE): Free Run Counter (FRC) Overflow interrupt enable bit. Bit 1 (TCCOE): TCC (TCC) Overflow interrupt enable bit. Bit 2 (EINT0E): External pin (EINT0) interrupt enable bit. Bit 3 (EINT1E): External pin (EINT1) interrupt enable bit. Bits 4 (PWM0IE): PWM0 period complete enable bit. Bits 5 (PWM1IE): PWM1 period complete enable bit. Bit 6 (RBFIE): SPI Read Buffer Full (EINT) interrupt enable bit. 0: disable function interrupt 1: enable function interrupt Bit 7 (GIE): Global interrupt control bit. Global interrupt is enabled by the ENI and RETI instructions and is disabled by the DISI instruction. 0: Global interrupt disable 1: Global interrupt enable 7.3.3 Key Wake-up Enable Control - KWUAIE (0x82) & KWUBIE (0x83) KWUAIE: Port A Key wake-up Interrupt Enable Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 KWUBE Bit 2 KWUAE Bit 1 KWU9E Bit 0 KWU8E Bit 0 ~Bit 3 (KWU8E ~ KWUBE): Enable or disable the PTA0 ~ PTA3 Key Wake-up function. 0: disable key wake-up function 1: enable key wake-up function Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 39 EM77F900 USB HUB+BB Controller KWUBIE: Port B Key Wake-up Interrupt Enable Control Register Bit 7 KWU7E Bit 6 KWU6E Bit 5 KWU5E Bit 4 KWU4E Bit 3 KWU3E Bit 2 KWU2E Bit 1 KWU1E Bit 0 KWU0E Bit 0 ~Bit 7 (KWU0 ~ KWU7): Enable or disable the PTB0 ~ PTB7 Key Wake-up function. 0: disable key wake-up function 1: enable key wake-up function 7.3.4 External Interrupts Edge Control - EINTED (0x84) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 EINT1ED Bit 0 EINT0ED Bit 0 (EINT0ED): Define which edge as an interrupt source for EINT0. Bit 1 (EINT1ED): Define which edge as an interrupt source for EINT1. 0: Falling Edge 1: Rising Edge Bit 2 ~ Bit 7 reserved 7.3.5 Serial Peripheral Serial (SPI) Enable Control Register - SPIC (0x85) Bit 7 SPI_RBF Bit 6 CES Bit 5 SBR2 Bit 4 SBR1 Bit 3 SBR0 Bit 2 SDID Bit 1 SDOD Bit 0 SPIS Bit 0 (SPIS): SPI start Bit 1 (SDOD): SPI data shift out direction 0: Most significant bit (MSB) transmitted first 1: Least significant bit (LSB) transmitted first Bit 2 (SDID): SPI data shift in direction. 0: Most significant bit (MSB) received first 1: Least significant bit (LSB) received first Bits 3 ~ 5 (SBR0 ~ SBR2): Configure the transmission mode and the clock rate. SBR2 (Bit5) 0 0 0 0 1 1 1 1 40 * SBR1 (Bit4) 0 0 1 1 0 0 1 1 SBR0 (Bit3) 0 1 0 1 0 1 0 1 Mode Master Master Master Master Master Slave N/A N/A Baud Rate Fosc/2 Fosc/4 Fosc/8 Fosc/16 Fosc/32 N/A N/A N/A Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Bit 6 (CES): Clock edge select bit. 0: Data shifts out on a rising edge, and shifts in on a falling edge. Data is on hold during the low level edge. 1: Data shifts out on falling edge, and shifts in on rising edge. Data is on hold during the high level edge. Bit 7 (SPI_RBF): SPI read buffer full flag. 7.3.6 I/O Control Registers - IOCA~IOCF (0x86~0x8B) OCX is used to determine the data direction of its corresponding I/O port bit. 0: configure a selected I/O pin as output 1: configure a selected I/O pin as input The only four least significant bits of Port F, and the only five least significant bits of port C are available. 7.3.7 Pull Up Resistance Control Registers for Ports A~F - PUCA~PUCF (0x8C ~ 0x91) Each bit of PUCX is used to control the pull-up resistors attached to its corresponding pin respectively. The theoretical value of the resistor is 64 K. However, due to processes, 35% variation in resistance must be taken into consideration. PUCX: Bit 7 PUCX7 Bit 6 PUCX6 Bit 5 PUCX5 Bit 4 PUCX4 Bit 3 PUCX3 Bit 2 PUCX2 Bit 1 PUCX1 Bit 0 PUCX0 0: Pull-up Resistors disconnected 1: Pull-up Resistors attached 7.3.8 Open Drain Control Registers of Port B - ODCB (0x92) ODCB: Open drain control of Port B. Bit 7 OPCB7 Bit 6 OPCB6 Bit 5 OPCB5 Bit 4 OPCB4 Bit 3 OPCB3 Bit 2 OPCB2 Bit 1 OPCB1 Bit 0 OPCB0 0: Open drain disabled 1: Open drain enabled 7.3.9 Timer Clock Counter Controller - TCCC (0x93) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TCCS0 Bit 2 PSR2 Bit 1 PSR1 Bit 0 PSR0 Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 41 EM77F900 USB HUB+BB Controller Bit 0 ~ 2 (PSR0 ~ PSR2): Prescaler for TCC. PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 Clock Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 Bit 3 (TCCS0): Clock Source Select. TCCS0 0 1 Clock Source Selected PLL Clock Source Selected ERC Clock Source Bits 4 ~ 7 are reserved. 7.3.10 Free Run Counter Controller - FRCC (0x94) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FRCCS Bit 0 (FRCCS): Clock Source Select FRCCS 0 1 Clock Source Selected PLL Clock Source Selected ERC Clock Source Bits 1 ~ 7 are reserved. 7.3.11 Watchdog Timer Controller - WDTC (0x95) Bit 7 GREEN Bit 6 Bit 5 Bit 4 WDTCE Bit 3 Bit 2 RAT2 Bit 1 RAT1 Bit 0 RAT0 Bit 0 ~ 2 (RAT0 ~ RAT2): WDT Prescaler RAT2 0 0 0 0 1 1 1 1 RAT1 0 0 1 1 0 0 1 1 RAT0 0 1 0 1 0 1 0 1 Clock Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 Bit 4 (WDTCE): Enable the WDT Counter 0: WDT disabled 1: WDT enabled 42 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Bits 7 (Green): for power saving purposes, the system clock can be changed to external RC mode. 0: Normal Mode 1: Green Mode Bits 3, 5 and 6 are reserved. 7.3.12 ADC analog Input Pin Select - ADCAIS (0x96) Bit 7 Bit 6 Bit 5 Bit 4 IMS2 Bit 3 IMS1 Bit 2 IMS0 Bit 1 CKR1 Bit 0 CKR0 CKR0 ~ CKR2 (Bit 0 ~ Bit 2): AD conversion Rate control bits. IMS2~IMS0 (Bit 2 ~ Bit 4): ADC configuration defined bit. Bits 5 ~ 7 are reserved. 7.3.13 ADC Configuration Register - ADCCR (0x97) Bit 7 ADRUN Bit 6 ADIE Bit 5 Bit 4 Bit 3 AIPS3 Bit 2 AIPS2 Bit 1 AIPS1 Bit 0 AIPS0 Bit 0 ~ Bit3 (AIPS0~AIPS3): Analog Input Select. Bit 6 ~ Bit 7 (ADIE): ADC interrupt enable. 0 = ADC interrupt disable 1 = ADC interrupt enable Bit 7 (ADRUN): ADC starts to RUN 0 = reset on completion of the conversion; this bit cannot be reset by software. 1 = an A/D conversion is started; this bit can be set by software. Bits 4 and 5 are reserved. 7.3.14 PWM Control Register - PWMCR (0x98) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 S_PWM1 Bit 2 S_PWM0 Bit 1 Bit 0 - Bit 2 (S_PWM0): Selected PWM0 output enable. Bit 3 (S_PWM1): Selected PWM1 output enable. 0 = disable PWM output 1 = enable PWM output Bits 0, 1 and 4 ~ 7 are reserved. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 43 EM77F900 USB HUB+BB Controller 7.3.15 BB Interrupt Control Register - RFINTE (0x99) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CSDE TX_AEE RX_AFE TX_ EMPTYE RX_OFE LINK_ DISE LOCK_OUTE LOCK_ INE Bit 0 (LOCK_INE): LOCK IN interrupt enable bit. Bit 1 (LOCK_OUTE): LOCK OUT interrupt enable bit. Bit 2 (LINK_DISE): LINK_DIS interrupt enable bit. Bit 3 (RX_OFE): The RX FIFO full interrupt enable bit. Bit 4 (TX_EMPTYE): The TX EMPTY interrupt enable bit. Bit 5 (RX_AFE): The RX FIFO almost full interrupt enable bit. Bit 6 (TX_AEE): The TX FIFO almost empty interrupt enable bit. Bit 7 (CSDE): The carrier-sense interrupt enable bit. 0 = disable function interrupt 1 = enable function interrupt 7.4 USB Status, Control and Configuration Registers These registers are function-oriented registers used by the USB to record, enable or disable the peripheral modules, interrupts, and the operation clock modes. Refer to Section 8.5. 7.5 Code Option (ROM-0x3FFF) Register SCLK is located on the very last bit of EM77F900's 16K program ROM. These values will be fetched first to be the system initial values during power-on. SCLKC: System Clock Control Register SCLKC 0x3FFF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 SCLK1 Bit 0 SCLK0 USBCLK RFCLK1 RFCLK0 SCLKC 0x3FFF Bit 15 - Bit 14 PROTECT Bit 13 - Bit 12 - Bit 11 - Bit 10 - Bit 9 - Bit 8 - Bit 1 ~ Bit 2 (SCLKS1 ~ SCLKS0): System Clock Frequency Select Control Bits SCLK1 0 0 1 1 44 * SCLK0 0 1 0 1 System Clock (MHz) 6 12 24 48 Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Bit 3 ~ Bit 4 (RFCK1 ~ RFCK0): Wireless Modem Clock Frequency Select Control Bits RFCLK1 0 0 1 1 RFCLK0 0 1 0 1 System Clock (MHz) 6 12 24 48 Bit 5 (USBCLK): USB / HUB 48MHz PLL Clock Source Control Bit 0: Disable 48 MHz oscillation from PLL. 1: Enable 48 MHz oscillation from PLL for USB/Hub as power-on. Bit 14 (PROTECT): Protect bit 0: Protect 1: No protect Bits 5 ~ 13, 15: Reserved SCLK [1:0] 00 00/01/10/11 01/10/11 00/01/10/11 00/01/10/11 RFCLK [1:0] USB_CLK 00 01/10/11 00/01/10/11 00/01/10/11 00/01/10/11 0 0 0 1 0/1 WDT_CON. GREEN 0 0 0 0 1 SYS CLK RF CLK USB CLK 6M (Bypass) 6M (Bypass) EXT 48MHz 6/12/24/48 12/24/48 6/12/24/48 ERC 12/24/48 6/12/24/48 - 6/12/24/48 PLL 48MHz - 8 Base Band (BB) 8.1 BB: Standard Interface to the RFW102 Series 8.1.1 Features Parallel interface to RFW102 modem Serial to Parallel conversion of RFW102 interface Input FIFO (RX_FIFO) Output FIFO (TX_FIFO) Preamble Correlation Packet Address Filter (Network and unique) CRC calculation Working Frequencies: 6-24MHz Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 45 EM77F900 USB HUB+BB Controller Power Saving modes: Idle, Power-down Inter-RFWAVES networks Carrier-sense. Discharge of the RFW-102 reference capacitor. Compensate for clock drifts between the transmitting EM77F900 and the receiving EM77F900 up to 1000ppm. Hence, the EM77F900 requires low performance crystal. Interrupt Driver - connected to the EM77F900's internal interrupt and informs the EM77F900 about BB events. 8.1.2 Description RFWAVES has developed a very low cost wireless modem (RFW102) for short range, cost-sensitive applications. The modem is a physical layer element (PHY) - allowing the transmission and reception of bits from one end to the other. In an RFWAVES application, the MCU is in charge of the MAC layer protocol. In order to reduce the real-time demands of the MCU handling the MAC protocol, the BB was developed. The BB enables the MCU an easy interface to RFW102 through a parallel interface, similar to memory access. It converts the fast serial input to 8-bits words, which are much easier for an 8-bit MCU to work with and requires a lower rate oscillator. It buffers the input through a TBD bytes FIFO, enabling the MCU to access the BB more efficiently. Instead of reading one byte per interrupt, the MCU can read up to 16 bytes in each interrupt. This reduces the MCU overhead in reading incoming words, insofar as stack stuffing and pipeline emptying are concerned, in cases where each incoming byte causes an interrupt. When using the FIFO, the MCU pays the same overhead for all the FIFO bytes as it paid for only one byte without a FIFO. Having a low-cost BB with a built-in state machine that can support basic wireless communication elements would present the following advantages: Shorter development time, hence shorter and more efficient time-to-market solution. Save CPU power and other resources for other applications. Offer an easy, standard integrated solution. 46 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 8.1.3 I/O and Package Description MCU RAM_ADDR [0~6] DATA [0~7] RD_n WR_n CS_n RST TX_AE RX_AF TX_EMPTY CS LOCK_IN LOCK_OUT SHDWN RF CLK 7 8 BB RAM_ADDR [0~6] Serial IO DATA [0~7] RD_n WR_n CS_n RST TX_AE RX_AF TX_EMPTY CS LOCK_IN LOCK_OUT SHDWN RF CLK TX_RX RF_Active RFW-102 Data IO TX_RX RF_Active Name Type Description This bus comprises of eight TRI-STATE input/output lines. The bus provides bidirectional communication between the system and the MCU. Data, control words, and status information are transferred via the DATA [0-7] data bus. When RD_n is low while the system is enabled, BB outputs one of its internal register values to DATA[0-7] according to RAM_ADDR[0-6]. When WR_n is low while the system is enabled, BB enables writing to its internal registers. The register is determined by RAM_ADDR [0-6] and the value DATA[0-7]. These four input signals determine the register to which the MCU writes to or reads from. Chip select input pin. When CS_n is low, the chip is selected; when high, the chip is disabled. This pin overrides all pins excluding RST. This enables communication between BB and the MCU. This pin functions as wake-up pin for power-down and idle modes. TX_AE TX_EMPTY RX_AF CS LOCK_IN LOCK_OUT O Interrupt driver pins. This pin goes high whenever any of the interrupt sources has an active high condition and is enabled via the IER. The purpose of this pin is to notify the MCU through its external interrupt pin that an event (such as empty TX_FIFO) has occurred. Goes low when IER register is read. DATA [0-7] I/O RD_n I WR_n I RAM_ADDR[0-6] I CS_n I Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 47 EM77F900 USB HUB+BB Controller Name Type Chip's reset pin. Description When this pin is set high, all registers and FIFOs are cleared to their initial values. All transceiver traffic is disabled and aborted. Reset is asynchronous to system clock. After power-up, a pulse in RST input should be applied (by POR). RST I SHDWN RF_ACTIVE I O Shut Down BB This output pin controls the RFW102 working/shutdown mode. It's values is determined by SCR4(1). Serial input or output according to TX_RX mode. It functions as serial interface for the RFW-102 (RFWAVES modem). When SERIAL_IO is input, it is a Schmitt-trigger input. This pin controls the RFW-102 operation mode. It should be connected to RFW-102 RX_TX input pin. SERIAL_IO I/O RX_TX O When RX_TX is low, RFW-102 is in receiving mode. When RX_TX is high, RFW-102 is in transmitting mode. In most cases RX_TX output pin is determined by SCR2(0) register. SCR3(7) and the capacitor discharge mechanism effect this pin. RF_CLK I Clock for RF operation 8.1.4 BB Architecture INT Interrupt Handler Address Filter RX FIFO Parallel Interface Receiver Preamble Correlation Serial Input/ Output Address Bus Data Bus Control & Status Registers CRC TX FIFO Transmitter Fig. 7-1 BB Block Diagram 48 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 8.2 BB Description 8.2.1 Reset A reset is achieved by holding the RST pin high for at least TBD oscillator cycles. To ensure a good power-up, a reset should be given to BB after power-up. 8.2.2 Power Saving Modes The BB was designed to work in similar working modes as a typical MCU. These modes enable the system to save power when the BB is not in use. 8.2.2.1 Power-Down Mode The MCU is able to halt all activity in BB by stopping its clock. This enables the MCU to reduce the power consumption of the BB to a minimum. All registers and FIFOs retain their values when BB is in power-down mode. BB enters power-down mode by setting bit TBD in register TBD to "1". This bit is set by MCU and cleared by BB. BB goes back to working mode by setting CS_n input pin to "0" for TBD msec. The wake-up time of the BB from power-down mode to fully operating mode is TBD msec. Since BB retains all the register values in power-down mode, special care should be given to the register values before it enters power-down. For example, the MCU should check that the BB is not in the middle of transmitting or receiving a packet. The RFACTIVE should be set low to shutdown the RFW-102, before entering power-down mode. 8.2.2.2 Idle Mode In idle mode, the BB internally blocks the clock input. The external clock is not stopped, but it is not routed to the internal logic. By doing this, the MCU achieves substantial power savings and yet the wake-up time is still relatively short. The power consumption is not minimal since the external clock is still active. All registers and FIFOs retain their values when BB is in idle mode. BB enters idle mode by setting bit TBD in register TBD to "1". This bit is set by MCU and cleared by BB. BB goes back to working mode by setting CS_n input pin to "0" for TBD sec. Since BB retains all the register values in idle mode, special care should be given to the register values before BB enters idle mode. For example, the MCU should check that the BB is not in the middle of transmitting or receiving a packet. In addition, the RFACTIVE should be set low to shutdown the RFW-102. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 49 EM77F900 USB HUB+BB Controller 8.2.3 Preamble Correlation The transmitting BB sends the PREAMBLE in order to synchronize the receiver to its transmission. BB transmits a fixed size PREAMBLE of 16 bits. The received PREAMBLE has a variable length of 16 receiver correlates the 16 is enabled. The purpose of the PREAMBLE is to filter the module packets from white noise or other transmissions on the channel. NODE_ID and NET_ID filter are used to filter packets from other module networks. The PREAMBLE is transmitted MSB to LSB (PRE-H first and then PRE-L). The value of the PREAMBLE is determined according to PRE-L and PRE-H registers. The BB has the same PREAMBLE when it is in transmitting mode (TX_RX=1) as when it is in receiving mode (TX_RX=0). The value of the PRE-L and PRE-H registers should be identical in the BB in all nodes in the network. 9 bits, determined by SCR2 [5:7]. The 9 9 bits from its PRE-L and PRE-H registers to the 16 bits in its input shift-register. If a correlation was found, then BB receiver state machine 8.2.4 Refresh Bit When receiving a valid packet, The RFWaves modem (PHY layer) has to receive a "1" symbol each time a certain period has elapsed in order to maintain its sensitivity. The time between adjacent "1" symbols is determined by the value of the reference capacitor. This constraint is transparent to the application layer since the BB adds a "1" symbol (refresh bit) if too many "0" symbols are transmitted consecutively. On the receiver side, these additional "1" symbols (refresh bits) are removed by the BB. This feature is transparent to the application layer. The application layer has only to initialize the maximum allowed number of consecutive x"00" bytes. The BB has the flexibility to add a refresh bit every 1 to 7 bytes. This is configured by RB (0:2) bits in the PPR register. The value of RB (0:2) bits in PPR register determines the overhead the refresh bit has on the throughput of the link. The refresh bit does not add substantial overhead on the bit stream, since it is only added when the number of consecutive x"00" bytes exceeds a certain value. The data that is sent is application dependent, so the application can be adjusted in order that there will be a negligible probability of this event happening. Typical RFWaves capacitor: C=1nF Normal discharge current = 200nA Each 10mV on the capacitor represents 1dB in receiving power. 50 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller I 200nA 1dB = = C V 1nF 10mV 50 sec The capacitor is charged with each received "1" symbol. The receiver is allowed to lose 1dB before a new "1" is to be received. Thus, after each 50 consecutive "0" bits in 1Mbps (50sec) a "1" symbol should be sent. In this case, setting RB [0:2] in the PPR register to be 5 ("101") would be sufficient (5 bytes = 40bits). When RB (0:2) bits are set to "000" a refresh bit is added to every transmitted byte, regardless of its content. This introduces a constant overhead of 12.5%. 8.2.5 Bit Structure The BB uses an oscillator ranging from 6~24 MHz. In order to determine the output and input bit rate, the BB must be configured to the number of clocks consisting each bit. This gives the applicator the control over the bit rate with certain restrictions. Each bit must have at least six clock cycles. The maximum bit rate is 1Mbps. The minimum bit rate is 10Kbps (TBD). However it is recommended to work only at 1Mbps since reducing the bit rate does not change the energy of a transmitted bit. Meaning, reducing the bit-rate does not improve the bit error rate or the range between the transmitter and the receiver. Bit Length Register (BLR) determines the number of clock cycles per bit (bit period). BLR value is given a fixed offset of 6, since the minimum number of clock cycles in one bit is 6. Bit Rate = Oscillator/(BLR+6). The BB outputs (for the RFW-102) the bit structure as shown below. Bit "1" Structure - Even Clock Number Bit "1" Structure - Odd Clock Number Clock Period Bit Period Clock Period Bit Period In the odd number of clocks example BLR=1. In the even number of clocks example BLR=2. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 51 EM77F900 USB HUB+BB Controller The number of clocks when the line is "1" is determined as follows: Number of "1"s = FLOOR ((BLR+ 6)/2 - 1). In case of "0" bit, BB output "0" value for BLR+6 clock pulses. * FLOOR - Rounds towards zero. 8.2.6 CRC The BB adds additional CRC information to each packet in the transmitter module, in order to enable the protocol to detect errors. The CRC is a redundant code, which is calculated and added to each packet on the transmitter side. The CRC is also calculated on the receiver side. The CRC calculation results of the receiver and the CRC field in the received packet are compared in the receiver using the CRC module in the chip. If CRC results are equal, then the receiver knows with reasonable probability that the packet was received correctly. If the CRC results are not equal then the receiver knows with probability 1 that the packet was received incorrectly. The CRC mode is configured in the PPR (3:4) register. Both the receiving node and the transmitting node in the network have to be in the same CRC mode. The BB can apply CRC in three different ways: 16-Bit CRC - using polynom1+X2+X15+X16. 8-Bit CRC - using polynomial 1+X+X2+X8. No CRC. This gives each application the flexibility to choose the adequate amount of overhead it adds to each packet and the corresponding level of protection the CRC code has. If CRC is enabled, then BB calculates the CRC of each incoming packet. It does not put the received CRC value in the RX_FIFO. It just puts the result of its calculation in the RX_FIFO as the last byte of the packet: 0x55 - CRC received correctly. 0xAA - CRC was received incorrectly. The status bit SSR (0) stores the result of the last received packet. 52 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 8.2.7 RX FIFO All received bytes are transferred to the RX_FIFO. The RX_FIFO stores the input data until the MCU reads the data from it. CRC and PREAMBLE bytes are not transferred to the RX_FIFO. The RX_FIFO is accessed just like all other read-only registers in the BB. The MCU cannot write to the RX_FIFO, it can only read from it. RX_FIFO_SIZE is 16 bytes. The purpose of having an input FIFO in BB is to reduce the real-time burden from the MCU. The FIFO is used as a buffer, which theoretically enables the MCU to read the incoming data every RX_FIFO_SIZE * 8 bit/byte * 1sec = 128 sec, and not every 1sec in the case of serial input, or every 8sec in the case where there is a serial to parallel converter. The actual buffer size for practical use is a bit smaller, since the MCU response time is taken into account. The MCU has three ways to learn about the RX_FIFO status: The RX FIFO Status Register (RFSR) contains the number of bytes in the RX_FIFO. BB INT pin. If configured appropriately, the INT pin will be "1" each time RX_FIFO is almost full. This invokes an MCU interrupt if the INT pin is connected to the MCU external interrupt pin. RX_FIFO Overflow Status Bit - bit RX_OF in SSR indicates when an overflow event has occurred. If a received byte is written to a full RX_FIFO, the last byte in the RX_FIFO is override and the RX_OF flag is raised. The RX_AF interrupt should invoke the MCU to read from the RX_FIFO. Using the almost full event gives the MCU 32sec (4 bytes x 8 sec) to respond before it loses data, assuming a bit rate of 1Mbps. It uses most of the RX_FIFO size even if the response latency of the MCU is very short. Should the MCU not respond properly to the almost full event, and an input byte is written to the RX_FIFO when it was full, then this byte would overrun the last byte in the RX_FIFO, meaning the byte that immediately preceded it. LOCK_OUT interrupt should also trigger the MCU to read from the RX_FIFO. In case a packet has ended and the RX_AF interrupt was not invoked, the MCU should be triggered by the LOCK_OUT interrupt. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 53 EM77F900 USB HUB+BB Controller 8.2.8 TX FIFO Transmitting data is done by writing it to the TX_FIFO. The interface to the TX_FIFO is similar to all the other write-only registers in BB. The purpose of the TX_FIFO is to reduce the real-time transmission process from the MCU. The TX_FIFO enables the MCU, theoretically, to write to the TX_FIFO every 128sec and not every 8sec, as is the case with a regular 8-bit shift register. The TX_FIFO Status Register (TFSR) indicates the number of bytes in the TX_FIFO. The TX_FIFO can also invoke an MCU interrupt if TX_FIFO almost empty event occurs. Almost empty flag will rise when there are only four empty bytes in the TX_FIFO. It gives the MCU 32sec response time to reload the TX_FIFO in case the transmitted packet is bigger than the TX_FIFO. In case the MCU writes to a full TX_FIFO, then this byte overruns the last byte in the TX_FIFO, meaning the byte that was written just before it. Writing to a full TX_FIFO sets the TX_OF flag in SSR. 8.2.9 Interrupt Driver The INT output pin is the summation of all interrupts source in the BB. Whenever an interrupt event has occurred and this interrupt is enabled (IER), the INT will go from low to high. The INT will remain high until the IIR register is read. The IIR register contains all the interrupt events that have occurred since the last read. It shows the event only for enabled interrupts. If an interrupt is disabled, even if the event that invoked this interrupt has occurred, the interrupt flag will be low. The IER register is used to enable/disable each of the interrupt. SCR4 (0) enables/disables all the interrupts. There are eight events in the BB that can cause the INT pin to go from low to high: 1. LOCK_IN - This interrupt indicates that the BB has started receiving a new packet. The PREAMBLE has been identified. If the NET_ID and/or the NODE_ID are enabled, then they have been identified correctly. This event signals the beginning of an incoming packet. 2. LOCK OUT - BB has just finished receiving a packet. This means that if the BB is in fixed packet size mode, then it has finished receiving PSR bytes not including CRC bytes. If BB is not in fixed packet size mode, then it has just finished receiving a packet of size as indicated in the packet header. Although RX_STOP and setting TX_RX=1 (SCR2) terminate the receiving of the packet, they do not cause a LOCK_OUT event, since the MCU is already aware of it (the MCU initiated it). The LOCK_OUT interrupt tells the MCU when to get data out of the RX_FIFO. 3. 54 * LINK_DIS - This interrupt indicates that a "Zero counter" capacitor discharge event has occurred. If a consecutive number of zero bits (according to SCR3 Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller (4:6)) have been received, this interrupt is set, even if zero count capacitor discharge is disabled (SCR3 (3) - EN_ZERO_DIS = '0'). The actual capacitor discharge and its interrupt are two separate registers (IER (2) for the interrupt and SCR3 (3) for the discharge). 4. RX_OF - This interrupt indicates that a byte from an incoming packet was discarded, since the RX_FIFO was already full. The receiver module tried to write a byte to a full RX_FIFO. The MCU should know that the corresponding packet is corrupted, since it is lacking at least one byte. 5. 6. 7. 8. TX_EMPTY - The BB has finished transmitting a packet. Meaning, the transmit shift register is empty and BB is now in RX mode (not TX mode). RX_FIFO_AF - RX_FIFO is almost full. If the MCU does not want the RX_FIFO to overflow, then it should empty it. TX_FIFO_AE - TX_FIFO is almost empty. If the MCU did not finish putting the transmitted packet in the TX_FIFO, then it should continue doing so now. CS - CS status line has gone from "1" to "0" invokes the CS interrupt. This signals the MCU that an unidentified (NET_ID or NODE_ID or PREAMBLE were not identified) packet has ended. If the MCU has a packet to transmit, and CS="1" then the MCU waits for this event. All these events can be masked. If an event is masked, then even if that event occurs, it does not set the INT pin to "1". The masking is done by register IER. The reason for masking is that in different applications or in different situation in the same application, these events have different priorities. The MCU determines which of these events will invoke an MCU interrupt. Moreover all these events can be masked together by IE in the IER register. If INT pin is set to "1", the MCU learns which event has occurred by reading the IIR register. The INT goes to "0" when the MCU reads from the IIR register. 8.2.10 Packet Size There are two types of packet structure determined by PPR[5] (Fixed). Fixed Sized Packet - all packets have the same, fixed size. The packet size is determined in the PSR register. The packet size can be 2 ~ 255 bytes. Variable Sized Packet - the header of the incoming packet determines the packet size. One of the header bytes contains the packet size. Bits SIZE_LOC[0:1] in LCR register determines the location (offset) of packet size inside each incoming packet header. The BB reads the packet size byte in the packet header according to the LCR register. In both cases the packet size does not include the CRC addition or the PREAMBLE. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 55 EM77F900 USB HUB+BB Controller 8.2.11 NET_ID and NODE_ID Filters NET_ID and NODE_ID are two filters in the receiver. They filter incoming packets according to their network address and node address. The address field in each incoming packet is compared to NET_ID byte and NODE_ID byte. If one of the above comparisons fail, then the packet is discarded and the MCU will not be aware of it. NET_ID and NODE_ID are both one byte. Their values are stored in NIR and BIR registers accordingly. The byte to which they are compared is set by LCR register. Each of them can be enabled or disabled independently (PPR register). NET_ID is targeted to be a filter on the network address. It is supposed to be common for all nodes in the network. NODE_ID is targeted to be a filter on the specific node address. It is supposed to be unique to each node in the network. The purpose of these filters is to save MCU power and to reduce its load. In a multi-node network, a node can filter all packets that are not sent to it, while in multi-network environment, a node can filter packets from other RFWaves networks. In certain network a multicast ability inside the network is required. Even if NODE_ID filter is applied, Addresses `111111XX' in NODE_ID filter are preserved for multicast transmissions. NODE_ID filter will not discard those four addresses in any case. 8.2.12 Carrier-sense Carrier-sense protocols are protocols in which a node (station) listens to the common channel before it starts transmitting. The node tries to identify other transmissions in order to avoid collision that might block its own transmission. In a wider perspective, a network that applies carrier-sense protocol utilizes the channel bandwidth more efficiently. A more efficient network enables lower power consumption to each node, shorter delay and higher probability of reaching the destination of each packet. The BB uses one complimentary technique in order to achieve very robust carrier-sense abilities. It has an internal implementation of RFWaves Network Carrier-Sense algorithm. This enables it to avoid collision with other RFWaves stations on its network or from other networks in the area. While the Carrier-Sense status bit in SSR (CS) tells the MCU when not to transmit, the two interrupt CS and LINK_DIS gives the MCU a flag when to transmit. LINK_DIS will be invoked whenever any transmission has ended, while CS interrupt will be invoked only when an RFWaves transmission has ended. Some applications can use some of the above mechanisms though not all of them - according to its needs. 56 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 8.2.12.1 RFWaves Carrier-Sense Algorithm Assuming our bit rate is 1Mbps. According to the described bit structure (Section 7.2.5 Bit Structure), the time difference between two rising on DATA_IO must be an integer number of 1sec. If we take into account the frequency deviation between the two BB oscillators, the time difference between two rising edges is 1sec . The depends on the frequency deviation between the two BB oscillators. The BB uses this quality in its carrier-sense algorithm. If an N (N = (CSR (0:3)*2)+2) number of "1" bits, where each is preceded by at least one "0" bit, are received with time difference of an integer number of 1sec between two consecutive "1" bits, then the CS flag in SSR equals `1'. Basically, the BB counts "0" to "1" transits on DATA_IO input, where the time difference between two transits should be an integer number (2) to 1sec. The number of consecutive "1" bits that conforms to this rule is counted in the following example (Figure 7-2) in ONE_CNT counter. ONE_CNT is incremented only if a "1" bit that comes after a "0" bit is received, where the time gap between the "1" bit and the preceding "1" bit is as mentioned above. If the time difference between two consecutive "1" bits is out of the allowed deviation, the ONE_CNT is reset. ONE_CNT is also reset if the number of consecutive "0" exceeds (CSR (4:7)*2)+2, where CSR is the last "1" bit received is counted in ZERO_CNT. ZERO_CNT is reset each time "1" bit is received. Both M and N values are determined in CSR register (CSR (7:4) and CSR (3:0) accordingly). (0) ONE_CNT=0 ZERO_CNT=1 (1) ONE_CNT=1 ZERO_CNT=0 DATA_IO Signal (2) ONE_CNT=1 ZERO_CNT=1 (3) ONE_CNT=2 ZERO_CNT=0 (4) ONE_CNT=2 ZERO_CNT=0 (6) ONE_CNT=1 ZERO_CNT=0 (5) ONE_CNT=2 ZERO_CNT=1 1usec Search Window 1usec 2 * 1usec Search Window 1usec 1usec Search Window Fig. 8-2 Carrier-Sense Example In the example shown in Figure 8-2, at time (1) a new "1" bit is received after a "0" bit was received. Thus, ONE_CNT equals 1 and ZERO_CNT is reset to 0. At time (2), a zero bit is received, so the ZERO_CNT is incremented. At time (3), a "1" is received after a "0" bit that was received before it. Thus ONE_CNT is incremented and ZERO_CNT is reset. At time (4) a "1" bit is received after a "1" bit, thus, there is no change in any counter. At time (6) a "1" bit is received out of the allowed window, so ONE_CNT is reset to 1. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 57 EM77F900 USB HUB+BB Controller The CSR register is used to configure the carrier-sense algorithm sensitivity. The CSR register determines the number of "1" bits that are required in order to decide that a carrier exists. The CSR also determines the number of successive "0" bits that reset the carrier-sense state machine. In SSR register, bit CS notifies whether a carrier was identified. Carrier-sense can also be used as an interrupt. When CS in SSR goes from `1' to `0' i.e. the transmission has stopped, a CS interrupt is invoked (if enabled in IER). The purpose of this interrupt is to inform the MCU that the channel is free again. If the BB identifies a packet, the carrier-sense algorithm halts. When the BB is in RX mode and LOCK flag in SSR is "0", the CS mechanism is working. When the LOCK flag in SSR is "1", the CS mechanism is not working, since the CS flag does not add any information because a PREAMBLE was identified already. After a PREAMBLE was identified the CS in SSR equals `1'. 8.2.13 Receiver Reference Capacitor Discharge The BB implements two independent mechanisms for receiver capacitor discharge: At the end of each received packet. Zero counter. Mechanism 1 is enabled/disabled by bit EN_CAP_DISCH in SCR3. Mechanism 2 is enabled/disabled by bit EN_ZERO_DISCH in SCR3. The number of "0" bits that will cause a discharge in Mechanism 2 is determined by bits ZERO_DISCH_CNT [0:2]. For both mechanisms, the discharge time is determined by CAP_DIS_PERIOD in SCR3. Discharge is done by setting RX_TX pin to `1' for a certain time and then setting it back to `0'. (*) More detailed explanations of the reference capacitor discharge algorithms and motivations can be found in the "RFW - Capacitor Discharge.pdf" document. 8.2.14 Changing BB Configuration It is not recommended to change the BB configuration while it is in the middle of receiving or transmitting a packet. Thus, before writing to any of the BB control registers (such as BLR, PRE-L, PRE-H, PPR etc): Change TX_RX mode to RX. Disable PREAMBLE search (SEARCH_EN in SCR2) Stop all RX receiving - RX_STOP. It is then safe to change the BB configuration. 58 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 8.2.15 Input Synchronizer Handling asynchronous inputs to the BB. Asynchronous Input Synchronized Input S R SET Q Q S R SET Q Q CLR CLR CLK 8.3 Register Description The registers in the BB are divided into three groups: Read-only registers which are mainly status registers. Write-only registers which are mainly control registers. Read and write registers. In case of a RST pulse, all registers are set to their default value. 8.3.1 Bit Length Register (BLR) This register is both a read and a write register. It determines the length of the bit in terms of clock cycles. The bit length will be (BLR+6) clocks, since the minimum length of a bit is 6 clocks. Default Value: 00 (0+6=6). 8.3.2 Preamble Low Register (PRE-L) This register is a write-only register. This register contains the 8 least significant bits of the PREAMBLE. Name PRE-L Bit 7 PR-7 Bit 6 PR-6 Bit 5 PR-5 Bit 4 PR-4 Bit 3 PR-3 Bit 2 PR-2 Bit 1 PR-1 Bit 0 PR-0 Default Value: 0xEB. 8.3.3 Preamble High Register (PRE-H) This register is a write-only register. This register contains the 8 most significant bits of the PREAMBLE. Name PRE-H Bit 7 PR-15 Bit 6 PR-14 Bit 5 PR-13 Bit 4 PR-12 Bit 3 PR-11 Bit 2 PR-10 Bit 1 PR-9 Bit 0 PR-8 Default Value: 0xFF. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 59 EM77F900 USB HUB+BB Controller 8.3.4 Packet Parameter Register (PPR) Name PPR Bit 7 NET ID_EN Bit 6 NODE ID_EN Bit 5 FIXED Bit 4 CRC1 Bit 3 CRC0 Bit 2 RB-2 Bit 1 RB-1 Bit 0 RB-0 This is a read and a write register. It contains control bits of the transmitted and received packet structure. Default Value: 0x3A Bits 0-2: Refresh Bits. RB-0 ~ RB-2 These bits determine the maximum number of successive "zero" bytes are allowed before an added "one" bit is stuffed to the packet by the transmitter state machine. The reason for this feature is to keep the RFW-102 reference capacitor charged. Refresh Bit Refresh bit is added to every byte. Refresh bit is added if 1 byte equals x"00". Refresh bit is added if 2 successive bytes equal x"00". Refresh bit is added if 3 successive bytes equal x"00". Refresh bit is added if 4 successive bytes equal x"00". Refresh bit is added if 5 successive bytes equal x"00". Refresh bit is added if 6 successive bytes equal x"00". Refresh bit is added if 7 successive bytes equal x"00". Bit 2 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 The value of the refresh bit is determined by the value of the reference capacitor. Bits 3, 4: CRC [0:1] These bits control the CRC operation for both transmit and receive mode: CRC No CRC CRC8 CRC8 CRC16 Bit 4 0 0 1 1 Bit 3 0 1 0 1 Bit 5: Fixed This controls the packet mode. When high system packets are fixed size and the length is specified in the Packet Size Register (PSR). When Fixed is low, the packet size is variable. The size is specified in the header of the incoming or outgoing packets. The location of the packet size field is specified in the LCR register. 60 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Bit 6: NODE_ID_EN This is NODE_ID control bit. 0: Disables Node ID search 1: Enables Node ID search according to LCR, BIR Bit 7: NET_ID_EN This is NET_ID control bit. 0: Disables Net ID search 1: Enables Net ID search according to LCR, NIR 8.3.5 System Control Register 1 (SCR1) Name N/A Bit 7 N/A Bit 6 N/A Bit 5 N/A Bit 4 N/A Bit 3 N/A Bit 2 N/A Bit 1 N/A Bit 0 N/A This byte is reserved. Default Value: 0x00 8.3.6 System Control Register 2 (SCR2) Name SCR2 Bit 7 PRE MASK 2 Bit 6 PRE MASK 1 Bit 5 PRE MASK 0 Bit 4 STOP RX Bit 3 TX FIFO RESET Bit 2 RX FIFO RESET Bit 1 SEAR CH EN Bit 0 TX_R X This register is a read and a write register. It controls the system operation modes. Bit 0: TX_RX Controls the transceiver mode: receive mode or transmit mode When TX_RX is low - BB is in receive mode (default mode). The output pin RX_TX is set to `0'. BB searches for a PREAMBLE. If PREAMBLE is found, it handles the process of receiving a packet. If SCR3 (7) is set, then the BB goes to RX mode and the output pin RX_TX is in TX mode. The capacitor discharge can change the output pin RX_TX to TX mode even if we are in RX mode in the BB. In this case the output pin RX_TX will be in TX for a short duration and then return to RX mode. When TX_RX is high - BB is in transmit mode. The output pin RX_TX is set to `1'. The BB handles the process of transmitting a packet according to the data in the TX_FIFO. When it finishes transmitting the packet, it automatically goes back to receive mode. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 61 EM77F900 USB HUB+BB Controller Bit 1: SEARCH_EN Preamble search enable bit. When 1: Enables the search for Preamble in receive mode. When 0: Disables the search for Preamble in receive mode, (used when user configures the system while in default receive mode). This bit's default value is `0'. It must be set to `1' in order to start receiving a packet. Bit 2: RX_FIFO_RESET This bit resets the RX_FIFO address pointers when set to Logic 1. This bit is set by the MCU and is cleared automatically by the BB. Bit 3: TX_FIFO_RESET This bit resets the TX_FIFO address pointers when set to Logic 1. This bit is set by the MCU and is cleared automatically by the BB. Bit 4: STOP_RX This bit stops receiving the current command, resets the RX_FIFO counters and start new searches for a preamble. This bit is set by the MCU and is cleared automatically by the BB. Bits 5-7: PRE_MASK [0:2] These bits determine the mask on PRE-H in preamble correlation. Meaning, it determines the size of the PREAMBLE in the receiver. The PRE-L is always used in the PREAMBLE correlation. BB cuts off bit from PRE-H register, starting from the MSB. PRE_Mask 0 0 0 0 0 1 1 1 1 PRE_Mask 1 0 0 1 1 0 0 1 1 PRE_Mask 2 0 1 0 1 0 1 0 1 Preamble Size 16 15 14 13 12 11 10 9 Default Value: 0x60 62 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 8.3.7 System Control Register 3 (SCR3) This register is a read and a write register. Name SCR3 Bit 7 LOW MODE Bit 6 ZERO DISCH CNT 2 Bit 5 ZERO DISCH CNT 1 Bit 4 ZERO DISCH CNT 0 Bit 3 EN ZERO DISCH. Bit 2 CAP DIS PERIOD Bit 1 EN CAP DISCH. Bit 0 - Bit 1: EN_CAP_DISCH Enables/disables capacitor discharge mechanism after each received packet: 0: Disables discharge 1: Enables discharge This bit overrides Bit 3 Bit 2: CAP_DIS_PERIOD Determines the capacitor discharge duration: 0: The pulse width is 36 clocks, (3 sec at 12 MHz clock). 1: The pulse width is 72 clocks, (3 sec at 24 MHz clock). Bit 3: EN_ZERO_DISCH Enables/disables zero counter mechanism for capacitor discharge: 0: Disables discharge 1: Enables discharge Bits 4-6: ZERO_DISCH_CNT [0:2] Determine the number of zero bits that will trigger a capacitor discharge by the zero counter mechanism. ZERO DISCH CNT 0 0 0 0 0 1 1 1 1 ZERO DISCH CNT 1 0 0 1 1 0 0 1 1 ZERO DISCH CNT 2 0 1 0 1 0 1 0 1 Number of Zeros 5 10 15 20 25 30 35 40 Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 63 EM77F900 USB HUB+BB Controller Bit 7: LOW_MODE Enables or disables low power mode for RFW-102: 0: Disables low mode (normal mode) 1: Enables low mode. BB is in RX mode, while RFW-102 is in TX mode. User has to put the BB into RX mode and disable RX and PREAMBLE search, before enabling LOW_MODE. This transfers the RFW-102 to TX mode using RX_TX pin, while the BB is still in RX mode. RFW-102 power consumption is lower in TX mode than in RX mode. BB cannot remain in TX mode, if it is not transmitting. Low mode is the combination of both of the above. Default Value: 0x01 8.3.8 System Control Register 4 (SCR4) This register is a read and a write register. Name SCR4 Bit 7 N/A Bit 6 N/A Bit 5 N/A Bit 4 N/A Bit 3 FIFO FLAGS Bit 2 WIN CONT Bit 1 RF_ACTIVE Bit 0 IE Bit 0: IE This flag enables all interrupts when set to `1'. When `0' all interrupts are disabled. Bit 1: RF_ACTIVE This bit controls the RF_ACTIVE pin. When this bit is high the RF Modem is active. Bit 2: WIN CONT This bit determines the size of the WINDOW in the Preamble search module. IF (BLR+6)>14 and WIN_CONT=1, then the preamble window size is 5 Bit 3: FIFO FLAGS Determines the RX_FIFO AF flag and TX_FIFO AE flag: IF FIFO FLAGS = 0 then AF = 12 and AE = 4 IF FIFO FLAGS = 1 then AF = 8 and AE = 8 Default Value: 0x00. 64 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 8.3.9 Transmit FIFO Status Register (TFSR) This register is a read-only register. It contains the number of bytes in the TX_FIFO. Default Value: 0x00 (TX_FIFO empty). 8.3.10 Receive FIFO Status Register (RFSR) This register is a read only register. It contains the number of bytes in the RX_FIFO. Default Value: 0x00 (TR_FIFO empty). 8.3.11 Location Control Register (LCR) This is a read and write register. Name LCR Bit 7 Bit 6 SIZE LOC 2 Bit 5 SIZE LOC 1 Bit 4 SIZE LOC 0 Bit 3 NET LOC1 Bit 2 NET LOC 0 Bit 1 NODE LOC 1 Bit 0 NODE LOC 0 Bits 0, 1: NODE_LOC [0:1] These bits determine the location of the NODE_ID parameter in the header (the location is specified in bytes excluding preamble). The location should be fixed for all of different kinds of packets transferred by the system. NODE_ID must never be set to be smaller than NET_ID, if both filters are enabled. Location 2 3 4 5 NODE LOC 1 0 0 1 1 NODE LOC 0 0 1 0 1 Bits 2 ~ 3: NET_LOC [0:1] These bits determine the location of the NET_ID parameter in the header (the location is specified in bytes excluding preamble). The location should be fixed for all the different kinds of packets transferred by the system. Location 1 2 3 4 NET LOC 1 0 0 1 1 NET LOC 0 0 1 0 1 Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 65 EM77F900 USB HUB+BB Controller Bits 4 ~ 5: SIZE_LOC [0:2] These bits determine the location of the Packet Size parameter in the header (the location is specified in bytes, excluding preamble). The location should be fixed for all the different kinds of packets transferred by the system. Location 2 3 4 5 6 7 8 9 Size LOC 2 0 0 0 0 1 1 1 1 Size LOC 1 0 0 1 1 0 0 1 1 Size LOC 0 0 1 0 1 0 1 0 1 Default Value: 0x00 8.3.12 Node Identity Register (BIR) This is a read and write register. When the Receiver State Machine builds the incoming packet, it compares the value in the BIR register to the received data at the location specified in LCR. If received NODE_ID and the expected NODE_ID are not equal, the packet is discarded. Four multicast NODE_ID addresses are implemented "111111XX". All packets whose 6 MSBs are "1" are not discarded. Default Value: 0x00 8.3.13 Net Identity Register (NIR) This is a read and a write register. When the Receiver State Machine builds the incoming packet, it compares the value in the NIR to the received data at the location specified in LCR. If received NET_ID and the expected NET_ID are not equal, the packet is discarded. Default Value: 0x00 66 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 8.3.14 System Status Register (SSR) Name SSR Bit 7 Bit 6 TX_UF Bit 5 BIT_ERROR Bit 4 LOCK Bit 3 CS Bit 2 TX EMPTY Bit 1 LOCKED Bit 0 CRC ERROR This register is a read-only register. It provides status information to the MCU concerning the communication line and the data transfer. Bits 1, 2, 3 can trigger the interrupt if enabled in the IER. Bits 0, 5 and 6 are set by H/W and cleared automatically after the MCU reads the register. Bits 1~4 are set and cleared by H/W. Bit 0: CRC_ERROR This flag indicates a CRC Error in the packet. The CRC Block sets this flag at the end of each received packet according to the CRC calculation result. BB compares the calculated CRC and the received CRC. When these values differ, the flag goes high. The flag is cleared only after the MCU reads the SSR register. If the MCU does not read the SSR register, this flag remains "1". Bit 1: LOCKED_IN This flag indicates that a packet is being received. Bit 1 is set to logic 1 whenever the system identifies a new incoming packet (triggers LOCK IN interrupt). The bit will reset to logic 0 when the packet ends (triggers LOCK OUT interrupt) or when one of the IDs fails (NET or BYTE). This indicator is important whenever we want to switch to transmit mode because it can tell us that the line is busy and that in most cases the transmission won't succeed. The Lock triggers interrupt for every change in the bit status. Bit 2: TX_EMPTY This bit is the Transmitter Empty flag. When this bit is high the system is available for loading the next packet for transmission and BB is in receive mode. When the flag is low, BB is in the middle of a packet transmission. When transmitting few successive packets, the MCU should wait to the end of a packet before it reload the TX_FIFO with the next packet. Bit 3: CS Carrier Sense detection bit. When this bit is high, the system has identified a structure of packet transmission in the air according to CSR. When low, no carrier has been detected. This bit is only valid in receive mode. The conditions for setting or clearing this flag are determined in CS register. When LOCKED is high then CS is meaningless. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 67 EM77F900 USB HUB+BB Controller Bit 4: LOCK This signals whether a PREAMBLE was identified or still searching. When flag is "0", the receiver is searching for PREAMBLE. When flag is "1" a PREAMBLE was identified. If a packet was discarded for any reason, LOCK flag goes to 1. Bit 5: BIT_ERROR This flag indicate that there was some error in the received package. The packet was not received according the expected timing specifications. The packet can still pass CRC verification. Bit 6:TX_UF This flag is set whenever the MCU reads a byte from an empty TX_FIFO. This flag indicates abnormal end of packet transmission. The MCU transmitter's state machine has expected to find a valid byte in the TX_FIFO according to the packet size, but it found an empty TX_FIFO. When this event occurs, the TX_EMPTY interrupt is invoked and TX_UF(under flow) flag is set to `1'. This flag is set by hardware and cleaned by MCU. It is cleaned whenever the MCU read the SSR register. Default Value: 0x04. 8.3.15 Packet Size Register (PSR) This is a read and a write register. It contains the Packet Size in byte units. When working in fixed size packets (see Control Bit-1), the size will be fixed for all types of packets. The size in PSR excludes 2 bytes of PREAMBLE and 2, 1 or 0 bytes of CRC. Default Value: 0x00. 8.3.16 Carrier Sense Register (CSR) This is both a read and a write register. Name CSR Bit 7 ZERO CNT.3 Bit 6 ZERO CNT.2 Bit 5 ZERO CNT.1 Bit 4 ZERO CNT.0 Bit 3 ONE CNT.3 Bit 2 ONE CNT.2 Bit 1 ONE CNT.1 Bit 0 ONE CNT.0 Bits 0-3: ONE_CNT [0:3] The number of successive "1" bits that set the carrier sense register high. Bit 4-7: ZERO_CNT [0:3] The number of successive "0" bits that reset the carrier sense register (CS='0'). Default Value: 0x44 68 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 8.4 Interrupt Registers 8.4.1 Interrupt Enable Register (IER) This register is a write and a read register. Name IER Bit 7 CS Bit 6 TX_AE Bit 5 RX AF Bit 4 TX EMPTY Bit 3 RX_OF Bit 2 LINK_ DIS Bit 1 LOCK OUT Bit 0 LOCK IN Default Value: 0x00. For all flags in this register: 0 - Disable; 1 - Enable Bit 0: LOCK_IN This flag enables/disables the LOCK IN interrupt. PREABLE + NODE_ID + NET_ID identified correctly triggers LOCK IN interrupt. Bit 1: LOCK_OUT This flag enables/disables the LOCK OUT interrupt. End of received packet triggers LOCK_OUT interrupt. Bit 2: LINK_DIS This flag enables/disables the LINK_DIS interrupt. The zero counter capacitor discharge triggers the LINK_DIS interrupt. Bit 3: RX_OF This flag enables/disables the RX_OF interrupt. End of received packet triggers RX_OF interrupt. Bit 4: TX_EMPTY This flag enables/disables the TX_EMPTY (Transmitter Empty) interrupt. TX_EMPTY interrupt tell the MCU that the transmitter has just finished transmitting a packet. BB goes to RX mode after finishing the transmission of a packet. Bit 5: RX_AF This flag enables/disables the RX_AF interrupt. The RX_AF interrupt is triggered when RX_FIFO AF flag goes from `0' to `1'. Bit 6: TX_AE This flag enables/disables the TX_AE interrupt. The TX_AE interrupt is triggered when TX_FIFO AE flag goes from `0' to `1'. Bit 7: CS This flag enables/disables the CS interrupt. CS flag in SSR negative edge triggers CS interrupt. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 69 EM77F900 USB HUB+BB Controller 8.4.2 Interrupt Identification Register (IIR) Name IIR Bit 7 CS Bit 6 TX AE Bit 5 RX AF Bit 4 TX EMPTY Bit 3 RX_OF Bit 2 LINK_D IS Bit 1 LOCK OUT Bit 0 LOCK IN This is a read only register. When the MCU accesses the IIR, all interrupts freeze. While the MCU access is occurring, the system records the changes in the interrupts but waits until the MCU access is complete before updating the register. A flag is active only when the matching interrupt enable bit is set, and does not depend on the IE bit value. The flags are set by H/W and cleared after the MCU reads the register. Bit 0: This bit reflects the LOCK IN flag interrupt when enabled by IER. LOCK_IN interrupt is invoke whenever a PREAMBLE+NET_ID+NODE_ID is recognized. If NET_ID is disabled, then a received PREAMBLE+ NODE_ID invokes the interrupt. If NODE_ID is disabled, then a received PREAMBLE+ NET_ID invokes the interrupt. If NET_ID and NODE_ID are disabled, then a received PREAMBLE invokes the interrupt. Bit 1: This bit reflects the LOCK OUT flag interrupt when enabled by IER. LOCK_OUT interrupt is invoked whenever RFW-D100 has finished receiving a packet. The end of the packet is determined according to the packet size. Bit 2: This bit reflects the LINK_DIS flag interrupt when enabled by IER. This interrupt is invoked by the zero counter capacitor discharge mechanism. Bit 3: This bit reflects the RX_OF flag interrupt when enabled by IER. Bit 4: This bit reflects the TX EMPTY flag interrupt when enabled by IER. Bit 5: This bit reflects the RX FIFO AF flag interrupt when enabled by IER. Bit 6: This bit reflects the TX FIFO AE flag interrupt when enabled by IER. Bit 7: CS - when CS flag goes from "1" to "0" an interrupt is invoked. 70 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 8.5 List of BB Register Mapping Register Address 0 (00000) 1 (00001) 2 (00010) 3 (00011) 4 (00100) 5 (00101) 6 (00110) 7 (00111) 8 (01000) 9 (01001) 10 (01010) 11 (01011) 12 (01100) 13 (01101) 14 (01110) 15 (01111) 16 (10000) 17 (10001) 18 (10010) 19 (10011) 20 (10100) --------Write TX_FIFO PRE_L PRE_H FRC_L FRC_H SCR1 SCR2 SCR3 SCR4 LCR BIR NIR PSR PPR BLR CSR IER IIR SSR TFR RFR --------Read RX_FIFO Default Values --0xFF 0xFF 0xFF 0xFF 0x00 0x60 0x01 0x00 0x00 0x00 0x00 0x00 0x3A 0x00 0x44 0x00 --0x04 0x00 0x00 --- 8.6 MCU BB Control Registers 8.6.1 Control Registers List RFAAR (0x2D): Register R2D indicates BB indirect RAM address. RFDB (0x2E): Register R2E indicates BB indirect RAM data. RFACR (0x2F): Register R2F indicates BB RAM access control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 RRST Bit 1 RFRD Bit 0 RFWR RFINTF (0x30): BB interrupt flags Bit 7 CSDF Bit 6 TX_AEF Bit 5 RX_AFF Bit 4 TX_ EMPTYF Bit 3 RX_OFF Bit 2 LINK_ DISF Bit 1 LOCK_OU TF Bit 0 LOCK_ INF Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 71 EM77F900 USB HUB+BB Controller RFINTE (0x99): BB interrupt enable. Bit 7 CSDE Bit 6 TX_AEE Bit 5 RX_AFE Bit 4 TX_ EMPTYE Bit 3 RX_OFE Bit 2 LINK_ DISE Bit 1 LOCK_OU TE Bit 0 LOCK_ INE PRIE (0x80): Peripherals enable control. Bit 7 SPIE Bit 6 Bit 5 WME Bit 4 ADE Bit 3 PWM1E Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE 8.6.2 BB Control Example ORG 0X0060 BC RETI ORG 0X0100 START: BS NOP BC BS MOV MOV ENI RF_TX_INITIAL: WRITE WRITE WRITE RFINTF, TX_EMPTYF // TX_EMPTY INT address // RF data send out, clear INT flag. RFACR, RRST RFACR, RRST PRIE, WME A, #0x10 RFINTE, A // BB reset. // BB power enable. // BB INT.TX_EMPTY enable. // enable all INT. // // // // Reset TX_FIFO, RX mode. Set bit rate. Set package size to be fixed. Refresh bit mode 1. CRC disabled // Set package size to 6. #SCR2, #8 #BLR, #10 #PPR, #33 WRITE WRITE WRITE RF_SEND_DATA: WRITE WRITE WRITE WRITE WRITE WRITE READ WRITE WRITE WRITE LOOP: JMP #PSR, #6 #PRE_H, #0xDC #PRE_L, #0xA7 #TX_FIFO, #0x01 #TX_FIFO, #TX_FIFO, #TX_FIFO, #TX_FIFO, #TX_FIFO, #0x02 #0x03 #0x04 #0x05 #0x06 // Set preamble High byte value. // Set preamble Low byte value. // Write first byte of package to TX_FIFO. // Write last byte of package to TX_FIFO. // Read TFR register data // enable TX_EMPTY INT // enable all INT. // move from RX to TX mode. LOOP // BB register write SUB WRITE_DATA_TO_RF: BC RFACR, RFWR NOP NOP BS RFACR, RFWR RET 72 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller READ_DATA_FROM_RF: NOP NOP NOP NOP BC RFACR, RFRD NOP NOP NOP NOP NOP MOV A, RFDB NOP NOP NOP BS RFACR, RFRD RET // BB register read SUB // Note the access time ; =============================================== WRITE MACRO #CON1, #CON2 // BB register write MACRO MOV A, #CON2 MOV RFDB, A MOV A, #CON1 MOV RFAAR, A CALL WRITE_DATA_TO_RF ENDM ; =============================================== READ MACRO #CON, REG // BB register read MACRO MOV A, #CON MOV RFAAR, A CALL READ_DATA_FROM_RF MOV REG, A ENDM Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 73 EM77F900 USB HUB+BB Controller 9 Universal Serial Bus Hub (USB Hub) 9.1 Instruction 9.2 Block Diagram Transceiver tx_dp tx_dm tx_oe_n rx_dp rx_dm rxd HUB usbint rden rdadr ubus 8 8 wren wradr dbus 8 8 18 MCU 9.3 USB Embedded Function FIFO Allocation End Point Number 0 1 2 3 End Point Type Control Interrupt / Bulk Interrupt / Bulk Interrupt / Bulk FIFO Size 64 byte IN 64 byte OUT 64 byte IN / OUT 64 byte IN / OUT 64 byte IN / OUT 74 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 9.4 Pin Description Pin I/O Description Speed USB device speed, always tie to 1 for upstream. Default value is 1 for downstream. 1: full speed device 0: low speed device Transceiver Suspend Disable transceiver when port is suspended or disabled. 1: Disable transceiver 0: Enable transceiver Output Data Plus USB output data plus used for upstream and downstream Ports 2-4 Output Data Minus USB output data minus used for upstream and downstream Ports 2-4 Output Enable USB data output enable used for upstream and downstream Ports 2-4 Input Data Plus USB input data plus used for upstream and downstream Ports 2-4 Input Data Minus USB input data minus used for upstream and downstream Ports 2-4 Input Data USB input data used for upstream and downstream Ports 2-4 Over Current Over-current indication of the downstream Ports 2-4 Power-on Switch Power-on switch of the downstream Ports 2-4 48MHz Clock for USB Reset An active low hardware reset signal to the USB. Clock Signal from MCU Interrupt Output Active high signals generated by the USB to the MCU. Read Enable The signal is asserted high for a read operation Read Address Bus Read address generated by MCU for the USB register selection. Data Output Data bus output to MCU Write Enable The signal is asserted high for a write operation. Write Address Bus Write address is generated by the MCU for the USB register selection. Data Input Data bus input to MCU speed[3:0] O suspend[3:0] O tx_dp[3:0] tx_dm[3:0] tx_oe_n[3:0] rx_dp[3:0] rx_dm[3:0] rxd[3:0] ovcur[3:1] pwron[3:1] usbclk rst_n mcuclk usbint[17:0] rden rdadr[7:0] ubus[7:0] wren wradr[7:0] dbus[7:0] O O O I I I I O I I I O I I O I I I Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 75 EM77F900 USB HUB+BB Controller 9.5 Timing Diagram of MCU Interface Symbol tcycle trs trh tras trah trdv tws twh twas twah twds twdh Parameter MCU clock cycle time Read enable setup time Read enable hold time Read address setup time Read address hold time Read data valid time Write enable setup time Write enable hold time Write address setup time Write address hold time Write data setup time Write data hold time Min 20ns 3ns 0.1ns 3ns 0.1ns - 3ns 0.1ns 3ns 0.1ns 3ns 0.1ns Max - - - - - 5ns - - - - - - 76 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 9.6 USB Hub and Function Register Summary P: Power-on reset; H: Hardware reset; S: Software reset Register USBTR GCNTR ADDR 0x1CC 0x1CD Reset P Bit 7 USBT7 Bit 6 USBT6 Bit 5 USBT5 FUNEN P/H Bit 4 USBT4 FUNRST P/H Bit 3 USBT3 RESUME P/H Bit 2 USBT2 SUSPEND P/H EP1DIR EP2DIR EP3DIR Bit 1 USBT1 PLUG P EP1TP1 EP2TP1 EP3TP1 INT0TX INT0TXE IDLEINT P/H IDLEINTE FADDR1 Bit 0 USBT0 URST P/H EP1TP0 EP2TP0 EP3TP0 INT0RX INT0RXE RSTINT P RSTINTE FADDR0 UOUT RE 0 X X NR TX N TX E0 R TX N X E1 R TX N X E2 R TX N X E3 EP0RXCT0 EP0TXCT0 EPCT0 EPCT0 EPCT0 EP0RX0 EP0TX0 EP1D0 EP2D0 EP3D0 OVCM HINT0RX HINT0RXE HADDR0 HOUT EP1CNTR EP2CNTR EP3CNTR EPINTR EPINTE 0x1CE 0x1CF 0x1D0 0x1D1 0x1D2 P/H/S P/H/S P/H/S P P EP1EN EP2EN EP3EN INT3 INT3E INT2 INT2E INT1 INT1E FRWPINT INT0IN INT0INE RUEINT P/H STAINTR 0x1D3 P P/H/S STAINTE FAR EP0RXTR EP0RXCSR EP0TXCSR EP1CSR EP2CSR EP3CSR EP0RXCTR EP0TXCTR EP1CTR EP2CTR EP3CTR EP0RXDA EP0TXDA EP1DAR EP2DAR EP3DAR HGSR HINTR HINTE HAR HEP0RXTR H PR C R E0X S 0x1D4 0x1D5 0x1D6 0x1D7 0x1D8 0x1D9 0x1DA 0x1DB 0x1DC 0x1DD 0x1DE 0x1DF 0x1E0 0x1E1 0x1E2 0x1E3 0x1E4 0x1E5 0x1E6 0x1E7 0x1E8 0x1E9 0x1EA 0x1EB P P P P/H/S P/H/S P/H/S P/H/S P/H/S X H/S H/S H/S H/S X X X X X H/S X X X X H/S HCDTOG0RX HPSTSCINT SOFINT EP0RX7 EP0TX7 EP1D7 EP2D7 EP3D7 CDTOG0RX FADDR6 FADDR5 FADDR4 FRWPINTE RUEINTE FADDR3 FADDR2 USETUPOW USETUP ERRSTS0RX S LL TS0RX ACKSTS0RX D G R 0 X DTOG0RX TA S TO E R R S A L TS TX T LS 0 STALLSTS1 STALLSTS2 STALLSTS3 EP0RXCT5 ACKSTS0TX ACKSTS1 ACKSTS2 ACKSTS3 EP0RXCT4 DTOGERR1 DTOGERR2 DTOGERR3 EP0RXCT3 EP0TXCT3 EP1CT3 EP2CT3 EP3CT3 EP0RX3 EP0TX3 EP1D3 EP2D3 EP3D3 DTOG0TX DTOG1 DTOG2 DTOG3 EP0RXCT2 E 0 CT2 P TX EPCT2 EPCT2 EPCT2 EP0RX2 EP0TX2 EP1D2 EP2D2 EP3D2 S S L0 E TA L RX S S L0 E TA L TX SESTALL1 SESTALL2 SESTALL3 EP0RXCT1 EP0TXCT1 EPCT1 EPCT1 EPCT1 EP0RX1 EP0TX1 EP1D1 EP2D1 EP3D1 CDTOG0TX ERRSTS0TX CDTOG1 CDTOG2 CDTOG3 ERRSTS1 ERRSTS2 ERRSTS3 EP0RXCT6 EP0TXCT6 EP0TXCT5 E 0 CT4 P TX EP1CT6 EP2CT6 EP3CT6 EP0RX6 EP0TX6 EP1D6 EP2D6 EP3D6 EP1CT5 EP2CT5 EP3CT5 EP0RX5 EP0TX5 EP1D5 EP2D5 EP3D5 CONFG EOF2INT EOF2INTE HADDR5 EP1CT4 EP2CT4 EP3CT4 EP0RX4 EP0TX4 EP1D4 EP2D4 EP3D4 RMWUPEN PWRM EOF1INT EOF1INTE HADDR4 HINT1 HINT1E HADDR3 PWRS/WM PWRS/W HINT0IN HINT0INE HADDR2 HINT0TX HINT0TXE HADDR1 HPSTSCINTE SOFINTE HADDR6 HSETUPOW HSETUP HERRSTS0RX H T L S S R H C TS0 S A L T 0 X A KS RX H T G R 0 X D O E RR HDTOG0RX HSESTALL0RX HRXEN0RX Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 77 EM77F900 USB HUB+BB Controller Register H PT C R E 0X S H PT C R E 1X S H PR C R E0X T H PT C R E 0X T H PR D R E0X A H PT D R E 0X A H PT D R E 1X A HPCONR HPSTAR HSR HPSR1 HPSR2 HPSR3 HPSR4 HPSCR1 HPSCR2 HPSCR3 HPSCR4 FNLR FNHR ADDR 0x1EC 0x1ED 0x1EE 0x1EF 0x1F0 0x1F1 0x1F2 0x1F3 0x1F4 0x1F5 0x1F6 0x1F7 0x1F8 0x1F9 0x1FA 0x1FB 0x1FC 0x1FD 0x1FE 0x1FF Reset H/S H/S X H/S X X X H/S X X X X X X X X X X X X Bit 7 Bit 6 Bit 5 H T LS ST S AL T 0 X H T LS ST S AL T 1 X Bit 4 H C S ST A K T 0X H C S ST A K T 1X - Bit 3 Bit 2 HDTOG0TX HDTOG1TX HEP0RXC2 Bit 1 H E T L0 X S S ALT H E T L1 X S S ALT HEP0RXC1 Bit 0 HTXEN0TX HTXEN1TX HEP0RXC0 HEP0TXC0 HEP0RXD0 HEP0TXD0 HSTSC HA D 0 PD R DMSTATE1 LPS PCSTS1 PCSTS2 PCSTS3 PCSTS4 PCSTSC1 PCSTSC2 PCSTSC3 PCSTSC4 FN0 FN8 HCDTOG0TX H R S ST E R T 0X HCDTOG1TX H R S ST E R T 1X HEP0RXC3 HEP0TXC3 HEP0RXD7 HEP0TXD7 HEP0RXD6 HEP0TXD6 HEP0RXD5 HEP0TXD5 HEP0RXD4 HEP0TXD4 HSTSCP4 CMDVLD DPSTATE4 DMSTATE4 HPCON5 DPSTATE3 HPCON4 DMSTATE3 HEP0RXD3 HEP0TXD3 HSTSCP3 HPCON3 DPSTATE2 OVIC LSDA1 LSDA2 LSDA3 LSDA4 PPWRSTA1 PPWRSTA2 PPWRSTA3 PPWRSTA4 PRTSTS1 PRTSTS2 PRTSTS3 PRTSTS4 PRTSTSC1 PRTSTSC PRTSTSC3 PRTSTSC FN7 FN6 FN5 4 FN4 POCI1 POCI2 POCI3 POCI4 POCIC1 POCIC2 POCIC3 POCIC4 FN3 HEP0TXC2 HEP0TXC1 HEP0RXD2 HEP0RXD1 HEP0TXD2 HEP0TXD1 HSTSCP2 HPADDR2 DMSTATE2 LPSC PSUSSTS1 PSUSSTS2 PSUSSTS3 PSUSSTS4 HSTSCP1 HPADDR1 DPSTATE1 OVI PENSTS1 PENSTS2 PENSTS3 PENSTS4 PSUSSTSC1 PENSTSC 1 PSUSSTS PENSTSC PSUSSTSC3 PENSTSC3 PSUSSTS C4 FN2 FN10 PENSTSC 4 FN1 FN9 9.6.1 USB General Control Register - GCNTR (0x1CD) Bit Field H/W S/W DF Description Software Reset S/W sets this bit and will reset the whole USB compound device. All registers return to their default value and the USB compound device will be in the default state. H/W will clear this bit after the reset is completed. Connect USB hub When set to 1 by S/W,1 will be driven to the connect pin, thus the pull-high resistance is connected to the USB bus, and the USB compound device is connected to the USB bus. When cleared to 0 by S/W, 0 will be driven to the connect pin, thus the pull-high resistance is not connected to the USB bus, and the USB compound device is not connected to the USB bus. This bit will be reset by S/W reset and USB reset. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) 0 URST R/W0C R/W 0 1 PLUG R R/W 0 78 * EM77F900 USB HUB+BB Controller Bit Field H/W S/W DF Description Suspend State Enable Set by S/W to force the whole USB compound device to enter suspend state. S/W is allowed to set this bit if the USB bus has been in the idle state for more than 3ms. The USB compound device will leave suspend state if S/W clears this bit or the resume bit is set. This bit will be cleared by H/W if resume bit is set. This bit will be reset by S/W reset and USB reset. Send Resume to USB Bus When set to 1, the USB compound device will send a resume signal to the USB bus after the USB bus has been in the idle state for more than 5ms. The resume signal will be driven for 5ms, H/W will clear this bit after completing resume sending. Software Reset Embedded Function S/W sets this bit which will reset the USB Embedded function. This bit should be set to 1 when the SetPortReset of this port is received. When this bit is set: All registers of the embedded function (EP1C, etc) return to their default value. All FIFOs of the embedded function are cleared. H/W will clear this bit after the reset is completed. Enable Embedded Function Embedded Function is connected and active only when this bit is set to 1. This bit should be cleared to 0 when the SetPortSuspend of this port is received. 2 SUSPEND R/W0C R/W 0 3 RESUME R/W0C R/W 0 4 FUNRST R/W0C R/W 0 5 FUNEN R R/W 0 7-6 Reserved Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 79 EM77F900 USB HUB+BB Controller 9.6.2 Endpoint X Control Register - EP1/2/3CNTR (0x1CE~0x1D0) Endpoint 1 Control Register (EP1CNTR) Endpoint 2 Control Register (EP2CNTR) Endpoint 3 Control Register (EP3CNTR) Bit Field H/W S/W DF Description Endpoint Type. These bits program the type of endpoint. 1-0 EPXTP R R/W 3 Bit1 Bit0 Type 0 0 Un-used 1 0 Bulk 1 1 Intterrupt Endpoint Direction. 2 4-3 5 7-6 EPXDIR Reserved Endpoint Enable/Disable EPXEN Reserved R R/W 0 0=Disable endpoint 1=Enable endpoint R R/W 1 0=OUT 1=IN 9.6.3 Endpoint Interrupt Event Status Register - EPINTR (0x1D1) Bit Field H/W S/W DF Description EP0 USB RX Event Set by H/W when either SETUP transaction ends with ACK or OUT transaction ends with ACK or STALL. It is also set when SETUPOW (EP0RXTK Register) bit is set. Needs to check EP0RXCS Register for details. When S/W clears all the OUT, SETUP and SETUPOW bits in EP0RXTR Register, this bit will be cleared automatically. EP0 USB TX Event Set by H/W when IN transaction ends with ACK or STALL. 1 INT0TX R/W R/W0C 0 When S/W writes a 0, it will clear this bit, when a 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. 0 INT0RX R/W R 0 80 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Bit Field H/W S/W DF Description EP0 USB IN Token Event Set by H/W when a valid IN token is received. When S/W writes a 0, it will clear this bit, when a 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. EP1 Interrupt Set by H/W when IN transaction (Interrupt IN / Bulk IN) ends with ACK or STALL or OUT transaction (Bulk OUT) ends with ACK or STALL. IN or OUT transaction is decided by Endpoint Type. When S/W writes a 0, it will clear this bit, when a 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. EP2 Interrupt Set by H/W when IN transaction (Interrupt IN / Bulk IN) ends with ACK or STALL or OUT transaction (Bulk OUT) ends with ACK or STALL. IN or OUT transaction is decided by Endpoint Type. When S/W writes a 0, it will clear this bit, when a 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. EP3 Interrupt Set by H/W when IN transaction (Interrupt IN / Bulk IN) ends with ACK or STALL or OUT transaction (Bulk OUT) ends with ACK or STALL. IN or OUT transaction is decided by Endpoint Type. When S/W writes a 0, it will clear this bit, when a 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. 2 INT0IN R/W R/W0C 0 3 INT1 R/W R/W0C 0 4 INT2 R/W R/W0C 0 5 INT3 R/W R/W0C 0 7-6 Reserved Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 81 EM77F900 USB HUB+BB Controller 9.6.4 Endpoint Interrupt Event Enable Control Register - EPINTE (0x1D2) Bit 0 1 2 3 4 5 7-6 Field INT0RXE INT0TXE INT0INE INT1E INT2E INT3E Reserved H/W R R R R R R S/W R/W R/W R/W R/W R/W R/W DF 0 0 0 0 0 0 Description EP0 USB RX Event Enable EP0 USB TX Event Enable EP0 USB IN Token Event Enable EP1 interrupt Enable EP2 interrupt Enable EP3 interrupt Enable 9.6.5 State Interrupt Event Flag Register - STAINTR (0x1D3) Bit Field H/W S/W DF Description USB Bus Reset Event Detect Set by H/W when reset signal is detected on the USB bus. After a USB bus reset, all registers return to their default value and the USB device will be in the default state. When S/W writes a 0, it will clear this bit, when a 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. USB Bus Suspend Detect Set by H/W when the USB bus is idle every 3ms. 1 IDLEINT R/W R/W0C 0 When S/W writes a 0, it will clear this bit, when a 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. USB Bus Resume Detect Set by H/W when resume signal is detected. 2 RUEINT R/W R/W0C 0 When S/W writes a 0, it will clear this bit, when a 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. Function Remote Wake-up interrupt 3 FRWPINT R/W R/W0C 0 The USB hardware sets this bit to signal that an external interrupt causes a remote wake-up. This remote wake-up should be assigned to a peripheral function. 0 RSTINT R/W R/W0C 0 7-4 82 * Reserved Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 9.6.6 State Interrupt Event Enable Control Register - STAINTE (0x1D4) Bit 0 1 2 3 7-4 Field RSTINTE IDLEINTE RUEINTE FRWPINTE H/W R R R R S/W R/W R/W R/W R/W DF 0 0 0 0 Description Enable USB Bus Reset Event Detect Enable USB Bus Suspend 3ms Detect Enable USB Bus Resume Detect Function Remote Wake-up interrupt Enable Reserved 9.6.7 Function Address Register - FAR (0x1D5) Bit 6-0 7 Field FADDR Reserved H/W R S/W R/W DF 0 Description USB Device Address 9.6.8 Endpoint 0 RX Token Register - EP0RXTR (0x1D6) Bit Field H/W S/W DF RX OUT Token 0 UOUT R/W R/W0C 0 Set by H/W to indicate OUT token is received and transaction ends with ACK or STALL. When S/W writes a 0, it will clear this bit, when a 1 is written, no change occurs. RX SETUP Token 1 USETUP R/W R/W0C 0 Set by H/W to indicate SETUP token is received and transaction ends with ACK. When S/W writes a 0, it will clear this bit, when a 1 is written, no change occurs. SETUP Overwrite 2 R/W R/W0C 0 Set by H/W to indicate SETUP token is received when RX FIFO is not empty (no matter it is ended with error or ACK). When S/W writes a 0, it will clear this bit, when a 1 is written, no change occurs. 7-3 Reserved Description USETUPOW Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 83 EM77F900 USB HUB+BB Controller 9.6.9 Endpoint 0 RX Command/Status Register - EP0RXCSR (0x1D7) Bit Field H/W S/W DF RX Enable Set by S/W to enable rx USB data. USB data will be written to FIFO and ACK will be returned if the bit "SESTALL" is not set. 0 RXEN0RX R/W0C R/W 1 Clear by H/W to indicate transaction ends with ACK or STALL. If this bit is 0,USB data will be discarded and NAK will be returned. SETUP packets will be written to FIFO even if this bit is not set and ACK will be returned always. This register will be reset by USB reset or S/W reset. Send STALL If set, STALL will be returned to the OUT transaction. 1 SESTALL0 RX S/W is allowed to set or clear this bit. R/W R/W 1 H/W clears this bit when SETUP transaction ends with ACK. H/W sets this bit when STALL is returned to any EP0 transaction. Data Toggle Bit 2 DTOG0RX R/W R 0 Update by H/W to indicate the data toggle bit for current USB transaction. Data Toggle Error 3 DTOGERR 0RX R/W R 0 Set by H/W to indicate toggle error occurs. Cleared when S/W writes a 0 to clear the EP0 RX event interrupt status. ACK Status 4 ACKSTS0RX Description R/W R 0 Set by H/W when a transaction is completed with ACK handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). STALL Status Set by H/W when a transaction is completed with STALL handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). Error Status Set by H/W to indicate either USB PID error, CRC error, bit stuffing error or no data phase from USB host occur. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL) or when SETUPOW (EP0RXTK Register) is set. Clear endpoint Toggle. When S/W writes a 1 to this bit, it will clear the DTOG bit which is in the same register. 5 STALLSTS 0RX R/W R 0 6 ERRSTS0RX R/W R 0 7 CDTOG0RX R/W0C W 0 84 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 9.6.10 Endpoint 0 TX Command/Status Register - EP0TXCSR (0x1D8) Bit Field H/W S/W DF TX Enable Set by S/W to enable tx USB data. USB data Is ready in the FIFO and will be sent to USB bus if the bit "SESTALL" is not set. S/W should write data then byte count the enabled tx. Cleared by H/W in two cases: Indicate IN transaction ends with ACK or STALL. After SETUP transaction ends with ACK. This register will be reset by USB reset or S/W reset. Send STALL If set, STALL will be returned to the IN transaction. 1 SESTALL0T X S/W is allowed to set or clear this bit. R/W R/W 1 H/W clears this bit when SETUP transaction ends with ACK. H/W sets this bit when STALL is returned to any EP0 transaction. Data Toggle Bit 2 3 DTOG0TX Reserved ACK Status 4 ACKSTS0TX R/W R 0 Set by H/W when a transaction is completed with ACK handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). STALL Status 5 STALLSTS 0TX R/W R 0 Set by H/W when a transaction is completed with STALL handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). Error Status 6 ERRSTS0TX Description 0 TXEN0TX R/W0C R/W 0 R/W R 1 Update by H/W to indicate the data toggle bit for current USB transaction. R/W R 0 Set by H/W to indicate either USB PID error, CRC error, bit stuffing error or no data phase from USB host occur. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL) or when SETUPOW (EP0RXTK Register) is set. Clear endpoint Toggle. When S/W writes 1 to this bit will clear the DTOG bit which is in the same register. 7 CDTOG0TX R/W0C W 0 Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 85 EM77F900 USB HUB+BB Controller 9.6.11 Endpoint X Command/Status Register - EP1/2/3CSR (0x1D9 ~ 0x1DB) Endpoint 1 command/status Register (EP1CSR) Endpoint 2 command/status Register (EP2CSR) Endpoint 3 command/status Register (EP3CSR) Bit Field H/W S/W DF Description RX Enable (Bulk Out) Set by S/W to enable rx USB data. USB data will be written to FIFO and ACK will be returned if the bit "SESTALL" is not set. Cleared by H/W to indicate transaction ends with ACK or STALL. If this bit is 0,USB data will be discarded and NAK will be returned. 0 RXTXENX R/W0C R/W 0 TX Enable (Interrupt In / Bulk In) Set by S/W to enable tx USB data. USB data Is ready in the FIFO and will be sent to USB bus if the bit "SESTALL" is not set. S/W should write data then byte count the enable tx. Cleared by H/W when the IN transaction ends with ACK or STALL. If the transaction ends with ACK, the following USB transaction will be returned with NAK if the bit "SESTALL" is not set. The register will be reset by USB reset or S/W reset. Send STALL 1 SESTALLX R/W R/W 1 If set, STALL will be returned for the transaction. S/W is allowed to set or clear this bit. Data Toggle Bit (Interrupt IN / Interrupt OUT / Bulk IN / Bulk OUT ) Update by H/W to indicate the data toggle bit for current USB transaction. Data Toggle Error (Interrupt OUT / Bulk OUT) Reserved (Interrupt In / Bulk In) 3 DTOGERRX 2 DTOGX R/W R 0 R/W R 0 Set by H/W to indicate toggle error occurs. Cleared when S/W writes a 0 which clears the EPn OUT event interrupt status. ACK Status Set by H/W when a transaction is completed with ACK handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). 4 ACKSTSX R/W R 0 86 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Bit Field H/W S/W DF STALL Status Description Set by H/W when a transaction is completed with STALL handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). Error Status Set by H/W to indicate either USB PID error, CRC error, bit stuffing error, time out without handshake response from USB host (for IN transaction) or no data phase from USB host occur (OUT transaction). This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). Clear endpoint Toggle 13 S/W writes 1 to this bit will clear the DTOG bit which in the same register. 5 STALLSTSX R/W R 0 6 ERRSTSX R/W R 0 7 CDTOGX R/W0C W 0 The following table lists the meaning in the EPXCSR for different Endpoint-Type: Bit 0 1 2 3 4 5 6 7 Interrupt IN RXTXEN (TX Enable) SESTALL DTOG Reserved ACKSTS STALLSTS ERRSTS CDTOG Interrupt OUT RXTXEN (RX Enable) SESTALL DTOG DTOGERR ACKSTS STALLSTS ERRSTS CDTOG Bulk IN RXTXEN (TX Enable) SESTALL DTOG Reserved ACKSTS STALLSTS ERRSTS CDTOG Bulk OUT RXTXEN (RX Enable) SESTALL DTOG DTOGERR ACKSTS STALLSTS ERRSTS CDTOG 9.6.12 Endpoint 0 RX Count Register - EP0RXCTR (0x1DC) Bit Field H/W S/W DF RX Byte Count 6-0 EP0RXCT R/W R 0 When receive enable is set to 1, this field specifies the receive byte counts in the receive FIFO. This register will be reset by USB reset or S/W reset. 7 Reserved Description Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 87 EM77F900 USB HUB+BB Controller 9.6.13 Endpoint 0 TX Count Register - EP0TXCTR (0x1DD) Bit Field H/W S/W DF TX Byte Count 6-0 EP0TXCT R R/W 0 When transmit enable is set to 1, this field specifies the transmit byte counts in the transmit FIFO. The H/W always accesses the FIFO from Address 0. This register will be reset by USB reset or S/W reset. 7 Reserved Description 9.6.14 Endpoint X Count Register - EP1/2/3CTR (0x1DE ~ 0x1E0) Endpoint 1 count Register (EP1CTR) Endpoint 2 count Register (EP2CTR) Endpoint 3 count Register (EP3CTR) Bit Field H/W S/W DF Description RX Byte Count (Bulk Out) When receive enable is set to 1, this field specifies the receive byte counts in the receive FIFO. 6-0 EPXCT R/W R/W 0 TX Byte Count (Interrupt In / Bulk In) When transmit enable is set to 1, this field specifies the transmit byte counts in the transmit FIFO. The H/W always accesses the FIFO from Address 0. This register will be reset by USB reset or S/W reset. 7 Reserved 9.6.15 Endpoint 0 RX Data Register - EP0RXDAR (0x1E1) Bit 7-0 Field EP0RX H/W R/W S/W R DF RX Data 0 Receive FIFO data will be read by S/W by reading this register. Description 9.6.16 Endpoint 0 TX Data Register - EP0TXDAR (0x1E2) Bit 7-0 Field EP0TX H/W R S/W W DF TX Data 0 When S/W writes data to this register, it will be written to transmit FIFO. Description 88 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 9.6.17 Endpoint X Data Register - EP1/2/3DAR (0x1E3 ~ 0x1E5) Endpoint 1 Data Register (EP1DAR) Endpoint 2 Data Register (EP2DAR) Endpoint 3 Data Register (EP3DAR) Bit Field H/W S/W DF Description RX Data (Bulk Out) R or W Receive FIFO data will be read by S/W by reading this register. TX Data (Interrupt In / Bulk In) When S/W writes data to this register, it will be written to the transmit FIFO. 7-0 EPXD R/W 0 9.6.18 Hub Global State Register - HGSR (0x1E6) Bit 0 Field OVCM H/W R S/W R/W DF 1 Description Overcurrent Sensing Mode 0=Global overcurrent sensing 1=Individual overcurrent sensing Power switching 1 PWRS/W R R/W 1 0=No Power switching 1=power switching Power switching Mode 2 PWRS/WM R R/W 1 0=Ganged power switching 1=Per port power switching Power Mode 3 PWRM R R/W 1 0=Bus-powered 1=Self-powered 0=Remote Wake-up is disable 1=Remote Wake-up is enable 0 = Not configured or Set configuration zero 1= Set configuration nonzero 4 5 7-6 RMWUPEN R R R/W R/W 1 0 CONFG Reserved Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 89 EM77F900 USB HUB+BB Controller 9.6.19 Hub Interrupt Event Register - HINTR (0x1E7) Bit Field H/W S/W DF Description HUB EP0 USB RX Event Set by H/W when either SETUP transaction ends with ACK or OUT transaction ends with ACK or STALL. It is also set when SETUPOW (HEP0RXTK Register) bit is set. Needs to check HEP0RXCS Register for details. When S/W clears all the OUT, SETUP and SETUPOW bits in HEP0RXTK Register, this bit will be cleared automatically. HUB EP0 USB TX Event Set by H/W when IN transaction ends with ACK or STALL. S/W writes 0 will clear this bit, writes 1 no change. Write by H/W gets higher priority if H/W writes and S/W writes occur at the same time. HUB EP0 USB IN Token Event Set by H/W when a valid IN token is received. 2 HINT0IN R/W R/W0C 0 HINT0RX R/W R 0 1 HINT0TX R/W R/W0C 0 0 S/W writes 0 will clear this bit, writes 1 no change. Write by H/W gets higher priority, if H/W writes and S/W writes occur at the same time. HUB EP1 interrupt Set by H/W when IN transaction ends with ACK or STALL. S/W writes 0 will clear this bit, writes 1 no change. Write by H/W gets higher priority if H/W write and S/W write occur at the same time. 3 HINT1 R/W R/W0C 0 4 5 6 EOF1INT E0F2INT SOFINT R/W R/W R/W R/W0C R/W0C R/W0C 0 0 0 EOF1 interrupt. Asserted 10 clocks before the expected start of a frame. EOF2 interrupt. Asserted 32 clocks before the expected start of a frame. Start of Frame interrupt. Asserted after the receipt of a valid SOF packet Hub and port status change interrupt. Asserted after any status change of both upstream and downstream port. 7 HPSTSCINT R/W R/W0C 0 90 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 9.6.20 Hub Interrupt Event Enable Control Register - HINTE (0x1E8) Bit 0 1 2 3 4 5 6 Field HINT0RXE HINT0TXE HINT0INE HINT1E EOF1INTE E0F2INTE SOFINTE H/W R R R R R R R R S/W R/W R/W R/W R/W R/W R/W R/W R/W DF 0 0 0 0 0 0 0 0 Description HUB EP0 USB RX Event Enable HUB EP0 USB TX Event Enable HUB EP0 USB IN Token Event Enable HUB EP1 interrupt Enable EOF1 interrupt Event Enable EOF2 interrupt Event Enable SOF interrupt Event Enable Port status interrupt Event Enable 7 HPSTSCINTE 9.6.21 Hub Address Register - HAR (0x1E9) Bit 6-0 7 Field HADDR Reserved H/W R S/W R/W DF 0 HUB Address Description 9.6.22 HUB Endpoint 0 RX Token Register - HEP0RXTR (0x1EA) Bit Field H/W S/W DF RX OUT Token 0 HOUT R/W R/W0C Description Set by H/W to indicate OUT token is received and transaction ends with ACK or STALL. When S/W writes a 0, it will clear this bit, when a 1 is written, no change occurs. RX SETUP Token Set by H/W to indicate SETUP token is received and transaction ends with ACK. When S/W writes a 0, it will clear this bit, when a 1 is written, no change occurs. SETUP Overwrite Set by H/W to indicate SETUP token is received when RX FIFO is not empty (no matter it is ended with error or ACK). When S/W writes a 0, it will clear this bit, when a 1 is written, no change occurs. 0 1 HSETUP R/W R/W0C 0 2 HSETUPOW R/W R/W0C 0 7-3 Reserved Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 91 EM77F900 USB HUB+BB Controller 9.6.23 HUB Endpoint 0 Rx Command/Status Register HEP0RXCSR (0x1EB) Bit Field H/W S/W DF Description RX Enable Set by S/W to enable rx USB data. USB data will be written to FIFO and ACK will be returned if the bit "SESTALL" is not set. 0 HRXEN0RX R/W0C R/W 1 Cleared by H/W to indicate that transaction ends with ACK or STALL. If this bit is 0, the USB data will be discarded and NAK will be returned. SETUP packets will be written to FIFO even if this bit is not set and ACK will be returned always. This register will be reset by USB reset or S/W reset. Send STALL If set, STALL will be returned to the OUT transaction. S/W is allowed to set or clear this bit. H/W clears this bit when SETUP transaction ends with ACK. H/W sets this bit when STALL is returned to any EP0 transaction. Data Toggle Bit Updated by H/W to indicate the data toggle bit for current USB transaction. Data Toggle Error Set by H/W to indicate toggle error occur. Cleared by S/W when writing a 0 that clears the EP0 RX event interrupt status. ACK Status Set by H/W when a transaction is completed with ACK handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). STALL Status Set by H/W when a transaction is completed with STALL handshake. his bit will be updated automatically at the next valid transaction (ends with ACK or STALL). Error Status Set by H/W to indicate either USB PID error, CRC error, bit stuffing error or no data phase from USB host occur. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL) or when SETUPOW (EP0RXTK Register) is set. Clear endpoint Toggle. When S/W writes a 1 to this bit, it will clear the DTOG bit which is in the same register. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) 1 HSESTAL L0RX R/W R/W 1 2 HDTOG0RX R/W R 0 3 HDTOGER R/W R0RX R 0 4 HACKSTS 0RX R/W R 0 5 HSTALLS TS0RX R/W R 0 6 HERRSTS 0RX R/W R 0 7 HCDTOG0 R/W0C RX W 0 92 * EM77F900 USB HUB+BB Controller 9.6.24 HUB Endpoint 0 TX Command/Status Register HEP0TXCSR (0x1EC) Bit Field H/W S/W DF TX Enable Set by S/W to enable TX USB data. USB data Is ready in the FIFO and will be sent to USB bus if the bit "SESTALL" is not set. S/W should write data then byte count the enable TX. Cleared by H/W in two cases: (1) Indicate IN transaction ends with ACK or STALL. (2) After SETUP transaction ends with ACK. This register will be reset by USB reset or S/W reset. Send STALL If set, STALL will be returned to the IN transaction. 1 HSESTALL0 TX S/W is allowed to set or clear this bit. R/W R/W 1 H/W clears this bit when SETUP transaction ends with ACK. H/W sets this bit when STALL is returned to any EP0 transaction. Data Toggle Bit 2 3 HDTOG0TX Reserved ACK Status 4 HACKSTS0 TX R/W R 0 Set by H/W when a transaction is completed with ACK handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). STALL Status 5 HSTALLST S0TX R/W R 0 Set by H/W when a transaction is completed with STALL handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). Error Status 6 HERRSTS0 TX R/W R 0 Set by H/W to indicate either USB PID error, CRC error, bit stuffing error or no data phase from USB host occur. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL) or when SETUPOW (EP0RXTK Register) is set. Clear endpoint Toggle. 7 HCDTOG0TX R/W0C Description 0 HTXEN0TX R/W0C R/W 0 R/W R 1 Update by H/W to indicate the data toggle bit for current USB transaction. W 0 S/W writes 1 to this bit will clear the DTOG bit which in the same register. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 93 EM77F900 USB HUB+BB Controller 9.6.25 HUB Endpoint 1 TX Command/Status Register HEP1TXCSR (0x1ED) Bit Field H/W S/W DF TX Enable Set by S/W to enable TX USB data. The USB data is ready in the FIFO and will be sent to USB bus if the bit "SESTALL" is not set. S/W should write data then byte count the enable TX. Cleared by H/W when the IN transaction ends with ACK or STALL. If the transaction ends with ACK, the following USB transaction will be returned with NAK if the bit "SESTALL" is not set. The register will be reset by USB reset or S/W reset. Send STALL If set, STALL will be returned to the OUT transaction. S/W is allowed to set or clear this bit. 1 HSTALL1TX Description 0 HTXEN1TX R/W0C R/W 0 R/W R/W 1 H/W clears this bit when SETUP transaction ends with ACK. H/W sets this bit when STALL is returned to any EP0 transaction. Data Toggle Bit 2 3 HDTOG1TX Reserved R/W R 0 Update by H/W to indicate the data toggle bit for current USB transaction. ACK Status 4 HACKSTS1 TX R/W R 0 Set by H/W when a transaction is completed with ACK handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). STALL Status 5 HSTALLST S1TX R/W R 0 Set by H/W when a transaction is completed with STALL handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). Error Status 6 HERRSTS1 TX R/W R 0 Set by H/W to indicate either USB PID error, CRC error, bit stuffing error or no data phase from USB host occur. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL) or when SETUPOW (EP0RXTK Register) is set. Clear endpoint Toggle. W 0 S/W writes a 1 to this bit to clear the DTOG bit which is in the same register. 7 HCDTOG1 R/W0C TX 94 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 9.6.26 HUB Endpoint 0 RX Count Register - HEP0RXCTR (0x1EE) Bit Field H/W S/W DF RX Byte Count 3-0 HEP0RXC R/W R 0 When receive enable is set to 1, this field specifies the receive byte counts in the receive FIFO. This register will be reset by USB reset or S/W reset. 7-4 Reserved Description 9.6.27 HUB Endpoint 0 TX count Register - HEP0TXCTR (0x1EF) Bit Field H/W S/W DF TX Byte Count 3-0 HEP0TXC R R/W 0 When transmit enable is set to 1, this field specifies the transmit byte counts in the transmit FIFO. H/W always accesses the FIFO from Address 0. This register will be reset by USB reset or S/W reset. 7-4 Reserved Description 9.6.28 HUB Endpoint 0 RX Data Register - HEP0RXDAR (0x1F0) Bit 7-0 Field DATA H/W R/W S/W R DF RX Data 0 Receive FIFO data will be read by S/W by reading this register. Description 9.6.29 HUB Endpoint 0 TX Data Register - HEP0TXDAR (0x1F1) Bit 7-0 Field DATA H/W R S/W W DF TX Data 0 When S/W writes data to this register, it will be written to transmit FIFO. Description 9.6.30 HUB Endpoint 1 TX Data Register - HEP1TXDAR (0x1F2) Bit 0 1 2 3 4 7-5 Field HSTSC HSTSCP1 HSTSCP2 HSTSCP3 HSTSCP4 Reserved H/W R R R R R S/W W W W W W DF 0 0 0 0 0 Hub Status Change Port 1 Status Change Port 2 Status Change Port 3 Status Change Port 4 Status Change Description Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 95 EM77F900 USB HUB+BB Controller 9.6.31 HUB Port Control Register - HPCONR (0x1F3) Bit Field H/W S/W DF HUB Port Address. These bit defines which port is being addressed for the command defined by HPCON. 2-0 HPADDR R R/W 0 Bit 2 Bit 1 Bit 0 Port Addressed 0 0 1 Port 1 0 1 0 Port 2 0 1 1 Port 3 1 0 0 Port 4 Encoded HUB Port Control Command. These bits are set and cleared by firmware upon receipt of a Host request. Bit 5 Bit 4 Bit 3 Action 0 0 0 SetPortFeature (PORT_SUSPEND) 5-3 HPCON R R/W 0 0 0 1 SetPortFeature (PORT_RESET) 0 1 0 SetPortFeature (PORT_POWER) 0 1 1 ClearPortFeature (PORT_ENABLE) 1 0 0 ClearPortFeature (PORT_SUSPEND) 1 0 1 ClearPortFeature (PORT_POWER) 1 1 0 Unused 1 1 1 Unused 6 Reserved Hub Port Command Valid 7 CMDVLD R/WOC W 0 It is set by the S/W when any port command is received from the host. It is cleared by the H/W. Description 96 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 9.6.32 HUB Port State Register - HPSTAR (0x1F4) Bit 0 Field DMSTATE1 H/W R/W S/W R DF 0 Description HUB Port 1 DM state: Embedded function Value of DM at last EOF. Set and cleared by hardware at EOF2. HUB Port 1 DP state: Embedded function Value of DP at last EOF. Set and cleared by hardware at EOF2. HUB Port 2 DM state: Downstream Port 1 2 DMSTATE2 R/W R 0 Value of DM at last EOF. Set and cleared by hardware at EOF2. HUB Port 2 DP state: Downstream Port 1 Value of DP at last EOF. Set and cleared by hardware at EOF2. 4 DMSTATE3 R/W R 0 HUB Port 3 DM state: Downstream Port 2 Value of DM at last EOF. Set and cleared by hardware at EOF2. 5 DPSTATE3 R/W R 0 HUB Port 3 DP state: Downstream port 2 Value of DP at last EOF. Set and cleared by hardware at EOF2. HUB Port 4 DM state: Downstram Port 3 Value of DM at last EOF. Set and cleared by hardware at EOF2. 7 DPSTATE4 R/W R 0 HUB Port 4 DP state: Downstream Port 3 Value of DP at last EOF. Set and cleared by hardware at EOF2. 1 DPSTATE1 R/W R 0 3 DPSTATE2 R/W R 0 6 DMSTATE4 R/W R 0 9.6.33 Hub Status Register - HSR (0x1F5) Bit 0 Field LPS H/W R/W S/W R DF 0 Description Hub Local Power Status 0=Local Power supply is good 1=Local Power supply is lost (inactive) 1 OVI R/W R 0 Overcurrent Indicator 0=No overcurrent condition exist 1=An overcurrent condition exist Hub Local Power Status Change 0=No change has occurred on the Local Power Status 1=Local Power Status has changed Overcurrent Indicator Change 3 OVIC R/W R/W0C 0 0=No change has occurred on the overcurrent Indicator 1=Overcurrent Indicator has changed 7-4 Reserved 2 LPSC R/W R/W0C 0 Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 97 EM77F900 USB HUB+BB Controller 9.6.34 Hub Port X Status Register - HPSR1/2/3/4 (0x1F6 ~ 0x1F9) Hub Port 1 Status Register (HPSR1) Hub Port 2 Status Register (HPSR2) Hub Port 3 Status Register (HPSR3) Hub Port 4 Status Register (HPSR4) Bit 0 Field PCSTSX H/W R/W S/W R DF 0 Description Port Connect Status 0=No device is present 1=A device is present on this port Port Enable Status 1 PENSTSX R/W R 0 0=Port is Disable 1=Port is enable Port Suspend Status 2 PSUSSTSX R/W R 0 0=Port not suspended 1=Port suspended Port Overcurrent Indicator 3 POCIX R/W R 0 0=All no overcurrent condition exists on this port 1=An overcurrent condition exists on this port Port Reset Status 4 PRTSTSX R/W R 0 0=Reset signaling not asserted 1=Reset signaling asserted. Port Power Status 5 PPWRSTSX R/W R 0 0=Port is powered OFF 1=Port is powered ON Low-Speed Device Attached 6 7 LSDAX Reserved R/W R 0 0=Full-speed device attached to this port 1=Low-speed device attached to this port 98 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 9.6.35 Hub Port X Status Change Register - HPSCR1/2/3/4 (0x1FA ~ 0x1FD) Hub Port 1 Status Change Register (HPSCR1) Hub Port 2 Status Change Register (HPSCR2) Hub Port 3 Status Change Register (HPSCR3) Hub Port 4 Status Change Register (HPSCR4) Bit 0 Field PCSTSCX H/W S/W DF 0 Description Port Connect Status Change R/W R/W0C 0=No change has occurred 1=Current Connect status has changed Port Enable Status Change 1 PENSTSCX R/W R/W0C 0 0=No change has occurred 1=Port Disabled due to port error. Port Suspend Status Change 2 PSUSSTSCX R/W R/W0C 0 0=No change has occurred 1=Resume complete Port Overcurrent Indicator Change 3 POCICX R/W R/W0C 0 0=No change has occurred 1=Port Overcurrent Indicator has changed Port Reset Status Change 4 7-5 PRTSTSCX R/W R/W0C Reserved 0 0=No change has occurred 1=Reset complete 9.6.36 Frame Number Low-Byte Register - FNLR (0x1FE) Bit 7-0 Field FNLR H/W R/W S/W R DF 0 Description Bits 0~7 of Frame Number (11 bits) 9.6.37 Frame Number High-Byte Register - FNHR (0x1FF) Bit 2-0 7-3 Field FNHR Reserved H/W R/W S/W R DF 0 Description Bits 8~10 of Frame Number (11 bits) Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 99 EM77F900 USB HUB+BB Controller 10 Direction Serial Peripheral Interface (SPI) 10.1 Introduction The EM77F900 communicates with other devices via SPI (Direction Serial Peripheral Interface) module, as shown in Fig. 10-1. To accomplish communication, SPI uses three wire synchronous protocols: Serial Clock, Serial Data Output, and Serial Data. If the EM77F900 is a master controller, it sends clock through the SCK pin. An 8-bit data is transmitted and received at the same time. If the EM77F900, however, is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted on a basis of both the clock rate and the selected edge. 10.2 Features 3-wire, full duplex synchronous transceiver Operation in either Master mode or Slave mode Programmable baud rates of communication Programming clock polarity Programmable data transmission order Interrupt flag available for read buffer full Up to 8 MHz (maximum) bit frequency 10.3 Block Diagram SDI SDO SCK Clock Generator SCK Clock Generator Shift Register (SPIS) SDO SDI Shift Register (SPIS) Read Buffer (SPIRB) SPI Master Write Buffer (SPIWB) Write Buffer (SPIWB) Read Buffer (SPIRB) SPI Slave Fig. 10-1 Typical SPI Transceiver Mode 100 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 10.4 Transceiver Timing SPIE SCK CES = 1 SCK CES = 0 SDO SDOD = 0 SDO SDOD = 1 SDI SDID = 0 SDI SDID = 1 RBF Fig. 10-2 SPI Transceiver Timing Diagram Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 10.5 SPI Related Registers As the SPI mode is defined, the related registers of this operation are shown below: SPIRB (0x1D): Serial Peripheral Interface Read Register SPIWB (0x1E): Serial Peripheral Interface Write Register INTF (0X11): Interrupt flag Bit 7 ADIF Bit 6 RBFIF Bit 5 PWM1IF Bit 4 PWM0IF Bit 3 EINT1F Bit 2 EINT0F Bit 1 TCCOF Bit 0 FRCOF PRIE (0x80): Peripherals Enable Control Bit 7 SPIE Bit 6 USBE Bit 5 BBE Bit 4 ADE Bit 3 PWM1E Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE INTE (0X81): Interrupt Enable Control Bit 7 GIE Bit 6 RBFIE Bit 5 PWM1IE Bit 4 PWM0IE Bit 3 EINT1E Bit 2 EINT0E Bit 1 TCCOE Bit 0 FRCOE SPIC (0X85): SPI Control Bit 7 SPI_RBF Bit 6 CES Bit 5 SBR2 Bit 4 SBR1 Bit 3 SBR0 Bit 2 SDID Bit 1 SDOD Bit 0 SPIS Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 101 EM77F900 USB HUB+BB Controller 10.6 Function Description 10.6.1 Block Diagram Description The following subsections describe the function of each blocks and signals. Fig. 10.2 depicts how the SPI communication is carried out. SDI: Serial Data In SCK: Serial clock SDO: Serial Data Out RBFIF: Set by Buffer Full Detector, and reset in software. SPIS: Loads the data in SPIWB register, and begin to shift Shift reg.: Shifting byte out and in. The order is defined by bit SDOD. Both the Shift register and the SPIWB registers are loaded at the same time. Once data are written to, the SPIS starts transmission/reception. The received data will be moved to the SPIRB register, as the shifting of the 8-bit data is completed. The RBFIF (Read Buffer Full) flag is equal to 1. SPIRB: Read buffer. The buffer will be updated, as the 8-bit shifting is completed. The data must be read before the next reception is finished. The RBF flag is cleared as the SPIRB register is read. SPIWB: Write buffer. The buffer will deny any write until the 8-bit shifting is completed. The SPIS bit will be kept in 1 if the communication is still undergoing. This flag must be cleared as the shifting is finished. Users can determine if the next write attempt is available. SBR2~SBR0: Programming the clock frequency/rates and sources. Edge Select: Selecting the appropriate clock edges by programming the CES bit. 10.6.2 Signal & Pin Description The three pins, SDI, SDO, and SCK, which are shown in Fig. 10.1, are explained in details as follows: SDI: Serial Data In Receive serially Defined as high-impedance, if not selected. Programmed the same clock rate and the same clock edge to latch on both the master device and slave device. The received byte will replace the corresponding transmitted byte. 102 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller The RBFIF bit will be set, as the SPI operation is complete. Timing is shown in Fig. 10-2. SCK: Serial Clock. Generated by a master device. Synchronize the data communication on both the SDI pin and the SDO pin. The CES used to select the edge to communicate. The SBR0~SBR2 used to determine the baud rate of communication. The ES, SBR0, SBR1, and SBR2 bit have no effect in the slave mode. Timing is shown in Fig. 10-2 SDO: Serial Data Out. Transmit serially. Programmed the same clock rate and the same clock edge to latch on both the master device and slave device. The received byte will replace the transmitted byte. The SPIS bit will be reset, as the SPI operation is completed. Timing is shown in Fig. 10-2. 11 Analog-to-Digital Converter (ADC) The analog-to-digital circuitry consists of one 16-to-1 multiplexer, two control registers (ADCIPC and ADCC), two data registers (HADCD and LADCD) and one ADC calculator with 10-bit resolution. The ADC functional block diagram is shown in Fig. 11-1. Port D [7:0] and Port E [7:0] can be selected as either normal digital I/O ports or analog input ports. A maximum of twelve analog input pins can be selected by the ADCIPC register [3:0], ADCPS3 ~ADCPS0 bits. Control bits, ADCIS3 ~ ADCIS0, of ADCIPC [7:4] are then used to select the ADC input channel that will supply analog signal to the ADC calculator. CK2 ~ CK0 control bits are used to select the desired conversion rate. The ADC module, then, utilizes successive approximation to convert the unknown analog signal into a 10-bit digital output value. Finally, the 10-bit result is fed to the HADCD and LADCD registers. If the ADC interrupt is enabled, ADC interrupt flag will be set to "1" as the analog-to-digital conversion is completed. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 103 EM77F900 USB HUB+BB Controller ADCF ADCE ADCD ADCC ADCB ADCA ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 Fsco 8-1 MUX Power Down 5 4 3 IMS[0:2] 3 2 1 0 AIPS[0:3] 2 1 0 7 7 ADIF DATA BUS 6 5 4 3 2 1 0 7 6 ADRUN 7 4 ADE 16 -1 Analog Switch Vref ADC ( successive approximation ) Start to Convert CKR[0:2] ADDATAH ADDATAL Fig 11-1 Analog-to-Digital Conversion Functional Block Diagram 11.1 ADC Control Registers As the ADC mode is defined, the related registers of this operation are shown below: INTF (0X11): Interrupt Flag Bit 7 ADIF Bit 6 RBFIF Bit 5 PWM1IF Bit 4 PWM0IF Bit 3 EINT1F Bit 2 EINT0F Bit 1 TCCOF Bit 0 FRCOF ADDATAH (0x1F): ADC 10-bit data Bit 7 ADD9 Bit 6 ADD8 Bit 5 ADD7 Bit 4 ADD6 Bit 3 ADD5 Bit 2 ADD4 Bit 1 ADD3 Bit 0 ADD2 ADDATAL (0x20): ADC 10-bit Data Bit 7 ADD1 Bit 6 ADD0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - When the A/D conversion is completed, Bit 9 ~ Bit 2 are loaded to the ADDATAH [7:0] and Bit 1 and Bit 0 are loaded to ADDATAL [7:6]. The ADCRUN bit is cleared, and the ADIF is set. PRIE (0x80): Peripherals Enable Control Bit 7 SPIE Bit 6 USBE Bit 5 BBE Bit 4 ADE Bit 3 PWM1E Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE 104 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller ADCAIS (0x96): ADC analog input pin select and conversion rate select Bit 7 Bit 6 Bit 5 IMS2 Bit 4 IMS1 Bit 3 IMS0 Bit 2 CKR2 Bit 1 CKR1 Bit 0 CKR0 IMS2~IMS0 (Bit 2 ~ Bit 4): ADC Configuration Definition Bit IMS PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 000 001 010 011 100 101 110 111 ADC A A A A A A A A F A A A A A A A A E D A A A A A A A D D A A A A A A A C D D A A A A A A B D D A A A A A A A D D D A A A A A 9 D D D A A A A A 8 D D D D A A A A 7 D D D D A A A A 6 D D D D D A A A 5 D D D D D A A A 4 D D D D D D A A 3 D D D D D D A A 2 D D D D D D D A 1 D D D D D D D A 0 CKR2~CKR0 (Bit 2 ~ Bit 0): AD conversion Rate Control Bits CKR2: CKR1: Divided Rate CKR0 000 001 010 011 100 101 110 111 /2 /4 /8 / 16 / 32 / 64 / 128 / 256 A/D Conversion Rate Unit: kHz 6MHz 12MHz 24MHz 48MHz Clock Source Clock Source Clock Source Clock Source 250 125 62.5 31.3 15.6 7.8 3.9 2.0 500 250 125 62.5 31.3 15.6 7.8 3.9 1000 500 250 125 62.5 31.3 15.6 7.8 2000 1000 500 250 125 62.5 31.3 15.6 ADCCR (0x97): ADC Configuration Register Bit 7 ADRUN Bit 6 ADIE Bit 5 Bit 4 Bit 3 AIPS3 Bit 2 SIPA2 Bit 1 AIPS1 Bit 0 AIPS0 AIPS0~AIPS3 (Bits 0~3): Analog Input Select 0000 = ADC0; 0001 = ADC1; 0010 = ADC2; 0011 = ADC3; 0100 = ADC4; 0101 = ADC5; 0110 = ADC6; 0111 = ADC7; 1000 = ADC8; 1001 = ADC9; 1010 = ADCA;1011 = ADCB; 1100 = ADCC; 1101 = ADCD; 1110 = ADCE; 1111 = ADCF; They only can be changed when the ADIF bit and the ADRUN bit are both LOW. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 105 EM77F900 USB HUB+BB Controller ADIE (Bit 6): ADC interrupt enable ADRUN (Bit 7): ADC starts to RUN 0 = reset on conversion completion; this bit cannot be reset by software. 1 = an A/D conversion is started; this bit can be set by software. 11.2 Programming Steps/Considerations Follow these steps to obtain data from the ADC: 1. 2. Set the ADC function power on (PRIE.ADE). Write to the three bits (IMS2:IMS0) on the ADCCR register to define the characteristics of PD and PF: Digital I/O, analog channels, and voltage reference pin. 3. Write to the ADCAIS register to configure the ADC module. i Select the ADC input channel (AIPS3: AIPS0) ii Define the ADC conversion clock rate (CKR2: CKR1: CKR0) 4. 5. 6. 7. 8. 9. Set the ADC interrupt enable (ADCCR.ADIE). Include "ENI" instruction, if the interrupt function is employed. Set the ADRUN bit to 1 to begin sampling. Wait for either the interrupt flag to be set or the ADC interrupt to occur. Read the conversion data register ADDATAH & ADDATAL. Clear the interrupt flag bit (INTF.ADIF). For the next conversion, go to Step 2 or Step 3 as required. At least 2Tct is required before the next acquisition starts. NOTE To obtain an accurate value, it is necessary to avoid any data transition on the I/O pins during AD conversion. 106 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 12 Dual Pulse Width Modulations (PWM0 and PWM1) 12.1 Overview The EM77F900 has two built-in PWM outputs with 16-bit resolution. Fig.12-1 shows the functional block diagram. A PWM output has a period and a duty cycle, and it keeps the output high. The baud rate of the PWM is the inverse of the period. Fig. 12-2 depicts the relationships between a period and a duty cycle. PWM0IF DT0H DT0L DT1H DT1L PWM1IF DL0H DL0L DL1H DL1L Set as compare match PWM0E Duty Compare Circuit PWM0IE PWM1IE Duty Compare Circuit Set as compa re match PWM1E PWM0 Q R Data Bus R Q PWM1 S TMR0HB TMR0LB TMR1HB TMR1LB S Set as compare match Period Compare Circuit Period Compare Circuit Set as compare match MUX PRD0H PRD0L PRD1H PRD1L MUX PWM0E Fosc/2 PWM1E Fosc/2 Fig. 11-1 Functional Block Diagram of the Dual PWM Period Period Period Duty DUTY = TMR Duty PRD= TMR Duty Fig. 11-2 PWM Output Timing Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 107 EM77F900 USB HUB+BB Controller 12.2 PWM Control Registers As the PWM mode is defined, the related registers of this operation are shown below: INTF (0x11): Interrupt flag Bit 7 ADIF Bit 6 RBFIF Bit 5 PWM1IF Bit 4 PWM0IF Bit 3 EINT1F Bit 2 EINT0F Bit 1 TCCOF Bit 0 FRCOF DT0L (0x21): Duty of PWM0 low byte Bit 7 DT07 Bit 6 DT06 Bit 5 DT05 Bit 4 DT04 Bit 3 DT03 Bit 2 DT02 Bit 1 DT01 Bit 0 DT00 DT0H (0x22): Duty of PWM0 high byte Bit 7 DT0F Bit 6 DT0E Bit 5 DT0D Bit 4 DT0C Bit 3 DT0B Bit 2 DT0A Bit 1 DT09 Bit 0 DT08 DL0L (0x25): Duty latch of PWM0 low byte Bit 7 DL07 Bit 6 DL06 Bit 5 DL05 Bit 4 DL04 Bit 3 DL03 Bit 2 DL02 Bit 1 DL01 Bit 0 DL00 DL0H (0x26): Duty latch of PWM0 high byte Bit 7 DL0F Bit 6 DL0E Bit 5 DL0D Bit 4 DL0C Bit 3 DL0B Bit 2 DL0A Bit 1 DL09 Bit 0 DL08 DT1L (0x27): Duty of PWM1 low byte Bit 7 DT17 Bit 6 DT16 Bit 5 DT15 Bit 4 DT14 Bit 3 DT13 Bit 2 DT12 Bit 1 DT11 Bit 0 DT10 DT1H (0x28): Duty of PWM1 high byte Bit 7 DT1F Bit 6 DT1E Bit 5 DT1D Bit 4 DT1C Bit 3 DT1B Bit 2 DT1A Bit 1 DT19 Bit 0 DT18 DL1L (0x2B): Duty latch of PWM1low byte Bit 7 DL17 Bit 6 DL16 Bit 5 DL15 Bit 4 DL14 Bit 3 DL13 Bit 2 DL12 Bit 1 DL11 Bit 0 DL10 DL2H (0x2C): Duty latch of PWM1 high byte Bit 7 DL1F Bit 6 DL1E Bit 5 DL1D Bit 4 DL1C Bit 3 DL1B Bit 2 DL1A Bit 1 DL19 Bit 0 DL18 The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared. DTX can be loaded at any time. However, it cannot be latched into DLX until the current value of DLX is equal to TMRX. 108 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller The following formula describes how to calculate the PWM duty cycle: Duty Cycle = (DTX+1) * (2/Fosc) PRD0L (0x23): Period of PWM0 low byte Bit 7 PRD07 Bit 6 PRD06 Bit 5 PRD05 Bit 4 PRD04 Bit 3 PRD03 Bit 2 PRD02 Bit 1 PRD01 Bit 0 PRD00 PRD0H (0x24): Period of PWM0 high byte Bit 7 PRD0F Bit 6 PRD0E Bit 5 PRD0D Bit 4 PRD0C Bit 3 PRD0B Bit 2 PRD0A Bit 1 PRD09 Bit 0 PRD08 PRD1L (0x29): Period of PWM1 low byte Bit 7 PRD17 Bit 6 PRD16 Bit 5 PRD15 Bit 4 PRD14 Bit 3 PRD13 Bit 2 PRD12 Bit 1 PRD11 Bit 0 PRD10 PRD1H (0x2A): Period of PWM1 high byte Bit 7 PRD1F Bit 6 PRD1E Bit 5 PRD1D Bit 4 PRD1C Bit 3 PRD1B Bit 2 PRD1A Bit 1 PRD19 Bit 0 PRD18 The PWM period is defined by writing to PRDX. When TMRX is equal to PRDX, the following events occur on the next increment cycle: TMRX is cleared. The PWMX pin is set to 1. The PWMX duty cycle is latched from DTPS to DUTY. NOTE The PWMX will not be set, if the duty cycle is 0. The PWMXIF pin is set to 1. The following formula describes how to calculate the PWM period: Period = (PRD +2) * (2/Fsco) The PWM function must be disabled before a new period is executed. In other words, bit PWMXE has to be reset in advance, if the contents of PRDX are reloaded. PRIE (0x80): Peripherals enable control Bit 7 SPIE Bit 6 USBE Bit 5 BBE Bit 4 ADE Bit 3 PWM1E Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE INTE (0x81): Interrupt enable control Bit 7 GIE Bit 6 RBFIE Bit 5 PWM1IE Bit 4 PWM0IE Bit 3 EINT1E Bit 2 EINT0E Bit 1 TCCOE Bit 0 FRCOE PWMCR (0x98): PWM control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 S_PWM1 Bit 2 S_PWM0 Bit 1 Bit 0 * 109 Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 12.3 PWM Programming Procedures/Steps (1) Load PRDX with the PWMX period. (2) Load DTX with the PWMX Duty Cycle. (3) Enable the interrupt function by setting PWMXIE in the INTE register, if required. (4) Set the PWM pin as output by setting PWMCR.S_PWMX. (5) Enable the PWM function by setting PWMXE bit in the PRIE register. (6) Write the desired new duty to DTX before TMRX is equal to PRDX, then this new DTX will be latched into DLX if various duty cycle is required for the next PWMX operation. (7) Clear PWMXE bit and write the desired new period to PRDX, then enable it again if various periods are required for the next PWMX operation. (8) Clear the PWMXIF before the next operation if interrupt PWMXIE is employed. 13 Interrupts 13.1 Introduction The EM77F900 has 20 interrupt sources. By priority, these interrupts are classified into three levels, namely; peripherals, wireless modem, and USB, as described in the following texts: The interrupt status registers record the interrupt requests in the corresponding control bits in the interrupt control registers. The global interrupt (GIE) is enabled by the ENI instruction and is disabled by the DISI instruction. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive interrupts. The flags in the Interrupt Status Register are set regardless of the status of their corresponding mask bits or the execution of DISI. Note that the logic AND of an interrupt flag and its corresponding interrupt control bit is 1 which makes the program counter point to the right interrupt vector. Refer to Fig. 13-1. The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of ENI). Before the interrupt subroutine is executed, the contents of ACC, SR, RAMBS0 and ROMPS will be saved by the hardware. After the interrupt service routine is finished, ACC, SR, RAMBS0 and ROMPS will be pushed back. 110 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller In EM77F900, individual interrupt sources have their own interrupt vectors, depicted in the following table: No Mnemonic Mask KWUAE KWUBE EINT0E EINT1E Status KWUAIF KWUBIF EINT0F EINT1F FRCOF TCCOF RBFIF ADCIF PWM0IF PWM1IF CSDF TX_AEF RX_AFF TX_EMPTYF RX_OFF LINK_DIS Priority Vector Function Mask Status Register Bit Register Bit 0x82 0x83 0x81 0x81 0x81 0x81 0x80 0x81 0x99 0x99 0x99 0x99 0x99 0x99 0x99 0x99 0x1D2 0x1D2 0x1D2 0x1D2 0x1D2 0x1D2 3~0 All 2 3 0 1 6 4 4 5 7 6 5 4 3 2 1 0 0 1 2 3 4 5 0x12 013 0x11 0x11 0x11 0x11 0x11 0x11 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x1D1 0x1D1 0x1D1 0x1D1 0x1D1 0x1D1 3~0 All 2 3 0 1 6 7 4 5 7 6 5 4 3 2 1 0 0 1 2 3 4 5 1 2 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 3 3 3 0x10 Key Wake Up 0x18 External Interrupt 0x20 FRC Overflow 0x28 TCC Overflow 0x30 SPI Read Buffer Full 3 FRCOE 4 TCCOE 5 RBFIE 6 ADCIE 7 PWM0IE PWM1IE 0x38 ADC complete 0x40 0x48 0x50 0x58 PWM period complete Carrier sense interrupt TX FIFO almost empty RX FIFO almost full 8 CSDE 9 TX_AEE 10 RX_AFE 11 TX_EMPTY 12 RX_OFE 13 LINK_DIS 0x60 TX FIFO empty 0x68 RX FIFO overflow 0x70 LINK_DIS interrupt 14 LOCK_OUTE LOCK_OUTF 15 LOCK_INE 16 INT0RXE 16 INT0TXE 16 INT0INE 17 INT1E 17 INT2E 17 INT3E LOCK_INF INT0RXF INT0TXF INT0INF INT1F INT2F INT3F 0x78 Lock out interrupt 0x80 Lock in interrupt EP0 USB RX Event 0x88 EP0 USB TX Event EP0 USB IN Token Event EP1 Interrupt 0x90 EP2 Interrupt EP3 Interrupt Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 111 EM77F900 USB HUB+BB Controller No Mnemonic Mask Status RSTINTF Priority Vector Function USB Bus Reset Event Detect USB Bus Suspend Event Detect Mask Status Register Bit Register Bit 0x1D4 0 0x1D3 0 18 RSTINTE 3 18 IDLEINTE IDLEINTF 3 0x1D4 1 0x1D3 1 18 RUEINTE RUEINTF 3 0x98 USB Bus Resume Event Detect 0x1D4 2 0x1D3 2 18 FRWPINTE FRWPINTF 3 Function Remote 0x1D4 Wake-Up Interrupt Hub EP0 USB RX 0x1E8 Event Hub EP0 USB TX 0x1E8 Event Hub EP0 USB IN Token Event Hub EP1 Interrupt EOF1 Interrupt EOF2 Interrupt Start Of Frame 0XA8 Interrupt Hub and Port Status Change Interrupt 0x1E8 0x1E8 0x1E8 0x1E8 0x1E8 3 0x1D3 3 19 HINT0RXE 19 HINT0TXE 19 HINT0INE 19 HINT1E 20 EOF1INTE 20 EOF2INTE 20 SOFINTE HINT0RXF HINT0TXF HINT0INF HINT1F EOF1INTF EOF2INTF SOFINTF 3 3 0xA0 3 3 3 3 3 0 1 2 3 4 5 6 0x1E7 0x1E7 0x1E7 0x1E7 0x1E7 0x1E7 0x1E7 0 1 2 3 4 5 6 20 HPSTSCINTE HPSTSCINTF 3 0x1E8 7 0x1E7 7 The interrupt priority is another useful feature provided by this IC. The latest interrupt, which has the highest priority than the others, will override and hold the currently executed interrupt until the interrupt is finished. Otherwise, the latest interrupt will be in queue right after its all peers. Global INT Enable Function INT Enable Function INT Flag Function INT Condition Happened Function Enable Fig. 13-1 Block Diagram of Interrupts 112 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 14 Circuitry of Input and Output Pins 14.1 Introduction The EM77F900 has six parallel ports, namely, Port A, Port B, Port C, Port D, Port E and Port F which only four least significant bits are available. That is, there are 42 available I/O pins. A control bit defines the configuration of its corresponding pin. Refer to Fig. 3.1 for the Pin Assignment. The I/O registers, from Port A to Port F, are bidirectional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the I/O control registers (IOCA, IOCB, IOCD, IOCE and IOCF) under program control. The I/O registers and I/O control registers are both readable and writable. Note that the source is different between the reading path of input and output pin while reading the I/O port. 15 Timer/Counter System 15.1 Introduction The EM77F900 provides two timer modules: 8-bit TCC (Time Clock/Counter), and 16-bit FRC (Free Run Counter). The clock sources of TCC come from one of the instruction cycle and low frequency oscillator (ERC). The clock source of FRC is from either instruction cycle or low frequency oscillator (ERC). 15.2 Time Clock Counter (TCC) An 8-bit counter is available as prescaler for the TCC. The prescaler ratio is determined by the PS0~PS2 bits. When in TCC mode, the prescaler is cleared each time an instruction writes to the TCC. TCC is an 8-bit timer/counter. If the TCC signal source is from the system clock, TCC will be incremented by 1 in every instruction cycle (without prescaler). If the TCC signal source is from the ERC clock input, TCC will be incremented by 1 on every falling edge or rising edge of the TCC pin. The prescaler counter (PRC) can be read from Address 0x0F. In the other words, the combination of TCC and PRC can be used as a 16-bit counter without prescaler. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 113 EM77F900 USB HUB+BB Controller 15.2.1 Block Diagram of TCC TCCS0 TCCE Data Bus Fosc 0 M U X PRC (8- bit Counter) Sync with Internal Clock 2 clocks delay TCCOF TCC ERC 1 PS0 PS1 PS2 8-1 MUX Fig. 14-1 Function Block Diagram of TCC 15.2.2 TCC Control Registers As the TCC mode is defined, the related registers involved in this operation are shown below: PRC (0x0F): Prescaler counter TCC (0x10): Timer clock/counter INTF (0x11): Interrupt flag. Bit 7 ADIF Bit 6 RBFIF Bit 5 PWM1IF Bit 4 PWM0IF Bit 3 EINT1F Bit 2 EINT0F Bit 1 TCCOF Bit 0 FRCOF PRIE (0x80): Peripherals enable control Bit 7 SPIE Bit 6 USBE Bit 5 BBE Bit 4 ADE Bit 3 PWM1E Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE INTE (0x81): Interrupt enable control Bit 7 GIE Bit 6 RBFIE Bit 5 PWM1IE Bit 4 PWM0IE Bit 3 EINT1E Bit 2 EINT0E Bit 1 TCCOE Bit 0 FRCOE TCCC (0x93): Timer clock/counter control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TCCS0 Bit 2 PS2 Bit 1 PS1 Bit 0 PS0 114 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 15.2.3 TCC Programming Procedures/Steps (1) Load TCCC with the prescaler and TCC clock source. (2) Load TCC with the TCC overflow period. (3) Enable the interrupt function by setting TCCOE in the INTE register, if required. (4) Enable the TCC function by setting the TCCE bit in the PRIE register. (5) Wait for either the interrupt flag to be set (TCCOF) or the TCC interrupt to occur. (6) The following formula describes how to calculate the TCC overflow period: 1 TCCTimer = (0 x 100 - TCC ) x Pr escaler ClockSource where Clock Source = Fosc or ERC 15.3 Free Run Counter Dual 8-bit counters, high byte register and low byte register, make up the 16-bit software programmable counter. The driving clock source is either the system clock divided by 2 or the low frequency oscillator. A read of the low byte register allows full control of the corresponding timer function. On the contrary, accessing a high byte register will inhibit the specific timer function until the corresponding low byte is read as well. 15.3.1 Block Diagram of FRC FRCE FRCCS Fosc 0 M U X Sync with Internal Clock L FRF HFRC FRCOF ERC 1 L FRFB Data Bus Fig. 14-2 Function Block Diagram of Timer 1 Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 115 EM77F900 USB HUB+BB Controller 15.3.2 FRC Control Registers As the FRC mode is defined, the related registers of this operation are shown below: INTF (0x11): Interrupt flag. Bit 7 ADIF Bit 6 RBFIF Bit 5 PWM1IF Bit 4 PWM0IF Bit 3 EINT1F Bit 2 EINT0F Bit 1 TCCOF Bit 0 FRCOF LFRC (0x1A): Least significant byte of 16-bit free run counter. HFRC (0x1B): Most significant byte of 16-bit free run counter. LFRCB (0x1C): Least significant byte buffer of 16-bit free run counter. PRIE (0x80): Peripherals enable control Bit 7 SPIE Bit 6 USBE Bit 5 BBE Bit 4 ADE Bit 3 PWM1E Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE INTE (0x81): Interrupt enable control Bit 7 GIE Bit 6 RBFIE Bit 5 PWM1IE Bit 4 PWM0IE Bit 3 EINT1E Bit 2 EINT0E Bit 1 TCCOE Bit 0 FRCOE FRCC (0x94): Free run counter control. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FRCCS 15.3.3 FRC Programming Procedures/Steps (1) Load LFRCB with the FRC overflow period low byte. (2) Load HFRC with the TCC overflow period high byte. Then LFRC will load with the LFRCB automatically. (3) Enable interrupt function by setting FRCOE in the INTE register, if required. (4) Enable FRC function by set FRCE bit in the PRIE register. (5) Wait for either the interrupt flag to be set (FRCOF) or the FRC interrupt to occur. (6) An access of low byte of a 16-bit counter receives the count value at the moment of the read. However, the contents of low byte will transfer to the buffer, the LFRCB register, if a high byte is read first. The value in the LFRCB register remains unchanged until the corresponding low byte is read. (7) The following formula describes how to calculate the FRC overflow period: 1 FRCTimer = (0 x 100 - HFRC : LFRC )x ClockSource where Clock Source = Fosc or ERC 116 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 16 Reset and Wake Up 16.1 Reset The reset can be caused by one of the following: (1) Power-on reset (2) /RESET pin input "low", or (3) Watchdog timer time-out (if enabled) The device will remain in a reset condition for a period of 10-bit external RC ripple counter (one oscillator start-up timer period) after the reset is detected. The initial Address is 000h. 16.2 The Status of RST, T, and P of the STATUS Register A reset condition can be caused by the following events: (1) A power-on condition (external); (2) A high-low-high pulse on the /RESET pin (external); and (3) Watchdog timer time-out (internal). The values of bits RST, T and P, listed in Table 17.1 can be used to check how the processor wakes up. Condition Power on WDTC instruction WDT timeout SLEP instruction Wake-up on a pin change during sleep mode RST 0 *P *P *P 1 T 1 1 0 *P 1 P 1 *P *P 0 0 *P: Previous status before reset Table 15.1 Values of RST, T and P after a reset Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 117 EM77F900 USB HUB+BB Controller 16.3 System Set-up (SSU) Time In order to have a successful start up, System Set-up Time (SSU) is employed to guarantee a stable clock for IC operation. It is made up of two delay sources: (1) External RC Oscillation Set-up Delay (IRCOSUD): External RC oscillation shared with a watchdog timer divided by a 10-bit ripple counter. The RC delay controlled by bit IRCDE in Code Option is optional. (2) Main Oscillation Set-up Delay (MOSUD): A 10-bit ripple counter is used to filter unstable main clocks at the beginning of power-on before the chip starts to run. This delay is performed right after IRCOSUD, if enabled. OSC1 10-bit Ripple Counter SSU 10-bit Ripple Counter RCSUTE Fig. 15-1 System Set up Time External RC Osc. 16.4 Wake-up Procedure on Power-on Reset Power-on Voltage Detector (POVD) will allow the VDD whose value is over the default threshold voltage (2.0 V for the EM77F900) to enter the IC, and the SSU delay starts. The following three cases may be taken into consideration: (1) /RESET pin goes high with VDD at the same time. In hardware, this pin and VDD are tied together. The internal reset will remain low until the SSU delay is over. (2) /RESET pin goes high during the SSU delay. It is similar to Case 1. The IC will start to operate when the SSU delay is over. /RESET pin goes high after an SSU delay. The EM77F900 will start program execution immediately. 118 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 17 Oscillators 17.1 Introduction The EM77F900 provides three main oscillators: One high frequency crystal oscillator (connected to OSCI and OSCO), external RC, and four PLL (Phase Lock Loop) Outputs. Versatile combinations of oscillation are provided for a wide range of applications. On-chip clock sources can be either dual clocks or single clock. 17.2 Clock Signal Distribution USB RF-BB USBCLK TUSB_CLK SYS_CLK 0/1=0 & RF_CLK 0/1=0 & USB_CLK=0 6 12 24 48 SYS_CLK 0/1 10 bit ADC SPI 16 bit PWM BYP 6 MHz RF_CLK 0/1 SR.GREEN SYS_NCLK PLL PD (Power Down) MCU Kernel SYS_ICLK ERC CLK TCCC.TCCS0 FRCC.FRCCS Serial Debug WDT 8 bit TCC 16 bit FRC Fig. 16-1 Clock Tours 17.3 PLL Oscillator The Phase-locked loop (PLL) technology is employed to produce four different frequencies: 6 MHz, 12MHz, 24MHz and 48 MHz (external 6MHz crystal). 6 MHz is the system clock source and 48 MHz is USB device and Hub clock source only. PLL is enabled except when entering Green and Sleep mode. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 119 EM77F900 USB HUB+BB Controller 18 Low-Power Mode 18.1 Introduction The EM77F900 has two power-saving modes, green mode and sleep mode. Figure 18-1 shows the mode change diagram. Power On Normal WDTC[7].Green=0 SLEP INST. Key Wake up 1. WDTC[7].Green=1 2. WDT Time out 3. /Reset 1. Key Wake-up 2. WDT Time out 3. /Reset Green SLEP INST. Sleep Fig. 17-1 Three Mode State 18.2 Green Mode The "GREEN" bit of WDTC [7] register is the only control bit used for mode switching, between normal mode and green mode. Its initial value is "0", normal mode. When "GREEN" bit is written with a 1, The MCU will switch to green mode from normal mode. In contrast, the MCU will go back to normal mode when the "GREEN" bit is written from 1 to 0. During green mode, the main oscillator will be turned off. The MCU and all the peripherals are driven by the external RC oscillator - ERC. Once RF peripheral is functional and then switched into green mode, the clock source of all other peripherals, except PLL, will be provided by ERC. PLL will keep running as RF circuit's clock source. 120 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 18.3 Sleep Mode The execution of "SLEP" instruction will turn the whole chip into Sleep mode. The main clock will be shut down. The ERC oscillator is halted also if the watchdog function is disabled. All registers, memory and I/O port remain in their previous states during sleep mode. The overflow of the watchdog timer driven by ERC will generate a reset to resume normal operation. Key Wake up (KWU) interrupt and /RESET pin are other methods to exit sleep mode. It is essential to wait for stable Oscillation start up time before normal operation. The stabilizing time is XXX. 19 Instruction Description 19.1 Instruction Set Summary Type 0000 0000 0000 0000 System Control 0000 0000 0000 0000 0000 1010 1010 1010 Table Look up 0000 0000 0000 0011 1010 Instruction Binary 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0000 0000 0000 1101 1011 0000 0000 0000 0000 0000 0000 0000 0000 0000 rrrr rrrr rrrr 0000 0000 0000 0000 kkkk 0000 0001 0010 0011 0100 0101 0110 0111 1000 rrrr rrrr rrrr 1010 1011 1100 0010 kkkk Mnemonic NOP WDTC RET RETI SLEP ENI DISI DAA (TRAP) TBRDP r TBRD r TBRDM r TBRDP A TBRD A TBRDM A TBL RETL #k Operation No operation WDT PC PC WDT 0 (Top of Stack) (Top of Stack); 0 Status Affected None None None None None None None C None TABPT+1 None None None None None None C, DC, Z None Cycles 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 1 1 Enable Interrupt Stop oscillator Enable Interrupt Disable Interrupt Decimal Adjust A ICE use r r r A A A R2 A PC k [Top of Stack] ROM[(TABPT[15:1])] ROM[(TABPT[15:1])] ROM[(TABPT[15:1])] TABPT-1 TABPT+1 ROM[(TABPT[15:1])] ROM[(TABPT[15:1])] ROM[(TABPT[15:1])] TABPT-1 R2+A TABPT TABPT TABPT TABPT Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 121 EM77F900 USB HUB+BB Controller Type 0000 0000 0000 0000 0000 0000 0000 0000 0000 Logic 0000 0000 1011 1011 1011 1011 0101 0101 0001 xxaa 0001 xxaa 0101 Compare Branch xxaa 0101 xxaa 0101 xxaa 0101 xxaa Process 0010 0010 0011 122 * Instruction Binary 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 00kk 01kk 10kk 11kk 10kk 11kk 0bbb aaaa 1bbb aaaa 0010 aaaa 0011 aaaa 0100 aaaa 0101 aaaa 0bbb 1bbb 0bbb rrrr rrrr kkkk Rrrr Rrrr kkkk Rrrr rrrr kkkk rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr aaaa rrrr aaaa rrrr aaaa rrrr aaaa rrrr aaaa rrrr aaaa rrrr rrrr rrrr rrrr rrrr kkkk rrrr rrrr kkkk rrrr rrrr kkkk rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr aaaa rrrr aaaa rrrr aaaa rrrr aaaa rrrr aaaa rrrr aaaa rrrr rrrr rrrr Mnemonic OR A, r OR r, A OR A, #k AND A, r AND r, A AND A, #k XOR A, r XOR r, A XOR A, #k COMA r COM r RRCA r, #k RRC r, #k RLCA r, #k RLC r, #k SHRA r, #k SHLA r, #k A r A A r A A r A A r Operation A .or. r r .or. A A .or. k A .and. r r .and. A A .and. k A .xor. r r .xor. A A .xor. k /r /r Status Affected Z Z Z Z Z Z Z Z Z Z Z C C C C None None None None None None None None None None None Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2/3* 2/3* 2/3* 2/3* 2/3* 2/3* 1 1 1 [C,r] rotate right k bits to [C,A] [C,r] rotate right k bits to [C,r] [C,r] rotate left k bits to [C,A] [C,r] rotate left k bits to [C,r] [C,r] shift right k bits to A Insert C into high order bits [C,r] shift left k bits to A Insert C into low order bits JBC r,b,addr If r(b)=0, jump to addr JBS r,b,addr If r(b)=1, jump to addr DJZA r,addr A DJZ r,addr JZA r,addr JZ r,addr BC r,b BS r,b BTG r,b r A r r(b) r(b) r(b) r-1, jump to addr if zero r-1, jump to addr if zero r+1, jump to addr if zero r+1, jump to addr if zero 0 1 /r(b) Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller Status Affected None None Z None Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z Z None Register r2 None None addr None Type 0011 0011 1010 0000 1010 0011 0011 0011 0100 Arithmetic 0100 0100 0100 0100 0101 0101 1010 1010 Move 0110 1010 110a Branch 111a Instruction Binary 1000 1001 1100 0000 1111 1100 1101 1110 0010 0011 0100 1110 1111 0000 0001 1000 1001 rrrr rrrr rrrr 0000 rrrr rrrr rrrr kkkk rrrr rrrr kkkk rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr 1101 rrrr rrrr rrrr kkkk rrrr rrrr kkkk rrrr rrrr rrrr rrrr rrrr rrrr Mnemonic SWAP r SWAPA r ZCHK r RPT CLR r ADD A,r ADD r,A ADD A,#k SUB A,r SUB r,A SUB A,#k INCA r INC r DECA r DEC r MOV A,r MOV r,A MOVRR r1, r2 MOV A,#k JMP addr Operation r(0:3) r(4:7) A(4:7) A(0:3) Z Z r(0:3) r(4:7) Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 if r < > 0 1 if r = 0 Single repeat CS times on next TBRD instruction r A r A A f A A r A r A r 0 A+r r+A A+k r-A r-A k-A r+1 r+1 r-1 r-1 r A r2 r2 r2 r2 r2 r2 r1 r1 r1 r1 r1 r1 Register r1 A PC k 0111 aaaa kkkk aaaa kkkk aaaa PC[13..16] unchange [Top of Stack] PC + 1 aaaa aaaa aaaa CALL addr PC addr None 1 PC [13..16] unchange Bank Page 1010 1010 1110 1101 0000 0000 0kkk 000k BANK #k PAGE #k R4(RAMBS0) R5(PAGES) k (0~6) k (0~1) None None 1 1 Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 123 EM77F900 USB HUB+BB Controller 20 Electrical Characteristics 20.1 Absolute Maximum Ratings Temperature under bias Storage temperature Input voltage Output voltage 0C -65C -0.3V -0.3V to to to to 70C 150C +3.6V +3.6V 20.2 DC Electrical Characteristic Ta=0C ~ 70 C, VDD=3.3V5%, VSS=0V Symbol Fxt IIL VIH VIL VIHT VILT VIHX VILX Parameter Condition Min DC - 0.8xVDD Typ - - - - - - - - - Max 48.0 2 - 0.2xVSS Unit MHz A V V V V V V V Crystal: VDD ~ 2.75V One cycle with one clock Input Leakage VIN = VDD, VSS Current for input pins Input High Voltage Input Low Voltage Port A ~ Port F Port A ~ Port F VSS 2.0 - 2.5 - 2.4 Input High Threshold /RST Voltage Input Low Threshold /RST Voltage Clock Input High Voltage Clock Input Low Voltage OSCI, OSCO OSCI, OSCO - 0.8 - 1.0 - Output High Voltage: IOH = -8.0 mA VOH1 PTA, PTC, PTD, PTE, PTF Output High Voltage: VOH2 PTB; IOH = -8.0 mA RFIO VOL1 VOL2 IPH ISB Output Low Voltage: IOL = 8.0 mA PTA, PTC, PTD, PTE, PTF Output Low Voltage: IOL = 8.0 mA (1) PTB; RFIO Pull-high current Pull-high active, input pin at VSS 2.4 - - V - - - - - - -6.5 - 0.4 0.4 - - V V A A All input and I/O pins at VDD, Power down current Output pin floating, WDT and all peripherals disabled. Operating supply current (VDD = 3.3V) Operating supply current (VDD = 3.3V) /RESET = 'High', Fosc = 32kHz (RC type), Output pin floating, WDT and all peripherals disabled. /RESET= 'High', Fosc = 6MHz (Crystal type), Output pin floating, and all peripherals disabled. ICC1 - - - A ICC3 - - - mA 124 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 20.3 Voltage Detector Electrical Characteristic Ta=25C Symbol Vdet Vrel Iss Vop Vdet/Ta Parameter Detect voltage Release voltage Current consumption Operating voltage Vdet Temperature characteristic Condition - - VDD = 3V - 0C Ta 70C Min 1.8 - - 0.7* - Typ 2.0 Vdet x 1.05 Max 2.2 Unit V V A V MV/C - - - 0.8 3.5 -2 * When the VDD voltage rises between Vop=0.7V and Vdet, the voltage detector output must be "Low". 20.4 AC Electrical Characteristic 20.4.1 MCU Ta=0C ~ 70 C, VDD=3.3 V5%, VSS=0V) Symbol Dclk Tins Ttcc Tdrh Trst Twdt Tset Thold Tdelay Parameter Input CLK duty cycle Instruction cycle time (CLKS="0") TCC input period Device reset hold time /RESET pulse width Watchdog timer period Input pin setup time Input pin hold time Output pin delay time Conditions - Crystal type RC type - Ta = 25C Ta = 25C Ta = 25C - - Cload=20pF Min 45 125 500 (Tins+20)/N* Typ 50 - - 18 - 18 0 20 50 Max 55 DC DC - 30 - 30 - - - Unit % ns ns ns ms ns ms ms ms ms 9 2000 9 - - - * N= selected prescaler ratio. Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) * 125 EM77F900 USB HUB+BB Controller 20.4.2 BB Ta=0C ~ 70 C, VDD=3.3 V5%, VSS=0V Symbol 1/tOSC tRDPW tCSRD tADRD tRDDV tRHDT tDHAR tRHDT tRDAN Parameter Oscillator frequency RD pulse width CS low to RD low Address valid for RD low RD low to Data valid Data float after RD. Data hold after RD Time between consecutive RD pulses Address valid after RD low Min 0.1 3*tOSC+ tOSC 0 - - 0 2*tOSC 3*tOSC+ Max 24 - - - 3*tOSC+ tOSC - - - Unit MHz ns ns ns ns ns ns ns ns >0 will be determined according to cell library simulation. The values above were determined according to behavioral simulations. They take into account only the BB digital state-machine. Thus, such values are for reference only. 126 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) EM77F900 USB HUB+BB Controller 21 Application Circuit VDD VDD RF MODULE 6MHz VDD VDD VDD VDD VDD VCC VCC USB Downstream USB Upstream Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) VDD DVSS0 PTA0/KWU8 PTA1/KWU9 PTA2/KWU A PTA3/KWUB /RST DVDD0 PTA4 PTA5 PTA6 PTA7/PWM0 AVSS TUSB_CL 0 K UPRT_D+ UPRT_DDPRT2_D+ DPRT2_DDPRT3_D+ DPRT3_DDPRT4_D+ DPRT4_DDVDD2 DPRT2_OVCUR_DET DPRT3_OVCUR_DET DPRT4_OVCUR_DET DPRT2_PWR_EN DPRT3_PWR_EN DPRT4_PWR_EN VUSB_3.3V AVDD0_5V PTD3/ADC3 PTD4/ADC4 PTD5/ADC5 PTD6/ADC6 PTD7/ADC7 VREF_ADC PTE0/ADC8 PTE1/ADC9 PTE2/ADCA PTE3/ADCB PTE4/ADCC2 PTE5/ADCD PTE6/ADCE PTE7/ADCF AVDD2 DVDD PTF0 PTF1 PTF2 PTF3 AVDD1 RF_ACTIVE TX_RX RFIO AVSS1 PTC0/SDI PTC1/SDO PTC2/SCK PTC3/EINT0 PTC4/EINT1 PTC5/PWM1 PLLC DVSS1 OSCO OSCI DVDD1 /PRST PGCLK PGDATA RCI NC NC NC NC NC DVSS3 AVSS2 PTD0/ADC0 PTD1/ADC1 PTD2/ADC2 PTB7/KWU PTB6/KWU 7 6 PTB5/KWU PTB4/KWU 5 PTB3/KWU 4 3 PTB2/KWU 2 PTB1/KWU 1 PTB0/KWU 0 TEST_C2 TEST_C1 TEST_C0 TEST_D7 TEST_D6 TEST_D5 TEST_D4 TEST_D3 TEST_D2 TEST_D1 TEST_D0 REG_C EM77F900 VDD VDD VDD VDD VCC * 127 EM77F900 USB HUB+BB Controller APPENDIX A Package Type ET NO EM77F900Q EM77F900Q Package Type QFP100 LQFP64 Pin Count 100 64 Package Size 14X20MM 10X10MM B Package Information 128 * Product Specification (V1.0) 07.31.2007 (This specification is subject to change without further notice) |
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