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TDA8133/D
+5.1 V AND +8 V DUAL-VOLTAGE REGULATOR WITH DISABLE AND RESET FUNCTIONS
PRELIMINARY DATA
FEATURES
s Input Voltage Range: 7 V to 18 V s Output Currents up to 750 mA s Fixed Precision Output 1 Voltage: 5.1 V 2% s Fixed Precision Output 2 Voltage: 8 V 2% s Output 1 with Reset Function s Output 2 with Disable Function by TTL Input s Short-circuit Protection at both Outputs s Thermal Protection s Low Dropout Voltage SIP9 (Plastic Package) ORDER CODE: TDA8133
DESCRIPTION
The TDA8133 and the TDA8133D are monolithic dual positive voltage regulators designed to provide fixed precision output voltages of 5.1 V and 8.0 V for currents up to 750 mA. An internal reset circuit generates a reset pulse when the voltage of Output 1 drops below the regulated voltage value. Output 2 can be disabled via the TTL input. Short-circuit and thermal protections are included in all versions. DIP16 (8 + 8) ORDER CODE: TDA8133D
INPUT1 9 8 7 6 5 4 3 2 1
Tab is connected to GROUND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND
OUTPUT1 INPUT2 OUTPUT2 DELAY CAPACITOR NTBC DISABLE RESET GROUND RESET DISABLE NTBC DELAY CAPACITOR OUTPUT2 INPUT2 INPUT1 OUTPUT1
September 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/13
TDA8133/D
TABLE OF CONTENTS
Chapter 1 Chapter 2
2.1 2.2 2.3
GENERAL INFORMATION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Absolute Maximum Ratings ................................................................................................ 4 Thermal Data ...................................................................................................................... 4 Electrical Characteristics ...................................................................................................... 4
Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7
CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 APPLICATION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
POWER DISSIPATION AND LAYOUT INDICATIONS . . . . . . . . . . . . . . . . . . . . . .9 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
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TDA8133/D
GENERAL INFORMATION
1
GENERAL INFORMATION
Figure 1: TDA8133 Block Diagram
DELAY CAPACITOR 3 6 Reference RESET
INPUT1
1
Regulator 1 Protection
9
OUTPUT1
INPUT2
2
Regulator 2
8
OUTPUT2
DISABLE
4
7 NTBC 5 GROUND NTBC: Not to be Connected
Figure 2: TDA8133D Block Diagram
DELAY CAPACITOR 3 5 Reference RESET
INPUT1
1
Regulator 1 Protection
8
OUTPUT1
INPUT2
2
Regulator 2
7
OUTPUT2
DISABLE
4
6 NTBC
Pins 9 to 16 GROUND
NTBC: Not to be Connected
3/13
ELECTRICAL CHARACTERISTICS
TDA8133/D
2
2.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
DC Input Voltage at pins INPUT1 and INPUT2 Disable Input Voltage at pin DISABLE Output Voltage at pin RESET Output Currents Power Dissipation Storage Temperature Junction Temperature
Symbol
VIN VDIS VRST IO1,2 Pt TSTG TJ
Value
20 20 20 Internally Limited Internally Limited -65 to +150 0 to +150
Unit
V V V
C C
2.2
Thermal Data
Parameter
Thermal Resistance (Junction-to-Case) Thermal Resistance 1 (Junction-to-Ambient) Maximum Recommended Junction Temperature Operating Free Air Temperature Range TDA8133 TDA8133D TDA8133 TDA8133D
Symbol
RthJC RthJA TJ TOPER
Value
9 15 50 56 140 0 to +70
Unit
C/W
C/W C C
1. Mounted on board. For more information, refer to Section 5.
2.3
Electrical Characteristics
TAMB = 25 C, VIN1 = 7 V, VIN2 = 10 V, unless otherwise specified.
Symbol
VO1 VO2 VIO1,2
Parameter
Output Voltage Output Voltage Dropout Voltage
Test Conditions
IO1 = 10 mA IO2 = 10 mA IO1,2 = 750 mA 7 V < VIN1 < 14 V 10 V < VIN2 < 14 V IO1,2 = 200 mA 5 mA < IO1 < 600 mA 5 mA < IO2 < 600 mA IO1 = 10 mA, OUTPUT2 Disabled
Min.
5 7.84
Typ.
5.1 8.00
Max.
5.2 8.16 1.4 50 80
Unit
V V V
VO1,2LI
Line Regulation
mV
VO1,2LO IQ
Load Regulation Quiescent Current
100 160 2
mV mA
4/13
TDA8133/D
Symbol
VO1RST VRTH tRD VRL IRH
ELECTRICAL CHARACTERISTICS
Parameter Test Conditions
K = VO1, VIN1 7 V See circuit description. Ce = 100 nF See circuit description.
Min.
K - 0.4 20
Typ.
K - 0.25 50 25
Max.
K - 0.1 75
Unit
V mV ms
Reset Threshold Voltage Reset Threshold Hysteresis Reset Pulse Delay
Saturation Voltage in Reset Condition IRESET = 5 mA Leakage Current in Normal Condition VRESET= 10 V V 0 10 6 K 0 = -----------------------T V 0 TJ = 0 to + 125C
0.4 10
V A
KO1, 2
Output Voltage Thermal Drift
100
ppm/C
IO1,2SC VDISH VDISL IDIS TJSD
Short Circuit Output Current
VIN1 = 7 V, VIN2 = 10 V VIN1,2 = 16 V1 2
1.6 1.0
A V
Disable Voltage when pin DISABLE is High (OUTPUT2 active) Disable Voltage when pin DISABLE is Low (OUTPUT2 disabled) Disable Bias Current 0 V < VDIS < 7 V
0.8 -100 145 2
V A C
Junction Temperature for Thermal Shutdown
1. The output short-circuit currents are tested one channel at time. During a short-circuit, a large consumption of power occurs, but the thermal protection circuit prevents any excessive temperatures. A safe permanent short-circuit protection is only guaranteed for input voltages up to 16 V.
5/13
CIRCUIT DESCRIPTION
TDA8133/D
3
CIRCUIT DESCRIPTION
The TDA8133 and the TDA8133D are dual-voltage regulators with Reset and Disable functions. The two regulation parts are supplied from a single voltage reference circuit trimmed by zener zapping during EWS testing. Since the supply voltage of this voltage reference is connected to pin INPUT1 (VIN1), the second regulator will not work if pin INPUT1 is not supplied. The output stages are designed using a Darlington configuration with a typical dropout voltage of 1.2 V. The Disable circuit will switch off pin OUTPUT2 if a voltage less than 0.8 V is applied to pin DISABLE. The Reset circuit checks the voltage at pin OUTPUT1. If this voltage drops below VO1 - 0.25 V (4.85 V Typ.), the "a" comparator (Figure 3) rapidly discharges the external capacitor (Ce) and the reset output immediately switches to low. When the voltage at pin OUTPUT1 exceeds VO1 - 0.2 V (4.9 V Typ.), the VCe voltage increases linearly to the reference voltage (VREF = 2.5 V) corresponding to a Reset Pulse Delay (tRD) as shown in Figure 4.
C e x 2.5V t RD = ------------------------10A
Afterwards, the reset output returns to high. To avoid glitches in the reset output, the second comparator "b" has a large hysteresis (1.9 V).
Figure 3: Reset Diagram
10 A VREF OUTPUT1 REG VREF = 2.5 V b RESET
+a 50 3 Ce VREF
+
0.6V
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TDA8133/D
Figure 4: Internal Reset Voltage
CIRCUIT DESCRIPTION
VO1 K VO1RST VRTH
RESET
K = Actual Value of VO1
Power On
tRD
tRD
Power Off
7/13
APPLICATION DIAGRAMS
TDA8133/D
4
APPLICATION DIAGRAMS
Figure 5: TDA8133 Typical Application
RESET Ce
6
RESET
0.1 F
3 DELAY CAPACITOR OUTPUT1 9 OUTPUT2 8
VIN1 VIN2 C1 C2
1 INPUT1 2 INPUT2
VO1 VO2 C3 C4
GROUND
5
NTBC 7
DISABLE 4
DISABLE C1 to C4 = 10 F
Figure 6: TDA8133D Typical Application
RESET Ce
5
RESET
0.1 F
3 DELAY CAPACITOR OUTPUT1 8 OUTPUT2 7
VIN1 VIN2 C1 C2
1 INPUT1 2 INPUT2
VO1 VO2 C3 C4
GROUND
NTBC 6
DISABLE 4
Pins 9 to 16
DISABLE C1 to C4 = 10 F
8/13
TDA8133/D
POWER DISSIPATION AND LAYOUT INDICATIONS
5
POWER DISSIPATION AND LAYOUT INDICATIONS
The power is mainly dissipated by the two device buffers. It can be calculated by the equation: P = (VIN1-VO1) x IO1 + (VIN2-VO2) x IO2 The following table lists the different RthJA values of these packages with or without a heat sink and the corresponding maximum power dissipation assuming:
q q
Maximum Ambient Temperature = 70 C Maximum Junction Temperature = 140 C
Device
TDA8133 Yes No TDA8133D Yes 32 2.2 20 56 to 40 3.5 1.25 to 1.75
Heat Sink
No
RthJA in C/W
50
PMAX in W
1.4
Figure 7: Thermal Resistance (Junction-to-Ambient) of DIP16 Package without Heat Sink
60 RthJA C/W 55 50 45 40
To optimize the thermal conductivity of the copper layer and the exchanges with the air, the solder must cover the maximum amount of this area. Test Board with "On Board" square heat sink area.
6 0 2 4 8 10 12 Copper area (cm) (35 m plus solder) Board is face-down
Figure 8: Metal plate mounted near the TDA8133D for heat sinking
Top View Bottom View
9/13
PACKAGE MECHANICAL DATA
TDA8133/D
6
PACKAGE MECHANICAL DATA
Figure 9: 9-Pin Plastic Single In Line Package
mm Dim. Min.
A a1 B b1 b3 C c1 c2 D d1 e e3 L L1 L2 L3 M N 3.2 1 3.1 3 17.6 0.25 14.5 2.54 20.32 1.122 0.85 3.3 0.43 1.32 21.2 0.5 1.6 0.033 2.7
Inches Max.
7.1 3 24.8 0.020 0.063 0.130 0.017 0.052 0.835 0.571 0.100 0.800 0.116 0.693 0.010 0.126 0.039 0.106
Typ.
Min.
Typ.
Max.
0.280 0.118 0.976
10/13
TDA8133/D
PACKAGE MECHANICAL DATA
Figure 10: 16-Pin Plastic Dual In-Line Package, 300-mil Width
mm Dim. Min.
A A1 A2 b b2 c D e E1 L 6.10 2.92 0.20 18.67 0.38 2.92 0.36 1.52 0.25 19.18 2.54 6.35 3.30 7.11 3.81 0.240 0.115 3.30 4.95 0.56 1.78 0.36 19.69 0.008 0.735
Inches Max.
5.33 0.015 0.115 0.014 0.060 0.010 0.755 0.100 0.250 0.130 0.280 0.150 0.130 0.195 0.022 0.070 0.014 0.775
Typ.
Min.
Typ.
Max.
0.210
11/13
REVISION HISTORY
TDA8133/D
7
REVISION HISTORY
Main Changes
First Issue Datasheet Update and addition of DIP16 Package General Update; DISABLE pin renamed DISABLE (function remains unchanged). Thermal Data updated. Thermal Data updated. Figure 1 and Figure 2 updated.
Revision
1.0 1.1 1.2 1.3 1.4
Date
March 1994 July 2001 August 2001 September 2001 October 2001
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TDA8133/D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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13/13

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