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Datasheet File OCR Text:

M58LR128HC M58LR128HD
128 Mbit (x16, Mux I/O, Multiple Bank, Multilevel interface, Burst) 1.8 V supply Flash memories
Features
Supply voltage - VDD = 1.7 V to 2.0 V for program, erase and read - VDDQ = 1.7 V to 2.0 V for I/O Buffers - VPP = 9 V for fast program Multiplexed address/data Synchronous / Asynchronous Read - Synchronous Burst Read mode: 66 MHz - Random Access: 70 ns Synchronous Burst Read Suspend Programming time - 2.5 s typical Word program time using Buffer Enhanced Factory Program command Memory organization - Multiple Bank memory array: 8 Mbit Banks - Parameter Blocks (top or bottom location) Dual operations - program/erase in one Bank while read in others - No delay between read and write operations Block locking - All blocks locked at power-up - Any combination of blocks can be locked with zero latency - WP for Block Lock-Down - Absolute Write Protection with VPP = VSS
FBGA

VFBGA44 (ZB) 7.7 x 9 mm

Security - 64 bit unique device number - 2112 bit user programmable OTP Cells Common Flash Interface (CFI) 100 000 program/erase cycles per block Electronic signature - Manufacturer Code: 20h - Top Device Codes: M58LR128HC: 882Eh - Bottom Device Codes M58LR128HD: 882Fh VFBGA44 package - ECOPACK(R) compliant

November 2007
Rev 2
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www.numonyx.com 1
Contents
M58LR128HC, M58LR128HD
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 Address Inputs (ADQ0-ADQ15 and A16-A22) . . . . . . . . . . . . . . . . . . . . . 13 Data Input/Output (ADQ0-ADQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VPP Program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VSSQ ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 3.2 3.3 3.4 3.5 3.6 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 4.2 4.3 4.4 Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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4.5 4.6 4.7 4.8 4.9 4.10
Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 The Blank Check command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Buffer Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . 25
4.10.1 4.10.2 4.10.3 Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Program and Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.11 4.12 4.13 4.14 4.15 4.16 4.17
Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Block Lock-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Program/Erase Controller status bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . 35 Erase Suspend status bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Erase/Blank Check status bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Program status bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 VPP status bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Program Suspend status bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Block Protection status bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Bank Write/Multiple Word Program status bit (SR0) . . . . . . . . . . . . . . . . 37
6
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1 6.2 6.3 6.4 6.5 6.6 Read Select bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 X-Latency bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Wait Polarity bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Data Output Configuration bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Wait Configuration bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Burst type bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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6.7 6.8 6.9
Valid Clock edge bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Wrap burst bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Burst length bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7
Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.1 7.2 7.3 Asynchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Synchronous Burst Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.2.1 Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Single Synchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8 9
Dual operations and Multiple Bank architecture . . . . . . . . . . . . . . . . . 49 Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.1 9.2 9.3 9.4 9.5 Reading a Block's lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Lock-Down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Locking operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . 52
10 11 12 13 14
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 54 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Appendix B Common Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Appendix C Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Appendix D Command interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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List of tables
M58LR128HC, M58LR128HD
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 M58LR128HC/D bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Factory Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Protection Register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 X-latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Program/Erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DC characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 DC characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Asynchronous Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Synchronous Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Reset and Power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 VFBGA44 7.7x9mm - 10x4 ball array, 0.50mm pitch, package mechanical data. . . . . . . . 73 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Top boot block addresses, M58LR128HC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Bottom boot block addresses, M58LR128HD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Primary Algorithm-Specific Extended Query Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Protection Register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Burst Read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Bank and Erase Block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Bank and Erase Block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Bank and Erase Block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Command Interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Command Interface states - modify table, next output state . . . . . . . . . . . . . . . . . . . . . . 107 Command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Command interface states - lock table, next output state . . . . . . . . . . . . . . . . . . . . . . . . 111 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 M58LR128HC/D memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 X-Latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 asynchronous random access Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Synchronous Burst Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Single Synchronous Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Synchronous Burst Read Suspend AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Clock input AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Reset and Power-up AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 VFBGA44 7.7x9mm - 10x4 ball array, 0.50mm pitch, Bottom View Package Outline . . . . 72 VFBGA44 daisy chain - package connections (top view through package) . . . . . . . . . . . . 74 VFBGA44 daisy chain - PCB connection proposal (top view through package). . . . . . . . . 75 Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Blank Check flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Buffer Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Program Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 98 Block Erase flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Erase Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Locking operations flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Protection Register Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . 102 Buffer Enhanced Factory Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . 103
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Description
M58LR128HC, M58LR128HD
1
Description
The M58LR128HC/D are 128 Mbit (8 Mbit x16) non-volatile Flash memories. They may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.7 V to 2.0 V VDD supply for the circuitry and a 1.7 V to 2.0 V VDDQ supply for the Input/Output pins. An optional 9 V VPP power supply is provided to speed up factory programming. The first sixteen address lines are multiplexed with the Data Input/Output signals on the multiplexed address/data bus ADQ0-ADQ15. The remaining address lines A16-A22 are the Most Significant Bit addresses. The devices feature an asymmetrical block architecture. The M58LR128HC/D have an array of 131 blocks, and are divided into 8 Mbit banks. There are 15 banks each containing 8 main blocks of 64 KWords, and one parameter bank containing 4 parameter blocks of 16 KWords and 7 main blocks of 64 KWords. The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory map is shown in Figure 3. The Parameter Blocks are located at the top of the memory address space for the M58LR128HC, and at the bottom for the M58LR128HD. Each block can be erased separately. Erase can be suspended, in order to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100 000 cycles using the supply voltage VDD. There is a Buffer Enhanced Factory programming command available to speed up programming. Program and erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports Synchronous Burst Read and Asynchronous Read from all blocks of the memory array; at power-up the device is configured for Asynchronous Read. In Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to 66 MHz. The Synchronous Burst Read operation can be suspended and resumed. The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. The M58LR128HC/D features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are locked at power-up.
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M58LR128HC, M58LR128HD
Description
The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protection Register and the other for the 16 One-Time-Programmable (OTP) Protection Registers of 128 bits each. The first Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by Numonyx, and a 64 bit segment One-Time-Programmable (OTP) by the user. The user programmable segment can be permanently protected. Figure 4, shows the Protection Register Memory Map. The M58LR128HC/D are offered in a VFBGA44, 7.7 x 9 mm, 0.50 mm pitch package. They are supplied with all the bits erased (set to '1').
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Description Figure 1. Logic diagram
VDD VDDQ VPP 16 A16-A22 W E G RP WP L K M58LR128HC M58LR128HD
M58LR128HC, M58LR128HD
ADQ0ADQ15
WAIT
VSS
VSSQ
AI13489
Table 1.
A16-A22
Signal names
Address Inputs Data Input/Outputs or Address Inputs, Command Inputs Chip Enable Output Enable Write Enable Reset Write Protect Clock Latch Enable Wait Supply Voltage Supply Voltage for Input/Output Buffers Optional Supply Voltage for Fast Program & Erase Ground Ground Input/Output Supply Not Connected Internally Do Not Use
ADQ0-ADQ15 E G W RP WP K L WAIT VDD VDDQ VPP VSS VSSQ NC DU
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Figure 2.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
M58LR128HC, M58LR128HD
A
NC
NC
B
C
WAIT VSS
A21 K VDD W VPP A19 A17
A22
D
VDDQ
A16
A20
L
NC
RP
WP
A18
E
VSSQ
VFBGA connections (top view through package)
E
VSS
ADQ7
ADQ6
ADQ13 ADQ3 ADQ2
ADQ12
ADQ9
ADQ8
G
F ADQ15 ADQ14 VSSQ ADQ5 ADQ4 ADQ11
ADQ10
VDDQ
ADQ1
ADQ0
G
H
NC
NC
Description
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ai12319
Description Table 2. M58LR128HC/D bank architecture
Bank Size 8 Mbits 8 Mbits 8 Mbits 8 Mbits ---Parameter Blocks 4 blocks of 16 KWords ----
M58LR128HC, M58LR128HD
Number Parameter Bank Bank 1 Bank 2 Bank 3 ----
Main Blocks 7 blocks of 64 KWords 8 blocks of 64 KWords 8 blocks of 64 KWords 8 blocks of 64 KWords ---8 blocks of 64 KWords 8 blocks of 64 KWords
Bank 14 Bank 15
8 Mbits 8 Mbits
-
Figure 3.
M58LR128HC/D memory map
M58LR128HC - Top Boot Block Address lines A22-A16 and ADQ15-ADQ0 000000h 00FFFFh 64 KWord 8 Main Blocks 64 KWord Parameter Bank M58LR128HD - Bottom Boot Block Address lines A22-A16 and ADQ15-ADQ0 000000h 003FFFh 00C000h 00FFFFh 010000h 01FFFFh 070000h 07FFFFh 080000h 08FFFFh Bank 1 0F0000h 0FFFFFh 100000h 10FFFFh Bank 2 170000h 17FFFFh 180000h 18FFFFh Bank 3 1F0000h 1FFFFFh 7 Main Blocks 64 KWord 16 KWord 4 Parameter Blocks Bank 15 16 KWord 780000h 78FFFFh 7F0000h 7FFFFFh 64 KWord 8 Main Blocks 64 KWord
AI13490
16 KWord 4 Parameter Blocks 16 KWord 64 KWord 7 Main Blocks 64 KWord 64 KWord 8 Main Blocks 64 KWord 64 KWord 8 Main Blocks 64 KWord 64 KWord 8 Main Blocks 64 KWord
Bank 15 070000h 07FFFFh
600000h 60FFFFh Bank 3 670000h 67FFFFh 680000h 68FFFFh Bank 2 6F0000h 6FFFFFh 700000h 70FFFFh Bank 1 770000h 77FFFFh 780000h 78FFFFh 7E0000h 7EFFFFh 7F0000h 7F3FFFh 7FC000h 7FFFFFh
64 KWord 8 Main Blocks 64 KWord 64 KWord 8 Main Blocks 64 KWord 64 KWord 8 Main Blocks 64 KWord 64 KWord
Parameter Bank
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M58LR128HC, M58LR128HD
Signal descriptions
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.
2.1
Address Inputs (ADQ0-ADQ15 and A16-A22)
The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller.
2.2
Data Input/Output (ADQ0-ADQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation.
2.3
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level.
2.4
Output Enable (G)
The Output Enable input controls data outputs during the Bus Read operation of the memory.
2.5
Write Enable (W)
The Write Enable input controls the Bus Write operation of the memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.
2.6
Write Protect (WP)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the Lock-Down is enabled and the protection status of the LockedDown blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (refer to Table 16: Lock status).
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Signal descriptions
M58LR128HC, M58LR128HD
2.7
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 21: DC characteristics - currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3 V logic without any additional circuitry. It can be tied to VRPH (refer to Table 22: DC characteristics - voltages).
2.8
Latch Enable (L)
Latch Enable latches the ADQ0-ADQ15 and A16-A22 address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH.
2.9
Clock (K)
The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is ignored during asynchronous read and in write operations.
2.10
Wait (WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at VIH or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAIT signal is forced deasserted when Output Enable is at VIH.
2.11
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase).
2.12
VDDQ supply voltage
VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply.
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M58LR128HC, M58LR128HD
Signal descriptions
2.13
VPP Program supply voltage
VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives absolute protection against program or erase, while VPP in the VPP1 range enables these functions (see Tables 21 and 22, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed.
2.14
VSS ground
VSS ground is the reference for the core supply. It must be connected to the system ground.
2.15
VSSQ ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS
Note:
Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1 F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 8: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents.
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Bus operations
M58LR128HC, M58LR128HD
3
Bus operations
There are six standard bus operations that control the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset. See Table 3: Bus operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations.
3.1
Bus Read
Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figures 9, 10 and 11 Read AC Waveforms, and Tables 23 and 24 Read AC Characteristics, for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write Commands to the memory or latch Input Data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses must be latched prior to the write operation by toggling Latch Enable (when Chip Enable is at VIL). The Latch Enable must be tied to VIH during the bus write operation. See Figures 14 and 15, Write AC Waveforms, and Tables 25 and 26, Write AC Characteristics, for details of the timing requirements.
3.3
Address Latch
Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at VIL during address latch operations. The addresses are latched on the rising edge of Latch Enable.
3.4
Output Disable
The outputs are high impedance when the Output Enable is at VIH.
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M58LR128HC, M58LR128HD
Bus operations
3.5
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power consumption is reduced to the standby level IDD3 and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished.
3.6
Reset
During Reset mode the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the Reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid. Table 3. Bus operations(1)
E VIL VIL VIL VIL VIH X G VIL VIH VIH VIH X X W VIH VIL X VIH X X L VIH VIH VIL VIH X X RP VIH VIH VIH VIH VIH VIL Hi-Z Hi-Z WAIT(2) ADQ15-ADQ0 Data Output Data Input Address Input Hi-Z Hi-Z Hi-Z
Operation Bus Read Bus Write Address Latch Output Disable Standby Reset
1. X = Don't care.
2. WAIT signal polarity is configured using the Set Configuration Register command.
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Command interface
M58LR128HC, M58LR128HD
4
Command interface
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the program and erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation. The Command Interface is reset to read mode when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly. Any invalid combination of commands will be ignored. Refer to Table 4: Command codes, Table 5: Standard commands, Table 6: Factory Commands, and Appendix D: Command interface state tables, for a summary of the Command Interface. Table 4. Command codes
Command Block Lock Confirm Set Configuration Register Confirm Alternative Program Setup Block Erase Setup Block Lock-Down Confirm Program Setup Clear Status Register Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set Configuration Register Setup Read Status Register Buffer Enhanced Factory Program Setup Read Electronic Signature Read CFI Query Program/Erase Suspend Blank Check Setup Protection Register Program Blank Check Confirm Program/Erase Resume, Block Erase Confirm, Block Unlock Confirm, Buffer Program or Buffer Enhanced Factory Program Confirm Buffer Program Read Array
Hex Code 01h 03h 10h 20h 2Fh 40h 50h 60h 70h 80h 90h 98h B0h BCh C0h CBh D0h E8h FFh
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M58LR128HC, M58LR128HD
Command interface
4.1
Read Array command
The Read Array command returns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command. Once a bank is in Read Array mode, subsequent read operations will output the data from the memory array. A Read Array command can be issued to any banks while programming or erasing in another bank. If the Read Array command is issued to a bank currently executing a program or erase operation, the bank will return to Read Array mode but the program or erase operation will continue, however the data output from the bank is not guaranteed until the program or erase operation has finished. The read modes of other banks are not affected.
4.2
Read Status Register command
The device contains a Status Register that is used to monitor program or erase operations. The Read Status Register command is used to read the contents of the Status Register for the addressed bank. One Bus Write cycle is required to issue the Read Status Register command. Once a bank is in Read Status Register mode, subsequent read operations will output the contents of the Status Register. The Status Register data is latched on the falling edge of the Chip Enable or Output Enable signals. Either Chip Enable or Output Enable must be toggled to update the Status Register data The Read Status Register command can be issued at any time, even during program or erase operations. The Read Status Register command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Status Register. A Read Array command is required to return the bank to Read Array mode. See Table 9 for the description of the Status Register Bits.
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Command interface
M58LR128HC, M58LR128HD
4.3
Read Electronic Signature command
The Read Electronic Signature command is used to read the Manufacturer and Device Codes, the Lock Status of the addressed bank, the Protection Register, and the Configuration Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once a bank is in Read Electronic Signature mode, subsequent read operations in the same bank will output the Manufacturer Code, the Device Code, the Lock Status of the addressed bank, the Protection Register, or the Configuration Register (see Table 7). The Read Electronic Signature command can be issued at any time, even during program or erase operations, except during Protection Register Program operations. Dual operations between the Parameter bank and the Electronic Signature location are not allowed (see Table 15: Dual operation limitations for details). If a Read Electronic Signature command is issued to a bank that is executing a program or erase operation the bank will go into Read Electronic Signature mode. Subsequent Bus Read cycles will output the Electronic Signature data and the Program/Erase controller will continue to program or erase in the background. The Read Electronic Signature command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Electronic Signature. A Read Array command is required to return the bank to Read Array mode.
4.4
Read CFI Query command
The Read CFI Query command is used to read data from the Common Flash Interface (CFI). One Bus Write cycle is required to issue the Read CFI Query command. Once a bank is in Read CFI Query mode, subsequent Bus Read operations in the same bank read from the Common Flash Interface. The Read CFI Query command can be issued at any time, even during program or erase operations. If a Read CFI Query command is issued to a bank that is executing a program or erase operation the bank will go into Read CFI Query mode. Subsequent Bus Read cycles will output the CFI data and the Program/Erase controller will continue to program or erase in the background. The Read CFI Query command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read from the CFI. A Read Array command is required to return the bank to Read Array mode. Dual operations between the Parameter Bank and the CFI memory space are not allowed (see Table 15: Dual operation limitations for details). See Appendix B: Common Flash Interface, Tables 32, 33, 34, 35, 36, 37, 38, 39, 40 and 41 for details on the information contained in the Common Flash Interface memory area.
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M58LR128HC, M58LR128HD
Command interface
4.5
Clear Status Register command
The Clear Status Register command can be used to reset (set to `0') all error bits (SR1, 3, 4 and 5) in the Status Register. One Bus Write cycle is required to issue the Clear Status Register command. The Clear Status Register command does not affect the read mode of the bank. The error bits in the Status Register do not automatically return to `0' when a new command is issued. The error bits in the Status Register should be cleared before attempting a new program or erase command.
4.6
Block Erase command
The Block Erase command is used to erase a block. It sets all the bits within the selected block to '1'. All previous data in the block is lost. If the block is protected then the erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command.

The first bus cycle sets up the Block Erase command. The second latches the block address and starts the Program/Erase Controller.
If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and SR5 are set and the command is aborted. Once the command is issued the bank enters Read Status Register mode and any read operation within the addressed bank will output the contents of the Status Register. A Read Array command is required to return the bank to Read Array mode. During Block Erase operations the bank containing the block being erased will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. The Block Erase operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed when the Block Erase operation is aborted, the block must be erased again. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 17: Program/Erase times and endurance cycles. See Appendix C, Figure 24: Block Erase flowchart and pseudo code, for a suggested flowchart for using the Block Erase command.
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Command interface
M58LR128HC, M58LR128HD
4.7
The Blank Check command
The Blank Check command is used to check whether a Main Array Block has been completely erased. Only one Block at a time can be checked. To use the Blank Check command VPP must be equal to VPPH. If VPP is not equal to VPPH, the device ignores the command and no error is shown in the Status Register. Two bus cycles are required to issue the Blank Check command:

The first bus cycle writes the Blank Check command (BCh) to any address in the Block to be checked. The second bus cycle writes the Blank Check Confirm command (CBh) to any address in the Block to be checked and starts the Blank Check operation.
If the second bus cycle is not Blank Check Confirm, Status Register bits SR4 and SR5 are set to '1' and the command aborts. Once the command is issued the addressed bank automatically enters the Status Register mode and further reads within the bank output the Status Register contents. The only operation permitted during Blank Check is Read Status Register. Dual Operations are not supported while a Blank Check operation is in progress. Blank Check operations cannot be suspended and are not allowed while the device is in Program/Erase Suspend. The SR7 Status Register bit indicates the status of the Blank Check operation in progress: SR7 = '0' means that the Blank Check operation is still ongoing. SR7 = '1' means that the operation is complete. The SR5 Status Register bit goes High (SR5 = '1') to indicate that the Blank Check operation has failed. At the end of the operation the bank remains in the Read Status Register mode until another command is written to the Command Interface. See Appendix C, Figure 21: Blank Check flowchart and pseudo code, for a suggested flowchart for using the Blank Check command. Typical Blank Check times are given in Table 17: Program/Erase times and endurance cycles.
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M58LR128HC, M58LR128HD
Command interface
4.8
Program command
The program command is used to program a single Word to the memory array. If the block being programmed is protected, then the Program operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the Program Command.

The first bus cycle sets up the Program command. The second latches the address and data to be programmed and starts the Program/Erase Controller.
Once the programming has started, read operations in the bank being programmed output the Status Register content. During a Program operation, the bank containing the Word being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. A Read Array command is required to return the bank to Read Array mode. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 17: Program/Erase times and endurance cycles. The Program operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed when the Program operation is aborted, the Word must be reprogrammed. See Appendix C, Figure 20: Program flowchart and pseudo code, for the flowchart for using the Program command.
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Command interface
M58LR128HC, M58LR128HD
4.9
Buffer Program command
The Buffer Program Command makes use of the device's 32-Word Write Buffer to speed up programming. Up to 32 Words can be loaded into the Write Buffer. The Buffer Program command dramatically reduces in-system programming time compared to the standard nonbuffered Program command. Four successive steps are required to issue the Buffer Program command. 1. The first Bus Write cycle sets up the Buffer Program command. The setup code can be addressed to any location within the targeted block.
After the first Bus Write cycle, read operations in the bank will output the contents of the Status Register. Status Register bit SR7 should be read to check that the buffer is available (SR7 = 1). If the buffer is not available (SR7 = 0), re-issue the Buffer Program command to update the Status Register contents. 2. The second Bus Write cycle sets up the number of Words to be programmed. Value n is written to the same block address, where n+1 is the number of Words to be programmed. Use n+1 Bus Write cycles to load the address and data for each Word into the Write Buffer. Addresses must lie within the range from the start address to the start address + n, where the start address is the location of the first data to be programmed. Optimum performance is obtained when the start address corresponds to a 32 Word boundary. The final Bus Write cycle confirms the Buffer Program command and starts the program operation.
3.
4.
All the addresses used in the Buffer Program operation must lie within the same block. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will set an error in the Status Register and abort the operation without affecting the data in the memory array. If the Status Register bits SR4 and SR5 are set to '1', the Buffer Program Command is not accepted. Clear the Status Register before re-issuing the command. If the block being programmed is protected an error will be set in the Status Register and the operation will abort without affecting the data in the memory array. During Buffer Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. See Appendix C, Figure 22: Buffer Program flowchart and pseudo code, for a suggested flowchart on using the Buffer Program command.
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M58LR128HC, M58LR128HD
Command interface
4.10
Buffer Enhanced Factory Program command
The Buffer Enhanced Factory Program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical. It is used to program one or more Write Buffer(s) of 32 Words to a block. Once the device enters Buffer Enhanced Factory Program mode, the Write Buffer can be reloaded any number of times as long as the address remains within the same block. Only one block can be programmed at a time. If the block being programmed is protected, then the Program operation will abort, the data in the block will not be changed and the Status Register will output the error. The use of the Buffer Enhanced Factory Program command requires certain operating conditions:

VPP must be set to VPPH VDD must be within operating range Ambient temperature TA must be 30C 10C The targeted block must be unlocked The start address must be aligned with the start of a 32 Word buffer boundary The address must remain the Start Address throughout programming.
Dual operations are not supported during the Buffer Enhanced Factory Program operation and the command cannot be suspended. The Buffer Enhanced Factory Program Command consists of three phases: the Setup Phase, the Program and Verify Phase, and the Exit Phase, Please refer to Table 6: Factory Commands for detail information.
4.10.1
Setup Phase
The Buffer Enhanced Factory Program command requires two Bus Write cycles to initiate the command.

The first Bus Write cycle sets up the Buffer Enhanced Factory Program command. The second Bus Write cycle confirms the command.
After the confirm command is issued, read operations output the contents of the Status Register. The read Status Register command must not be issued as it will be interpreted as data to program. The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready to proceed to the next phase. If an error is detected, SR4 goes high (set to `1') and the Buffer Enhanced Factory Program operation is terminated. See Status Register section for details on the error.
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Command interface
M58LR128HC, M58LR128HD
4.10.2
Program and Verify Phase
The Program and Verify Phase requires 32 cycles to program the 32 Words to the Write Buffer. The data is stored sequentially, starting at the first address of the Write Buffer, until the Write Buffer is full (32 Words). To program less than 32 Words, the remaining Words should be programmed with FFFFh. Three successive steps are required to issue and execute the Program and Verify Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check that the P/E.C. is ready for the next Word. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address must remain the Start Address as the P/E.C. increments the address location.If any address that is not in the same block as the Start Address is given, the Program and Verify Phase terminates. Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next Word. Once the Write Buffer is full, the data is programmed sequentially to the memory array. After the program operation the device automatically verifies the data and reprograms if necessary.
2.
3.
The Program and Verify phase can be repeated, without re-issuing the command, to program additional 32 Word locations as long as the address remains in the same block. 4. Finally, after all Words, or the entire block have been programmed, write one Bus Write operation to any address outside the block containing the Start Address, to terminate Program and Verify Phase.
Status Register bit SR0 must be checked to determine whether the program operation is finished. The Status Register may be checked for errors at any time but it must be checked after the entire block has been programmed.
4.10.3
Exit Phase
Status Register P/E.C. bit SR7 set to `1' indicates that the device has exited the Buffer Enhanced Factory Program operation and returned to Read Status Register mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details. For optimum performance the Buffer Enhanced Factory Program command should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the internal algorithm will continue to work properly but some degradation in performance is possible. Typical program times are given in Table 17. See Appendix C, Figure 28: Buffer Enhanced Factory Program flowchart and pseudo code, for a suggested flowchart on using the Buffer Enhanced Factory Program command.
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M58LR128HC, M58LR128HD
Command interface
4.11
Program/Erase Suspend command
The Program/Erase Suspend command is used to pause a Program or Block Erase operation. The command can be addressed to any bank. The Program/Erase Resume command is required to restart the suspended operation. One bus write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be set to `1'. The following commands are accepted during Program/Erase Suspend: - - - - - Program/Erase Resume Read Array (data from erase-suspended block or program-suspended Word is not valid) Read Status Register Read Electronic Signature Read CFI Query.
Additionally, if the suspended operation was a Block Erase then the following commands are also accepted: - - - - - - - Clear Status Register Set Configuration Register Program (except in erase-suspended block) Buffer Program (except in erase suspended blocks) Block Lock Block Lock-Down Block Unlock.
During an erase suspend the block being erased can be protected by issuing the Block Lock or Block Lock-Down commands. When the Program/Erase Resume command is issued the operation will complete. It is possible to accumulate multiple suspend operations. For example: suspend an erase operation, start a program operation, suspend the program operation, then read the array. If a Program command is issued during a Block Erase Suspend, the erase operation cannot be resumed until the program operation has completed. The Program/Erase Suspend command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corresponding data. Refer to Dual Operations section for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to VIH. Program/erase is aborted if Reset, RP, goes to VIL. See Appendix C, Figure 23: Program Suspend & Resume flowchart and pseudo code, and Figure 25: Erase Suspend & Resume flowchart and pseudo code, for flowcharts for using the Program/Erase Suspend command.
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Command interface
M58LR128HC, M58LR128HD
4.12
Program/Erase Resume command
The Program/Erase Resume command is used to restart the program or erase operation suspended by the Program/Erase Suspend command. One Bus Write cycle is required to issue the command. The command can be issued to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corresponding data. If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the program operation has completed. See Appendix C, Figure 23: Program Suspend & Resume flowchart and pseudo code, and Figure 25: Erase Suspend & Resume flowchart and pseudo code, for flowcharts for using the Program/Erase Resume command.
4.13
Protection Register Program command
The Protection Register Program command is used to program the user One-TimeProgrammable (OTP) segments of the Protection Register and the two Protection Register Locks. The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as shown in Figure 4: Protection Register memory map. The segments are programmed one Word at a time. When shipped all bits in the segment are set to `1'. The user can only program the bits to `0'. Two Bus Write cycles are required to issue the Protection Register Program command.

The first bus cycle sets up the Protection Register Program command. The second latches the address and data to be programmed to the Protection Register and starts the Program/Erase Controller.
Read operations to the bank being programmed output the Status Register content after the program operation has started. Attempting to program a previously protected Protection Register will result in a Status Register error. The Protection Register Program cannot be suspended. Dual operations between the Parameter Bank and the Protection Register memory space are not allowed (see Table 15: Dual operation limitations for details) The two Protection Register Locks are used to protect the OTP segments from further modification. The protection of the OTP segments is not reversible. Refer to Figure 4: Protection Register memory map, and Table 8: Protection Register locks, for details on the Lock bits. See Appendix C, Figure 27: Protection Register Program flowchart and pseudo code, for a flowchart for using the Protection Register Program command.
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M58LR128HC, M58LR128HD
Command interface
4.14
Set Configuration Register command
The Set Configuration Register command is used to write a new value to the Configuration Register. Two Bus Write cycles are required to issue the Set Configuration Register command.

The first cycle sets up the Set Configuration Register command and the address corresponding to the Configuration Register content. The second cycle writes the Configuration Register data and the confirm command.
The Configuration Register data must be written as an address during the bus write cycles, that is ADQ0 = CR0, ADQ1 = CR1, ..., ADQ15 = CR15. Addresses A16-Amax are ignored. Read operations output the array content after the Set Configuration Register command is issued. The Read Electronic Signature command is required to read the updated contents of the Configuration Register.
4.15
Block Lock command
The Block Lock command is used to lock a block and prevent program or erase operations from changing the data in it. All blocks are locked after power-up or reset. Two Bus Write cycles are required to issue the Block Lock command.

The first bus cycle sets up the Block Lock command. The second Bus Write cycle latches the block address and locks the block.
The lock status can be monitored for each block using the Read Electronic Signature command. Table 16 shows the Lock Status after issuing a Block Lock command. Once set, the Block Lock bits remain set even after a hardware reset or power-down/powerup. They are cleared by a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation. See Appendix C, Figure 26: Locking operations flowchart and pseudo code, for a flowchart for using the Lock command.
4.16
Block Unlock command
The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Block Unlock command.

The first bus cycle sets up the Block Unlock command. The second Bus Write cycle latches the block address and unlocks the block.
The lock status can be monitored for each block using the Read Electronic Signature command. Table 16 shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 26: Locking operations flowchart and pseudo code, for a flowchart for using the Block Unlock command.
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Command interface
M58LR128HC, M58LR128HD
4.17
Block Lock-Down command
The Block Lock-Down command is used to lock-down a locked or unlocked block. A locked-down block cannot be programmed or erased. The lock status of a locked-down block cannot be changed when WP is low, VIL. When WP is high, VIH, the lock-down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block Lock-Down command.

The first bus cycle sets up the Block Lock-Down command. The second Bus Write cycle latches the block address and locks-down the block.
The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 16 shows the Lock Status after issuing a Block Lock-Down command. Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 26: Locking operations flowchart and pseudo code, for a flowchart for using the Lock-Down command.
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M58LR128HC, M58LR128HD Table 5. Standard commands(1)
Bus operations Cycles Commands 1st cycle Op. Read Array Read Status Register Read Electronic Signature Read CFI Query Clear Status Register Block Erase Program 1+ 1+ 1+ 1+ 1 2 2 Write Write Write Write Write Write Write Write Buffer Program(4) n+4 Write Write Program/Erase Suspend Program/Erase Resume Protection Register Program Set Configuration Register Block Lock Block Unlock Block Lock-Down 1 1 2 2 2 2 2 Write Write Write Write Write Write Write Add BKA BKA BKA BKA X BKA or BA(3) BKA or WA(3) BA PA1 PAn+1 X X PRA CRD BKA or BA(3) BKA or BA(3) BKA or BA(3) Data FFh 70h 90h 98h 50h 20h 40h or 10h E8h PD1 PDn+1 B0h D0h C0h 60h 60h 60h 60h Op.
Command interface
2nd cycle Add WA BKA(2) BKA
(2)
Data RD SRD ESD QD
Read Read Read Read
BKA(2)
Write Write Write Write Write
BA WA BA PA2 X
D0h PD n PD2 D0h
Write Write Write Write Write
PRA CRD BA BA BA
PRD 03h 01h D0h 2Fh
1. X = Don't Care, WA = Word Address in targeted bank, RD = Read Data, SRD = Status Register Data, ESD = Electronic Signature Data, QD = Query Data, BA = Block Address, BKA = Bank Address, PD = Program Data, PRA = Protection Register Address, PRD = Protection Register Data, CRD = Configuration Register Data. 2. Must be same bank as in the first cycle. The signature addresses are listed in Table 7. 3. Any address within the bank can be used. 4. n+1 is the number of Words to be programmed.
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Command interface Table 6. Factory Commands
M58LR128HC, M58LR128HD
Bus Write operations(1) Command Phase Cycles 1st Add Blank Check Setup 2 2 BA BKA or WA(2) WA1 NOT BA1(4) 2nd 3rd Final -1 Add Data Final Add Data
Data Add Data Add Data BCh 80h PD1 X BA WA1 WA1 CBh D0h PD2 WA1 PD3
Buffer Enhanced Program/ 32 Factory Verify(3) Program Exit 1
WA1 PD31 WA1 PD32
1. WA = Word Address in targeted bank, BKA = Bank Address, PD = Program Data, BA = Block Address, X = Don't Care. 2. Any address within the bank can be used. 3. The Program/Verify phase can be executed any number of times as long as the data is to be programmed to the same block. 4. WA1 is the Start Address, NOT BA1 = Not Block Address of WA1.
Table 7.
Electronic signature codes
Code Address (h) Bank Address + 00 Top Bank Address + 01 Bank Address + 01 Data (h) 0020 882E (M58LR128HC) 882F (M58LR128HD) 0001 0000 Block Address + 02 Locked and Locked-Down Unlocked and Locked-Down 0003 0002 Bank Address + 03 Bank Address + 05 Numonyx Factory Default DRC(1) CR(1) 0002 Bank Address + 80 0000 Bank Address + 81 Bank Address + 84 Unique Device Number OTP Area PRLD(1) OTP Area
Manufacturer Code Device Code Bottom Locked Unlocked Block Protection
Die Revision Code Configuration Register Protection Register PR0 Lock
OTP Area Permanently Locked
Protection Register PR0 Bank Address + 85 Bank Address + 88 Protection Register PR1 through PR16 Lock Protection Registers PR1-PR16 Bank Address + 89 Bank Address + 8A Bank Address + 109
1. CR = Configuration Register, PRLD = Protection Register Lock Data, DRC = Die Revision Code.
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M58LR128HC, M58LR128HD Figure 4. Protection Register memory map
PROTECTION REGISTERS
Command interface
109h
PR16
User Programmable OTP
102h
91h
PR1
User Programmable OTP
8Ah Protection Register Lock 89h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
88h 85h 84h
PR0 User Programmable OTP
Unique device number 81h 80h Protection Register Lock 10
AI07563
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Command interface Table 8. Protection Register locks
Lock
M58LR128HC, M58LR128HD
Description Number Address Bits Bit 0 Lock 1 80h Bit 1 preprogrammed to protect Unique Device Number, address 81h to 84h in PR0 protects 64bits of OTP segment, address 85h to 88h in PR0
Bits 2 to 15 reserved Bit 0 Bit 1 Bit 2 ---Lock 2 89h protects 128bits of OTP segment PR1 protects 128bits of OTP segment PR2 protects 128bits of OTP segment PR3 ---protects 128bits of OTP segment PR14 protects 128bits of OTP segment PR15 protects 128bits of OTP segment PR16
Bit 13 Bit 14 Bit 15
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M58LR128HC, M58LR128HD
Status Register
5
Status Register
The Status Register provides information on the current or previous program or erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to VIH. The Status Register can only be read using single Asynchronous or Single Synchronous reads. Bus Read operations from any address within the bank, always read the Status Register during program and erase operations. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to `1' the Status Register should be reset before issuing another command. The bits in the Status Register are summarized in Table 9: Status Register bits. Refer to Table 9 in conjunction with the following text descriptions.
5.1
Program/Erase Controller status bit (SR7)
The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller Status bit is Low (set to `0'), the Program/Erase Controller is active; when the bit is High (set to `1'), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status bit is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High.
5.2
Erase Suspend status bit (SR6)
The Erase Suspend Status bit indicates that an erase operation has been suspended in the addressed block. When the Erase Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status bit should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR6 is set within the Erase Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low.
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Status Register
M58LR128HC, M58LR128HD
5.3
Erase/Blank Check status bit (SR5)
The Erase/Blank Check Status bit is used to identify if there was an error during a Block Erase operation. When the Erase/Blank Check Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that it has erased correctly. The Erase/Blank Check Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). The Erase/Blank Check Status bit is also used to indicate whether an error occurred during the Blank Check operation: if the data at one or more locations in the block where the Blank Check command has been issued is different from FFFFh, SR5 is set to '1'. Once set High, the Erase/Blank Check Status bit must be set Low by a Clear Status Register command or a hardware reset before a new erase command is issued, otherwise the new command will appear to fail.
5.4
Program status bit (SR4)
The Program Status bit is used to identify if there was an error during a program operation. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the Word and still failed to verify that it has programmed correctly. Attempting to program a '1' to an already programmed bit while VPP = VPPH will also set the Program Status bit High. If VPP is different from VPPH, SR4 remains Low (set to '0') and the attempt is not shown. Once set High, the Program Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program command is issued, otherwise the new command will appear to fail.
5.5
VPP status bit (SR3)
The VPP Status bit is used to identify an invalid voltage on the VPP pin during program and erase operations. The VPP pin is only sampled at the beginning of a program or erase operation. Program and erase operations are not guaranteed if VPP becomes invalid during an operation When the VPP Status bit is Low (set to `0'), the voltage on the VPP pin was sampled at a valid voltage. When the VPP Status bit is High (set to `1'), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK, the memory is protected and program and erase operations cannot be performed. Once set High, the VPP Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued, otherwise the new command will appear to fail.
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M58LR128HC, M58LR128HD
Status Register
5.6
Program Suspend status bit (SR2)
The Program Suspend Status bit indicates that a program operation has been suspended in the addressed block. The Program Suspend Status bit should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low.
5.7
Block Protection status bit (SR1)
The Block Protection Status bit is used to identify if a Program or Block Erase operation has tried to modify the contents of a locked or locked-down block. When the Block Protection Status bit is High (set to `1'), a program or erase operation has been attempted on a locked or locked-down block Once set High, the Block Protection Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued, otherwise the new command will appear to fail.
5.8
Bank Write/Multiple Word Program status bit (SR0)
The Bank Write Status bit indicates whether the addressed bank is programming or erasing. In Buffer Enhanced Factory Program mode the Multiple Word Program bit shows if the device is ready to accept a new Word to be programmed to the memory array. The Bank Write Status bit should only be considered valid when the Program/Erase Controller Status SR7 is Low (set to `0'). When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low (set to `0'), the addressed bank is executing a program or erase operation. When the Program/Erase Controller Status bit is Low (set to `0') and the Bank Write Status bit is High (set to `1'), a program or erase operation is being executed in a bank other than the one being addressed. In Buffer Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to `0'), the device is ready for the next Word, if the Multiple Word Program Status bit is High (set to `1') the device is not ready for the next Word. For further details on how to use the Status Register, see the Flowcharts and Pseudocodes provided in Appendix C.
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Status Register Table 9.
Bit
M58LR128HC, M58LR128HD Status Register bits
Name Type Logic Level(1) '1' Ready Busy Erase Suspended Erase In progress or Completed Erase/Blank Check Error Erase/Blank Check Success Program Error Program Success VPP Invalid, Abort VPP OK Program Suspended Program In Progress or Completed Program/Erase on protected Block, Abort No operation to protected blocks SR7 = `1' Not Allowed '1' SR7 = `0' Bank Write Status Status SR7 = `1' '0' SR7 = `0' Program or erase operation in addressed bank Program or erase operation in a bank other than the addressed bank No Program or erase operation in the device Definition
SR7 P/E.C. Status Erase Suspend Status Erase/Blank Check Status
Status '0' '1' Status '0' '1' Error '0' '1' Error '0' '1'
SR6
SR5
SR4 Program Status
SR3 VPP Status Program Suspend Status Block Protection Status
Error '0' '1' Status '0' '1' Error '0'
SR2
SR1
SR0 SR7 = `1' Not Allowed Multiple Word Program Status (Buffer Enhanced Factory Program mode) '1' Status '0' SR7 = `0'
1. Logic level '1' is High, '0' is Low.
the device is NOT ready for the next SR7 = `0' Buffer loading or is going to exit the BEFP mode SR7 = `1' the device has exited the BEFP mode the device is ready for the next Buffer loading
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M58LR128HC, M58LR128HD
Configuration Register
6
Configuration Register
The Configuration Register is used to configure the type of bus access that the memory will perform. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface using the Set Configuration Register command. After a reset or power-up the device is configured for asynchronous read (CR15 = 1). The Configuration Register bits are described in Table 11 They specify the selection of the burst length, burst type, burst X latency and the read operation. Refer to Figures 5 and 6 for examples of synchronous burst configurations.
6.1
Read Select bit (CR15)
The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous Read operations. When the Read Select bit is set to '1', read operations are asynchronous; when the Read Select bit is set to '0', read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the Read Select bit is set to '1' for asynchronous access.
6.2
X-Latency bits (CR13-CR11)
The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address being latched and the first data becoming available. Refer to Figure 5: X-Latency and data output configuration example. For correct operation the X-Latency bits can only assume the values in Table 11: Configuration Register. Table 10 shows how to set the X-Latency parameter, taking into account the speed class of the device and the Frequency used to read the Flash memory in Synchronous mode. Table 10. X-latency settings
fmax 30 MHz 40 MHz 54 MHz 66 MHz tKmin 33 ns 25 ns 19 ns 15 ns X-Latency min 2 3 4 4
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Configuration Register
M58LR128HC, M58LR128HD
6.3
Wait Polarity bit (CR10)
The Wait Polarity bit is used to set the polarity of the Wait signal used in Synchronous Burst Read mode. During Synchronous Burst Read mode the Wait signal indicates whether the data output are valid or a WAIT state must be inserted. When the Wait Polarity bit is set to `0' the Wait signal is active Low. When the Wait Polarity bit is set to `1' the Wait signal is active High.
6.4
Data Output Configuration bit (CR9)
The Data Output Configuration bit is used to configure the output to remain valid for either one or two clock cycles during synchronous mode. When the Data Output Configuration Bit is '0' the output data is valid for one clock cycle, when the Data Output Configuration Bit is '1' the output data is valid for two clock cycles. The Data Output Configuration must be configured using the following condition:
tK > tKQV + tQVK_CPU tK is the clock period tQVK_CPU is the data setup time required by the system CPU tKQV is the clock to data valid time.
where

If this condition is not satisfied, the Data Output Configuration bit should be set to `1' (two clock cycles). Refer to Figure 5: X-Latency and data output configuration example.
6.5
Wait Configuration bit (CR8)
The Wait Configuration bit is used to control the timing of the Wait output pin, WAIT, in Synchronous Burst Read mode. When WAIT is asserted, Data is Not Valid and when WAIT is deasserted, Data is Valid. When the Wait Configuration bit is Low (set to '0') the Wait output pin is asserted during the WAIT state. When the Wait Configuration bit is High (set to '1'), the Wait output pin is asserted one data cycle before the WAIT state.
6.6
Burst type bit (CR7)
The Burst Type bit determines the sequence of addresses read during Synchronous Burst Reads. The Burst Type bit is High (set to '1'), as the memory outputs from sequential addresses only. See Table 12: Burst type definition, for the sequence of addresses output from a given starting address in sequential mode.
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M58LR128HC, M58LR128HD
Configuration Register
6.7
Valid Clock edge bit (CR6)
The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during synchronous read operations. When the Valid Clock Edge bit is Low (set to '0') the falling edge of the Clock is the active edge. When the Valid Clock Edge bit is High (set to '1') the rising edge of the Clock is the active edge.
6.8
Wrap burst bit (CR3)
The Wrap Burst bit, CR3, is used to select between wrap and no wrap. Synchronous burst reads can be confined inside the 4, 8 or 16 Word boundary (wrap) or overcome the boundary (no wrap). When the Wrap Burst bit is Low (set to `0') the burst read wraps. When it is High (set to `1') the burst read does not wrap.
6.9
Burst length bits (CR2-CR0)
The Burst Length bits are used to set the number of Words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 Words, 8 Words, 16 Words or continuous burst, where all the Words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode, in 4, 8 or 16 Words no-wrap, depending on the starting address, the device asserts the WAIT signal to indicate that a delay is necessary before the data is output. If the starting address is shifted by 1, 2 or 3 positions from the four-Word boundary, WAIT is asserted for 1, 2 or 3 clock cycles, respectively, when the burst sequence crosses the first 16-Word boundary, to indicate that the device needs an internal delay to read the successive Words in the array. WAIT will be asserted only once during a continuous burst access. See also Table 12: Burst type definition. CR14, CR5 and CR4 are reserved for future use.
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Configuration Register Table 11.
Bit CR15 CR14
M58LR128HC, M58LR128HD Configuration Register
Description Read Select 1 Reserved 010 011 100 2 clock latency(1) 3 clock latency 4 clock latency 5 clock latency 6 clock latency 7 clock latency (default) Asynchronous Read (Default at power-on) Value 0 Description Synchronous Read
CR13-CR11
X-Latency
101 110 111
Other configurations reserved 0 CR10 Wait Polarity 1 CR9 Data Output Configuration 0 1 0 CR8 Wait Configuration 1 0 CR7 Burst Type 1 0 CR6 CR5-CR4 CR3 Valid Clock Edge 1 Reserved 0 Wrap Burst 1 001 010 CR2-CR0 Burst Length 011 111 16 Words Continuous (default) No Wrap (default) 4 Words 8 Words Wrap Rising Clock edge (default) Sequential (default) Falling Clock edge WAIT is active High Data held for one clock cycle Data held for two clock cycles (default)(1) WAIT is active during WAIT state (default) WAIT is active one data cycle before WAIT state(1) Reserved WAIT is active Low (default)
1. The combination X-Latency=2, Data held for two clock cycles and Wait active one data cycle before the WAIT state is not supported.
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M58LR128HC, M58LR128HD Table 12.
Mode Start Add 0 1 2 3 Wrap ... 7 ... 12 13 14 15 7-4-5-6 7-0-1-2-3-4-56 7-8-9-10-11-12-13-1415-0-1-2-3-4-5-6
Configuration Register
Burst type definition
4 Words Sequential 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8 Words Sequential 0-1-2-3-4-5-67 1-2-3-4-5-6-70 2-3-4-5-6-7-01 16 Words Continuous Burst Sequential 0-1-2-3-4-5-6-7-8-9-1011-12-13-14-15 1-2-3-4-5-6-7-8-9-1011-12-13-14-15-0 2-3-4-5-6-7-8-9-10-1112-13-14-15-0-1 0-1-2-3-4-5-6... 1-2-3-4-5-6-7-...15-WAIT-16-1718... 2-3-4-5-6-7...15-WAIT-WAIT-1617-18... 3-4-5-6-7...15-WAIT-WAITWAIT-16-17-18...
3-4-5-6-7-0-1- 3-4-5-6-7-8-9-10-11-122 13-14-15-0-1-2
7-8-9-10-11-12-13-14-15-WAITWAIT-WAIT-16-17...
12-13-14-15-16-17-18... 13-14-15-WAIT-16-17-18... 14-15-WAIT-WAIT-16-17-18.... 15-WAIT-WAIT-WAIT-16-17-18...
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Configuration Register Table 12.
Mode Start Add 0
M58LR128HC, M58LR128HD Burst type definition (continued)
4 Words Sequential 0-1-2-3 8 Words Sequential 0-1-2-3-4-5-67 1-2-3-4-5-6-78 2-3-4-5-6-7-89... 3-4-5-6-7-8-910 16 Words Continuous Burst Sequential 0-1-2-3-4-5-6-7-8-9-1011-12-13-14-15 1-2-3-4-5-6-7-8-9-1011-12-13-14-15-WAIT16 2-3-4-5-6-7-8-9-10-1112-13-14-15-WAITWAIT-16-17 3-4-5-6-7-8-9-10-11-1213-14-15-WAIT-WAITWAIT-16-17-18
1
1-2-3-4
2
2-3-4-5
3 ... 7 ... 12
3-4-5-6
No-wrap
7-8-9-10
7-8-9-10-1112-13-14
7-8-9-10-11-12-13-1415-WAIT-WAIT-WAIT16-17-18-19-20-21-22
Same as for Wrap (Wrap /No Wrap has no effect on Continuous Burst)
12-13-1415 13-14-15WAIT-16 14-15WAITWAIT-1617 15-WAITWAITWAIT-1617-18
12-13-14-1516-17-18-19 13-14-15WAIT-16-1718-19-20 14-15-WAITWAIT-16-1718-19-20-21 15-WAITWAIT-WAIT16-17-18-1920-21-22
12-13-14-15-16-17-1819-20-21-22-23-24-2526-27 13-14-15-WAIT-16-1718-19-20-21-22-23-2425-26-27-28 14-15-WAIT-WAIT-1617-18-19-20-21-22-2324-25-26-27-28-29 15-WAIT-WAIT-WAIT16-17-18-19-20-21-2223-24-25-26-27-28-2930
13
14
15
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M58LR128HC, M58LR128HD Figure 5. X-Latency and data output configuration example
X-latency 1st cycle K 2nd cycle 3rd cycle 4th cycle
Configuration Register
E
L
A22-A16
VALID ADDRESS tQVK_CPU tKQV tK
ADQ15-ADQ0 VALID ADDRESS VALID DATA VALID DATA
AI12321
1. The settings shown are X-latency = 4, Data Output held for one clock cycle.
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Configuration Register Figure 6.
E
M58LR128HC, M58LR128HD
Wait configuration example
K
L
G
A22-A16
VALID ADDRESS
ADQ15-ADQ0
VALID ADDRESS
VALID DATA VALID DATA
NOT VALID
VALID DATA
WAIT CR8 = '0' CR10 = '0' WAIT CR8 = '1' CR10 = '0' WAIT CR8 = '0' CR10 = '1' WAIT CR8 = '1' CR10 = '1'
AI12322
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M58LR128HC, M58LR128HD
Read modes
7
Read modes
Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is `don't care' for the data output, the read operation is asynchronous; if the data output is synchronized with clock, the read operation is synchronous. The read mode and format of the data output are determined by the Configuration Register. (See Configuration Register section for details). All banks support both asynchronous and synchronous read operations.
7.1
Asynchronous Read mode
In Asynchronous Read operations the clock signal is `don't care'. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to `1' for asynchronous operations. The device features an Automatic Standby mode. During Asynchronous Read operations, after a bus inactivity of 150ns, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. In Asynchronous Read mode, the WAIT signal is always de-asserted. See Table 23: Asynchronous Read AC characteristics, Figure 9: asynchronous random access Read AC waveforms, for details.
7.2
Synchronous Burst Read mode
In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence starts at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and data is output on each data cycle after a delay which depends on the X latency bits CR13-CR11 of the Configuration Register. The number of Words to be output during a Synchronous Burst Read operation can be configured as 4 Words, 8 Words, 16 Words or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9). The order of the data output can be modified through the Wrap Burst bit in the Configuration Register. The burst sequence is sequential and can be confined inside the 4, 8 or 16 Word boundary (Wrap) or overcome the boundary (No Wrap).
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Read modes
M58LR128HC, M58LR128HD
The WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence and on the burst configuration. WAIT is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16 Word burst. It is only deasserted when output data are valid or when G is at VIH. In Continuous Burst Read mode a WAIT state will occur when crossing the first 16 Word boundary. If the starting address is aligned to the Burst Length (4, 8 or 16 Words) the wrapped configuration has no impact on the output sequence. The WAIT signal can be configured to be active Low or active High by setting CR10 in the Configuration Register. See Table 24: Synchronous Read AC characteristics, and Figure 10: Synchronous Burst Read AC waveforms, for details.
7.2.1
Synchronous Burst Read Suspend
A Synchronous Burst Read operation can be suspended, freeing the data bus for other higher priority devices. It can be suspended during the initial access latency time (before data is output) or after the device has output data. When the Synchronous Burst Read operation is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. A Synchronous Burst Read operation is suspended when Chip Enable, E, is Low and the current address has been latched (on a Latch Enable rising edge or on a valid clock edge). The Clock signal is then halted at VIH or at VIL, and Output Enable, G, goes High. When Output Enable, G, becomes Low again and the Clock signal restarts, the Synchronous Burst Read operation is resumed exactly where it stopped. WAIT being gated by E, it will remain active and will not revert to high impedance when G goes High. So if two or more devices are connected to the system's READY signal, to prevent bus contention the WAIT signal of the M58LR128HC/D should not be directly connected to the system's READY signal. WAIT will revert to high-impedance when Chip Enable, E, goes High. See Table 24: Synchronous Read AC characteristics, and Figure 12: Synchronous Burst Read Suspend AC waveforms, for details.
7.3
Single Synchronous Read mode
Single Synchronous Read operations are similar to Synchronous Burst Read operations except that the memory outputs the same data to the end of the operation. Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Configuration Register Status or Protection Register. When the addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is deasserted when Output Enable, G, is at VIH or for the one clock cycle during which output data is valid. Otherwise, it is asserted. See Table 24: Synchronous Read AC characteristics, and Figure 10: Synchronous Burst Read AC waveforms, for details.
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M58LR128HC, M58LR128HD
Dual operations and Multiple Bank architecture
8
Dual operations and Multiple Bank architecture
The Multiple Bank Architecture of the M58LR128HC/D gives greater flexibility for software developers to split the code and data spaces within the memory array. The Dual Operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. The Dual Operations feature means that while programming or erasing in one bank, read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in program or erase mode). If a read operation is required in a bank, which is programming or erasing, the program or erase operation can be suspended. Also if the suspended operation was erase then a program command can be issued to another block, so the device can have one block in Erase Suspend mode, one programming and other banks in read mode. Bus Read operations are allowed in another bank between setup and confirm cycles of program or erase operations. By using a combination of these features, read operations are possible at any moment in the M58LR128HC/D device. Dual operations between the Parameter Bank and either of the CFI, the OTP or the Electronic Signature memory space are not allowed. Table 15 shows which dual operations are allowed or not between the CFI, the OTP, the Electronic Signature locations and the memory array. Tables 13 and 14 show the dual operations possible in other banks and in the same bank. Table 13. Dual operations allowed in other banks
Commands allowed in another bank Status of bank Read Array Yes Yes Yes Yes Yes Read Read Read Status CFI Electronic Register Query Signature Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Program, Buffer Program Yes - - - Yes Block Erase Yes - - - - Program Program /Erase /Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes
Idle Programming Erasing Program Suspended Erase Suspended
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Dual operations and Multiple Bank architecture Table 14. Dual operations allowed in same bank
M58LR128HC, M58LR128HD
Commands allowed in same bank Status of bank Read Array Yes - -
(1) (1)
Read Read Read Status CFI Electronic Register Query Signature Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Program, Buffer Program Yes - - - Yes(1)
Block Erase Yes - - - -
Program Program /Erase /Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes
Idle Programming Erasing Program Suspended Erase Suspended
Yes(2) Yes(2)
1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed. 2. Not allowed in the Block that is being erased or in the Word that is being programmed.
Table 15.
Dual operation limitations
Commands allowed Read Main Blocks
Current Status
Read CFI / OTP / Electronic Signature
Read Parameter Blocks
Located in Parameter Bank No
Not Located in Parameter Bank Yes
Programming / Erasing Parameter Blocks Located in Parameter Bank Not Located in Parameter Bank
No
No
Yes
No
No
Yes
Programming / Erasing Main Blocks
Yes No
Yes No
Yes No
In Different Bank Only No
Programming OTP
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M58LR128HC, M58LR128HD
Block locking
9
Block locking
The M58LR128HC/D features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection.

Lock/Unlock - this first level allows software only control of block locking. Lock-Down - this second level requires hardware interaction before locking can be changed. VPP VPPLK - the third level offers a complete hardware protection against program and erase on all blocks.
The protection status of each block can be set to Locked, Unlocked, and Locked-Down. Table 16, defines all of the possible protection states (WP, ADQ1, ADQ0), and Appendix C, Figure 26, shows a flowchart for the locking operations.
9.1
Reading a Block's lock status
The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode issue the Read Electronic Signature command. Subsequent reads at the address specified in Table 7, will output the protection status of that block. The lock status is represented by ADQ0 and ADQ1. ADQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. ADQ0 is automatically set when entering Lock-Down. ADQ1 indicates the Lock-Down status and is set by the Lock-Down command. ADQ1 cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system.
9.2
Locked state
The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from program or erase operations. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Locked-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command.
9.3
Unlocked state
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powereddown. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command.
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Block locking
M58LR128HC, M58LR128HD
9.4
Lock-Down state
Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. Locked-Down blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the Write Protect, WP, input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When WP=1 (VIH) the Lock-Down function is disabled (1,1,x) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. When the Lock-Down function is disabled (WP=1) blocks can be locked (1,1,1) and unlocked (1,1,0) as desired. When WP=0 blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes that were made while WP=1. Device reset or power-down resets all blocks, including those in Lock-Down, to the Locked state.
9.5
Locking operations during Erase Suspend
Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the Status Register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend.
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M58LR128HC, M58LR128HD Table 16. Lock status
Next Protection Status(1) (WP, ADQ1, ADQ0) After Block Lock Command 1,0,1 1,0,1 1,1,1 1,1,1 0,0,1 0,0,1 0,1,1 After Block Unlock Command 1,0,0 1,0,0 1,1,0 1,1,0 0,0,0 0,0,0 0,1,1 After Block Lock-Down Command 1,1,1 1,1,1 1,1,1 1,1,1 0,1,1 0,1,1 0,1,1
Block locking
Current Protection Status(1) (WP, ADQ1, ADQ0) Current State 1,0,0 1,0,1
(2)
Program/Erase Allowed yes no yes no yes no no
After WP transition 0,0,0 0,0,1 0,1,1 0,1,1 1,0,0 1,0,1 1,1,1 or 1,1,0(3)
1,1,0 1,1,1 0,0,0 0,0,1
(2)
0,1,1
1. The lock status is defined by the write protect pin and by ADQ1 (`1' for a locked-down block) and ADQ0 (`1' for a locked block) as read in the Read Electronic Signature command with ADQ1 = VIH and ADQ0 = VIL. 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. 3. A WP transition to VIH on a locked block will restore the previous ADQ0 value, giving a 111 or 110.
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Program and erase times and endurance cycles
M58LR128HC, M58LR128HD
10
Program and erase times and endurance cycles
The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 17. Exact erase times may change depending on the memory array condition. The best case is when all the bits in the block are at `0' (pre-programmed). The worst case is when all the bits in the block are at `1' (not preprogrammed). Usually, the system overhead is negligible with respect to the erase time. In the M58LR128HC/D the maximum number of Program/Erase cycles depends on the VPP voltage supply used.
Table 17.
Program/Erase times and endurance cycles(1) (2)
Condition Parameter Block (16 KWord) Min Typ 0.4 1.2 1.5 12 12 384 768 5 5 100,000 100,000 10 20 Typical after 100kW/E Cycles 1 3 Max 2.5 4 4 180 180 Unit s s s s s s ms s s cycles cycles
Parameter
Erase
Main Block (64 KWord) Single Word
Preprogrammed Not Preprogrammed Word Program
VPP = VDD
Program(3)
Buffer Program Buffer (32 Words) (Buffer Program) Main Block (64 KWord) Program
Suspend Latency Erase Main Blocks Program/Erase Cycles (per Block) Parameter Blocks
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M58LR128HC, M58LR128HD Table 17.
Program and erase times and endurance cycles
Program/Erase times and endurance cycles(1) (2) (continued)
Condition Parameter Block (16 KWord) Min Typ 0.4 1 10 2.5 80 80 160 160 1.28 1.28 1000 2500 16 4 Typical after 100kW/E Cycles Max 2.5 4 170 Unit s s s s s s ms ms s s cycles cycles ms ms
Parameter
Erase Main Block (64 KWord) Word Program Single Word Buffer Enhanced Factory Program(4) Buffer Program Buffer (32 Words) VPP = VPPH Program
(3)
Buffer Enhanced Factory Program Buffer Program
Main Block (64 KWords)
Buffer Enhanced Factory Program Buffer Program
Bank (8 Mbits)
Buffer Enhanced Factory Program
Main Blocks Program/Erase Cycles (per Block) Parameter Blocks Main Blocks Blank Check Parameter Blocks
1. TA = -25 to 85C; VDD = 1.7V to 2V; VDDQ = 1.7V to 2V.
2. Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution). 3. Excludes the time needed to execute the command sequence. 4. This is an average value on the entire device.
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Maximum rating
M58LR128HC, M58LR128HD
11
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 18.
Symbol TA TBIAS TSTG VIO VDD VDDQ VPP IO tVPPH
Absolute maximum ratings
Value Parameter Min Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Input/Output Supply Voltage Program Voltage Output Short Circuit Current Time for VPP at VPPH -25 -25 -65 -0.5 -0.2 -0.2 -0.2 Max 85 85 125 3.8 2.5 2.5 10 100 100 C C C V V V V mA hours Unit
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M58LR128HC, M58LR128HD
DC and AC parameters
12
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 19: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 19. Operating and AC measurement conditions
M58LR128HC/D Parameter Min VDD supply voltage VDDQ supply voltage VPP supply voltage (factory environment) VPP supply voltage (application environment) Ambient operating temperature Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages 0 to VDDQ VDDQ/2 1.7 1.7 8.5 -0.4 -25 30 5 70 Max 2.0 2.0 9.5 VDDQ+0.4 85 V V V V C pF ns V V Units
Figure 7.
AC measurement I/O waveform
VDDQ VDDQ/2 0V
AI06161
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DC and AC parameters Figure 8. AC measurement load circuit
VDDQ
M58LR128HC, M58LR128HD
VDDQ VDD 16.7k DEVICE UNDER TEST 0.1F 0.1F CL 16.7k
CL includes JIG capacitance
AI06162
Table 20.
Symbol CIN COUT
Capacitance(1)
Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min 6 8 Max 8 12 Unit pF pF
1. Sampled only, not 100% tested.
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M58LR128HC, M58LR128HD Table 21.
Symbol ILI ILO
DC and AC parameters
DC characteristics - currents
Parameter Input Leakage Current Output Leakage Current Supply Current Asynchronous Read (f=5MHz) Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, G = VIH 4 Word 13 18 20 25 28 22 22 22 8 10 8 10 23 Typ Max 1 1 15 20 22 27 30 50 50 50 20 25 20 25 40 Unit A A mA mA mA mA mA A A A mA mA mA mA mA
IDD1
Supply Current Synchronous Read (f=66MHz)
8 Word 16 Word Continuous
IDD2 IDD3 IDD4
Supply Current (Reset) Supply Current (Standby) Supply Current (Automatic Standby) Supply Current (Program)
RP = VSS 0.2V E = VDD 0.2V K=VSS E = VIL, G = VIH VPP = VPPH VPP = VDD
IDD5(1) Supply Current (Erase)
VPP = VPPH VPP = VDD Program/Erase in one Bank, Asynchronous Read in another Bank Program/Erase in one Bank, Synchronous Read (Continuous f=66MHz) in another Bank E = VDD 0.2V K=VSS VPP = VPPH VPP = VDD VPP = VPPH VPP = VDD VPP VDD VPP VDD
Supply Current IDD6(1),(2) (Dual Operations)
38
55
mA
IDD7(1)
Supply Current Program/ Erase Suspended (Standby) VPP Supply Current (Program)
22 2 0.2 2 0.2 0.2 0.2
50 5 5 5 5 5 5
A mA A mA A A A
IPP1(1) VPP Supply Current (Erase) IPP2 IPP3
(1)
VPP Supply Current (Read) VPP Supply Current (Standby)
1. Sampled only, not 100% tested. 2. VDD Dual Operation current is the sum of read and program or erase currents.
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DC and AC parameters Table 22.
Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO VRPH
M58LR128HC, M58LR128HD
DC characteristics - voltages
Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP Program Voltage-Logic VPP Program Voltage Factory Program or Erase Lockout VDD Lock Voltage RP pin Extended High Voltage IOL = 100A IOH = -100A Program, Erase Program, Erase VDDQ -0.1 1.3 8.5 1.8 9.0 3.3 9.5 0.4 1 3.3 Test Condition Min 0 VDDQ -0.4 Typ Max 0.4 VDDQ + 0.4 0.1 Unit V V V V V V V V V
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tAVQV ADQ0-ADQ15 VALID DATA VALID ADDRESS Hi-Z
M58LR128HC, M58LR128HD Figure 9.
A16-A22 VALID ADDRESS tAVAV tAVLH L tLLLH tLLQV tELLH E tELQV tEHQZ tEHQX G tGLQV tGLQX tELTV WAIT(1) Hi-Z tGHQX tLHGL tLHAX
VALID
asynchronous random access Read AC waveforms
tGHQZ tEHTZ
Valid Address Latch Notes: 1- Write Enable, W, is High, WAIT is active Low.
Outputs Enabled
Data Valid
Standby
AI12322
DC and AC parameters
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DC and AC parameters Table 23.
Symbol tAVAV tAVQV tELTV tELQV(2) Read Timings tEHTZ tEHQX(1) tEHQZ(1) tGLQV(2) tGLQX(1) tGHQX
(1)
M58LR128HC, M58LR128HD Asynchronous Read AC characteristics
M58LR128HC/D Alt tRC tACC Parameter 70 Address Valid to Next Address Valid Address Valid to Output Valid (Random) Chip Enable Low to Wait Valid tCE Chip Enable Low to Output Valid Chip Enable High to Wait Hi-Z tOH tHZ tOE tOLZ tOH tDF tAVADVH tELADVH tADVHAX Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Address Valid to Latch Enable High Chip Enable Low to Latch Enable High Latch Enable High to Address Transition Min Max Max Max Max Min Max Max Min Min Max Min Min Min Min Max Min 70 70 11 70 14 0 14 20 0 0 14 7 10 7 7 70 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tGHQZ(1) tAVLH Latch Timings tELLH tLHAX tLLLH tLLQV tLHGL
tADVLADVH Latch Enable Pulse Width tADVLQV tADVHGL Latch Enable Low to Output Valid (Random) Latch Enable High to Output Enable Low
1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
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M58LR128HC, M58LR128HD
ADQ0-ADQ15
VALID ADDRESS
VALID
VALID
VALID
NOT VALID
VALID
A16-A22
VALID ADDRESS
tAVLH tLLLH
L tEHQX tKHQV Note 1 tKHAX tEHEL tKHQX tEHQZ
tLLKH
tAVKH
K
tELKH
E tGLQV tGLQX tGHQX tGHQZ
Figure 10. Synchronous Burst Read AC waveforms
G tKHTV tGLTV Note 2 X Latency Valid Data Flow Note 2 tKHTX Note 2 Boundary Crossing Standby tEHTZ
tELTV
Hi-Z
WAIT
Address Latch
DC and AC parameters
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge.
63/114
AI12324
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VALID NOT VALID NOT VALID NOT VALID NOT VALID NOT VALID tLLKH tKHQV Note 1 tKHAX tEHEL tEHQX tEHQZ
DC and AC parameters
ADQ0-ADQ15
VALID ADDRESS
A16-A22
VALID ADDRESS
tAVLH
tLLLH
L
tAVKH
K(3)
tELKH
E tGLQX tGLQV tGHQX tGHQZ
Figure 11. Single Synchronous Read AC waveforms
G tELTV tGLTV tKHTV tGHTV tEHTZ
Hi-Z
WAIT(2)
M58LR128HC, M58LR128HD
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge.
AI12325
M58LR128HC, M58LR128HD
ADQ0-ADQ15
VALID ADDRESS
VALID
VALID
VALID
VALID
A16-A22
VALID ADDRESS
tAVLH tLLLH
L tEHQX tKHQV Note 1 Note 3 tEHEL tEHQZ
tLLKH
tAVKH
K(4)
tELKH
tKHAX
E tGLQX tGLQV tGHQZ tGLQV tGHQX tGHQZ
G tGLTV tEHTZ
Figure 12. Synchronous Burst Read Suspend AC waveforms
tELTV
Hi-Z
WAIT(2)
DC and AC parameters
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. The CLOCK signal can be held high or low 4. Address latched and data output on the rising clock edge.
AI12326
65/114
DC and AC parameters Figure 13. Clock input AC waveform
tKHKL
M58LR128HC, M58LR128HD
tKHKH
tf
tr
tKLKH
AI06981
Table 24.
Symbol tAVKH tELKH tELTV Synchronous Read Timings tEHEL tEHTZ tGHTV tGLTV tKHAX tKHQV tKHTV tKHQX tKHTX tLLKH Clock Specifications tKHKH(3) tKHKL tKLKH tf tr
Synchronous Read AC characteristics(1) (2)
M58LR128HC/D Alt tAVCLKH tELCLKH Parameter 70 Address Valid to Clock High Chip Enable Low to Clock High Chip Enable Low to Wait Valid Chip Enable Pulse Width (subsequent synchronous reads) Chip Enable High to Wait Hi-Z Output Enable High to Wait Valid Output Enable Low to Wait Valid tCLKHAX tCLKHQV tCLKHQX Clock High to Address Transition Clock High to Output Valid Clock High to WAIT Valid Clock High to Output Transition Clock High to WAIT Transition Min Min Max Min Max Min Max Min Max 5 5 11 14 14 11 11 7 11 ns ns ns ns ns ns ns ns ns Unit
Min Min Min Min
3 5 15 3.5
ns ns ns ns
tADVLCLKH Latch Enable Low to Clock High tCLK Clock Period (66MHz) Clock High to Clock Low Clock Low to Clock High Clock Fall or Rise Time
Max
3
ns
1. Sampled only, not 100% tested. 2. For other timings please refer to Table 23: Asynchronous Read AC characteristics. 3. The device can support jitters of +/-5% on clock frequency.
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PROGRAM OR ERASE tAVAV BANK ADD. tLHAX BANK ADDRESS tAVLH tLLLH tDVWH VALID ADDRESS VALID ADDRESS tWHDX COMMAND VALID ADD. CMD OR DATA VALID ADD. STATUS REGISTER tAVAV
ADQ0-ADQ15
M58LR128HC, M58LR128HD
A16-A22
L tELLH tWHLL tELLH tELQV tLHGL
E tELWL tWHEH
G tGHLL tWLWH tWHEL
Figure 14. Write AC waveforms, Write Enable controlled
W tWHWL tWPHWH tWHWPL tQVWPL
WP tWHVPL
VPP tVPHWH tQVVPL
K SET-UP COMMAND CONFIRM COMMAND STATUS REGISTER READ 1ST POLLING
Ai12327
DC and AC parameters
67/114
DC and AC parameters Table 25.
Symbol tAVAV tAVLH tDVWH tELLH Write Enable Controlled Timings tELWL tELQV tGHLL tLHAX tLHGL tLLLH tWHDX tWHEH tWHEL(2) tWHLL tWHWL tWLWH tQVVPL Protection Timings tQVWPL tVPHWH tWHVPL tWHWPL tWPHWH tVPS tWPH tWP tDH tCH tCS tDS
M58LR128HC, M58LR128HD Write AC characteristics, Write Enable controlled(1)
M58LR128HC/D Alt tWC Parameter 70 Address Valid to Next Address Valid Address Valid to Latch Enable High Data Valid to Write Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Write Enable Low Chip Enable Low to Output Valid Output Enable High to Latch Enable Low Latch Enable High to Address Transition Latch Enable High to Output Enable Low Latch Enable Pulse Width Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Chip Enable Low Write Enable High to Latch Enable Low Write Enable High to Write Enable Low Write Enable Low to Write Enable High Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 70 7 40 10 0 70 20 7 5 7 0 0 25 0 25 45 0 0 200 200 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Output (Status Register) Valid to VPP Low Min Output (Status Register) Valid to Write Protect Low VPP High to Write Enable High Write Enable High to VPP Low Write Enable High to Write Protect Low Write Protect High to Write Enable High Min Min Min Min Min
1. Sampled only, not 100% tested. 2. tWHEL has the values shown when reading in the targeted bank or when reading following a Set Configuration Register command.System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued, tWHEL is 0ns.
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PROGRAM OR ERASE tAVAV BANK ADD tLHAX BANK ADDRESS tAVLH tLLLH VALID ADDRESS VALID ADDRESS tDVEH tEHDX COMMAND VALID ADD CMD OR DATA VALID ADD STATUS REGISTER tAVAV
ADQ0-ADQ15
M58LR128HC, M58LR128HD
A16-A22
L tELLH tEHLL tELLH tLHGL
E tELEH tWLEL tEHEL tELQV
G tGHLL tEHWH tWHEL
Figure 15. Write AC waveforms, Chip Enable controlled
W tEHWPL tWPHEH tQVWPL
WP tEHVPL tVPHEH tQVVPL
VPP
K SET-UP COMMAND CONFIRM COMMAND STATUS REGISTER READ 1ST POLLING
Ai12328
DC and AC parameters
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DC and AC parameters Table 26.
Symbol tAVAV tAVLH tDVEH tEHDX Chip Enable Controlled Timings tEHEL tEHLL tEHWH tELEH tELLH tELQV tGHLL tLHAX tLHGL tLLLH tWHEL(2) tWLEL tEHVPL Protection Timings tEHWPL tQVVPL tQVWPL tVPHEH tWPHEH tVPS tCS tCH tWP tDS tDH
M58LR128HC, M58LR128HD Write AC characteristics, Chip Enable controlled(1)
M58LR128HC/D Alt tWC Parameter 70 Address Valid to Next Address Valid Address Valid to Latch Enable High Data Valid to Chip Enable High Chip Enable High to Input Transition Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 70 7 40 0 25 0 0 45 10 70 20 20 5 7 25 0 200 200 0 0 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tWPH Chip Enable High to Chip Enable Low Chip Enable High to Latch Enable Low Chip Enable High to Write Enable High Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Output Valid Output Enable High to Latch Enable Low Latch Enable High to Address Transition Latch Enable High to Output Enable Low Latch Enable Pulse Width Write Enable High to Chip Enable Low Write Enable Low to Chip Enable Low Chip Enable High to VPP Low Chip Enable High to Write Protect Low Output (Status Register) Valid to VPP Low Output (Status Register) Valid to Write Protect Low VPP High to Chip Enable High Write Protect High to Chip Enable High
1. Sampled only, not 100% tested. 2. tWHEL has the values shown when reading in the targeted bank or when reading following a Set Configuration Register command.System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued, tWHEL is 0ns.
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M58LR128HC, M58LR128HD Figure 16. Reset and Power-up AC waveforms
DC and AC parameters
W, E, G, L
tPHWL tPHEL tPHGL tPHLL
tPLWL tPLEL tPLGL tPLLL
RP tVDHPH VDD, VDDQ Power-Up Reset
AI06976
tPLPH
Table 27.
Symbol
Reset and Power-up AC characteristics
M58LR128HC/D Parameter Reset Low to Write Enable Low, Chip Enable Low, Output Enable Low, Latch Enable Low Reset High to Write Enable Low Chip Enable Low Output Enable Low Latch Enable Low RP Pulse Width Supply Voltages High to Reset High Test Condition 70 During Program During Erase Other Conditions Min Min Min 10 20 70 Unit s s ns
tPLWL tPLEL tPLGL tPLLL tPHWL tPHEL tPHGL tPHLL tPLPH(1),(2) tVDHPH(3)
Min
30
ns
Min Min
50 150
ns s
1. The device Reset is possible but not guaranteed if tPLPH < 50ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.
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Package mechanical
M58LR128HC, M58LR128HD
13
Package mechanical
In order to meet environmental requirements, Numonyx offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 17. VFBGA44 7.7x9mm - 10x4 ball array, 0.50mm pitch, Bottom View Package Outline
D D2 D1 FE FE1 SD
E1 SE
E2
E
BALL "A1"
FD1 FD
e
b
ddd
A
A1
A2
BGA-Z47
1. Drawing is not to scale.
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M58LR128HC, M58LR128HD Table 28.
Package mechanical
VFBGA44 7.7x9mm - 10x4 ball array, 0.50mm pitch, package mechanical data
millimeters inches Max 1.00 0.15 0.66 0.32 7.70 4.50 6.50 0.08 9.00 1.50 3.50 0.50 1.60 0.60 3.75 2.75 0.25 0.25 - - - - - - 8.90 9.10 0.354 0.059 0.138 0.020 0.063 0.024 0.148 0.108 0.010 0.010 - - - - - - 0.350 0.27 7.60 0.37 7.80 0.026 0.013 0.303 0.177 0.256 0.003 0.358 0.011 0.299 0.015 0.307 0.006 Typ Min Max 0.039
Symbol Typ A A1 A2 b D D1 D2 ddd E E1 E2 e FD FD1 FE FE1 SD SE Min
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Package mechanical
M58LR128HC, M58LR128HD
Figure 18. VFBGA44 daisy chain - package connections (top view through package)
AI08181
1
2
3
4
5
6
7
8
9
10
11
12
13
14
G
C
D
74/114
H
A
B
E
F
M58LR128HC, M58LR128HD
Package mechanical
Figure 19. VFBGA44 daisy chain - PCB connection proposal (top view through package)
AI08182
13
14
4
5
6
7
8
9
10
11
1
2
G
C
D
START POINT H A B E F
3
END POINT
12
75/114
Part numbering
M58LR128HC, M58LR128HD
14
Part numbering
Table 29.
Example: Device Type M58 Architecture L = Multilevel, Multiple Bank, Burst Mode Operating Voltage R = VDD = 1.7V to 2.0V, VDDQ = 1.7V to 2.0V Density 128 = 128 Mbit (x16) Technology H = 90nm technology Parameter Location C = Top Boot, Mux I/O D = Bottom Boot, Mux I/O Speed 70 = 70ns Package ZB = VFBGA44, 7.7 x 9mm, 0.50mm pitch Temperature Range 5 = -25 to 85C Packing Option E = ECOPACK(R) Package, Standard Packing U = ECOPACK(R) Package, Tape & Reel Packing, 16mm
Ordering information scheme
M58LR128HD 70 ZB 5 E
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.), for Daisy chain ordering information or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you.
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M58LR128HC, M58LR128HD
Block address tables
Appendix A
Table 30.
Block address tables
Top boot block addresses, M58LR128HC
# 0 1 2 Parameter Bank 3 4 5 6 7 8 9 10 11 12 13 Bank 1 14 15 16 17 18 19 20 21 Bank 2 22 23 24 25 26 27 28 29 Bank 3 30 31 32 33 34 Size (KWord) 16 16 16 16 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range 7FC000-7FFFFF 7F8000-7FBFFF 7F4000-7F7FFF 7F0000-7F3FFF 7E0000-7EFFFF 7D0000-7DFFFF 7C0000-7CFFFF 7B0000-7BFFFF 7A0000-7AFFFF 790000-79FFFF 780000-78FFFF 770000-77FFFF 760000-76FFFF 750000-75FFFF 740000-74FFFF 730000-73FFFF 720000-72FFFF 710000-71FFFF 700000-70FFFF 6F0000-6FFFFF 6E0000-6EFFFF 6D0000-6DFFFF 6C0000-6CFFFF 6B0000-6BFFFF 6A0000-6AFFFF 690000-69FFFF 680000-68FFFF 670000-67FFFF 660000-66FFFF 650000-65FFFF 640000-64FFFF 630000-63FFFF 620000-62FFFF 610000-61FFFF 600000-60FFFF
Bank(1)
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Block address tables Table 30.
M58LR128HC, M58LR128HD Top boot block addresses, M58LR128HC (continued)
# 35 36 37 Bank 4 38 39 40 41 42 43 44 45 Bank 5 46 47 48 49 50 51 52 53 Bank 6 54 55 56 57 58 59 60 61 Bank 7 62 63 64 65 66 Size (KWord) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range 5F0000-5FFFFF 5E0000-5EFFFF 5D0000-5DFFFF 5C0000-5CFFFF 5B0000-5BFFFF 5A0000-5AFFFF 590000-59FFFF 580000-58FFFF 570000-57FFFF 560000-56FFFF 550000-55FFFF 540000-54FFFF 530000-53FFFF 520000-52FFFF 510000-51FFFF 500000-50FFFF 4F0000-4FFFFF 4E0000-4EFFFF 4D0000-4DFFFF 4C0000-4CFFFF 4B0000-4BFFFF 4A0000-4AFFFF 490000-49FFFF 480000-48FFFF 470000-47FFFF 460000-46FFFF 450000-45FFFF 440000-44FFFF 430000-43FFFF 420000-42FFFF 410000-41FFFF 400000-40FFFF
Bank(1)
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M58LR128HC, M58LR128HD Table 30. Top boot block addresses, M58LR128HC (continued)
# 67 68 69 Bank 8 70 71 72 73 74 75 76 77 Bank 9 78 79 80 81 82 83 84 85 Bank 10 86 87 88 89 90 91 92 93 Bank 11 94 95 96 97 98 Size (KWord) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64
Block address tables
Bank(1)
Address Range 3F0000-3FFFFF 3E0000-3EFFFF 3D0000-3DFFFF 3C0000-3CFFFF 3B0000-3BFFFF 3A0000-3AFFFF 390000-39FFFF 380000-38FFFF 370000-37FFFF 360000-36FFFF 350000-35FFFF 340000-34FFFF 330000-33FFFF 320000-32FFFF 310000-31FFFF 300000-30FFFF 2F0000-2FFFFF 2E0000-2EFFFF 2D0000-2DFFFF 2C0000-2CFFFF 2B0000-2BFFFF 2A0000-2AFFFF 290000-29FFFF 280000-28FFFF 270000-27FFFF 260000-26FFFF 250000-25FFFF 240000-24FFFF 230000-23FFFF 220000-22FFFF 210000-21FFFF 200000-20FFFF
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Block address tables Table 30.
M58LR128HC, M58LR128HD Top boot block addresses, M58LR128HC (continued)
# 99 100 101 Bank 12 102 103 104 105 106 107 108 109 Bank 13 110 111 112 113 114 115 116 117 Bank 14 118 119 120 121 122 123 124 125 Bank 15 126 127 128 129 130 Size (KWord) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range 1F0000-1FFFFF 1E0000-1EFFFF 1D0000-1DFFFF 1C0000-1CFFFF 1B0000-1BFFFF 1A0000-1AFFFF 190000-19FFFF 180000-18FFFF 170000-17FFFF 160000-16FFFF 150000-15FFFF 140000-14FFFF 130000-13FFFF 120000-12FFFF 110000-11FFFF 100000-10FFFF 0F0000-0FFFFF 0E0000-0EFFFF 0D0000-0DFFFF 0C0000-0CFFFF 0B0000-0BFFFF 0A0000-0AFFFF 090000-09FFFF 080000-08FFFF 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 000000-00FFFF
Bank(1)
1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only; Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
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M58LR128HC, M58LR128HD Table 31. Bottom boot block addresses, M58LR128HD
# 130 129 128 Bank 15 127 126 125 124 123 122 121 120 Bank 14 119 118 117 116 115 114 113 112 Bank 13 111 110 109 108 107 106 105 104 Bank 12 103 102 101 100 99 Size (KWord) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64
Block address tables
Bank(1)
Address Range 7F0000-7FFFFF 7E0000-7EFFFF 7D0000-7DFFFF 7C0000-7CFFFF 7B0000-7BFFFF 7A0000-7AFFFF 790000-79FFFF 780000-78FFFF 770000-77FFFF 760000-76FFFF 750000-75FFFF 740000-74FFFF 730000-73FFFF 720000-72FFFF 710000-71FFFF 700000-70FFFF 6F0000-6FFFFF 6E0000-6EFFFF 6D0000-6DFFFF 6C0000-6CFFFF 6B0000-6BFFFF 6A0000-6AFFFF 690000-69FFFF 680000-68FFFF 670000-67FFFF 660000-66FFFF 650000-65FFFF 640000-64FFFF 630000-63FFFF 620000-62FFFF 610000-61FFFF 600000-60FFFF
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Block address tables Table 31.
M58LR128HC, M58LR128HD Bottom boot block addresses, M58LR128HD (continued)
# 98 97 96 Bank 11 95 94 93 92 91 90 89 88 Bank 10 87 86 85 84 83 82 81 80 Bank 9 79 78 77 76 75 74 73 72 Bank 8 71 70 69 68 67 Size (KWord) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range 5F0000-5FFFFF 5E0000-5EFFFF 5D0000-5DFFFF 5C0000-5CFFFF 5B0000-5BFFFF 5A0000-5AFFFF 590000-59FFFF 580000-58FFFF 570000-57FFFF 560000-56FFFF 550000-55FFFF 540000-54FFFF 530000-53FFFF 520000-52FFFF 510000-51FFFF 500000-50FFFF 4F0000-4FFFFF 4E0000-4EFFFF 4D0000-4DFFFF 4C0000-4CFFFF 4B0000-4BFFFF 4A0000-4AFFFF 490000-49FFFF 480000-48FFFF 470000-47FFFF 460000-46FFFF 450000-45FFFF 440000-44FFFF 430000-43FFFF 420000-42FFFF 410000-41FFFF 400000-40FFFF
Bank(1)
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M58LR128HC, M58LR128HD Table 31.
Block address tables
Bottom boot block addresses, M58LR128HD (continued)
# 66 65 64 Bank 7 63 62 61 60 59 58 57 56 Bank 6 55 54 53 52 51 50 49 48 Bank 5 47 46 45 44 43 42 41 40 Bank 4 39 38 37 36 35 Size (KWord) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range 3F0000-3FFFFF 3E0000-3EFFFF 3D0000-3DFFFF 3C0000-3CFFFF 3B0000-3BFFFF 3A0000-3AFFFF 390000-39FFFF 380000-38FFFF 370000-37FFFF 360000-36FFFF 350000-35FFFF 340000-34FFFF 330000-33FFFF 320000-32FFFF 310000-31FFFF 300000-30FFFF 2F0000-2FFFFF 2E0000-2EFFFF 2D0000-2DFFFF 2C0000-2CFFFF 2B0000-2BFFFF 2A0000-2AFFFF 290000-29FFFF 280000-28FFFF 270000-27FFFF 260000-26FFFF 250000-25FFFF 240000-24FFFF 230000-23FFFF 220000-22FFFF 210000-21FFFF 200000-20FFFF
Bank(1)
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Block address tables Table 31.
M58LR128HC, M58LR128HD Bottom boot block addresses, M58LR128HD (continued)
# 34 33 32 Bank 3 31 30 29 28 27 26 25 24 Bank 2 23 22 21 20 19 18 17 16 Bank 1 15 14 13 12 11 10 9 8 Parameter Bank 7 6 5 4 3 2 1 0 Size (KWord) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 16 16 16 16 Address Range 1F0000-1FFFFF 1E0000-1EFFFF 1D0000-1DFFFF 1C0000-1CFFFF 1B0000-1BFFFF 1A0000-1AFFFF 190000-19FFFF 180000-18FFFF 170000-17FFFF 160000-16FFFF 150000-15FFFF 140000-14FFFF 130000-13FFFF 120000-12FFFF 110000-11FFFF 1F0000-1FFFFF 0F0000-0FFFFF 0E0000-0EFFFF 0D0000-0DFFFF 0C0000-0CFFFF 0B0000-0BFFFF 0A0000-0AFFFF 090000-09FFFF 080000-08FFFF 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF
Bank(1)
1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only; Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
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M58LR128HC, M58LR128HD
Common Flash Interface
Appendix B
Common Flash Interface
The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 32, 33, 34, 35, 36, 37, 38, 39, 40 and 41 show the addresses used to retrieve the data. The Query data is always presented on the lowest order data outputs (ADQ0-ADQ7), the other outputs (ADQ8-ADQ15) are set to 0. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Figure 4: Protection Register memory map). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by Numonyx. Issue a Read Array command to return to Read mode. Table 32.
Offset 000h 010h 01Bh 027h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Security Code Area
Query structure overview
Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional) Lock Protection Register Unique device Number and User Programmable OTP
080h
1. The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 33, 34, 35 and 36. Query data is always presented on the lowest order data outputs.
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Common Flash Interface Table 33.
Offset 000h 001h 002h 003h 004h-00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah
M58LR128HC, M58LR128HD
CFI query identification string
Sub-section Name 0020h 882Eh 882Fh reserved DRC reserved 0051h 0052h 0059h 0001h 0000h offset = P = 000Ah 0001h 0000h 0000h value = A = 0000h 0000h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 36) Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported Address for Alternate Algorithm extended Query table p = 10Ah Query Unique ASCII String "QRY" Manufacturer Code Device Code Reserved Die Revision Code Reserved "Q" "R" "Y" M58LR128HC M58LR128HD Description Value Numonyx Top Bottom
NA
NA
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M58LR128HC, M58LR128HD Table 34.
Offset
Common Flash Interface
CFI query system interface information
Data Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Typical time-out per single byte/word program = 2n s Typical time-out for Buffer Program = 2 s Typical time-out per individual block erase = Typical time-out for full chip erase = 2n ms Maximum time-out for word program = 2 times typical Maximum time-out for Buffer Program = 2n times typical
n n n
Value
01Bh
0017h
1.7V
01Ch
0020h
2V
01Dh
0085h
8.5V
01Eh 01Fh 020h 021h 022h 023h 024h 025h 026h
0095h 0004h 0009h 000Ah 0000h 0004h 0004h 0002h 0000h
9.5V 16s 512s
2n
ms
1s NA 256s 8192s 4s NA
Maximum time-out per individual block erase = 2 times typical Maximum time-out for chip erase = 2n times typical
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Common Flash Interface Table 35.
Offset 027h 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh TOP DEVICES 02Fh 030h 031h 032h 033h 034h 035h 038h 02Dh 02Eh BOTTOM DEVICES 02Fh 030h 031h 032h 033h 034h 035h 038h
M58LR128HC, M58LR128HD
Device geometry definition
Data 0018h 0001h 0000h 0006h 0000h 0002h 007Eh 0000h 0000h 0002h 0003h 0000h 0080h 0000h Description Device Size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of identical sized erase block regions within the device bit 7 to 0 = x = number of Erase Block Regions Erase Block Region 1 Information Number of identical-size erase blocks = 007Eh+1 Erase Block Region 1 Information Block size in Region 1 = 0200h * 256 Byte Erase Block Region 2 Information Number of identical-size erase blocks = 0003h+1 Erase Block Region 2 Information Block size in Region 2 = 0080h * 256 Byte Value 16 MBytes x16 Async. 64 Bytes
2
127 128 KByte 4 32 KByte NA 4 32 KBytes 127 128 KBytes NA
Reserved Reserved for future erase block region information 0003h 0000h 0080h 0000h 007Eh 0000h 0000h 0002h Erase Block Region 1 Information Number of identical-size erase block = 0003h+1 Erase Block Region 1 Information Block size in Region 1 = 0080h * 256 bytes Erase Block Region 2 Information Number of identical-size erase block = 007Eh+1 Erase Block Region 2 Information Block size in Region 2 = 0200h * 256 bytes
Reserved Reserved for future erase block region information
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M58LR128HC, M58LR128HD Table 36.
Offset (P)h = 10Ah
Common Flash Interface
Primary Algorithm-Specific Extended Query Table
Data 0050h 0052h 0049h Primary Algorithm extended Query table unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte. bit 0 Chip Erase supported(1 = Yes, 0 = No) bit 1 Erase Suspend supported(1 = Yes, 0 = No) bit 2 Program Suspend supported(1 = Yes, 0 = No) bit 3 Legacy Lock/Unlock supported(1 = Yes, 0 = No) bit 4 Queued Erase supported(1 = Yes, 0 = No) bit 5 Instant individual block locking supported(1 = Yes, 0 = No) bit 6 Protection bits supported(1 = Yes, 0 = No) bit 7 Page mode read supported(1 = Yes, 0 = No) bit 8 Synchronous read supported(1 = Yes, 0 = No) bit 9 Simultaneous operation supported(1 = Yes, 0 = No) bit 10 to 31 Reserved; undefined bits are `0'. If bit 31 is '1' then another 31 bit field of optional features follows at the end of the bit-30 field. Supported Functions after Suspend Read Array, Read Status Register and CFI Query Description Value "P" "R" "I" "1" "3"
(P+3)h =10Dh (P+4)h = 10Eh (P+5)h = 10Fh
0031h 0033h 00E6h 0003h
(P+7)h = 111h
0000h
(P+8)h = 112h
0000h
No Yes Yes No No Yes Yes Yes Yes Yes
(P+9)h = 113h
0001h bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1 Reserved; undefined bits are `0' Yes
(P+A)h = 114h
0003h
Block Protect Status Defines which bits in the Block Status Register section of the Query are implemented. bit 0 Block protect Status Register Lock/Unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0' VDD Logic Supply Optimum Program/Erase voltage (highest performance)
(P+B)h = 115h
0000h
Yes Yes
(P+C)h = 116h
0018h bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP Supply Optimum Program/Erase voltage
1.8V
(P+D)h = 117h
0090h
bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV
9V
89/114
Common Flash Interface Table 37.
Offset (P+E)h = 118h (P+F)h = 119h (P+10)h = 11Ah (P+ 11)h = 11Bh (P+12)h = 11Ch (P+13)h = 11Dh (P+14)h = 11Eh (P+15)h = 11Fh (P+16)h = 120h (P+17)h = 121h (P+18)h = 122h (P+19)h = 123h (P+1A)h = 124h (P+1B)h = 125h (P+1C)h = 126h
M58LR128HC, M58LR128HD
Protection Register information
Data 0002h Description Number of protection register fields in JEDEC ID space. 0000h indicates that 256 fields are available. Value 2 80h 00h 8 Bytes 8 Bytes 89h Protection Register 2: Protection Description Bits 0-31 protection register address Bits 32-39 n number of factory programmed regions (lower byte) Bits 40-47 n number of factory programmed regions (upper byte) Bits 48-55 2n bytes in factory programmable region Bits 56-63 n number of user programmable regions (lower byte) Bits 64-71 n number of user programmable regions (upper byte) Bits 72-79 2n bytes in user programmable region 00h 00h 00h 0 0 0 16 0 16
0080h Protection Field 1: Protection Description 0000h Bits 0-7 Lower byte of protection register address Bits 8-15 Upper byte of protection register address 0003h Bits 16-23 2n bytes in factory pre-programmed region 0003h Bits 24-31 2n bytes in user programmable region 0089h 0000h 0000h 0000h 0000h 0000h 0000h 0010h 0000h 0004h
Table 38.
Offset
Burst Read information
Data Description Value
(P+1D)h = 127h
Page-mode read capability bits 0-7 n' such that 2n HEX value represents the number of 0003h read-page bytes. See offset 0028h for device word width to determine page-mode data output width. 0004h Number of synchronous mode read configuration fields that follow.
8 Bytes
(P+1E)h = 128h
4
(P+1F)h = 129h
Synchronous mode read capability configuration 1 bit 3-7 Reserved bit 0-2 n' such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear 0001h bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 0028h for word width to determine the burst data output width. 0002h Synchronous mode read capability configuration 2 0003h Synchronous mode read capability configuration 3 0007h Synchronous mode read capability configuration 4
4
(P+20)h = 12Ah (P-21)h = 12Bh (P+22)h = 12Ch
8 16 Cont.
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M58LR128HC, M58LR128HD Table 39. Bank and Erase Block region information(1) (2)
Flash memory (bottom)
Common Flash Interface
Flash memory (top) Offset (P+23)h = 12Dh Data 02h
Description Offset (P+23)h = 12Dh Data 02h Number of Bank Regions within the device
1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank Regions. There are two Bank Regions, see Table 30 and Table 31.
Table 40.
Bank and Erase Block region 1 information
M58LR128HD (bottom) Description Offset (P+24)h = 12Eh (P+25)h = 12Fh Data 01h Number of identical banks within Bank Region 1 00h Number of program or erase operations allowed in Bank Region 1: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in Bank Region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region(2). Bank Region 1 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region Bank Region 1 (Erase Block Type 1) Minimum block erase cycles x 1000
M58LR128HC (top) Offset (P+24)h = 12Eh (P+25)h = 12Fh Data 0Fh 00h
(P+26)h = 130h
11h
(P+26)h = 130h
11h
(P+27)h = 131h
00h
(P+27)h = 131h
00h
(P+28)h = 132h
00h
(P+28)h = 132h
00h
(P+29)h = 133h
01h
(P+29)h = 133h
02h
(P+2A)h = 134h (P+2B)h = 135h (P+2C)h = 136h (P+2D)h = 137h (P+2E)h = 138h (P+2F)h = 139h
07h 00h 00h 02h 64h 00h
(P+2A)h = 134h (P+2B)h = 135h (P+2C)h = 136h (P+2D)h = 137h (P+2E)h = 138h (P+2F)h = 139h
03h 00h 80h 00h 64h 00h
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Common Flash Interface Table 40.
M58LR128HC, M58LR128HD
Bank and Erase Block region 1 information (continued)
M58LR128HD (bottom) Description Offset Data Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 1 (Erase Block Type 1): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Bank Region 1 Erase Block Type 2 Information
M58LR128HC (top) Offset Data
(P+30)h = 13Ah
01h
(P+30)h = 13Ah
01h
(P+31)h = 13Bh
03h
(P+31)h = 13Bh
03h
(P+32)h = 13Ch (P+33)h = 13Dh (P+34)h = 13Eh (P+35)h = 13Fh (P+36)h = 140h (P+37)h = 141h
06h 00h 00h 02h 64h 00h
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: nx256 = number of bytes in erase block region Bank Region 1 (Erase Block Type 2) Minimum block erase cycles x 1000 Bank Regions 1 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 1 (Erase Block Type 2): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved
(P+38)h = 142h
01h
(P+39)h = 143h
03h
1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank Regions. There are two Bank Regions, see Table 30 to Table 31. 3. Although the device supports Page Read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device.
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M58LR128HC, M58LR128HD Table 41. Bank and Erase Block region 2 information
M58LR128HD (bottom)
Common Flash Interface
M58LR128HC (top) Offset (P+32)h = 13Ch (P+33)h = 13Dh Data 01h 00h
Description Offset (P+3A)h = 144h (P+3B)h = 145h Data 0Fh Number of identical banks within Bank Region 2 00h Number of program or erase operations allowed in Bank Region 2: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in Bank Region 2 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(2) Bank Region 2 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region Bank Region 2 (Erase Block Type 1) Minimum block erase cycles x 1000 Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved
(P+34)h = 13Eh
11h
(P+3C)h = 146h
11h
(P+35)h = 13Fh
00h
(P+3D)h = 147h
00h
(P+36)h = 140h
00h
(P+3E)h = 148h
00h
(P+37)h = 141h
02h
(P+3F)h = 149h
01h
(P+38)h = 142h (P+39)h = 143h (P+3A)h = 144h (P+3B)h = 145h (P+3C)h = 146h (P+3D)h = 147h
06h 00h 00h 02h 64h 00h
(P+40)h = 14Ah (P+41)h = 14Bh (P+42)h = 14Ch (P+43)h = 14Dh (P+44)h = 14Eh (P+45)h = 14Fh
07h 00h 00h 02h 64h 00h
(P+3E)h = 148h
01h
(P+46)h = 150h
01h
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Common Flash Interface Table 41.
M58LR128HC, M58LR128HD
Bank and Erase Block region 2 information (continued)
M58LR128HD (bottom) Description Offset Data Bank Region 2 (Erase Block Type 1):Page mode and Synchronous mode capabilities (defined in Table 38) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region Bank Region 2 (Erase Block Type 2) Minimum block erase cycles x 1000 Bank Region 2 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 2 (Erase Block Type 2): Page mode and Synchronous mode capabilities (defined in Table 38) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+48)h = 152h (P+43)h = 153h Feature Space definitions Reserved
M58LR128HC (top) Offset Data
(P+3F)h = 149h
03h
(P+47)h = 151h
03h
(P+40)h = 14Ah (P+41)h = 14Bh (P+42)h = 14Ch (P+43)h = 14Dh (P+44)h = 14Eh (P+45)h = 14Fh
03h 00h 80h 00h 64h 00h
(P+46)h = 150h
01h
(P+47)h = 151h
03h
(P+48)h = 152h (P+49)h = 153h
1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank Regions. There are two Bank Regions, see Table 30 and Table 31. 3. Although the device supports Page Read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device.
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M58LR128HC, M58LR128HD
Flowcharts and pseudo codes
Appendix C
Flowcharts and pseudo codes
Figure 20. Program flowchart and pseudo code
Start program_command (addressToProgram, dataToProgram) {: Write 40h or 10h (3) writeToFlash (addressToProgram, 0x40); /*writeToFlash (addressToProgram, 0x10);*/ /*see note (3)*/ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram); "see note (3)"; /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ; YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End } NO Program to Protected Block Error (1, 2) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
Write Address & Data
Read Status Register (3)
SR7 = 1
AI06170b
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used.
95/114
Flowcharts and pseudo codes Figure 21. Blank Check flowchart and pseudo code
Start
M58LR128HC, M58LR128HD
blank_check_command (blockToCheck) { Write Block Address & BCh writeToFlash (blockToCheck, 0xBC);
Write Block Address & CBh
writeToFlash (blockToCheck, 0xCB); /* Memory enters read status state after the Blank Check Command */
do { Read Status Register (1) status_register = readFlash (blockToCheck); /* see note (1) */ /* E or G must be toggled */ } while (status_register.SR7==0); SR7 = 1 YES SR4 = 1 SR5 = 1 YES Command Sequence Error (2) if (status_register.SR4==1) && (status_register.SR5==1) /* command sequence error */ error_handler () ; NO
SR5 = 0
NO
Blank Check Error (2)
if (status_register.SR5==1) /* Blank Check error */ error_handler () ;
End
}
ai10520c
1. Any address within the bank can equally be used. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
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M58LR128HC, M58LR128HD Figure 22. Buffer Program flowchart and pseudo code
Start
Flowcharts and pseudo codes
Buffer Program E8h Command, Start Address Read Status Register
Buffer_Program_command (Start_Address, n, buffer_Program[] ) /* buffer_Program [] is an array structure used to store the address and data to be programmed to the Flash memory (the address must be within the segment Start Address and Start Address+n) */ { do {writeToFlash (Start_Address, 0xE8) ;
status_register=readFlash (Start_Address);
SR7 = 1 YES Write n(1), Start Address
NO
} while (status_register.SR7==0);
writeToFlash (Start_Address, n);
Write Buffer Data, Start Address
writeToFlash (buffer_Program[0].address, buffer_Program[0].data); /*buffer_Program[0].address is the start address*/
X=0
x = 0;
X=n NO
YES
while (xWrite Next Buffer Data, Next Program Address(2)
{ writeToFlash (buffer_Program[x+1].address, buffer_Program[x+1].data);
x++; X=X+1 } Program Buffer to Flash Confirm D0h
writeToFlash (Start_Address, 0xD0);
Read Status Register
do {status_register=readFlash (Start_Address);
SR7 = 1 YES Full Status Register Check(3)
NO
} while (status_register.SR7==0);
full_status_register_check(); }
End
AI08913b
1. n + 1 is the number of data being programmed. 2. Next Program data is an element belonging to buffer_Program[].data; Next Program address is an element belonging to buffer_Program[].address 3. Routine for Error Check by reading SR3, SR4 and SR1.
97/114
Flowcharts and pseudo codes Figure 23. Program Suspend & Resume flowchart and pseudo code
Start
M58LR128HC, M58LR128HD
Write B0h
program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if program has already completed */
Write 70h do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
Read Status Register
SR7 = 1 YES SR2 = 1
NO
} while (status_register.SR7== 0) ;
NO
Program Complete
if (status_register.SR2==0) /*program completed */ { writeToFlash (bank_address, 0xFF) ; read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/ } else { writeToFlash (bank_address, 0xFF) ;
Write FFh
YES Write FFh
Read Data
Read data from another address
read_data ( ); /*read data from another address*/
Write D0h
writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/
Write 70h(1) } Program Continues with Bank in Read Status Register Mode }
writeToFlash (bank_address, 0x70) ; /*read status register to check if program has completed */
AI10117b
1. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.
98/114
M58LR128HC, M58LR128HD Figure 24. Block Erase flowchart and pseudo code
Flowcharts and pseudo codes
Start erase_command ( blockToErase ) { writeToFlash (blockToErase, 0x20) ; /*see note (2) */ writeToFlash (blockToErase, 0xD0) ; /* Memory enters read status state after the Erase Command */
Write 20h (2)
Write Block Address & D0h
Read Status Register (2)
do { status_register=readFlash (blockToErase) ; /* see note (2) */ /* E or G must be toggled*/
SR7 = 1
NO } while (status_register.SR7== 0) ;
YES SR3 = 0 YES SR4, SR5 = 1 NO SR5 = 0 YES SR1 = 0 YES End } NO Erase to Protected Block Error (1) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Erase Error (1) if ( (status_register.SR5==1) ) /* erase error */ error_handler ( ) ; YES Command Sequence Error (1) if ( (status_register.SR4==1) && (status_register.SR5==1) ) /* command sequence error */ error_handler ( ) ; NO VPP Invalid Error (1) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
AI10976
1. If an error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can equally be used.
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Flowcharts and pseudo codes Figure 25. Erase Suspend & Resume flowchart and pseudo code
M58LR128HC, M58LR128HD
Start
Write B0h
erase_suspend_command ( ) { writeToFlash (bank_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if erase has already completed */
Write 70h
Read Status Register
do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
SR7 = 1 YES SR6 = 1
NO
} while (status_register.SR7== 0) ;
NO
Erase Complete
if (status_register.SR6==0) /*erase completed */ { writeToFlash (bank_address, 0xFF) ;
Write FFh
Read Data YES Write FFh Read data from another block or Program/Set Configuration Register or Block Lock/Unlock/Lock-Down Write D0h else }
read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/
{ writeToFlash (bank_address, 0xFF) ; read_program_data ( ); /*read or program data from another block*/
writeToFlash (bank_address, 0xD0) ; /*write 0xD0 to resume erase*/ writeToFlash (bank_address, 0x70) ; /*read status register to check if erase has completed */ } }
Write 70h(1)
Erase Continues with Bank in Read Status Register Mode
AI13882
1. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.
100/114
M58LR128HC, M58LR128HD Figure 26. Locking operations flowchart and pseudo code
Flowcharts and pseudo codes
Start
Write 60h (1)
locking_operation_command (address, lock_operation) { writeToFlash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; writeToFlash (address, 0x90) ; /*see note (1) */
Write 01h, D0h or 2Fh
Write 90h (1)
Read Block Lock States
Locking change confirmed? YES Write FFh (1)
NO
if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/
writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/ /*see note (1) */ }
End
AI06176b
1. Any address within the bank can equally be used.
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Flowcharts and pseudo codes Figure 27. Protection Register Program flowchart and pseudo code
M58LR128HC, M58LR128HD
Start
Write C0h (3)
protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; /*see note (3) */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram) ; /* see note (3) */ /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ;
Write Address & Data
Read Status Register (3)
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO
VPP Invalid Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.SR4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;
}
AI06177b
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used.
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M58LR128HC, M58LR128HD
Flowcharts and pseudo codes
Figure 28. Buffer Enhanced Factory Program flowchart and pseudo code
Start Write 80h to Address WA1 SETUP PHASE
Buffer_Enhanced_Factory_Program_Command (start_address, DataFlow[]) {
writeToFlash (start_address, 0x80) ;
Write D0h to Address WA1
writeToFlash (start_address, 0xD0) ; do { do { status_register = readFlash (start_address);
Read Status Register
NO
SR7 = 0 YES
NO
SR4 = 1
Initialize count X=0 Write PDX Address WA1
if (status_register.SR4==1) { /*error*/ if (status_register.SR3==1) error_handler ( ) ;/*VPP error */ if (status_register.SR1==1) error_handler ( ) ;/* Locked Block */ PROGRAM AND } VERIFY PHASE while (status_register.SR7==1) x=0; /* initialize count */ do { writeToFlash (start_address, DataFlow[x]);
Read Status Register SR3 and SR1for errors
Exit
Increment Count X=X+1
x++;
NO
X = 32 YES Read Status Register
}while (x<32) do {
status_register = readFlash (start_address);
NO
SR0 = 0 YES
}while (status_register.SR0==1)
NO
Last data? YES Write FFFFh to Address = NOT WA1
} while (not last data)
writeToFlash (another_block_address, FFFFh)
EXIT PHASE
Read Status Register
do { status_register = readFlash (start_address)
NO
SR7 = 1
}while (status_register.SR7==0)
YES Full Status Register Check End
full_status_register_check();
}
AI07302a
103/114
Command interface state tables
M58LR128HC, M58LR128HD
Appendix D
Table 42.
Command interface state tables
Command Interface states - modify table, next state(1)
Command Input Erase Read Confirm Buffer Clear Electronic Blank P/E Resume, Blank Program, Read Status Check Block Unlock Check Program/ Status Register Signature , Read confirm, confirm Erase Register setup (5) CFI Query BEFP (CBh) Suspend (70h) (BCh) (3)(4) (50h) Confirm (B0h) (90h, 98h) (D0h) Blank Check setup Ready (unlock block) OTP Busy OTP Busy IS in OTP Busy OTP busy IS in OTP Busy OTP Busy
Current CI State
Block Buffer BEFP Read Program Program Erase, (3)(4) Setup Array(2) Setup (3)(4) Setup(3)(4) (FFh) (80h) (10/40h) (E8h) (20h)
Ready
Ready
Program Setup
BP Setup
Erase Setup
BEFP Setup
Ready
Lock/CR Setup Setup Busy OTP IS in OTP busy Setup
Ready (Lock Error)
Ready (Lock Error)
OTP Busy
Program Busy IS in Program Program Program Busy Busy Busy IS in Program Busy Program Suspend
Busy
Program Busy
Program Busy
Program
IS in Program Busy Suspend IS in PS Setup Buffer Load 1 Buffer Load 2 Confirm PS IS in PS PS IS in Program Suspend
Program Busy
PS
Program Busy
Program Suspend
Program Suspend Buffer Program Load 1 (give word count load (N-1)); if N=0 go to Buffer Program Confirm. Else (N 0) go to Buffer Program Load 2 (data load) Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program will fail at this point if any block address is different from the first address) Ready (error) BP Busy IS in BP Busy BP Busy IS in BP Busy BP Busy BP Busy Ready (error) BP Suspend Buffer Program Busy
Buffer Program
Busy IS in BP Busy Suspend IS in BP Suspend
Buffer Program Busy BP BP IS in BP BP IS in BP Suspend Suspend Suspend Suspend Suspend
BP busy
Buffer Program Suspend
Buffer Program Suspend
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M58LR128HC, M58LR128HD Table 42.
Command interface state tables
Command Interface states - modify table, next state(1) (continued)
Command Input Erase Read Confirm Buffer Clear Electronic Blank P/E Resume, Blank Program, Read Status Check Block Unlock Check Program/ Status Register Signature , Read confirm, setup confirm Erase Register (5) CFI Query BEFP (BCh) (CBh) Suspend (70h) (3)(4) (50h) Confirm (B0h) (90h, 98h) (D0h) Erase Busy Erase Busy Ready (error) Erase Suspend Erase Busy
Current CI State
Block Buffer BEFP Read Program Program Erase, (3)(4) Setup Array(2) Setup (3)(4) Setup(3)(4) (FFh) (80h) (10/40h) (E8h) (20h)
Setup Busy IS in Erase Busy Suspend IS in ES Setup IS in Program Program Busy in Busy in ES ES Erase Busy IS in Erase Busy
Ready (error) Erase Busy IS in Erase Busy
Erase
Erase Busy
Erase Program BP in ES Suspend in ES
IS in Erase Suspend
ES
Erase Busy
Erase Suspend
Erase Suspend Program Busy in Erase Suspend Program Busy in ES
Busy
IS in Program Busy in ES
Program Busy in ES
PS in ES
Program Busy in Erase Suspend
Program IS in in Erase Program Suspend busy in ES Suspend PS in ES IS in PS in ES Setup Buffer Load 1 IS in PS in PS in ES ES
Program busy in Erase Suspend
IS in Program Suspend in ES
PS in ES
Program Busy in ES
Program Suspend in Erase Suspend
Program Suspend in Erase Suspend Buffer Program Load 1 in Erase Suspend (give word count load (N-1)); if N=0 go to Buffer Program confirm. Else (N 0) go to Buffer Program Load 2 Buffer Program Load 2 in Erase Suspend (data load)
Buffer Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program Load 2 will fail at this point if any block address is different from the first address) Confirm Buffer Program in Erase Suspend BP Busy in ES Erase Suspend (sequence error) IS in BP Busy in ES BP busy in ES IS in BP busy in ES BP Busy in ES Erase Suspend (sequence error) BP Suspend in ES
Busy
BP Busy in ES
Buffer Program Busy in ES
IS in BP busy in ES
Buffer Program Busy in Erase Suspend
BP BP IS in BP BP IS in BP Suspend Suspend Suspend Suspend in Erase Suspend Suspend Suspend in ES in ES in ES in ES IS in BP Suspend in ES
BP Busy in Erase Suspend
Buffer Program Suspend in Erase Suspend
BP Suspend in Erase Suspend
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Command interface state tables Table 42.
M58LR128HC, M58LR128HD
Command Interface states - modify table, next state(1) (continued)
Command Input Erase Read Confirm Buffer Clear Electronic Blank P/E Resume, Blank Program, Read Status Check Block Unlock Check Program/ Status Register Signature , Read confirm, setup confirm Erase Register (5) CFI Query BEFP (BCh) (CBh) Suspend (70h) (3)(4) (50h) Confirm (B0h) (90h, 98h) (D0h) Blank Check busy Blank Check busy
Current CI State
Block Buffer BEFP Read Program Program Erase, (3)(4) Setup Array(2) Setup (3)(4) Setup(3)(4) (FFh) (80h) (10/40h) (E8h) (20h)
Setup Blank Check Busy Blank IS in Blank Check Check busy busy Blank Check busy
Ready (error)
Ready (error)
IS in Blank Check busy Erase Suspend BEFP Busy BEFP Busy(6)
Lock/CR Setup in Erase Suspend Buffer EFP Setup Busy
Erase Suspend (Lock Error) Ready (error)
Erase Suspend (Lock Error) Ready (error)
1. CI = Command Interface, CR = Configuration register, BEFP = Buffer Enhanced Factory program, P/E C = Program/Erase controller, IS = Illegal State, BP = Buffer Program, ES = Erase Suspend. 2. At power-up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data output. 3. The two cycle command should be issued to the same bank address. 4. If the P/E C is active, both cycles are ignored. 5. The Clear Status Register command clears the SR error bits except when the P/E C. is busy or suspended. 6. BEFP is allowed only when Status Register bit SR0 is reset to '0'. BEFP is busy if Block Address is first BEFP Address. Any other commands are treated as data.
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M58LR128HC, M58LR128HD Table 43.
Command interface state tables
Command Interface states - modify table, next output state(1) (2)
Command Input Erase Confirm Block Blank P/E Resume, Buffer Erase, BEFP Block Unlock (4) Setup Check Program Setup (5) setup confirm, BEFP (5) (E8h) (80h) (BCh) Confirm(4)(5) (10/40h) (20h) (D0h) Read Clear Electronic Blank Program/ Read Status Status signature, Check Erase confirm Suspend Register Register Read CFI Query (CBh) (B0h) (70h) (50h) (90h, 98h)
Current CI State
Read Program Array Setup(4)
(3)
(FFh)
Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Buffer Program Load 2 Buffer Program Confirm Buffer Program Setup in Erase Suspend Buffer Program Load 1 in Erase Suspend Buffer Program Load 2 in Erase Suspend Buffer Program Confirm in Erase Suspend Blank Check setup Lock/CR Setup Lock/CR Setup in Erase Suspend
Status Register
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Command interface state tables Table 43.
M58LR128HC, M58LR128HD
Command Interface states - modify table, next output state(1) (2) (continued)
Command Input Erase Confirm Block Blank P/E Resume, Buffer Erase, BEFP Block Unlock (4) Setup Check Program Setup (5) setup confirm, BEFP (5) (E8h) (80h) (BCh) Confirm(4)(5) (10/40h) (20h) (D0h) Read Clear Electronic Blank Program/ Read Status Status signature, Check Erase confirm Suspend Register Register Read CFI Query (CBh) (B0h) (70h) (50h) (90h, 98h) Status Register
Current CI State
Read Program Array Setup(4)
(3)
(FFh)
OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Buffer Program Suspend Program Busy in Erase Suspend Buffer Program Busy in Erase Suspend Program Suspend in Erase Suspend Buffer Program Suspend in Erase Suspend Blank Check busy Illegal State Output Unchanged
Array
Status Register
Output Unchanged
Output Status Unchang Electronic Register ed Signature/ CFI
1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank output state. 2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller. 3. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data output. 4. The two cycle command should be issued to the same bank address. 5. If the P/E.C. is active, both cycles are ignored.
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M58LR128HC, M58LR128HD Table 44. Command interface states - lock table, next state(1)
Command Input Block Lock Confirm (01h) Block LockDown Confirm (2Fh)
Command interface state tables
Current CI State
Lock/CR Setup(2) (60h)
OTP Setup(2) (C0h)
Set CR Confirm (03h)
Block Address (WA0)(3) (XXXXh)
Illegal Command(4)
P/E C operation completed
(5)
Ready Lock/CR Setup Setup OTP Busy IS in OTP busy Setup Busy Program IS in Program busy Suspend IS in PS Setup Buffer Load 1 Buffer Load 2 Confirm Buffer Program Busy IS in Buffer Program busy Suspend IS in BP Suspend Setup Busy IS in Erase busy Suspend IS in ES
Lock/CR Setup
OTP Setup Ready OTP Busy
Ready Ready (Lock error)
N/A N/A N/A
Ready (Lock error)
IS in OTP Busy OTP Busy Program Busy IS in Program Busy Program busy IS in PS
OTP Busy
Ready IS Ready N/A
Program Busy
Ready IS Ready
Program Suspend N/A Program Suspend Buffer Program Load 1 (give word count load (N-1)); Buffer Program Load 2(6) Exit see note (6) N/A N/A N/A N/A Buffer Program Busy Ready
Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program will fail at this point if any block address is different from the first address) Ready (error) IS in BP Busy
Buffer Program Busy
IS Ready
IS in BP Suspend
Buffer Program Suspend N/A Buffer Program Suspend Ready (error) N/A Erase Busy Erase Busy Ready IS ready
IS in Erase Busy
Erase
Lock/CR Setup in ES
IS in ES Erase Suspend
Erase Suspend N/A
109/114
Command interface state tables Table 44.
M58LR128HC, M58LR128HD
Command interface states - lock table, next state(1) (continued)
Command Input Block Lock Confirm (01h) Block LockDown Confirm (2Fh) Block Address (WA0)(3) (XXXXh) P/E C operation completed
(5)
Current CI State
Lock/CR Setup(2) (60h)
OTP Setup(2) (C0h)
Set CR Confirm (03h)
Illegal Command(4)
Setup Busy Program in Erase Suspend IS in Program busy in ES Suspend IS in PS in ES Setup Buffer Load 1 IS in PS in ES IS in Program busy in ES
Program Busy in Erase Suspend Program Busy in Erase Suspend Program Busy in Erase Suspend Program Suspend in Erase Suspend
N/A ES IS in ES
N/A Program Suspend in Erase Suspend Buffer Program Load 1 in Erase Suspend (give word count load (N-1)) Buffer Program Load 2 in Erase Suspend(7) Exit see note (7) N/A
Buffer Load 2
Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program will fail at this point if any block address is different from the first address) Erase Suspend (sequence error) IS in BP busy in ES Buffer Program Busy in Erase Suspend BP busy in ES IS in BP suspend in ES Buffer Program Suspend in Erase Suspend
Buffer Program in Erase Suspend
Confirm Busy IS in BP busy in ES Suspend IS in BP Suspend in ES Setup
ES IS in ES
N/A Buffer Program Suspend in Erase Suspend
Ready (error) IS in Blank Check busy Erase Suspend (Lock error) Blank Check busy Erase Suspend Ready (error) BEFP Busy(8) Exit BEFP Busy(8) Erase Suspend (Lock error)
N/A Ready N/A N/A N/A
Blank Check
Blank Check busy
Lock/CR Setup in ES Setup BEFP Busy
1. CI = Command Interface, CR = Configuration register, BEFP = Buffer Enhanced Factory program, P/E C = Program/Erase controller, IS = Illegal State, BP = Buffer program, ES = Erase suspend, WA0 = Address in a block different from first BEFP address. 2. If the P/E C is active, both cycle are ignored. 3. BEFP Exit when Block Address is different from first Block Address and data are FFFFh. 4. Illegal commands are those not defined in the command set. 5. N/A: not available. In this case the state remains unchanged. 6. If N=0 go to Buffer Program Confirm. Else (not =0) go to Buffer Program Load 2 (data load) 7. If N=0 go to Buffer Program Confirm in Erase suspend. Else (not =0) go to Buffer Program Load 2 in Erase suspend. 8. BEFP is allowed only when Status Register bit SR0 is set to '0'. BEFP is busy if Block Address is first BEFP Address. Any other commands are treated as data.
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M58LR128HC, M58LR128HD Table 45.
Command interface state tables
Command interface states - lock table, next output state (1) (2)
Command Input
Current CI State
Lock/CR Setup(3)( 60h)
Blank Check setup (BCh)
OTP Setup(3) (C0h)
Blank Check confirm (CBh)
P. E./C. Illegal Block Lock Block Lock- Set CR BEFP Confirm Down Confirm Exit(4) Command Operation (5) Completed (01h) Confirm (2Fh) (03h) (FFFFh)
Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Status Register Buffer Program Load 2 Buffer Program Confirm Buffer Program Setup in Erase Suspend Buffer Program Load 1 in Erase Suspend Buffer Program Load 2 in Erase Suspend Buffer Program Confirm in Erase Suspend Blank Check setup Lock/CR Setup Lock/CR Setup in Erase Suspend Status Register Array Status Register Output Unchanged
111/114
Command interface state tables Table 45.
M58LR128HC, M58LR128HD
Command interface states - lock table, next output state (continued)(1) (2)
Command Input
Current CI State
Lock/CR Setup(3)( 60h)
Blank Check setup (BCh)
OTP Setup(3) (C0h)
Blank Check confirm (CBh)
P. E./C. Block Lock Block Lock- Set CR BEFP Illegal Confirm Down Confirm Exit(4) Command Operation (5) Completed (01h) Confirm (2Fh) (03h) (FFFFh)
OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Buffer Program Suspend Status Register Program Busy in Erase Suspend Buffer Program Busy in Erase Suspend Program Suspend in Erase Suspend Buffer Program Suspend in Erase Suspend Blank Check busy Illegal State Output Unchanged Output Unchanged Array Output Unchanged
1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank's output state. 2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller. 3. If the P/E.C. is active, both cycles are ignored. 4. BEFP Exit when Block Address is different from first Block Address and data are FFFFh. 5. Illegal commands are those not defined in the command set.
112/114
M58LR128HC, M58LR128HD
Revision history
Revision history
Table 46.
Date 12-Oct-2006
Document revision history
Revision 0.1 Initial release. Document status promoted from Target Specification to full Datasheet. The Set Configuration Register command is accepted during Block Erase Suspend. Appendix D: Command interface state tables updated. Small text changes. Applied Numonyx branding. Changes
26-Feb-2007
1
13-Nov-2007
2
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M58LR128HC, M58LR128HD
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