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| P3C1256 HIGH SPEED 32K x 8 3.3V STATIC CMOS RAM FEATURES 3.3V Power Supply High Speed (Equal Access and Cycle Times) -- 12/15/20/25 ns (Commercial) -- 15/20/25 ns (Industrial) Low Power Single 3.3 Volts 0.3Volts Power Supply Easy Memory Expansion Using CE and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages --28-Pin TSOP and SOJ DESCRIPTION The P3C1256 is a 262,144-bit high-speed CMOS static RAM organized as 32Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 3.3V 0.3V tolerance power supply. Access times as fast as 12 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P3C1256 is a member of a family of PACE RAMTM products offering fast access times. The P3C1256 device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A14. Reading is accomplished by device selection (CE and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE is HIGH or WE is LOW. Package options for the P3C1256 include 28-pin TSOP and SOJ packages. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS SOJ (J5) 1519B TOP VIEW See end of datasheet for TSOP pin configuration Document # SRAM122 REV B 1 Revised August 2006 P3C1256 RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE Temperature Range (Ambient) Commercial (0C to 70C) Industrial (-40C to 85C) Supply Voltage 3.0V VCC 3.6V 3.0 VCC 3.6V MAXIMUM RATINGS(1) Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. Symbol VCC VTERM TA STG IOUT ILAT Parameter Supply Voltage with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Ambient Temperature Storage Temperature Output Current into Low Outputs Latch-up Current >200 Min -0.5 -0.5 -40 -55 Max 7.0 VCC + 0.5 85 125 25 Unit V V C C mA mA DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Symbol VOH VOL VIH VIL ILI ILO ISB ISB1 Parameter Output High Voltage (I/O0 - I/O7) Output Low Voltage (I/O0 - I/O8) Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current VCC Current TTL Standby Current VCC Current CMOS Standby Current GND VIN VCC GND VOUT VCC CE = VCC VCC = 3.6V, IOUT = 0 mA CE = VCC VCC = 3.6V, IOUT = 0 mA CE = VCC Test Conditions IOH = -4mA, VCC = 3.0V IOL = 8 mA IOL = 10 mA 2.2 -0.5(3) -5 -5 Min 2.4 0.4 0.5 VCC + 0.3 0.8 +5 +5 20 Max Unit V V V V V A A mA 3 mA Document # SRAM122 REV B Page 2 of 10 P3C1256 CAPACITANCES(4) (VCC = 5.0V, TA = 25C, f = 1.0 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Conditions VIN = 0V VOUT = 0V Max 10 10 Unit pF pF POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Parameter Dynamic Operating Current Temperature Test Range Conditions Commercial Industrial * * -12 110 N/A -15 100 115 -20 95 110 -25 90 105 Unit mA mA *Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e., CE, and WE VIL (max), OE is high. Switching inputs are 0V and 3V. AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol tRC tAA tAC tOH tLZ tHZ tOE tOLZ tOHZ tPU tPD Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time 0 12 0 6 0 15 -12 Min 12 12 12 2 2 7 7 0 7 0 20 2 2 8 9 0 9 0 20 Max Min 15 15 15 2 2 9 11 0 10 -15 Max Min 20 20 20 2 2 10 12 -20 Max Min 25 25 25 -25 Max Unit ns ns ns ns ns ns ns ns ns ns ns Document # SRAM122 REV B Page 3 of 10 P3C1256 TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5) OE TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7) Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than -3.0V and -100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ cycle. 6. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE transition LOW. 8. Transition is measured 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. Read Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM122 REV B Page 4 of 10 P3C1256 AC CHARACTERISTICS--WRITE CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 3 -12 Min 12 10 10 0 9 0 8 0 7 3 Max Min 15 12 12 0 11 0 10 0 8 3 -15 Max Min 20 15 15 0 15 0 12 0 10 3 -20 Max Min 25 18 18 0 18 0 15 0 11 -25 Max Unit ns ns ns ns ns ns ns ns ns ns TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11) WE Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show tWZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state 13. Write Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM122 REV B Page 5 of 10 P3C1256 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10) CE AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 TRUTH TABLE Mode Standby Standby DOUT Disabled Read Write CE H X L L L OE X X H L X WE X X H H L I/O High Z High Z High Z DOUT High Z Power Standby Standby Active Active Active Figure 1. Output Load * including scope and test fixture. Note: Because of the ultra-high speed of the P3C1256, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 F high frequency capacitor is also required between VCC and ground. To avoid signal Figure 2. Thevenin Equivalent reflections, proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.73V (Thevenin Voltage) at the comparator input, and a 116 resistor must be used in series with DOUT to match 166 (Thevenin Resistance). Document # SRAM122 REV B Page 6 of 10 P3C1256 DATA RETENTION CHARACTERISTICS Symbol VDR ICCDR tCDR tR *TA = +25C tRC = Read Cycle Time Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Test Conditons Min 2.0 Typ.* VCC = 2.0V 3.0V Max VCC = 2.0V 3.0V Unit V CE VCC -0.2V, VIN VCC -0.2V or VIN 0.2V 0 tRC 10 15 600 900 A ns ns This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM TSOP PIN CONFIGURATION Document # SRAM122 REV B Page 7 of 10 P3C1256 ORDERING INFORMATION SELECTION GUIDE The P3C1256 is available in the following temperature, speed and package options. Speed Temperature Package Range 12 15 20 25 Commercial TSOP -12TC -15TC -20TC -25TC Plastic SOJ Industrial TSOP Plastic SOJ N/A = Not Available -12JC N/A N/A -15JC -15TI -15JI -20JC -20TI -20JI -25JC -25TI -25JI Document # SRAM122 REV B Page 8 of 10 P3C1256 Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q J5 28 (300 mil) Min Max 0.120 0.148 0.078 0.014 0.020 0.007 0.011 0.700 0.730 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 - SOJ SMALL OUTLINE IC PACKAGE Pkg # # Pins Symbol A A2 b D E e HD T1 28 Min Max 0.039 0.047 0.036 0.040 0.007 0.011 0.461 0.469 0.311 0.319 0.022 BSC 0.520 0.535 TSOP THIN SMALL OUTLINE PACKAGE Document # SRAM122 REV B Page 9 of 10 P3C1256 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A B ISSUE DATE 1997 Oct-05 Aug-06 SRAM122 P3C1256 HIGH SPEED 32K x 8 3.3V STATIC CMOS RAM ORIG. OF CHANGE DAB JDB JDB DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Updated SOJ package information Document # SRAM122 REV B Page 10 of 10 |
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