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| Ordering number : ENN8301 Bi-CMOS IC LV23200T Overview For Home Stereo System 1-chip Tuner IC Incorporating PLL The LV23200T is a one-chip tuner IC incorporating PLL for home stereo system. Functions * AM tuner Changeover of the constant in RFAMP, MIX, OSC, IF AMP, DET, AGC, SD, OSC BUFF, IF BUFF, and AGC modes. * FM tuner 1stIFAMP, IF limiter AMP, DET (COIL type) , S-METER, SD, AFC, IF BUFF. * MPX PLL STEREO DECODER, forced MONO, AUDIO MUTE, function to prevent interference from a neighboring station, PILOT canceling function. * PLL frequency synthesizer. Features * Tuner IC and PLL IC integrated into one chip. * MPX-VCO incorporated and without need of adjustment. * FM/AM output level independent setting possible. * MOS transistor for active LPF incorporated. Specitications Maximum Ratings at Ta = 25 C Parameter Maximum supply voltage Symbol VCC max VDD max Operating temperature Storage temperature Topr Tstg VCC VDD Conditions Ratings 7.0 6.0 -20 to +80 -40 to +125 Unit V V C C Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. 92706 / 72005 MS PC B8-8475 No.8301-1/17 LV23200T Operating Condition at Ta = 25 C Parameter Recommended supply voltage Symbol VCC VDD Operating supply voltage range VCC op VDD op1 X'tal oscillation = 4.5MHz Conditions Ratings 5.0 3.0 4.5 to 6.0 2.7 to 3.3 Unit V V V V * Handle pin 34 with care because its electrostatic voltage at C = 200pF and R = 0 is 110 V. Operating Characteristics at Ta = 25C, VCC = 5.0V, VDD = 3.0V Parameter [Current dissipation] FM tuner block AM tuner block PLL block ICCFM ICCAM IDDFM No input in FM mode No input in AM mode X'tal = 4.5MHz, No input at tuner 25 14 2.0 35 24 3.0 45 34 4.0 mA mA mA Symbol Conditions min Ratings typ max Unit [FM-FE characteristics (MPX)] : FM-IF (5PIN) input, fc = 10.7MHz, fm = 1kHz, 75kHzdev (L+R = 90%, Pilot = 10%) Demodulation output 3dB sensitivity 1 3dB sensitivity 2 Total harmonic distortion Signal-to-noise ratio AM suppression ratio SD sensitivity Total harmonic distortion Separation ST sensitivity Mute attenuation Carrier leakage VO LS1 LS2 THD1 S/N AMR SD-1 THD2 SEP VL MUTE CL VIN = 100dBV VIN = 70dBV reference, input at -3dB at input of FIFA (pin 1) VIN = 100dBV reference, input at -3dB at input of FMFA (pin 5) VIN = 100dBV, MONO VIN = 100dBV VIN = 100dBV, AM = 30% 0%mod, SD sensitivity mode 1 VIN = 100dBV, MAIN-MOD VIN = 100dBV, L output/R output VIN = 100dBV, (L+R)+Pilot VIN = 100dBV, L output VIN = 100dBV, (L+R)+Pilot 30 30 70 36 43 0.4 76 40 50 0.5 45 3.0 60 40 5.5 57 1.5 1.5 % dB dB dBV % dB % dB dB 35 40 dBV 450 550 28 650 33 mVrms dBV [AM characteristics] : fc = 999kHz, fm = 1kHz, 30%mod Demodulation output 1 Demodulation output 2 Signal-to-noise ratio 1 Signal-to-noise ratio 2 Total harmonic distortion SD sensitivity [PLL characteristics] Internal return resistance Built-in output resistance Hysteresis width Output high level voltage Output low level voltage Rf Rd VHIS VOH VOL1 VOL2 XIN XOUT CE, CL, DI PD ; IO = -1mA PD ; IO = 1mA BO ; IO = 1mA BO ; IO = 5mA VOL3 VOL4 Output high level voltage IIH1 IIH2 IIH3 Input high level current IIL1 IIL2 IIL3 DO ; IO = 1mA AOUT ; IO = 1mA, AIN = 2.0V CE, CL, DI ; VI = 6.0V XIN ; VI = VDD AIN ; VI = 6.0V CE, CL, DI ; VI = 0V XIN ; VI = 0V AIN ; VI = 0V 0.16 0.16 VDD-1.0 1.0 0.25 1.25 0.25 0.5 5.0 0.9 200 5.0 0.9 200 8 250 0.1VDD M k V V V V V V V A A nA A A nA VO1 VO2 S/N1 S/N2 THD SD-ON VIN = 23dBV, 30%mod, fm = 1kHz VIN = 80dBV, 30%mod, fm = 1kHz VIN = 23dBV VIN = 80dBV VIN = 80dBV 0%mod (Internally fixed sensitivity) 14 50 170 15 48 80 240 20 54 0.4 24 1.3 34 130 310 mVrms mVrms dB dB % dBV Continued on next page. No.8301-2/17 LV23200T Continued from preceding page. Parameter Output off-leak current Symbol IOFF1 IOFF2 "H" level 3-state off-leak current "L" level 3-state off-leak current IOFFH IOFFL Conditions min BO, AOUT ; VO = 10V DO ; VO = 6.0V PD ; VO = 6.0V PD ; VO = 0V 0.01 0.01 Ratings typ max 5.0 5.0 200 200 A A nA nA Unit Package Dimensions unit : mm 3253B No.8301-3/17 LV23200T Description of Pin Functions No. 1 Functions FM 1stIF-AMP input Voltage (V) 1.6V Internal Equivalent Circuit Rin = 330 Remarks Input impedance ri (Rin). 1 Rin 2 REG 2.2V Reference voltage of AM/FM IF/MPX 2 block. Vreg = 2.2V 3 FM 1st IF-AMP output 3.0V Output impedance ro (Rout). Rout = 300 3 Rout 4 AM MIX output VCC MIX coil used between pins 4 and 8 4 (VCC voltage). 5 FM IF input Vreg Input impedance ri (Rin). Rin = 330 5 Rin 2 6 7 GND AM IF input 0V 2.2V AM/FM IF/MPX block GND Input impedance ri (Rin). Rin = 2k 7 Rin 2 8 VCC 5.0V AM/FM IF/MPX block VCC Continued on next page. No.8301-4/17 LV23200T Continued from preceding page. No. 9 FM DET Functions Voltage (V) VCC Internal Equivalent Circuit Remarks Recommended detection coil. 600BCAS-10790Z 10 Phase comparator filter VCC-1.0V R = 10k 10 R 11 Pilot filter VCC-1.0V R = 10k 11 R 12 13 L output R output 2.5V Output impedance ro (Rout). Rout = 7.7k 12 Rout ( 13 ) 15 CE - Chip enable pin At changeover from "L" to "H": Address latching. At changeover from "H" to "L": Data latching. 15 S 16 DI - Serial data input pin Sets data in synchronization with rise of data clock. 16 S 17 CL - Data clock input pin. 17 S 18 DO - Data output pin 18 Outputs various data in synchronization with fall of data clock in the OUT mode. Continued on next page. No.8301-5/17 LV23200T Continued from preceding page. No. 19 20 X IN X OUT Functions Voltage (V) - - Internal Equivalent Circuit Remarks Clock for internal reference Connect a 4.5 MHz crystal oscillator. 19 20 21 22 VDD Pilot canceling output 3.0V Vreg AM/FM IF/MPX block VDD Output impedance ro (Rout). Rout = 30k 22 2 Rout 23 AM detection output 0.8V (FM) Vreg (AM) Output impedance ro (Rout). Rout = 10k Rout 23 24 MPX input Vreg MPX inverse input pin. RNF = 20k RNF 24 25 PLL input Vreg Input impedance ri (Rin). Rin = 20k 25 Rin 26 FM detection output Vreg+0.7V Output impedance ro (Rout). 26 Rout Rout = 3.3k Adjusts separation using the capacitance value of a section between this pin and GND. Continued on next page. No.8301-6/17 LV23200T Continued from preceding page. No. 27 Functions SD monitor Voltage (V) VDD Internal Equivalent Circuit Active "L" Remarks Open collector. VDD 27 28 FMS meter and AM AGC outputs 0.2V (FM) 0.8V (AM) Internal load resistance R = 13.9k Determines the SD response speed during SEEK by a capacitor externally connected to pin 28. 28 R 29 PD - PLL charge pump output pin. 29 30 31 AIN AOUT - - Nch MOS transistor for PLL active low 30 pass filter. 31 32 AM OSC VCC OSC coil used between pins 32 and 8 32 (VCC voltage). 33 AFC Vreg Enables adjustment of the FM SD band width by external resistor between pins 33 and 2 (Vreg voltage). 33 Continued on next page. No.8301-7/17 LV23200T Continued from preceding page. No. 34 Functions AM RF input Voltage (V) Vreg Internal Equivalent Circuit Remarks Use pin 34 with the same potential as for pin 32 (AFC voltage). 34 35 FM OSC input VCC V CC 35 Use pin 35 through pull-up to pin 8 (VCC voltage) by resistance load. 36 BO - Pin dedicated for output. 36 No.8301-8/17 LV23200T Composition of DI control data (serial data input) (1) IN1 mode Address DI 00010100 DNC SNS DVS CTE P10 P12 P13 P14 P15 P11 R0 R1 TEST0 R2 TEST1 (12)TEST (3)IF-CTR (13)Don't care (1)P-CTR (2) IN2 mode Address DI 10010100 BDSW1 (2)R-CTR (11)IFS TEST2 IFS STSW DOC0 DOC1 DOC2 SDC0 SDC1 IFSW DNC (15)SDC (9)O-PORT (15)SDC (5)BDSW (14)STSW Description of DI control Data No. (1) Control block data Programmable divider data P0 to P15 DVS, SNS Description * Data to set the dividing number of programmable divider Binary value with P15 assumed to be MSB. LSB varies according to DVS and SNS. (* : Don't care) DVS 1 0 0 SNS * 1 0 LSB P0 P0 P4 set dividing number (N) 272 to 65535 272 to 65535 4 to 4095 Actual dividing Twice the set value Set value Set value Related data * P0 to P3 invalid when LSB : P4 * To select the signal input (FMIN, AMIN) to the programmable divider and to change the input frequency range. (* : Don't care) DVS 1 0 0 SNS * 1 0 Input FMIN AMIN AMIN Operation frequency range 10 to 160MHz 2 to 40MHz 0.5 to 10MHz (4)IFSW (13)Don't care (7)UNLOCK (3)IF-CTR (10)PD-C (6)DO-C (8)DZ-C DLC GT0 GT1 DZ0 DZ1 UL0 UL1 BO 0 1 0 R3 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 Continued on next page. No.8301-9/17 LV23200T Continued from preceding page. No. (2) Control block data Reference divider data R0 to R3 * Reference frequency (fref) selection data R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference frequency 25kHz 25kHz 25kHz 25kHz 12.5kHz 6.25kHz 3.125kHz 3.125kHz 5kHz 5kHz 5kHz 1kHz 3kHz 15kHz PLL INHIBIT+X'tal OSC PLL INHIBIT Description Related data * PLL INHIBIT * The programmable divider and IF counter stop, with FMIN, AMIN, HCTR and LCTR inputs being in the pull-down condition (GND), and the charge pump has the high impedance. (3) IF counter control data CTE GT0, GT1 * IF counter counting start data CTE = 1 : Counting start = 0 : Counting start * Determines the counting time of universal counter GT1 0 0 1 1 (4) MUTE control data IFSW (5) FM/AM BAND selection control data BDSW * Data to determine the output of output port BDSW, controlling selection of BAND. "Data" = 0 : AM 1 : FM GT0 0 1 0 1 Counting time 4ms 8ms 16ms 32ms Wait time 3 to 4ms 3 to 4ms 3 to 4ms 3 to 4ms IFS * Data to determine the output of output port IFSW, controlling the MUTE function. "Data" = 0 : at receiving 1 : MUTE Continued on next page. No.8301-10/17 LV23200T Continued from preceding page. No. (6) Control block data DO pin control data DOC0 DOC1 DOC2 * Data to control DO pin output DOC2 0 0 0 0 1 1 1 1 DOC1 0 0 1 1 0 0 1 1 DOC0 0 1 0 1 0 1 0 1 Open Low when unlock is detected. end-UC (See the item with asterisk below) Open Open Low when SDON Low when stereo Open DO pin condition Description Related data UL0, UL1 CTE * The open condition is selected at power ON/reset. * IF counter counting end check 1 Counting start 2 Counting end ~ ~ 3 CE : HI DO pin 1 With end-UC set and IF counter starting (CTE = 01), DO pin opens automatically. 2 At end of counting of the IF counter, DO pin goes LOW and check on counting end can be made. 3 DO pin opens when serial data is entered/output (CE pin : Hi) Note : DO pin is always in the open condition during data input (IN1 and IN2 modes, during CE : Hi period), regardless of DO pin control data (DOC0 to 2). In the DO pin condition during data output (OUT mode, CE-Hi period), the content of internal DO serial data is output in synchronization with CL pin signal, regardless of DO pin control data (DOC). (7) Unlock detection data UL0, UL1 * Phase error (E) detection width selection data to judge if PLL is locked. Phase error exceeding the detection width is judged to mean that PLL is locked (* : don't care) UL1 0 0 1 UL0 0 1 * E Detection width Stop 0 6.67s Detection output Open Direct output of E E extended by 1 to 2 ms DOC0 DOC1 DOC2 * DO pin is LOW. Serial data output : UL = 0. (8) Phase comparator control data DZ0, DZ1 * Data to control the dead zone of phase comparator DZ1 0 0 1 1 (9) Output port data BO (10) Charge pump control data DLC DZ0 0 1 0 1 Dead zone mode DZA DZB DZC DZD Dead zone width : DZA ~ ~ Continued on next page. No.8301-11/17 LV23200T Continued from preceding page. No. (14) Control block data Forced monaural control data STSW (15) SD sensitivity control data SDC "Data" = 0 : MONO 1 : STEREO Description Related data * Data to determine the output of output port STSW, controlling the forced stereo functions. * Data to determine the output of output ports SDC, controlling the SD sensitivity "Data" = SDC0 : 0, SDC1 : 0 SD sensitivity 1 = 50dBV (Typ) SDC0 : 0, SDC1 : 1 SD sensitivity 2 = 52dBV (Typ) SDC0 : 1, SDC1 : 0 SD sensitivity 3 = 57dBV (Typ) SDC0 : 1, SDC1 : 1 SD sensitivity 4 = 62dBV (Typ) * Above data values indicate the difference of SD sensitivity levels and are reference values. DO control data (serial data output) composition (1) OUT mode Address DI 01010100 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 UL C9 C8 C7 C6 C5 C4 C3 C2 C1 (1)IN-PORT Description of DO output data No. (1) Control block data Stereo and SD indicators control data STIND, SDIND (2) PLL unlock data UL (3) IF counter, binary counter C19 to C0 Description Related data * Data latching stereo and SD indicator conditions. Latching made in the data output (OUT) mode. SDINDStereo indicator condition STINDSD indicator condition 0 : ST ON, 1 : ST OFF 0 : SD ON, 1 : SD OFF UL0 UL1 CTE GT0 GT1 * Data latching the content of unlock detection circuit UL0 : At unlock 1 : At lock or in the detection stop mode * Data latching the content of IF counter (20-bit binary counter) C19MSB of binary counter C0 LSB of binary counter (3)IF-CTR C0 DO SDIND STIND 0 No.8301-12/17 LV23200T Serial data input (IN1/IN2) tSU, tHD, tEL, tES, tEH0.75s tLC<0.75s CL : Normally Hi tEL CE tES tEH CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC Internal data CL : Normally Low tEL CE tES tEH CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC Internal data Serial data output (OUT) tSU, tHD, tEL, tES, tEH0.75s tDC, tDH<0.35s CL : Normally Hi tEL CE tES tEH CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tDC DO I2 tDC I1 UL C3 C2 C1 tDH C0 CL : Normally Hi tEL CE tES tEH CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tDC DO I2 tDC I1 UL C3 C2 C1 tDH C0 (Note) DO pin is an Nch open drain pin, so that the data varying time (tDC and tDH) differs depending on the pull-up resistance and substrate capacity. No.8301-13/17 LV23200T Serial data timing tCH CL VIH DI VIL tSU DO tHD VIH VIL VIH tCL ~~ CE VIH ~ VIL VIL ~~~~~~ tEL tES ~~~~~~~ VIL VIH VIL VIH tEH tDC tDC tDH tLC Old New Internal data latch << When CL stops at the "L" level >> tCH CL VIH VIL VIH DI VIL DO tSU tCL ~ CE VIH ~ VIL VIH ~ VIL tEL tES VIH tEH tHD VIL tDC ~~~~~~ VIH ~~~~~~~ tDH tLC Old New Internal data latch << When CL stops at the "H" level >> Parameter Data setup time Data hold time Clock "L" level time Clock "H" level time CE wait time CE setup time CE hold time Data latch change time Data output time Symbol tSU tHD tCL tCH tEL tES tEH tLC tDC tDH DO, CL DO, CE Differs depending on the pull-up resistance and substrate capacity Pin DI, CL DI, CL CL CL CE, CL CE, CL CE, CL Conditions Min 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.35 Typ Max Unit s s s s s s s s s No.8301-14/17 LV23200T Block Diagram No.8301-15/17 LV23200T Test Circuit No.8301-16/17 LV23200T Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of July, 2005. Specifications and information herein are subject to change without notice. PS No.8301-17/17 |
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